drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 /*
  48  * The ADMA2 descriptor table size is calculated as the maximum number of
  49  * segments (128), times 2 to allow for an alignment descriptor for each
  50  * segment, plus 1 for a nop end descriptor, all multipled by the 32-bit
  51  * descriptor size (8).
  52  */
  53 #define ADMA_SIZE       ((128 * 2 + 1) * 8)
  54
  55 static unsigned int debug_quirks = 0;
  56 static unsigned int debug_quirks2;
  57
  58 static void sdhci_finish_data(struct sdhci_host *);
  59
  60 static void sdhci_finish_command(struct sdhci_host *);
  61 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  62 static void sdhci_tuning_timer(unsigned long data);
  63 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  64
  65 #ifdef CONFIG_PM_RUNTIME
  66 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  67 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  68 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  69 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  70 #else
  71 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  72 {
  73         return 0;
  74 }
  75 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  76 {
  77         return 0;
  78 }
  79 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  80 {
  81 }
  82 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  83 {
  84 }
  85 #endif
  86
  87 static void sdhci_dumpregs(struct sdhci_host *host)
  88 {
  89         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  90                 mmc_hostname(host->mmc));
  91
  92         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  93                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  94                 sdhci_readw(host, SDHCI_HOST_VERSION));
  95         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  96                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  97                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  98         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  99                 sdhci_readl(host, SDHCI_ARGUMENT),
 100                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
 101         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 102                 sdhci_readl(host, SDHCI_PRESENT_STATE),
 103                 sdhci_readb(host, SDHCI_HOST_CONTROL));
 104         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 105                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 106                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 107         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 108                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 109                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 110         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 111                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 112                 sdhci_readl(host, SDHCI_INT_STATUS));
 113         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 114                 sdhci_readl(host, SDHCI_INT_ENABLE),
 115                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 116         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 117                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 118                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 119         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 120                 sdhci_readl(host, SDHCI_CAPABILITIES),
 121                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 122         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 123                 sdhci_readw(host, SDHCI_COMMAND),
 124                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 125         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 126                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 127
 128         if (host->flags & SDHCI_USE_ADMA)
 129                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 130                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 131                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 132
 133         pr_debug(DRIVER_NAME ": ===========================================\n");
 134 }
 135
 136 /*****************************************************************************\
 137  *                                                                           *
 138  * Low level functions                                                       *
 139  *                                                                           *
 140 \*****************************************************************************/
 141
 142 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 143 {
 144         u32 present;
 145
 146         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 147             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 148                 return;
 149
 150         if (enable) {
 151                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 152                                       SDHCI_CARD_PRESENT;
 153
 154                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 155                                        SDHCI_INT_CARD_INSERT;
 156         } else {
 157                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 158         }
 159
 160         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 161         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 162 }
 163
 164 static void sdhci_enable_card_detection(struct sdhci_host *host)
 165 {
 166         sdhci_set_card_detection(host, true);
 167 }
 168
 169 static void sdhci_disable_card_detection(struct sdhci_host *host)
 170 {
 171         sdhci_set_card_detection(host, false);
 172 }
 173
 174 void sdhci_reset(struct sdhci_host *host, u8 mask)
 175 {
 176         unsigned long timeout;
 177
 178         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 179
 180         if (mask & SDHCI_RESET_ALL) {
 181                 host->clock = 0;
 182                 /* Reset-all turns off SD Bus Power */
 183                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 184                         sdhci_runtime_pm_bus_off(host);
 185         }
 186
 187         /* Wait max 100 ms */
 188         timeout = 100;
 189
 190         /* hw clears the bit when it's done */
 191         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 192                 if (timeout == 0) {
 193                         pr_err("%s: Reset 0x%x never completed.\n",
 194                                 mmc_hostname(host->mmc), (int)mask);
 195                         sdhci_dumpregs(host);
 196                         return;
 197                 }
 198                 timeout--;
 199                 mdelay(1);
 200         }
 201 }
 202 EXPORT_SYMBOL_GPL(sdhci_reset);
 203
 204 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 205 {
 206         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 207                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 208                         SDHCI_CARD_PRESENT))
 209                         return;
 210         }
 211
 212         host->ops->reset(host, mask);
 213
 214         if (mask & SDHCI_RESET_ALL) {
 215                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 216                         if (host->ops->enable_dma)
 217                                 host->ops->enable_dma(host);
 218                 }
 219
 220                 /* Resetting the controller clears many */
 221                 host->preset_enabled = false;
 222         }
 223 }
 224
 225 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 226
 227 static void sdhci_init(struct sdhci_host *host, int soft)
 228 {
 229         if (soft)
 230                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 231         else
 232                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 233
 234         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 235                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 236                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 237                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 238                     SDHCI_INT_RESPONSE;
 239
 240         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 241         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 242
 243         if (soft) {
 244                 /* force clock reconfiguration */
 245                 host->clock = 0;
 246                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 247         }
 248 }
 249
 250 static void sdhci_reinit(struct sdhci_host *host)
 251 {
 252         sdhci_init(host, 0);
 253         /*
 254          * Retuning stuffs are affected by different cards inserted and only
 255          * applicable to UHS-I cards. So reset these fields to their initial
 256          * value when card is removed.
 257          */
 258         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 259                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 260
 261                 del_timer_sync(&host->tuning_timer);
 262                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 263                 host->mmc->max_blk_count =
 264                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 265         }
 266         sdhci_enable_card_detection(host);
 267 }
 268
 269 static void sdhci_activate_led(struct sdhci_host *host)
 270 {
 271         u8 ctrl;
 272
 273         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 274         ctrl |= SDHCI_CTRL_LED;
 275         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 276 }
 277
 278 static void sdhci_deactivate_led(struct sdhci_host *host)
 279 {
 280         u8 ctrl;
 281
 282         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 283         ctrl &= ~SDHCI_CTRL_LED;
 284         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 285 }
 286
 287 #ifdef SDHCI_USE_LEDS_CLASS
 288 static void sdhci_led_control(struct led_classdev *led,
 289         enum led_brightness brightness)
 290 {
 291         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 292         unsigned long flags;
 293
 294         spin_lock_irqsave(&host->lock, flags);
 295
 296         if (host->runtime_suspended)
 297                 goto out;
 298
 299         if (brightness == LED_OFF)
 300                 sdhci_deactivate_led(host);
 301         else
 302                 sdhci_activate_led(host);
 303 out:
 304         spin_unlock_irqrestore(&host->lock, flags);
 305 }
 306 #endif
 307
 308 /*****************************************************************************\
 309  *                                                                           *
 310  * Core functions                                                            *
 311  *                                                                           *
 312 \*****************************************************************************/
 313
 314 static void sdhci_read_block_pio(struct sdhci_host *host)
 315 {
 316         unsigned long flags;
 317         size_t blksize, len, chunk;
 318         u32 uninitialized_var(scratch);
 319         u8 *buf;
 320
 321         DBG("PIO reading\n");
 322
 323         blksize = host->data->blksz;
 324         chunk = 0;
 325
 326         local_irq_save(flags);
 327
 328         while (blksize) {
 329                 if (!sg_miter_next(&host->sg_miter))
 330                         BUG();
 331
 332                 len = min(host->sg_miter.length, blksize);
 333
 334                 blksize -= len;
 335                 host->sg_miter.consumed = len;
 336
 337                 buf = host->sg_miter.addr;
 338
 339                 while (len) {
 340                         if (chunk == 0) {
 341                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 342                                 chunk = 4;
 343                         }
 344
 345                         *buf = scratch & 0xFF;
 346
 347                         buf++;
 348                         scratch >>= 8;
 349                         chunk--;
 350                         len--;
 351                 }
 352         }
 353
 354         sg_miter_stop(&host->sg_miter);
 355
 356         local_irq_restore(flags);
 357 }
 358
 359 static void sdhci_write_block_pio(struct sdhci_host *host)
 360 {
 361         unsigned long flags;
 362         size_t blksize, len, chunk;
 363         u32 scratch;
 364         u8 *buf;
 365
 366         DBG("PIO writing\n");
 367
 368         blksize = host->data->blksz;
 369         chunk = 0;
 370         scratch = 0;
 371
 372         local_irq_save(flags);
 373
 374         while (blksize) {
 375                 if (!sg_miter_next(&host->sg_miter))
 376                         BUG();
 377
 378                 len = min(host->sg_miter.length, blksize);
 379
 380                 blksize -= len;
 381                 host->sg_miter.consumed = len;
 382
 383                 buf = host->sg_miter.addr;
 384
 385                 while (len) {
 386                         scratch |= (u32)*buf << (chunk * 8);
 387
 388                         buf++;
 389                         chunk++;
 390                         len--;
 391
 392                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 393                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 394                                 chunk = 0;
 395                                 scratch = 0;
 396                         }
 397                 }
 398         }
 399
 400         sg_miter_stop(&host->sg_miter);
 401
 402         local_irq_restore(flags);
 403 }
 404
 405 static void sdhci_transfer_pio(struct sdhci_host *host)
 406 {
 407         u32 mask;
 408
 409         BUG_ON(!host->data);
 410
 411         if (host->blocks == 0)
 412                 return;
 413
 414         if (host->data->flags & MMC_DATA_READ)
 415                 mask = SDHCI_DATA_AVAILABLE;
 416         else
 417                 mask = SDHCI_SPACE_AVAILABLE;
 418
 419         /*
 420          * Some controllers (JMicron JMB38x) mess up the buffer bits
 421          * for transfers < 4 bytes. As long as it is just one block,
 422          * we can ignore the bits.
 423          */
 424         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 425                 (host->data->blocks == 1))
 426                 mask = ~0;
 427
 428         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 429                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 430                         udelay(100);
 431
 432                 if (host->data->flags & MMC_DATA_READ)
 433                         sdhci_read_block_pio(host);
 434                 else
 435                         sdhci_write_block_pio(host);
 436
 437                 host->blocks--;
 438                 if (host->blocks == 0)
 439                         break;
 440         }
 441
 442         DBG("PIO transfer complete.\n");
 443 }
 444
 445 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 446 {
 447         local_irq_save(*flags);
 448         return kmap_atomic(sg_page(sg)) + sg->offset;
 449 }
 450
 451 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 452 {
 453         kunmap_atomic(buffer);
 454         local_irq_restore(*flags);
 455 }
 456
 457 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 458 {
 459         __le32 *dataddr = (__le32 __force *)(desc + 4);
 460         __le16 *cmdlen = (__le16 __force *)desc;
 461
 462         /* SDHCI specification says ADMA descriptors should be 4 byte
 463          * aligned, so using 16 or 32bit operations should be safe. */
 464
 465         cmdlen[0] = cpu_to_le16(cmd);
 466         cmdlen[1] = cpu_to_le16(len);
 467
 468         dataddr[0] = cpu_to_le32(addr);
 469 }
 470
 471 static int sdhci_adma_table_pre(struct sdhci_host *host,
 472         struct mmc_data *data)
 473 {
 474         int direction;
 475
 476         u8 *desc;
 477         u8 *align;
 478         dma_addr_t addr;
 479         dma_addr_t align_addr;
 480         int len, offset;
 481
 482         struct scatterlist *sg;
 483         int i;
 484         char *buffer;
 485         unsigned long flags;
 486
 487         /*
 488          * The spec does not specify endianness of descriptor table.
 489          * We currently guess that it is LE.
 490          */
 491
 492         if (data->flags & MMC_DATA_READ)
 493                 direction = DMA_FROM_DEVICE;
 494         else
 495                 direction = DMA_TO_DEVICE;
 496
 497         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 498                 host->align_buffer, 128 * 4, direction);
 499         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 500                 goto fail;
 501         BUG_ON(host->align_addr & 0x3);
 502
 503         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 504                 data->sg, data->sg_len, direction);
 505         if (host->sg_count == 0)
 506                 goto unmap_align;
 507
 508         desc = host->adma_desc;
 509         align = host->align_buffer;
 510
 511         align_addr = host->align_addr;
 512
 513         for_each_sg(data->sg, sg, host->sg_count, i) {
 514                 addr = sg_dma_address(sg);
 515                 len = sg_dma_len(sg);
 516
 517                 /*
 518                  * The SDHCI specification states that ADMA
 519                  * addresses must be 32-bit aligned. If they
 520                  * aren't, then we use a bounce buffer for
 521                  * the (up to three) bytes that screw up the
 522                  * alignment.
 523                  */
 524                 offset = (4 - (addr & 0x3)) & 0x3;
 525                 if (offset) {
 526                         if (data->flags & MMC_DATA_WRITE) {
 527                                 buffer = sdhci_kmap_atomic(sg, &flags);
 528                                 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
 529                                         (PAGE_SIZE - offset));
 530                                 memcpy(align, buffer, offset);
 531                                 sdhci_kunmap_atomic(buffer, &flags);
 532                         }
 533
 534                         /* tran, valid */
 535                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 536
 537                         BUG_ON(offset > 65536);
 538
 539                         align += 4;
 540                         align_addr += 4;
 541
 542                         desc += 8;
 543
 544                         addr += offset;
 545                         len -= offset;
 546                 }
 547
 548                 BUG_ON(len > 65536);
 549
 550                 /* tran, valid */
 551                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 552                 desc += 8;
 553
 554                 /*
 555                  * If this triggers then we have a calculation bug
 556                  * somewhere. :/
 557                  */
 558                 WARN_ON((desc - host->adma_desc) >= ADMA_SIZE);
 559         }
 560
 561         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 562                 /*
 563                 * Mark the last descriptor as the terminating descriptor
 564                 */
 565                 if (desc != host->adma_desc) {
 566                         desc -= 8;
 567                         desc[0] |= 0x2; /* end */
 568                 }
 569         } else {
 570                 /*
 571                 * Add a terminating entry.
 572                 */
 573
 574                 /* nop, end, valid */
 575                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 576         }
 577
 578         /*
 579          * Resync align buffer as we might have changed it.
 580          */
 581         if (data->flags & MMC_DATA_WRITE) {
 582                 dma_sync_single_for_device(mmc_dev(host->mmc),
 583                         host->align_addr, 128 * 4, direction);
 584         }
 585
 586         return 0;
 587
 588 unmap_align:
 589         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 590                 128 * 4, direction);
 591 fail:
 592         return -EINVAL;
 593 }
 594
 595 static void sdhci_adma_table_post(struct sdhci_host *host,
 596         struct mmc_data *data)
 597 {
 598         int direction;
 599
 600         struct scatterlist *sg;
 601         int i, size;
 602         u8 *align;
 603         char *buffer;
 604         unsigned long flags;
 605         bool has_unaligned;
 606
 607         if (data->flags & MMC_DATA_READ)
 608                 direction = DMA_FROM_DEVICE;
 609         else
 610                 direction = DMA_TO_DEVICE;
 611
 612         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 613                 128 * 4, direction);
 614
 615         /* Do a quick scan of the SG list for any unaligned mappings */
 616         has_unaligned = false;
 617         for_each_sg(data->sg, sg, host->sg_count, i)
 618                 if (sg_dma_address(sg) & 3) {
 619                         has_unaligned = true;
 620                         break;
 621                 }
 622
 623         if (has_unaligned && data->flags & MMC_DATA_READ) {
 624                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 625                         data->sg_len, direction);
 626
 627                 align = host->align_buffer;
 628
 629                 for_each_sg(data->sg, sg, host->sg_count, i) {
 630                         if (sg_dma_address(sg) & 0x3) {
 631                                 size = 4 - (sg_dma_address(sg) & 0x3);
 632
 633                                 buffer = sdhci_kmap_atomic(sg, &flags);
 634                                 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
 635                                         (PAGE_SIZE - size));
 636                                 memcpy(buffer, align, size);
 637                                 sdhci_kunmap_atomic(buffer, &flags);
 638
 639                                 align += 4;
 640                         }
 641                 }
 642         }
 643
 644         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 645                 data->sg_len, direction);
 646 }
 647
 648 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 649 {
 650         u8 count;
 651         struct mmc_data *data = cmd->data;
 652         unsigned target_timeout, current_timeout;
 653
 654         /*
 655          * If the host controller provides us with an incorrect timeout
 656          * value, just skip the check and use 0xE.  The hardware may take
 657          * longer to time out, but that's much better than having a too-short
 658          * timeout value.
 659          */
 660         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 661                 return 0xE;
 662
 663         /* Unspecified timeout, assume max */
 664         if (!data && !cmd->busy_timeout)
 665                 return 0xE;
 666
 667         /* timeout in us */
 668         if (!data)
 669                 target_timeout = cmd->busy_timeout * 1000;
 670         else {
 671                 target_timeout = data->timeout_ns / 1000;
 672                 if (host->clock)
 673                         target_timeout += data->timeout_clks / host->clock;
 674         }
 675
 676         /*
 677          * Figure out needed cycles.
 678          * We do this in steps in order to fit inside a 32 bit int.
 679          * The first step is the minimum timeout, which will have a
 680          * minimum resolution of 6 bits:
 681          * (1) 2^13*1000 > 2^22,
 682          * (2) host->timeout_clk < 2^16
 683          *     =>
 684          *     (1) / (2) > 2^6
 685          */
 686         count = 0;
 687         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 688         while (current_timeout < target_timeout) {
 689                 count++;
 690                 current_timeout <<= 1;
 691                 if (count >= 0xF)
 692                         break;
 693         }
 694
 695         if (count >= 0xF) {
 696                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 697                     mmc_hostname(host->mmc), count, cmd->opcode);
 698                 count = 0xE;
 699         }
 700
 701         return count;
 702 }
 703
 704 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 705 {
 706         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 707         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 708
 709         if (host->flags & SDHCI_REQ_USE_DMA)
 710                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 711         else
 712                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 713
 714         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 715         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 716 }
 717
 718 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 719 {
 720         u8 count;
 721
 722         if (host->ops->set_timeout) {
 723                 host->ops->set_timeout(host, cmd);
 724         } else {
 725                 count = sdhci_calc_timeout(host, cmd);
 726                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 727         }
 728 }
 729
 730 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 731 {
 732         u8 ctrl;
 733         struct mmc_data *data = cmd->data;
 734         int ret;
 735
 736         WARN_ON(host->data);
 737
 738         if (data || (cmd->flags & MMC_RSP_BUSY))
 739                 sdhci_set_timeout(host, cmd);
 740
 741         if (!data)
 742                 return;
 743
 744         /* Sanity checks */
 745         BUG_ON(data->blksz * data->blocks > 524288);
 746         BUG_ON(data->blksz > host->mmc->max_blk_size);
 747         BUG_ON(data->blocks > 65535);
 748
 749         host->data = data;
 750         host->data_early = 0;
 751         host->data->bytes_xfered = 0;
 752
 753         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 754                 host->flags |= SDHCI_REQ_USE_DMA;
 755
 756         /*
 757          * FIXME: This doesn't account for merging when mapping the
 758          * scatterlist.
 759          */
 760         if (host->flags & SDHCI_REQ_USE_DMA) {
 761                 int broken, i;
 762                 struct scatterlist *sg;
 763
 764                 broken = 0;
 765                 if (host->flags & SDHCI_USE_ADMA) {
 766                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 767                                 broken = 1;
 768                 } else {
 769                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 770                                 broken = 1;
 771                 }
 772
 773                 if (unlikely(broken)) {
 774                         for_each_sg(data->sg, sg, data->sg_len, i) {
 775                                 if (sg->length & 0x3) {
 776                                         DBG("Reverting to PIO because of "
 777                                                 "transfer size (%d)\n",
 778                                                 sg->length);
 779                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 780                                         break;
 781                                 }
 782                         }
 783                 }
 784         }
 785
 786         /*
 787          * The assumption here being that alignment is the same after
 788          * translation to device address space.
 789          */
 790         if (host->flags & SDHCI_REQ_USE_DMA) {
 791                 int broken, i;
 792                 struct scatterlist *sg;
 793
 794                 broken = 0;
 795                 if (host->flags & SDHCI_USE_ADMA) {
 796                         /*
 797                          * As we use 3 byte chunks to work around
 798                          * alignment problems, we need to check this
 799                          * quirk.
 800                          */
 801                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 802                                 broken = 1;
 803                 } else {
 804                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 805                                 broken = 1;
 806                 }
 807
 808                 if (unlikely(broken)) {
 809                         for_each_sg(data->sg, sg, data->sg_len, i) {
 810                                 if (sg->offset & 0x3) {
 811                                         DBG("Reverting to PIO because of "
 812                                                 "bad alignment\n");
 813                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 814                                         break;
 815                                 }
 816                         }
 817                 }
 818         }
 819
 820         if (host->flags & SDHCI_REQ_USE_DMA) {
 821                 if (host->flags & SDHCI_USE_ADMA) {
 822                         ret = sdhci_adma_table_pre(host, data);
 823                         if (ret) {
 824                                 /*
 825                                  * This only happens when someone fed
 826                                  * us an invalid request.
 827                                  */
 828                                 WARN_ON(1);
 829                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 830                         } else {
 831                                 sdhci_writel(host, host->adma_addr,
 832                                         SDHCI_ADMA_ADDRESS);
 833                         }
 834                 } else {
 835                         int sg_cnt;
 836
 837                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 838                                         data->sg, data->sg_len,
 839                                         (data->flags & MMC_DATA_READ) ?
 840                                                 DMA_FROM_DEVICE :
 841                                                 DMA_TO_DEVICE);
 842                         if (sg_cnt == 0) {
 843                                 /*
 844                                  * This only happens when someone fed
 845                                  * us an invalid request.
 846                                  */
 847                                 WARN_ON(1);
 848                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 849                         } else {
 850                                 WARN_ON(sg_cnt != 1);
 851                                 sdhci_writel(host, sg_dma_address(data->sg),
 852                                         SDHCI_DMA_ADDRESS);
 853                         }
 854                 }
 855         }
 856
 857         /*
 858          * Always adjust the DMA selection as some controllers
 859          * (e.g. JMicron) can't do PIO properly when the selection
 860          * is ADMA.
 861          */
 862         if (host->version >= SDHCI_SPEC_200) {
 863                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 864                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 865                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 866                         (host->flags & SDHCI_USE_ADMA))
 867                         ctrl |= SDHCI_CTRL_ADMA32;
 868                 else
 869                         ctrl |= SDHCI_CTRL_SDMA;
 870                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 871         }
 872
 873         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 874                 int flags;
 875
 876                 flags = SG_MITER_ATOMIC;
 877                 if (host->data->flags & MMC_DATA_READ)
 878                         flags |= SG_MITER_TO_SG;
 879                 else
 880                         flags |= SG_MITER_FROM_SG;
 881                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 882                 host->blocks = data->blocks;
 883         }
 884
 885         sdhci_set_transfer_irqs(host);
 886
 887         /* Set the DMA boundary value and block size */
 888         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 889                 data->blksz), SDHCI_BLOCK_SIZE);
 890         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 891 }
 892
 893 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 894         struct mmc_command *cmd)
 895 {
 896         u16 mode;
 897         struct mmc_data *data = cmd->data;
 898
 899         if (data == NULL) {
 900                 /* clear Auto CMD settings for no data CMDs */
 901                 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 902                 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 903                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 904                 return;
 905         }
 906
 907         WARN_ON(!host->data);
 908
 909         mode = SDHCI_TRNS_BLK_CNT_EN;
 910         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 911                 mode |= SDHCI_TRNS_MULTI;
 912                 /*
 913                  * If we are sending CMD23, CMD12 never gets sent
 914                  * on successful completion (so no Auto-CMD12).
 915                  */
 916                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 917                         mode |= SDHCI_TRNS_AUTO_CMD12;
 918                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 919                         mode |= SDHCI_TRNS_AUTO_CMD23;
 920                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 921                 }
 922         }
 923
 924         if (data->flags & MMC_DATA_READ)
 925                 mode |= SDHCI_TRNS_READ;
 926         if (host->flags & SDHCI_REQ_USE_DMA)
 927                 mode |= SDHCI_TRNS_DMA;
 928
 929         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 930 }
 931
 932 static void sdhci_finish_data(struct sdhci_host *host)
 933 {
 934         struct mmc_data *data;
 935
 936         BUG_ON(!host->data);
 937
 938         data = host->data;
 939         host->data = NULL;
 940
 941         if (host->flags & SDHCI_REQ_USE_DMA) {
 942                 if (host->flags & SDHCI_USE_ADMA)
 943                         sdhci_adma_table_post(host, data);
 944                 else {
 945                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 946                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 947                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 948                 }
 949         }
 950
 951         /*
 952          * The specification states that the block count register must
 953          * be updated, but it does not specify at what point in the
 954          * data flow. That makes the register entirely useless to read
 955          * back so we have to assume that nothing made it to the card
 956          * in the event of an error.
 957          */
 958         if (data->error)
 959                 data->bytes_xfered = 0;
 960         else
 961                 data->bytes_xfered = data->blksz * data->blocks;
 962
 963         /*
 964          * Need to send CMD12 if -
 965          * a) open-ended multiblock transfer (no CMD23)
 966          * b) error in multiblock transfer
 967          */
 968         if (data->stop &&
 969             (data->error ||
 970              !host->mrq->sbc)) {
 971
 972                 /*
 973                  * The controller needs a reset of internal state machines
 974                  * upon error conditions.
 975                  */
 976                 if (data->error) {
 977                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 978                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 979                 }
 980
 981                 sdhci_send_command(host, data->stop);
 982         } else
 983                 tasklet_schedule(&host->finish_tasklet);
 984 }
 985
 986 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 987 {
 988         int flags;
 989         u32 mask;
 990         unsigned long timeout;
 991
 992         WARN_ON(host->cmd);
 993
 994         /* Wait max 10 ms */
 995         timeout = 10;
 996
 997         mask = SDHCI_CMD_INHIBIT;
 998         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 999                 mask |= SDHCI_DATA_INHIBIT;
1000
1001         /* We shouldn't wait for data inihibit for stop commands, even
1002            though they might use busy signaling */
1003         if (host->mrq->data && (cmd == host->mrq->data->stop))
1004                 mask &= ~SDHCI_DATA_INHIBIT;
1005
1006         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1007                 if (timeout == 0) {
1008                         pr_err("%s: Controller never released "
1009                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1010                         sdhci_dumpregs(host);
1011                         cmd->error = -EIO;
1012                         tasklet_schedule(&host->finish_tasklet);
1013                         return;
1014                 }
1015                 timeout--;
1016                 mdelay(1);
1017         }
1018
1019         timeout = jiffies;
1020         if (!cmd->data && cmd->busy_timeout > 9000)
1021                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1022         else
1023                 timeout += 10 * HZ;
1024         mod_timer(&host->timer, timeout);
1025
1026         host->cmd = cmd;
1027         host->busy_handle = 0;
1028
1029         sdhci_prepare_data(host, cmd);
1030
1031         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1032
1033         sdhci_set_transfer_mode(host, cmd);
1034
1035         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1036                 pr_err("%s: Unsupported response type!\n",
1037                         mmc_hostname(host->mmc));
1038                 cmd->error = -EINVAL;
1039                 tasklet_schedule(&host->finish_tasklet);
1040                 return;
1041         }
1042
1043         if (!(cmd->flags & MMC_RSP_PRESENT))
1044                 flags = SDHCI_CMD_RESP_NONE;
1045         else if (cmd->flags & MMC_RSP_136)
1046                 flags = SDHCI_CMD_RESP_LONG;
1047         else if (cmd->flags & MMC_RSP_BUSY)
1048                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1049         else
1050                 flags = SDHCI_CMD_RESP_SHORT;
1051
1052         if (cmd->flags & MMC_RSP_CRC)
1053                 flags |= SDHCI_CMD_CRC;
1054         if (cmd->flags & MMC_RSP_OPCODE)
1055                 flags |= SDHCI_CMD_INDEX;
1056
1057         /* CMD19 is special in that the Data Present Select should be set */
1058         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1059             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1060                 flags |= SDHCI_CMD_DATA;
1061
1062         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1063 }
1064 EXPORT_SYMBOL_GPL(sdhci_send_command);
1065
1066 static void sdhci_finish_command(struct sdhci_host *host)
1067 {
1068         int i;
1069
1070         BUG_ON(host->cmd == NULL);
1071
1072         if (host->cmd->flags & MMC_RSP_PRESENT) {
1073                 if (host->cmd->flags & MMC_RSP_136) {
1074                         /* CRC is stripped so we need to do some shifting. */
1075                         for (i = 0;i < 4;i++) {
1076                                 host->cmd->resp[i] = sdhci_readl(host,
1077                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1078                                 if (i != 3)
1079                                         host->cmd->resp[i] |=
1080                                                 sdhci_readb(host,
1081                                                 SDHCI_RESPONSE + (3-i)*4-1);
1082                         }
1083                 } else {
1084                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1085                 }
1086         }
1087
1088         host->cmd->error = 0;
1089
1090         /* Finished CMD23, now send actual command. */
1091         if (host->cmd == host->mrq->sbc) {
1092                 host->cmd = NULL;
1093                 sdhci_send_command(host, host->mrq->cmd);
1094         } else {
1095
1096                 /* Processed actual command. */
1097                 if (host->data && host->data_early)
1098                         sdhci_finish_data(host);
1099
1100                 if (!host->cmd->data)
1101                         tasklet_schedule(&host->finish_tasklet);
1102
1103                 host->cmd = NULL;
1104         }
1105 }
1106
1107 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1108 {
1109         u16 preset = 0;
1110
1111         switch (host->timing) {
1112         case MMC_TIMING_UHS_SDR12:
1113                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1114                 break;
1115         case MMC_TIMING_UHS_SDR25:
1116                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1117                 break;
1118         case MMC_TIMING_UHS_SDR50:
1119                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1120                 break;
1121         case MMC_TIMING_UHS_SDR104:
1122         case MMC_TIMING_MMC_HS200:
1123                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1124                 break;
1125         case MMC_TIMING_UHS_DDR50:
1126                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1127                 break;
1128         default:
1129                 pr_warn("%s: Invalid UHS-I mode selected\n",
1130                         mmc_hostname(host->mmc));
1131                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1132                 break;
1133         }
1134         return preset;
1135 }
1136
1137 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1138 {
1139         int div = 0; /* Initialized for compiler warning */
1140         int real_div = div, clk_mul = 1;
1141         u16 clk = 0;
1142         unsigned long timeout;
1143
1144         host->mmc->actual_clock = 0;
1145
1146         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1147
1148         if (clock == 0)
1149                 return;
1150
1151         if (host->version >= SDHCI_SPEC_300) {
1152                 if (host->preset_enabled) {
1153                         u16 pre_val;
1154
1155                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1156                         pre_val = sdhci_get_preset_value(host);
1157                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1158                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1159                         if (host->clk_mul &&
1160                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1161                                 clk = SDHCI_PROG_CLOCK_MODE;
1162                                 real_div = div + 1;
1163                                 clk_mul = host->clk_mul;
1164                         } else {
1165                                 real_div = max_t(int, 1, div << 1);
1166                         }
1167                         goto clock_set;
1168                 }
1169
1170                 /*
1171                  * Check if the Host Controller supports Programmable Clock
1172                  * Mode.
1173                  */
1174                 if (host->clk_mul) {
1175                         for (div = 1; div <= 1024; div++) {
1176                                 if ((host->max_clk * host->clk_mul / div)
1177                                         <= clock)
1178                                         break;
1179                         }
1180                         /*
1181                          * Set Programmable Clock Mode in the Clock
1182                          * Control register.
1183                          */
1184                         clk = SDHCI_PROG_CLOCK_MODE;
1185                         real_div = div;
1186                         clk_mul = host->clk_mul;
1187                         div--;
1188                 } else {
1189                         /* Version 3.00 divisors must be a multiple of 2. */
1190                         if (host->max_clk <= clock)
1191                                 div = 1;
1192                         else {
1193                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1194                                      div += 2) {
1195                                         if ((host->max_clk / div) <= clock)
1196                                                 break;
1197                                 }
1198                         }
1199                         real_div = div;
1200                         div >>= 1;
1201                 }
1202         } else {
1203                 /* Version 2.00 divisors must be a power of 2. */
1204                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1205                         if ((host->max_clk / div) <= clock)
1206                                 break;
1207                 }
1208                 real_div = div;
1209                 div >>= 1;
1210         }
1211
1212 clock_set:
1213         if (real_div)
1214                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1215         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1216         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1217                 << SDHCI_DIVIDER_HI_SHIFT;
1218         clk |= SDHCI_CLOCK_INT_EN;
1219         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1220
1221         /* Wait max 20 ms */
1222         timeout = 20;
1223         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1224                 & SDHCI_CLOCK_INT_STABLE)) {
1225                 if (timeout == 0) {
1226                         pr_err("%s: Internal clock never "
1227                                 "stabilised.\n", mmc_hostname(host->mmc));
1228                         sdhci_dumpregs(host);
1229                         return;
1230                 }
1231                 timeout--;
1232                 mdelay(1);
1233         }
1234
1235         clk |= SDHCI_CLOCK_CARD_EN;
1236         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1237 }
1238 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1239
1240 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1241                             unsigned short vdd)
1242 {
1243         struct mmc_host *mmc = host->mmc;
1244         u8 pwr = 0;
1245
1246         if (!IS_ERR(mmc->supply.vmmc)) {
1247                 spin_unlock_irq(&host->lock);
1248                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1249                 spin_lock_irq(&host->lock);
1250                 return;
1251         }
1252
1253         if (mode != MMC_POWER_OFF) {
1254                 switch (1 << vdd) {
1255                 case MMC_VDD_165_195:
1256                         pwr = SDHCI_POWER_180;
1257                         break;
1258                 case MMC_VDD_29_30:
1259                 case MMC_VDD_30_31:
1260                         pwr = SDHCI_POWER_300;
1261                         break;
1262                 case MMC_VDD_32_33:
1263                 case MMC_VDD_33_34:
1264                         pwr = SDHCI_POWER_330;
1265                         break;
1266                 default:
1267                         BUG();
1268                 }
1269         }
1270
1271         if (host->pwr == pwr)
1272                 return;
1273
1274         host->pwr = pwr;
1275
1276         if (pwr == 0) {
1277                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1278                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1279                         sdhci_runtime_pm_bus_off(host);
1280                 vdd = 0;
1281         } else {
1282                 /*
1283                  * Spec says that we should clear the power reg before setting
1284                  * a new value. Some controllers don't seem to like this though.
1285                  */
1286                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1287                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1288
1289                 /*
1290                  * At least the Marvell CaFe chip gets confused if we set the
1291                  * voltage and set turn on power at the same time, so set the
1292                  * voltage first.
1293                  */
1294                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1295                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1296
1297                 pwr |= SDHCI_POWER_ON;
1298
1299                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1300
1301                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1302                         sdhci_runtime_pm_bus_on(host);
1303
1304                 /*
1305                  * Some controllers need an extra 10ms delay of 10ms before
1306                  * they can apply clock after applying power
1307                  */
1308                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1309                         mdelay(10);
1310         }
1311 }
1312
1313 /*****************************************************************************\
1314  *                                                                           *
1315  * MMC callbacks                                                             *
1316  *                                                                           *
1317 \*****************************************************************************/
1318
1319 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1320 {
1321         struct sdhci_host *host;
1322         int present;
1323         unsigned long flags;
1324         u32 tuning_opcode;
1325
1326         host = mmc_priv(mmc);
1327
1328         sdhci_runtime_pm_get(host);
1329
1330         spin_lock_irqsave(&host->lock, flags);
1331
1332         WARN_ON(host->mrq != NULL);
1333
1334 #ifndef SDHCI_USE_LEDS_CLASS
1335         sdhci_activate_led(host);
1336 #endif
1337
1338         /*
1339          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1340          * requests if Auto-CMD12 is enabled.
1341          */
1342         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1343                 if (mrq->stop) {
1344                         mrq->data->stop = NULL;
1345                         mrq->stop = NULL;
1346                 }
1347         }
1348
1349         host->mrq = mrq;
1350
1351         /*
1352          * Firstly check card presence from cd-gpio.  The return could
1353          * be one of the following possibilities:
1354          *     negative: cd-gpio is not available
1355          *     zero: cd-gpio is used, and card is removed
1356          *     one: cd-gpio is used, and card is present
1357          */
1358         present = mmc_gpio_get_cd(host->mmc);
1359         if (present < 0) {
1360                 /* If polling, assume that the card is always present. */
1361                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1362                         present = 1;
1363                 else
1364                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1365                                         SDHCI_CARD_PRESENT;
1366         }
1367
1368         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1369                 host->mrq->cmd->error = -ENOMEDIUM;
1370                 tasklet_schedule(&host->finish_tasklet);
1371         } else {
1372                 u32 present_state;
1373
1374                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1375                 /*
1376                  * Check if the re-tuning timer has already expired and there
1377                  * is no on-going data transfer and DAT0 is not busy. If so,
1378                  * we need to execute tuning procedure before sending command.
1379                  */
1380                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1381                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1382                     (present_state & SDHCI_DATA_0_LVL_MASK)) {
1383                         if (mmc->card) {
1384                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1385                                 tuning_opcode =
1386                                         mmc->card->type == MMC_TYPE_MMC ?
1387                                         MMC_SEND_TUNING_BLOCK_HS200 :
1388                                         MMC_SEND_TUNING_BLOCK;
1389
1390                                 /* Here we need to set the host->mrq to NULL,
1391                                  * in case the pending finish_tasklet
1392                                  * finishes it incorrectly.
1393                                  */
1394                                 host->mrq = NULL;
1395
1396                                 spin_unlock_irqrestore(&host->lock, flags);
1397                                 sdhci_execute_tuning(mmc, tuning_opcode);
1398                                 spin_lock_irqsave(&host->lock, flags);
1399
1400                                 /* Restore original mmc_request structure */
1401                                 host->mrq = mrq;
1402                         }
1403                 }
1404
1405                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1406                         sdhci_send_command(host, mrq->sbc);
1407                 else
1408                         sdhci_send_command(host, mrq->cmd);
1409         }
1410
1411         mmiowb();
1412         spin_unlock_irqrestore(&host->lock, flags);
1413 }
1414
1415 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1416 {
1417         u8 ctrl;
1418
1419         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1420         if (width == MMC_BUS_WIDTH_8) {
1421                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1422                 if (host->version >= SDHCI_SPEC_300)
1423                         ctrl |= SDHCI_CTRL_8BITBUS;
1424         } else {
1425                 if (host->version >= SDHCI_SPEC_300)
1426                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1427                 if (width == MMC_BUS_WIDTH_4)
1428                         ctrl |= SDHCI_CTRL_4BITBUS;
1429                 else
1430                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1431         }
1432         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1433 }
1434 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1435
1436 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1437 {
1438         u16 ctrl_2;
1439
1440         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1441         /* Select Bus Speed Mode for host */
1442         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1443         if ((timing == MMC_TIMING_MMC_HS200) ||
1444             (timing == MMC_TIMING_UHS_SDR104))
1445                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1446         else if (timing == MMC_TIMING_UHS_SDR12)
1447                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1448         else if (timing == MMC_TIMING_UHS_SDR25)
1449                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1450         else if (timing == MMC_TIMING_UHS_SDR50)
1451                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1452         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1453                  (timing == MMC_TIMING_MMC_DDR52))
1454                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1455         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1456 }
1457 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1458
1459 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1460 {
1461         unsigned long flags;
1462         u8 ctrl;
1463         struct mmc_host *mmc = host->mmc;
1464
1465         spin_lock_irqsave(&host->lock, flags);
1466
1467         if (host->flags & SDHCI_DEVICE_DEAD) {
1468                 spin_unlock_irqrestore(&host->lock, flags);
1469                 if (!IS_ERR(mmc->supply.vmmc) &&
1470                     ios->power_mode == MMC_POWER_OFF)
1471                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1472                 return;
1473         }
1474
1475         /*
1476          * Reset the chip on each power off.
1477          * Should clear out any weird states.
1478          */
1479         if (ios->power_mode == MMC_POWER_OFF) {
1480                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1481                 sdhci_reinit(host);
1482         }
1483
1484         if (host->version >= SDHCI_SPEC_300 &&
1485                 (ios->power_mode == MMC_POWER_UP) &&
1486                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1487                 sdhci_enable_preset_value(host, false);
1488
1489         if (!ios->clock || ios->clock != host->clock) {
1490                 host->ops->set_clock(host, ios->clock);
1491                 host->clock = ios->clock;
1492
1493                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1494                     host->clock) {
1495                         host->timeout_clk = host->mmc->actual_clock ?
1496                                                 host->mmc->actual_clock / 1000 :
1497                                                 host->clock / 1000;
1498                         host->mmc->max_busy_timeout =
1499                                 host->ops->get_max_timeout_count ?
1500                                 host->ops->get_max_timeout_count(host) :
1501                                 1 << 27;
1502                         host->mmc->max_busy_timeout /= host->timeout_clk;
1503                 }
1504         }
1505
1506         sdhci_set_power(host, ios->power_mode, ios->vdd);
1507
1508         if (host->ops->platform_send_init_74_clocks)
1509                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1510
1511         host->ops->set_bus_width(host, ios->bus_width);
1512
1513         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1514
1515         if ((ios->timing == MMC_TIMING_SD_HS ||
1516              ios->timing == MMC_TIMING_MMC_HS)
1517             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1518                 ctrl |= SDHCI_CTRL_HISPD;
1519         else
1520                 ctrl &= ~SDHCI_CTRL_HISPD;
1521
1522         if (host->version >= SDHCI_SPEC_300) {
1523                 u16 clk, ctrl_2;
1524
1525                 /* In case of UHS-I modes, set High Speed Enable */
1526                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1527                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1528                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1529                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1530                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1531                     (ios->timing == MMC_TIMING_UHS_SDR25))
1532                         ctrl |= SDHCI_CTRL_HISPD;
1533
1534                 if (!host->preset_enabled) {
1535                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1536                         /*
1537                          * We only need to set Driver Strength if the
1538                          * preset value enable is not set.
1539                          */
1540                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1541                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1542                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1543                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1544                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1545                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1546
1547                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1548                 } else {
1549                         /*
1550                          * According to SDHC Spec v3.00, if the Preset Value
1551                          * Enable in the Host Control 2 register is set, we
1552                          * need to reset SD Clock Enable before changing High
1553                          * Speed Enable to avoid generating clock gliches.
1554                          */
1555
1556                         /* Reset SD Clock Enable */
1557                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1558                         clk &= ~SDHCI_CLOCK_CARD_EN;
1559                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1560
1561                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1562
1563                         /* Re-enable SD Clock */
1564                         host->ops->set_clock(host, host->clock);
1565                 }
1566
1567                 /* Reset SD Clock Enable */
1568                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1569                 clk &= ~SDHCI_CLOCK_CARD_EN;
1570                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1571
1572                 host->ops->set_uhs_signaling(host, ios->timing);
1573                 host->timing = ios->timing;
1574
1575                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1576                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1577                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1578                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1579                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1580                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1581                         u16 preset;
1582
1583                         sdhci_enable_preset_value(host, true);
1584                         preset = sdhci_get_preset_value(host);
1585                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1586                                 >> SDHCI_PRESET_DRV_SHIFT;
1587                 }
1588
1589                 /* Re-enable SD Clock */
1590                 host->ops->set_clock(host, host->clock);
1591         } else
1592                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1593
1594         /*
1595          * Some (ENE) controllers go apeshit on some ios operation,
1596          * signalling timeout and CRC errors even on CMD0. Resetting
1597          * it on each ios seems to solve the problem.
1598          */
1599         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1600                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1601
1602         mmiowb();
1603         spin_unlock_irqrestore(&host->lock, flags);
1604 }
1605
1606 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1607 {
1608         struct sdhci_host *host = mmc_priv(mmc);
1609
1610         sdhci_runtime_pm_get(host);
1611         sdhci_do_set_ios(host, ios);
1612         sdhci_runtime_pm_put(host);
1613 }
1614
1615 static int sdhci_do_get_cd(struct sdhci_host *host)
1616 {
1617         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1618
1619         if (host->flags & SDHCI_DEVICE_DEAD)
1620                 return 0;
1621
1622         /* If polling/nonremovable, assume that the card is always present. */
1623         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1624             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1625                 return 1;
1626
1627         /* Try slot gpio detect */
1628         if (!IS_ERR_VALUE(gpio_cd))
1629                 return !!gpio_cd;
1630
1631         /* Host native card detect */
1632         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1633 }
1634
1635 static int sdhci_get_cd(struct mmc_host *mmc)
1636 {
1637         struct sdhci_host *host = mmc_priv(mmc);
1638         int ret;
1639
1640         sdhci_runtime_pm_get(host);
1641         ret = sdhci_do_get_cd(host);
1642         sdhci_runtime_pm_put(host);
1643         return ret;
1644 }
1645
1646 static int sdhci_check_ro(struct sdhci_host *host)
1647 {
1648         unsigned long flags;
1649         int is_readonly;
1650
1651         spin_lock_irqsave(&host->lock, flags);
1652
1653         if (host->flags & SDHCI_DEVICE_DEAD)
1654                 is_readonly = 0;
1655         else if (host->ops->get_ro)
1656                 is_readonly = host->ops->get_ro(host);
1657         else
1658                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1659                                 & SDHCI_WRITE_PROTECT);
1660
1661         spin_unlock_irqrestore(&host->lock, flags);
1662
1663         /* This quirk needs to be replaced by a callback-function later */
1664         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1665                 !is_readonly : is_readonly;
1666 }
1667
1668 #define SAMPLE_COUNT    5
1669
1670 static int sdhci_do_get_ro(struct sdhci_host *host)
1671 {
1672         int i, ro_count;
1673
1674         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1675                 return sdhci_check_ro(host);
1676
1677         ro_count = 0;
1678         for (i = 0; i < SAMPLE_COUNT; i++) {
1679                 if (sdhci_check_ro(host)) {
1680                         if (++ro_count > SAMPLE_COUNT / 2)
1681                                 return 1;
1682                 }
1683                 msleep(30);
1684         }
1685         return 0;
1686 }
1687
1688 static void sdhci_hw_reset(struct mmc_host *mmc)
1689 {
1690         struct sdhci_host *host = mmc_priv(mmc);
1691
1692         if (host->ops && host->ops->hw_reset)
1693                 host->ops->hw_reset(host);
1694 }
1695
1696 static int sdhci_get_ro(struct mmc_host *mmc)
1697 {
1698         struct sdhci_host *host = mmc_priv(mmc);
1699         int ret;
1700
1701         sdhci_runtime_pm_get(host);
1702         ret = sdhci_do_get_ro(host);
1703         sdhci_runtime_pm_put(host);
1704         return ret;
1705 }
1706
1707 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1708 {
1709         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1710                 if (enable)
1711                         host->ier |= SDHCI_INT_CARD_INT;
1712                 else
1713                         host->ier &= ~SDHCI_INT_CARD_INT;
1714
1715                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1716                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1717                 mmiowb();
1718         }
1719 }
1720
1721 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1722 {
1723         struct sdhci_host *host = mmc_priv(mmc);
1724         unsigned long flags;
1725
1726         sdhci_runtime_pm_get(host);
1727
1728         spin_lock_irqsave(&host->lock, flags);
1729         if (enable)
1730                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1731         else
1732                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1733
1734         sdhci_enable_sdio_irq_nolock(host, enable);
1735         spin_unlock_irqrestore(&host->lock, flags);
1736
1737         sdhci_runtime_pm_put(host);
1738 }
1739
1740 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1741                                                 struct mmc_ios *ios)
1742 {
1743         struct mmc_host *mmc = host->mmc;
1744         u16 ctrl;
1745         int ret;
1746
1747         /*
1748          * Signal Voltage Switching is only applicable for Host Controllers
1749          * v3.00 and above.
1750          */
1751         if (host->version < SDHCI_SPEC_300)
1752                 return 0;
1753
1754         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1755
1756         switch (ios->signal_voltage) {
1757         case MMC_SIGNAL_VOLTAGE_330:
1758                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1759                 ctrl &= ~SDHCI_CTRL_VDD_180;
1760                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1761
1762                 if (!IS_ERR(mmc->supply.vqmmc)) {
1763                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1764                                                     3600000);
1765                         if (ret) {
1766                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1767                                         mmc_hostname(mmc));
1768                                 return -EIO;
1769                         }
1770                 }
1771                 /* Wait for 5ms */
1772                 usleep_range(5000, 5500);
1773
1774                 /* 3.3V regulator output should be stable within 5 ms */
1775                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1776                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1777                         return 0;
1778
1779                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1780                         mmc_hostname(mmc));
1781
1782                 return -EAGAIN;
1783         case MMC_SIGNAL_VOLTAGE_180:
1784                 if (!IS_ERR(mmc->supply.vqmmc)) {
1785                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1786                                         1700000, 1950000);
1787                         if (ret) {
1788                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1789                                         mmc_hostname(mmc));
1790                                 return -EIO;
1791                         }
1792                 }
1793
1794                 /*
1795                  * Enable 1.8V Signal Enable in the Host Control2
1796                  * register
1797                  */
1798                 ctrl |= SDHCI_CTRL_VDD_180;
1799                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1800
1801                 /* 1.8V regulator output should be stable within 5 ms */
1802                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1803                 if (ctrl & SDHCI_CTRL_VDD_180)
1804                         return 0;
1805
1806                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1807                         mmc_hostname(mmc));
1808
1809                 return -EAGAIN;
1810         case MMC_SIGNAL_VOLTAGE_120:
1811                 if (!IS_ERR(mmc->supply.vqmmc)) {
1812                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1813                                                     1300000);
1814                         if (ret) {
1815                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1816                                         mmc_hostname(mmc));
1817                                 return -EIO;
1818                         }
1819                 }
1820                 return 0;
1821         default:
1822                 /* No signal voltage switch required */
1823                 return 0;
1824         }
1825 }
1826
1827 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1828         struct mmc_ios *ios)
1829 {
1830         struct sdhci_host *host = mmc_priv(mmc);
1831         int err;
1832
1833         if (host->version < SDHCI_SPEC_300)
1834                 return 0;
1835         sdhci_runtime_pm_get(host);
1836         err = sdhci_do_start_signal_voltage_switch(host, ios);
1837         sdhci_runtime_pm_put(host);
1838         return err;
1839 }
1840
1841 static int sdhci_card_busy(struct mmc_host *mmc)
1842 {
1843         struct sdhci_host *host = mmc_priv(mmc);
1844         u32 present_state;
1845
1846         sdhci_runtime_pm_get(host);
1847         /* Check whether DAT[3:0] is 0000 */
1848         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1849         sdhci_runtime_pm_put(host);
1850
1851         return !(present_state & SDHCI_DATA_LVL_MASK);
1852 }
1853
1854 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1855 {
1856         struct sdhci_host *host = mmc_priv(mmc);
1857         u16 ctrl;
1858         int tuning_loop_counter = MAX_TUNING_LOOP;
1859         int err = 0;
1860         unsigned long flags;
1861
1862         sdhci_runtime_pm_get(host);
1863         spin_lock_irqsave(&host->lock, flags);
1864
1865         /*
1866          * The Host Controller needs tuning only in case of SDR104 mode
1867          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1868          * Capabilities register.
1869          * If the Host Controller supports the HS200 mode then the
1870          * tuning function has to be executed.
1871          */
1872         switch (host->timing) {
1873         case MMC_TIMING_MMC_HS200:
1874         case MMC_TIMING_UHS_SDR104:
1875                 break;
1876
1877         case MMC_TIMING_UHS_SDR50:
1878                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1879                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1880                         break;
1881                 /* FALLTHROUGH */
1882
1883         default:
1884                 spin_unlock_irqrestore(&host->lock, flags);
1885                 sdhci_runtime_pm_put(host);
1886                 return 0;
1887         }
1888
1889         if (host->ops->platform_execute_tuning) {
1890                 spin_unlock_irqrestore(&host->lock, flags);
1891                 err = host->ops->platform_execute_tuning(host, opcode);
1892                 sdhci_runtime_pm_put(host);
1893                 return err;
1894         }
1895
1896         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1897         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1898         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1899
1900         /*
1901          * As per the Host Controller spec v3.00, tuning command
1902          * generates Buffer Read Ready interrupt, so enable that.
1903          *
1904          * Note: The spec clearly says that when tuning sequence
1905          * is being performed, the controller does not generate
1906          * interrupts other than Buffer Read Ready interrupt. But
1907          * to make sure we don't hit a controller bug, we _only_
1908          * enable Buffer Read Ready interrupt here.
1909          */
1910         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1911         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1912
1913         /*
1914          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1915          * of loops reaches 40 times or a timeout of 150ms occurs.
1916          */
1917         do {
1918                 struct mmc_command cmd = {0};
1919                 struct mmc_request mrq = {NULL};
1920
1921                 cmd.opcode = opcode;
1922                 cmd.arg = 0;
1923                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1924                 cmd.retries = 0;
1925                 cmd.data = NULL;
1926                 cmd.error = 0;
1927
1928                 if (tuning_loop_counter-- == 0)
1929                         break;
1930
1931                 mrq.cmd = &cmd;
1932                 host->mrq = &mrq;
1933
1934                 /*
1935                  * In response to CMD19, the card sends 64 bytes of tuning
1936                  * block to the Host Controller. So we set the block size
1937                  * to 64 here.
1938                  */
1939                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1940                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1941                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1942                                              SDHCI_BLOCK_SIZE);
1943                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1944                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1945                                              SDHCI_BLOCK_SIZE);
1946                 } else {
1947                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1948                                      SDHCI_BLOCK_SIZE);
1949                 }
1950
1951                 /*
1952                  * The tuning block is sent by the card to the host controller.
1953                  * So we set the TRNS_READ bit in the Transfer Mode register.
1954                  * This also takes care of setting DMA Enable and Multi Block
1955                  * Select in the same register to 0.
1956                  */
1957                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1958
1959                 sdhci_send_command(host, &cmd);
1960
1961                 host->cmd = NULL;
1962                 host->mrq = NULL;
1963
1964                 spin_unlock_irqrestore(&host->lock, flags);
1965                 /* Wait for Buffer Read Ready interrupt */
1966                 wait_event_interruptible_timeout(host->buf_ready_int,
1967                                         (host->tuning_done == 1),
1968                                         msecs_to_jiffies(50));
1969                 spin_lock_irqsave(&host->lock, flags);
1970
1971                 if (!host->tuning_done) {
1972                         pr_info(DRIVER_NAME ": Timeout waiting for "
1973                                 "Buffer Read Ready interrupt during tuning "
1974                                 "procedure, falling back to fixed sampling "
1975                                 "clock\n");
1976                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1977                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1978                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1979                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1980
1981                         err = -EIO;
1982                         goto out;
1983                 }
1984
1985                 host->tuning_done = 0;
1986
1987                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1988
1989                 /* eMMC spec does not require a delay between tuning cycles */
1990                 if (opcode == MMC_SEND_TUNING_BLOCK)
1991                         mdelay(1);
1992         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1993
1994         /*
1995          * The Host Driver has exhausted the maximum number of loops allowed,
1996          * so use fixed sampling frequency.
1997          */
1998         if (tuning_loop_counter < 0) {
1999                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2000                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2001         }
2002         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2003                 pr_info(DRIVER_NAME ": Tuning procedure"
2004                         " failed, falling back to fixed sampling"
2005                         " clock\n");
2006                 err = -EIO;
2007         }
2008
2009 out:
2010         /*
2011          * If this is the very first time we are here, we start the retuning
2012          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2013          * flag won't be set, we check this condition before actually starting
2014          * the timer.
2015          */
2016         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2017             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2018                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2019                 mod_timer(&host->tuning_timer, jiffies +
2020                         host->tuning_count * HZ);
2021                 /* Tuning mode 1 limits the maximum data length to 4MB */
2022                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2023         } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2024                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2025                 /* Reload the new initial value for timer */
2026                 mod_timer(&host->tuning_timer, jiffies +
2027                           host->tuning_count * HZ);
2028         }
2029
2030         /*
2031          * In case tuning fails, host controllers which support re-tuning can
2032          * try tuning again at a later time, when the re-tuning timer expires.
2033          * So for these controllers, we return 0. Since there might be other
2034          * controllers who do not have this capability, we return error for
2035          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2036          * a retuning timer to do the retuning for the card.
2037          */
2038         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2039                 err = 0;
2040
2041         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2042         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2043         spin_unlock_irqrestore(&host->lock, flags);
2044         sdhci_runtime_pm_put(host);
2045
2046         return err;
2047 }
2048
2049
2050 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2051 {
2052         /* Host Controller v3.00 defines preset value registers */
2053         if (host->version < SDHCI_SPEC_300)
2054                 return;
2055
2056         /*
2057          * We only enable or disable Preset Value if they are not already
2058          * enabled or disabled respectively. Otherwise, we bail out.
2059          */
2060         if (host->preset_enabled != enable) {
2061                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2062
2063                 if (enable)
2064                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2065                 else
2066                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2067
2068                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2069
2070                 if (enable)
2071                         host->flags |= SDHCI_PV_ENABLED;
2072                 else
2073                         host->flags &= ~SDHCI_PV_ENABLED;
2074
2075                 host->preset_enabled = enable;
2076         }
2077 }
2078
2079 static void sdhci_card_event(struct mmc_host *mmc)
2080 {
2081         struct sdhci_host *host = mmc_priv(mmc);
2082         unsigned long flags;
2083
2084         /* First check if client has provided their own card event */
2085         if (host->ops->card_event)
2086                 host->ops->card_event(host);
2087
2088         spin_lock_irqsave(&host->lock, flags);
2089
2090         /* Check host->mrq first in case we are runtime suspended */
2091         if (host->mrq && !sdhci_do_get_cd(host)) {
2092                 pr_err("%s: Card removed during transfer!\n",
2093                         mmc_hostname(host->mmc));
2094                 pr_err("%s: Resetting controller.\n",
2095                         mmc_hostname(host->mmc));
2096
2097                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2098                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2099
2100                 host->mrq->cmd->error = -ENOMEDIUM;
2101                 tasklet_schedule(&host->finish_tasklet);
2102         }
2103
2104         spin_unlock_irqrestore(&host->lock, flags);
2105 }
2106
2107 static const struct mmc_host_ops sdhci_ops = {
2108         .request        = sdhci_request,
2109         .set_ios        = sdhci_set_ios,
2110         .get_cd         = sdhci_get_cd,
2111         .get_ro         = sdhci_get_ro,
2112         .hw_reset       = sdhci_hw_reset,
2113         .enable_sdio_irq = sdhci_enable_sdio_irq,
2114         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2115         .execute_tuning                 = sdhci_execute_tuning,
2116         .card_event                     = sdhci_card_event,
2117         .card_busy      = sdhci_card_busy,
2118 };
2119
2120 /*****************************************************************************\
2121  *                                                                           *
2122  * Tasklets                                                                  *
2123  *                                                                           *
2124 \*****************************************************************************/
2125
2126 static void sdhci_tasklet_finish(unsigned long param)
2127 {
2128         struct sdhci_host *host;
2129         unsigned long flags;
2130         struct mmc_request *mrq;
2131
2132         host = (struct sdhci_host*)param;
2133
2134         spin_lock_irqsave(&host->lock, flags);
2135
2136         /*
2137          * If this tasklet gets rescheduled while running, it will
2138          * be run again afterwards but without any active request.
2139          */
2140         if (!host->mrq) {
2141                 spin_unlock_irqrestore(&host->lock, flags);
2142                 return;
2143         }
2144
2145         del_timer(&host->timer);
2146
2147         mrq = host->mrq;
2148
2149         /*
2150          * The controller needs a reset of internal state machines
2151          * upon error conditions.
2152          */
2153         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2154             ((mrq->cmd && mrq->cmd->error) ||
2155              (mrq->sbc && mrq->sbc->error) ||
2156              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2157                             (mrq->data->stop && mrq->data->stop->error))) ||
2158              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2159
2160                 /* Some controllers need this kick or reset won't work here */
2161                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2162                         /* This is to force an update */
2163                         host->ops->set_clock(host, host->clock);
2164
2165                 /* Spec says we should do both at the same time, but Ricoh
2166                    controllers do not like that. */
2167                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2168                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2169         }
2170
2171         host->mrq = NULL;
2172         host->cmd = NULL;
2173         host->data = NULL;
2174
2175 #ifndef SDHCI_USE_LEDS_CLASS
2176         sdhci_deactivate_led(host);
2177 #endif
2178
2179         mmiowb();
2180         spin_unlock_irqrestore(&host->lock, flags);
2181
2182         mmc_request_done(host->mmc, mrq);
2183         sdhci_runtime_pm_put(host);
2184 }
2185
2186 static void sdhci_timeout_timer(unsigned long data)
2187 {
2188         struct sdhci_host *host;
2189         unsigned long flags;
2190
2191         host = (struct sdhci_host*)data;
2192
2193         spin_lock_irqsave(&host->lock, flags);
2194
2195         if (host->mrq) {
2196                 pr_err("%s: Timeout waiting for hardware "
2197                         "interrupt.\n", mmc_hostname(host->mmc));
2198                 sdhci_dumpregs(host);
2199
2200                 if (host->data) {
2201                         host->data->error = -ETIMEDOUT;
2202                         sdhci_finish_data(host);
2203                 } else {
2204                         if (host->cmd)
2205                                 host->cmd->error = -ETIMEDOUT;
2206                         else
2207                                 host->mrq->cmd->error = -ETIMEDOUT;
2208
2209                         tasklet_schedule(&host->finish_tasklet);
2210                 }
2211         }
2212
2213         mmiowb();
2214         spin_unlock_irqrestore(&host->lock, flags);
2215 }
2216
2217 static void sdhci_tuning_timer(unsigned long data)
2218 {
2219         struct sdhci_host *host;
2220         unsigned long flags;
2221
2222         host = (struct sdhci_host *)data;
2223
2224         spin_lock_irqsave(&host->lock, flags);
2225
2226         host->flags |= SDHCI_NEEDS_RETUNING;
2227
2228         spin_unlock_irqrestore(&host->lock, flags);
2229 }
2230
2231 /*****************************************************************************\
2232  *                                                                           *
2233  * Interrupt handling                                                        *
2234  *                                                                           *
2235 \*****************************************************************************/
2236
2237 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2238 {
2239         BUG_ON(intmask == 0);
2240
2241         if (!host->cmd) {
2242                 pr_err("%s: Got command interrupt 0x%08x even "
2243                         "though no command operation was in progress.\n",
2244                         mmc_hostname(host->mmc), (unsigned)intmask);
2245                 sdhci_dumpregs(host);
2246                 return;
2247         }
2248
2249         if (intmask & SDHCI_INT_TIMEOUT)
2250                 host->cmd->error = -ETIMEDOUT;
2251         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2252                         SDHCI_INT_INDEX))
2253                 host->cmd->error = -EILSEQ;
2254
2255         if (host->cmd->error) {
2256                 tasklet_schedule(&host->finish_tasklet);
2257                 return;
2258         }
2259
2260         /*
2261          * The host can send and interrupt when the busy state has
2262          * ended, allowing us to wait without wasting CPU cycles.
2263          * Unfortunately this is overloaded on the "data complete"
2264          * interrupt, so we need to take some care when handling
2265          * it.
2266          *
2267          * Note: The 1.0 specification is a bit ambiguous about this
2268          *       feature so there might be some problems with older
2269          *       controllers.
2270          */
2271         if (host->cmd->flags & MMC_RSP_BUSY) {
2272                 if (host->cmd->data)
2273                         DBG("Cannot wait for busy signal when also "
2274                                 "doing a data transfer");
2275                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2276                                 && !host->busy_handle) {
2277                         /* Mark that command complete before busy is ended */
2278                         host->busy_handle = 1;
2279                         return;
2280                 }
2281
2282                 /* The controller does not support the end-of-busy IRQ,
2283                  * fall through and take the SDHCI_INT_RESPONSE */
2284         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2285                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2286                 *mask &= ~SDHCI_INT_DATA_END;
2287         }
2288
2289         if (intmask & SDHCI_INT_RESPONSE)
2290                 sdhci_finish_command(host);
2291 }
2292
2293 #ifdef CONFIG_MMC_DEBUG
2294 static void sdhci_show_adma_error(struct sdhci_host *host)
2295 {
2296         const char *name = mmc_hostname(host->mmc);
2297         u8 *desc = host->adma_desc;
2298         __le32 *dma;
2299         __le16 *len;
2300         u8 attr;
2301
2302         sdhci_dumpregs(host);
2303
2304         while (true) {
2305                 dma = (__le32 *)(desc + 4);
2306                 len = (__le16 *)(desc + 2);
2307                 attr = *desc;
2308
2309                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2310                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2311
2312                 desc += 8;
2313
2314                 if (attr & 2)
2315                         break;
2316         }
2317 }
2318 #else
2319 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2320 #endif
2321
2322 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2323 {
2324         u32 command;
2325         BUG_ON(intmask == 0);
2326
2327         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2328         if (intmask & SDHCI_INT_DATA_AVAIL) {
2329                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2330                 if (command == MMC_SEND_TUNING_BLOCK ||
2331                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2332                         host->tuning_done = 1;
2333                         wake_up(&host->buf_ready_int);
2334                         return;
2335                 }
2336         }
2337
2338         if (!host->data) {
2339                 /*
2340                  * The "data complete" interrupt is also used to
2341                  * indicate that a busy state has ended. See comment
2342                  * above in sdhci_cmd_irq().
2343                  */
2344                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2345                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2346                                 host->cmd->error = -ETIMEDOUT;
2347                                 tasklet_schedule(&host->finish_tasklet);
2348                                 return;
2349                         }
2350                         if (intmask & SDHCI_INT_DATA_END) {
2351                                 /*
2352                                  * Some cards handle busy-end interrupt
2353                                  * before the command completed, so make
2354                                  * sure we do things in the proper order.
2355                                  */
2356                                 if (host->busy_handle)
2357                                         sdhci_finish_command(host);
2358                                 else
2359                                         host->busy_handle = 1;
2360                                 return;
2361                         }
2362                 }
2363
2364                 pr_err("%s: Got data interrupt 0x%08x even "
2365                         "though no data operation was in progress.\n",
2366                         mmc_hostname(host->mmc), (unsigned)intmask);
2367                 sdhci_dumpregs(host);
2368
2369                 return;
2370         }
2371
2372         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2373                 host->data->error = -ETIMEDOUT;
2374         else if (intmask & SDHCI_INT_DATA_END_BIT)
2375                 host->data->error = -EILSEQ;
2376         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2377                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2378                         != MMC_BUS_TEST_R)
2379                 host->data->error = -EILSEQ;
2380         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2381                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2382                 sdhci_show_adma_error(host);
2383                 host->data->error = -EIO;
2384                 if (host->ops->adma_workaround)
2385                         host->ops->adma_workaround(host, intmask);
2386         }
2387
2388         if (host->data->error)
2389                 sdhci_finish_data(host);
2390         else {
2391                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2392                         sdhci_transfer_pio(host);
2393
2394                 /*
2395                  * We currently don't do anything fancy with DMA
2396                  * boundaries, but as we can't disable the feature
2397                  * we need to at least restart the transfer.
2398                  *
2399                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2400                  * should return a valid address to continue from, but as
2401                  * some controllers are faulty, don't trust them.
2402                  */
2403                 if (intmask & SDHCI_INT_DMA_END) {
2404                         u32 dmastart, dmanow;
2405                         dmastart = sg_dma_address(host->data->sg);
2406                         dmanow = dmastart + host->data->bytes_xfered;
2407                         /*
2408                          * Force update to the next DMA block boundary.
2409                          */
2410                         dmanow = (dmanow &
2411                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2412                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2413                         host->data->bytes_xfered = dmanow - dmastart;
2414                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2415                                 " next 0x%08x\n",
2416                                 mmc_hostname(host->mmc), dmastart,
2417                                 host->data->bytes_xfered, dmanow);
2418                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2419                 }
2420
2421                 if (intmask & SDHCI_INT_DATA_END) {
2422                         if (host->cmd) {
2423                                 /*
2424                                  * Data managed to finish before the
2425                                  * command completed. Make sure we do
2426                                  * things in the proper order.
2427                                  */
2428                                 host->data_early = 1;
2429                         } else {
2430                                 sdhci_finish_data(host);
2431                         }
2432                 }
2433         }
2434 }
2435
2436 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2437 {
2438         irqreturn_t result = IRQ_NONE;
2439         struct sdhci_host *host = dev_id;
2440         u32 intmask, mask, unexpected = 0;
2441         int max_loops = 16;
2442
2443         spin_lock(&host->lock);
2444
2445         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2446                 spin_unlock(&host->lock);
2447                 return IRQ_NONE;
2448         }
2449
2450         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2451         if (!intmask || intmask == 0xffffffff) {
2452                 result = IRQ_NONE;
2453                 goto out;
2454         }
2455
2456         do {
2457                 /* Clear selected interrupts. */
2458                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2459                                   SDHCI_INT_BUS_POWER);
2460                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2461
2462                 DBG("*** %s got interrupt: 0x%08x\n",
2463                         mmc_hostname(host->mmc), intmask);
2464
2465                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2466                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2467                                       SDHCI_CARD_PRESENT;
2468
2469                         /*
2470                          * There is a observation on i.mx esdhc.  INSERT
2471                          * bit will be immediately set again when it gets
2472                          * cleared, if a card is inserted.  We have to mask
2473                          * the irq to prevent interrupt storm which will
2474                          * freeze the system.  And the REMOVE gets the
2475                          * same situation.
2476                          *
2477                          * More testing are needed here to ensure it works
2478                          * for other platforms though.
2479                          */
2480                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2481                                        SDHCI_INT_CARD_REMOVE);
2482                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2483                                                SDHCI_INT_CARD_INSERT;
2484                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2485                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2486
2487                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2488                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2489
2490                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2491                                                        SDHCI_INT_CARD_REMOVE);
2492                         result = IRQ_WAKE_THREAD;
2493                 }
2494
2495                 if (intmask & SDHCI_INT_CMD_MASK)
2496                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2497                                       &intmask);
2498
2499                 if (intmask & SDHCI_INT_DATA_MASK)
2500                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2501
2502                 if (intmask & SDHCI_INT_BUS_POWER)
2503                         pr_err("%s: Card is consuming too much power!\n",
2504                                 mmc_hostname(host->mmc));
2505
2506                 if (intmask & SDHCI_INT_CARD_INT) {
2507                         sdhci_enable_sdio_irq_nolock(host, false);
2508                         host->thread_isr |= SDHCI_INT_CARD_INT;
2509                         result = IRQ_WAKE_THREAD;
2510                 }
2511
2512                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2513                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2514                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2515                              SDHCI_INT_CARD_INT);
2516
2517                 if (intmask) {
2518                         unexpected |= intmask;
2519                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2520                 }
2521
2522                 if (result == IRQ_NONE)
2523                         result = IRQ_HANDLED;
2524
2525                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2526         } while (intmask && --max_loops);
2527 out:
2528         spin_unlock(&host->lock);
2529
2530         if (unexpected) {
2531                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2532                            mmc_hostname(host->mmc), unexpected);
2533                 sdhci_dumpregs(host);
2534         }
2535
2536         return result;
2537 }
2538
2539 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2540 {
2541         struct sdhci_host *host = dev_id;
2542         unsigned long flags;
2543         u32 isr;
2544
2545         spin_lock_irqsave(&host->lock, flags);
2546         isr = host->thread_isr;
2547         host->thread_isr = 0;
2548         spin_unlock_irqrestore(&host->lock, flags);
2549
2550         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2551                 sdhci_card_event(host->mmc);
2552                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2553         }
2554
2555         if (isr & SDHCI_INT_CARD_INT) {
2556                 sdio_run_irqs(host->mmc);
2557
2558                 spin_lock_irqsave(&host->lock, flags);
2559                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2560                         sdhci_enable_sdio_irq_nolock(host, true);
2561                 spin_unlock_irqrestore(&host->lock, flags);
2562         }
2563
2564         return isr ? IRQ_HANDLED : IRQ_NONE;
2565 }
2566
2567 /*****************************************************************************\
2568  *                                                                           *
2569  * Suspend/resume                                                            *
2570  *                                                                           *
2571 \*****************************************************************************/
2572
2573 #ifdef CONFIG_PM
2574 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2575 {
2576         u8 val;
2577         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2578                         | SDHCI_WAKE_ON_INT;
2579
2580         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2581         val |= mask ;
2582         /* Avoid fake wake up */
2583         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2584                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2585         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2586 }
2587 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2588
2589 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2590 {
2591         u8 val;
2592         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2593                         | SDHCI_WAKE_ON_INT;
2594
2595         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2596         val &= ~mask;
2597         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2598 }
2599
2600 int sdhci_suspend_host(struct sdhci_host *host)
2601 {
2602         sdhci_disable_card_detection(host);
2603
2604         /* Disable tuning since we are suspending */
2605         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2606                 del_timer_sync(&host->tuning_timer);
2607                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2608         }
2609
2610         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2611                 host->ier = 0;
2612                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2613                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2614                 free_irq(host->irq, host);
2615         } else {
2616                 sdhci_enable_irq_wakeups(host);
2617                 enable_irq_wake(host->irq);
2618         }
2619         return 0;
2620 }
2621
2622 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2623
2624 int sdhci_resume_host(struct sdhci_host *host)
2625 {
2626         int ret = 0;
2627
2628         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2629                 if (host->ops->enable_dma)
2630                         host->ops->enable_dma(host);
2631         }
2632
2633         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2634                 ret = request_threaded_irq(host->irq, sdhci_irq,
2635                                            sdhci_thread_irq, IRQF_SHARED,
2636                                            mmc_hostname(host->mmc), host);
2637                 if (ret)
2638                         return ret;
2639         } else {
2640                 sdhci_disable_irq_wakeups(host);
2641                 disable_irq_wake(host->irq);
2642         }
2643
2644         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2645             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2646                 /* Card keeps power but host controller does not */
2647                 sdhci_init(host, 0);
2648                 host->pwr = 0;
2649                 host->clock = 0;
2650                 sdhci_do_set_ios(host, &host->mmc->ios);
2651         } else {
2652                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2653                 mmiowb();
2654         }
2655
2656         sdhci_enable_card_detection(host);
2657
2658         /* Set the re-tuning expiration flag */
2659         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2660                 host->flags |= SDHCI_NEEDS_RETUNING;
2661
2662         return ret;
2663 }
2664
2665 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2666 #endif /* CONFIG_PM */
2667
2668 #ifdef CONFIG_PM_RUNTIME
2669
2670 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2671 {
2672         return pm_runtime_get_sync(host->mmc->parent);
2673 }
2674
2675 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2676 {
2677         pm_runtime_mark_last_busy(host->mmc->parent);
2678         return pm_runtime_put_autosuspend(host->mmc->parent);
2679 }
2680
2681 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2682 {
2683         if (host->runtime_suspended || host->bus_on)
2684                 return;
2685         host->bus_on = true;
2686         pm_runtime_get_noresume(host->mmc->parent);
2687 }
2688
2689 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2690 {
2691         if (host->runtime_suspended || !host->bus_on)
2692                 return;
2693         host->bus_on = false;
2694         pm_runtime_put_noidle(host->mmc->parent);
2695 }
2696
2697 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2698 {
2699         unsigned long flags;
2700
2701         /* Disable tuning since we are suspending */
2702         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2703                 del_timer_sync(&host->tuning_timer);
2704                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2705         }
2706
2707         spin_lock_irqsave(&host->lock, flags);
2708         host->ier &= SDHCI_INT_CARD_INT;
2709         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2710         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2711         spin_unlock_irqrestore(&host->lock, flags);
2712
2713         synchronize_hardirq(host->irq);
2714
2715         spin_lock_irqsave(&host->lock, flags);
2716         host->runtime_suspended = true;
2717         spin_unlock_irqrestore(&host->lock, flags);
2718
2719         return 0;
2720 }
2721 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2722
2723 int sdhci_runtime_resume_host(struct sdhci_host *host)
2724 {
2725         unsigned long flags;
2726         int host_flags = host->flags;
2727
2728         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2729                 if (host->ops->enable_dma)
2730                         host->ops->enable_dma(host);
2731         }
2732
2733         sdhci_init(host, 0);
2734
2735         /* Force clock and power re-program */
2736         host->pwr = 0;
2737         host->clock = 0;
2738         sdhci_do_set_ios(host, &host->mmc->ios);
2739
2740         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2741         if ((host_flags & SDHCI_PV_ENABLED) &&
2742                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2743                 spin_lock_irqsave(&host->lock, flags);
2744                 sdhci_enable_preset_value(host, true);
2745                 spin_unlock_irqrestore(&host->lock, flags);
2746         }
2747
2748         /* Set the re-tuning expiration flag */
2749         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2750                 host->flags |= SDHCI_NEEDS_RETUNING;
2751
2752         spin_lock_irqsave(&host->lock, flags);
2753
2754         host->runtime_suspended = false;
2755
2756         /* Enable SDIO IRQ */
2757         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2758                 sdhci_enable_sdio_irq_nolock(host, true);
2759
2760         /* Enable Card Detection */
2761         sdhci_enable_card_detection(host);
2762
2763         spin_unlock_irqrestore(&host->lock, flags);
2764
2765         return 0;
2766 }
2767 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2768
2769 #endif
2770
2771 /*****************************************************************************\
2772  *                                                                           *
2773  * Device allocation/registration                                            *
2774  *                                                                           *
2775 \*****************************************************************************/
2776
2777 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2778         size_t priv_size)
2779 {
2780         struct mmc_host *mmc;
2781         struct sdhci_host *host;
2782
2783         WARN_ON(dev == NULL);
2784
2785         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2786         if (!mmc)
2787                 return ERR_PTR(-ENOMEM);
2788
2789         host = mmc_priv(mmc);
2790         host->mmc = mmc;
2791
2792         return host;
2793 }
2794
2795 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2796
2797 int sdhci_add_host(struct sdhci_host *host)
2798 {
2799         struct mmc_host *mmc;
2800         u32 caps[2] = {0, 0};
2801         u32 max_current_caps;
2802         unsigned int ocr_avail;
2803         unsigned int override_timeout_clk;
2804         int ret;
2805
2806         WARN_ON(host == NULL);
2807         if (host == NULL)
2808                 return -EINVAL;
2809
2810         mmc = host->mmc;
2811
2812         if (debug_quirks)
2813                 host->quirks = debug_quirks;
2814         if (debug_quirks2)
2815                 host->quirks2 = debug_quirks2;
2816
2817         override_timeout_clk = host->timeout_clk;
2818
2819         sdhci_do_reset(host, SDHCI_RESET_ALL);
2820
2821         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2822         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2823                                 >> SDHCI_SPEC_VER_SHIFT;
2824         if (host->version > SDHCI_SPEC_300) {
2825                 pr_err("%s: Unknown controller version (%d). "
2826                         "You may experience problems.\n", mmc_hostname(mmc),
2827                         host->version);
2828         }
2829
2830         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2831                 sdhci_readl(host, SDHCI_CAPABILITIES);
2832
2833         if (host->version >= SDHCI_SPEC_300)
2834                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2835                         host->caps1 :
2836                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2837
2838         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2839                 host->flags |= SDHCI_USE_SDMA;
2840         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2841                 DBG("Controller doesn't have SDMA capability\n");
2842         else
2843                 host->flags |= SDHCI_USE_SDMA;
2844
2845         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2846                 (host->flags & SDHCI_USE_SDMA)) {
2847                 DBG("Disabling DMA as it is marked broken\n");
2848                 host->flags &= ~SDHCI_USE_SDMA;
2849         }
2850
2851         if ((host->version >= SDHCI_SPEC_200) &&
2852                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2853                 host->flags |= SDHCI_USE_ADMA;
2854
2855         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2856                 (host->flags & SDHCI_USE_ADMA)) {
2857                 DBG("Disabling ADMA as it is marked broken\n");
2858                 host->flags &= ~SDHCI_USE_ADMA;
2859         }
2860
2861         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2862                 if (host->ops->enable_dma) {
2863                         if (host->ops->enable_dma(host)) {
2864                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2865                                         mmc_hostname(mmc));
2866                                 host->flags &=
2867                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2868                         }
2869                 }
2870         }
2871
2872         if (host->flags & SDHCI_USE_ADMA) {
2873                 /*
2874                  * We need to allocate descriptors for all sg entries
2875                  * (128) and potentially one alignment transfer for
2876                  * each of those entries.
2877                  */
2878                 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2879                                                      ADMA_SIZE, &host->adma_addr,
2880                                                      GFP_KERNEL);
2881                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2882                 if (!host->adma_desc || !host->align_buffer) {
2883                         dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2884                                           host->adma_desc, host->adma_addr);
2885                         kfree(host->align_buffer);
2886                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2887                                 mmc_hostname(mmc));
2888                         host->flags &= ~SDHCI_USE_ADMA;
2889                         host->adma_desc = NULL;
2890                         host->align_buffer = NULL;
2891                 } else if (host->adma_addr & 3) {
2892                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2893                                 mmc_hostname(mmc));
2894                         host->flags &= ~SDHCI_USE_ADMA;
2895                         dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2896                                           host->adma_desc, host->adma_addr);
2897                         kfree(host->align_buffer);
2898                         host->adma_desc = NULL;
2899                         host->align_buffer = NULL;
2900                 }
2901         }
2902
2903         /*
2904          * If we use DMA, then it's up to the caller to set the DMA
2905          * mask, but PIO does not need the hw shim so we set a new
2906          * mask here in that case.
2907          */
2908         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2909                 host->dma_mask = DMA_BIT_MASK(64);
2910                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2911         }
2912
2913         if (host->version >= SDHCI_SPEC_300)
2914                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2915                         >> SDHCI_CLOCK_BASE_SHIFT;
2916         else
2917                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2918                         >> SDHCI_CLOCK_BASE_SHIFT;
2919
2920         host->max_clk *= 1000000;
2921         if (host->max_clk == 0 || host->quirks &
2922                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2923                 if (!host->ops->get_max_clock) {
2924                         pr_err("%s: Hardware doesn't specify base clock "
2925                                "frequency.\n", mmc_hostname(mmc));
2926                         return -ENODEV;
2927                 }
2928                 host->max_clk = host->ops->get_max_clock(host);
2929         }
2930
2931         /*
2932          * In case of Host Controller v3.00, find out whether clock
2933          * multiplier is supported.
2934          */
2935         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2936                         SDHCI_CLOCK_MUL_SHIFT;
2937
2938         /*
2939          * In case the value in Clock Multiplier is 0, then programmable
2940          * clock mode is not supported, otherwise the actual clock
2941          * multiplier is one more than the value of Clock Multiplier
2942          * in the Capabilities Register.
2943          */
2944         if (host->clk_mul)
2945                 host->clk_mul += 1;
2946
2947         /*
2948          * Set host parameters.
2949          */
2950         mmc->ops = &sdhci_ops;
2951         mmc->f_max = host->max_clk;
2952         if (host->ops->get_min_clock)
2953                 mmc->f_min = host->ops->get_min_clock(host);
2954         else if (host->version >= SDHCI_SPEC_300) {
2955                 if (host->clk_mul) {
2956                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2957                         mmc->f_max = host->max_clk * host->clk_mul;
2958                 } else
2959                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2960         } else
2961                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2962
2963         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2964                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2965                                         SDHCI_TIMEOUT_CLK_SHIFT;
2966                 if (host->timeout_clk == 0) {
2967                         if (host->ops->get_timeout_clock) {
2968                                 host->timeout_clk =
2969                                         host->ops->get_timeout_clock(host);
2970                         } else {
2971                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2972                                         mmc_hostname(mmc));
2973                                 return -ENODEV;
2974                         }
2975                 }
2976
2977                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2978                         host->timeout_clk *= 1000;
2979
2980                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
2981                         host->ops->get_max_timeout_count(host) : 1 << 27;
2982                 mmc->max_busy_timeout /= host->timeout_clk;
2983         }
2984
2985         if (override_timeout_clk)
2986                 host->timeout_clk = override_timeout_clk;
2987
2988         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2989         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2990
2991         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2992                 host->flags |= SDHCI_AUTO_CMD12;
2993
2994         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2995         if ((host->version >= SDHCI_SPEC_300) &&
2996             ((host->flags & SDHCI_USE_ADMA) ||
2997              !(host->flags & SDHCI_USE_SDMA))) {
2998                 host->flags |= SDHCI_AUTO_CMD23;
2999                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3000         } else {
3001                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3002         }
3003
3004         /*
3005          * A controller may support 8-bit width, but the board itself
3006          * might not have the pins brought out.  Boards that support
3007          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3008          * their platform code before calling sdhci_add_host(), and we
3009          * won't assume 8-bit width for hosts without that CAP.
3010          */
3011         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3012                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3013
3014         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3015                 mmc->caps &= ~MMC_CAP_CMD23;
3016
3017         if (caps[0] & SDHCI_CAN_DO_HISPD)
3018                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3019
3020         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3021             !(mmc->caps & MMC_CAP_NONREMOVABLE))
3022                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3023
3024         /* If there are external regulators, get them */
3025         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3026                 return -EPROBE_DEFER;
3027
3028         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3029         if (!IS_ERR(mmc->supply.vqmmc)) {
3030                 ret = regulator_enable(mmc->supply.vqmmc);
3031                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3032                                                     1950000))
3033                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3034                                         SDHCI_SUPPORT_SDR50 |
3035                                         SDHCI_SUPPORT_DDR50);
3036                 if (ret) {
3037                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3038                                 mmc_hostname(mmc), ret);
3039                         mmc->supply.vqmmc = NULL;
3040                 }
3041         }
3042
3043         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3044                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3045                        SDHCI_SUPPORT_DDR50);
3046
3047         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3048         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3049                        SDHCI_SUPPORT_DDR50))
3050                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3051
3052         /* SDR104 supports also implies SDR50 support */
3053         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3054                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3055                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3056                  * field can be promoted to support HS200.
3057                  */
3058                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
3059                         mmc->caps2 |= MMC_CAP2_HS200;
3060                         if (IS_ERR(mmc->supply.vqmmc) ||
3061                                         !regulator_is_supported_voltage
3062                                         (mmc->supply.vqmmc, 1100000, 1300000))
3063                                 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3064                 }
3065         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3066                 mmc->caps |= MMC_CAP_UHS_SDR50;
3067
3068         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3069                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3070                 mmc->caps |= MMC_CAP_UHS_DDR50;
3071
3072         /* Does the host need tuning for SDR50? */
3073         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3074                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3075
3076         /* Does the host need tuning for SDR104 / HS200? */
3077         if (mmc->caps2 & MMC_CAP2_HS200)
3078                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3079
3080         /* Driver Type(s) (A, C, D) supported by the host */
3081         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3082                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3083         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3084                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3085         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3086                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3087
3088         /* Initial value for re-tuning timer count */
3089         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3090                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3091
3092         /*
3093          * In case Re-tuning Timer is not disabled, the actual value of
3094          * re-tuning timer will be 2 ^ (n - 1).
3095          */
3096         if (host->tuning_count)
3097                 host->tuning_count = 1 << (host->tuning_count - 1);
3098
3099         /* Re-tuning mode supported by the Host Controller */
3100         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3101                              SDHCI_RETUNING_MODE_SHIFT;
3102
3103         ocr_avail = 0;
3104
3105         /*
3106          * According to SD Host Controller spec v3.00, if the Host System
3107          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3108          * the value is meaningful only if Voltage Support in the Capabilities
3109          * register is set. The actual current value is 4 times the register
3110          * value.
3111          */
3112         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3113         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3114                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3115                 if (curr > 0) {
3116
3117                         /* convert to SDHCI_MAX_CURRENT format */
3118                         curr = curr/1000;  /* convert to mA */
3119                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3120
3121                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3122                         max_current_caps =
3123                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3124                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3125                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3126                 }
3127         }
3128
3129         if (caps[0] & SDHCI_CAN_VDD_330) {
3130                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3131
3132                 mmc->max_current_330 = ((max_current_caps &
3133                                    SDHCI_MAX_CURRENT_330_MASK) >>
3134                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3135                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3136         }
3137         if (caps[0] & SDHCI_CAN_VDD_300) {
3138                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3139
3140                 mmc->max_current_300 = ((max_current_caps &
3141                                    SDHCI_MAX_CURRENT_300_MASK) >>
3142                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3143                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3144         }
3145         if (caps[0] & SDHCI_CAN_VDD_180) {
3146                 ocr_avail |= MMC_VDD_165_195;
3147
3148                 mmc->max_current_180 = ((max_current_caps &
3149                                    SDHCI_MAX_CURRENT_180_MASK) >>
3150                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3151                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3152         }
3153
3154         /* If OCR set by external regulators, use it instead */
3155         if (mmc->ocr_avail)
3156                 ocr_avail = mmc->ocr_avail;
3157
3158         if (host->ocr_mask)
3159                 ocr_avail &= host->ocr_mask;
3160
3161         mmc->ocr_avail = ocr_avail;
3162         mmc->ocr_avail_sdio = ocr_avail;
3163         if (host->ocr_avail_sdio)
3164                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3165         mmc->ocr_avail_sd = ocr_avail;
3166         if (host->ocr_avail_sd)
3167                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3168         else /* normal SD controllers don't support 1.8V */
3169                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3170         mmc->ocr_avail_mmc = ocr_avail;
3171         if (host->ocr_avail_mmc)
3172                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3173
3174         if (mmc->ocr_avail == 0) {
3175                 pr_err("%s: Hardware doesn't report any "
3176                         "support voltages.\n", mmc_hostname(mmc));
3177                 return -ENODEV;
3178         }
3179
3180         spin_lock_init(&host->lock);
3181
3182         /*
3183          * Maximum number of segments. Depends on if the hardware
3184          * can do scatter/gather or not.
3185          */
3186         if (host->flags & SDHCI_USE_ADMA)
3187                 mmc->max_segs = 128;
3188         else if (host->flags & SDHCI_USE_SDMA)
3189                 mmc->max_segs = 1;
3190         else /* PIO */
3191                 mmc->max_segs = 128;
3192
3193         /*
3194          * Maximum number of sectors in one transfer. Limited by DMA boundary
3195          * size (512KiB).
3196          */
3197         mmc->max_req_size = 524288;
3198
3199         /*
3200          * Maximum segment size. Could be one segment with the maximum number
3201          * of bytes. When doing hardware scatter/gather, each entry cannot
3202          * be larger than 64 KiB though.
3203          */
3204         if (host->flags & SDHCI_USE_ADMA) {
3205                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3206                         mmc->max_seg_size = 65535;
3207                 else
3208                         mmc->max_seg_size = 65536;
3209         } else {
3210                 mmc->max_seg_size = mmc->max_req_size;
3211         }
3212
3213         /*
3214          * Maximum block size. This varies from controller to controller and
3215          * is specified in the capabilities register.
3216          */
3217         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3218                 mmc->max_blk_size = 2;
3219         } else {
3220                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3221                                 SDHCI_MAX_BLOCK_SHIFT;
3222                 if (mmc->max_blk_size >= 3) {
3223                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3224                                 mmc_hostname(mmc));
3225                         mmc->max_blk_size = 0;
3226                 }
3227         }
3228
3229         mmc->max_blk_size = 512 << mmc->max_blk_size;
3230
3231         /*
3232          * Maximum block count.
3233          */
3234         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3235
3236         /*
3237          * Init tasklets.
3238          */
3239         tasklet_init(&host->finish_tasklet,
3240                 sdhci_tasklet_finish, (unsigned long)host);
3241
3242         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3243
3244         if (host->version >= SDHCI_SPEC_300) {
3245                 init_waitqueue_head(&host->buf_ready_int);
3246
3247                 /* Initialize re-tuning timer */
3248                 init_timer(&host->tuning_timer);
3249                 host->tuning_timer.data = (unsigned long)host;
3250                 host->tuning_timer.function = sdhci_tuning_timer;
3251         }
3252
3253         sdhci_init(host, 0);
3254
3255         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3256                                    IRQF_SHARED, mmc_hostname(mmc), host);
3257         if (ret) {
3258                 pr_err("%s: Failed to request IRQ %d: %d\n",
3259                        mmc_hostname(mmc), host->irq, ret);
3260                 goto untasklet;
3261         }
3262
3263 #ifdef CONFIG_MMC_DEBUG
3264         sdhci_dumpregs(host);
3265 #endif
3266
3267 #ifdef SDHCI_USE_LEDS_CLASS
3268         snprintf(host->led_name, sizeof(host->led_name),
3269                 "%s::", mmc_hostname(mmc));
3270         host->led.name = host->led_name;
3271         host->led.brightness = LED_OFF;
3272         host->led.default_trigger = mmc_hostname(mmc);
3273         host->led.brightness_set = sdhci_led_control;
3274
3275         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3276         if (ret) {
3277                 pr_err("%s: Failed to register LED device: %d\n",
3278                        mmc_hostname(mmc), ret);
3279                 goto reset;
3280         }
3281 #endif
3282
3283         mmiowb();
3284
3285         mmc_add_host(mmc);
3286
3287         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3288                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3289                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3290                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3291
3292         sdhci_enable_card_detection(host);
3293
3294         return 0;
3295
3296 #ifdef SDHCI_USE_LEDS_CLASS
3297 reset:
3298         sdhci_do_reset(host, SDHCI_RESET_ALL);
3299         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3300         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3301         free_irq(host->irq, host);
3302 #endif
3303 untasklet:
3304         tasklet_kill(&host->finish_tasklet);
3305
3306         return ret;
3307 }
3308
3309 EXPORT_SYMBOL_GPL(sdhci_add_host);
3310
3311 void sdhci_remove_host(struct sdhci_host *host, int dead)
3312 {
3313         struct mmc_host *mmc = host->mmc;
3314         unsigned long flags;
3315
3316         if (dead) {
3317                 spin_lock_irqsave(&host->lock, flags);
3318
3319                 host->flags |= SDHCI_DEVICE_DEAD;
3320
3321                 if (host->mrq) {
3322                         pr_err("%s: Controller removed during "
3323                                 " transfer!\n", mmc_hostname(mmc));
3324
3325                         host->mrq->cmd->error = -ENOMEDIUM;
3326                         tasklet_schedule(&host->finish_tasklet);
3327                 }
3328
3329                 spin_unlock_irqrestore(&host->lock, flags);
3330         }
3331
3332         sdhci_disable_card_detection(host);
3333
3334         mmc_remove_host(mmc);
3335
3336 #ifdef SDHCI_USE_LEDS_CLASS
3337         led_classdev_unregister(&host->led);
3338 #endif
3339
3340         if (!dead)
3341                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3342
3343         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3344         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3345         free_irq(host->irq, host);
3346
3347         del_timer_sync(&host->timer);
3348
3349         tasklet_kill(&host->finish_tasklet);
3350
3351         if (!IS_ERR(mmc->supply.vqmmc))
3352                 regulator_disable(mmc->supply.vqmmc);
3353
3354         if (host->adma_desc)
3355                 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3356                                   host->adma_desc, host->adma_addr);
3357         kfree(host->align_buffer);
3358
3359         host->adma_desc = NULL;
3360         host->align_buffer = NULL;
3361 }
3362
3363 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3364
3365 void sdhci_free_host(struct sdhci_host *host)
3366 {
3367         mmc_free_host(host->mmc);
3368 }
3369
3370 EXPORT_SYMBOL_GPL(sdhci_free_host);
3371
3372 /*****************************************************************************\
3373  *                                                                           *
3374  * Driver init/exit                                                          *
3375  *                                                                           *
3376 \*****************************************************************************/
3377
3378 static int __init sdhci_drv_init(void)
3379 {
3380         pr_info(DRIVER_NAME
3381                 ": Secure Digital Host Controller Interface driver\n");
3382         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3383
3384         return 0;
3385 }
3386
3387 static void __exit sdhci_drv_exit(void)
3388 {
3389 }
3390
3391 module_init(sdhci_drv_init);
3392 module_exit(sdhci_drv_exit);
3393
3394 module_param(debug_quirks, uint, 0444);
3395 module_param(debug_quirks2, uint, 0444);
3396
3397 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3398 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3399 MODULE_LICENSE("GPL");
3400
3401 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3402 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");