drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 static unsigned int debug_quirks = 0;
  48 static unsigned int debug_quirks2;
  49
  50 static void sdhci_finish_data(struct sdhci_host *);
  51
  52 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_tuning_timer(unsigned long data);
  56
  57 #ifdef CONFIG_PM_RUNTIME
  58 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  59 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  60 #else
  61 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  62 {
  63         return 0;
  64 }
  65 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  66 {
  67         return 0;
  68 }
  69 #endif
  70
  71 static void sdhci_dumpregs(struct sdhci_host *host)
  72 {
  73         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  74                 mmc_hostname(host->mmc));
  75
  76         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  77                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  78                 sdhci_readw(host, SDHCI_HOST_VERSION));
  79         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  80                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  81                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  82         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  83                 sdhci_readl(host, SDHCI_ARGUMENT),
  84                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  85         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  86                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  87                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  88         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  89                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  90                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  91         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  92                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  93                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  94         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  95                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  96                 sdhci_readl(host, SDHCI_INT_STATUS));
  97         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  98                 sdhci_readl(host, SDHCI_INT_ENABLE),
  99                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 100         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 101                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 102                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 103         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 104                 sdhci_readl(host, SDHCI_CAPABILITIES),
 105                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 106         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 107                 sdhci_readw(host, SDHCI_COMMAND),
 108                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 109         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 110                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 111
 112         if (host->flags & SDHCI_USE_ADMA)
 113                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 114                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 115                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 116
 117         pr_debug(DRIVER_NAME ": ===========================================\n");
 118 }
 119
 120 /*****************************************************************************\
 121  *                                                                           *
 122  * Low level functions                                                       *
 123  *                                                                           *
 124 \*****************************************************************************/
 125
 126 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 127 {
 128         u32 ier;
 129
 130         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 131         ier &= ~clear;
 132         ier |= set;
 133         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 134         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 135 }
 136
 137 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 138 {
 139         sdhci_clear_set_irqs(host, 0, irqs);
 140 }
 141
 142 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 143 {
 144         sdhci_clear_set_irqs(host, irqs, 0);
 145 }
 146
 147 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 148 {
 149         u32 present, irqs;
 150
 151         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 152             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 153                 return;
 154
 155         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 156                               SDHCI_CARD_PRESENT;
 157         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 158
 159         if (enable)
 160                 sdhci_unmask_irqs(host, irqs);
 161         else
 162                 sdhci_mask_irqs(host, irqs);
 163 }
 164
 165 static void sdhci_enable_card_detection(struct sdhci_host *host)
 166 {
 167         sdhci_set_card_detection(host, true);
 168 }
 169
 170 static void sdhci_disable_card_detection(struct sdhci_host *host)
 171 {
 172         sdhci_set_card_detection(host, false);
 173 }
 174
 175 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 176 {
 177         unsigned long timeout;
 178         u32 uninitialized_var(ier);
 179
 180         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 181                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 182                         SDHCI_CARD_PRESENT))
 183                         return;
 184         }
 185
 186         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 187                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 188
 189         if (host->ops->platform_reset_enter)
 190                 host->ops->platform_reset_enter(host, mask);
 191
 192         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 193
 194         if (mask & SDHCI_RESET_ALL)
 195                 host->clock = 0;
 196
 197         /* Wait max 100 ms */
 198         timeout = 100;
 199
 200         /* hw clears the bit when it's done */
 201         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 202                 if (timeout == 0) {
 203                         pr_err("%s: Reset 0x%x never completed.\n",
 204                                 mmc_hostname(host->mmc), (int)mask);
 205                         sdhci_dumpregs(host);
 206                         return;
 207                 }
 208                 timeout--;
 209                 mdelay(1);
 210         }
 211
 212         if (host->ops->platform_reset_exit)
 213                 host->ops->platform_reset_exit(host, mask);
 214
 215         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 216                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 217
 218         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 219                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
 220                         host->ops->enable_dma(host);
 221         }
 222 }
 223
 224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 225
 226 static void sdhci_init(struct sdhci_host *host, int soft)
 227 {
 228         if (soft)
 229                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 230         else
 231                 sdhci_reset(host, SDHCI_RESET_ALL);
 232
 233         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 234                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 235                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 236                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 237                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 238
 239         if (soft) {
 240                 /* force clock reconfiguration */
 241                 host->clock = 0;
 242                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 243         }
 244 }
 245
 246 static void sdhci_reinit(struct sdhci_host *host)
 247 {
 248         sdhci_init(host, 0);
 249         /*
 250          * Retuning stuffs are affected by different cards inserted and only
 251          * applicable to UHS-I cards. So reset these fields to their initial
 252          * value when card is removed.
 253          */
 254         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 255                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 256
 257                 del_timer_sync(&host->tuning_timer);
 258                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 259                 host->mmc->max_blk_count =
 260                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 261         }
 262         sdhci_enable_card_detection(host);
 263 }
 264
 265 static void sdhci_activate_led(struct sdhci_host *host)
 266 {
 267         u8 ctrl;
 268
 269         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 270         ctrl |= SDHCI_CTRL_LED;
 271         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 272 }
 273
 274 static void sdhci_deactivate_led(struct sdhci_host *host)
 275 {
 276         u8 ctrl;
 277
 278         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 279         ctrl &= ~SDHCI_CTRL_LED;
 280         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 281 }
 282
 283 #ifdef SDHCI_USE_LEDS_CLASS
 284 static void sdhci_led_control(struct led_classdev *led,
 285         enum led_brightness brightness)
 286 {
 287         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 288         unsigned long flags;
 289
 290         spin_lock_irqsave(&host->lock, flags);
 291
 292         if (host->runtime_suspended)
 293                 goto out;
 294
 295         if (brightness == LED_OFF)
 296                 sdhci_deactivate_led(host);
 297         else
 298                 sdhci_activate_led(host);
 299 out:
 300         spin_unlock_irqrestore(&host->lock, flags);
 301 }
 302 #endif
 303
 304 /*****************************************************************************\
 305  *                                                                           *
 306  * Core functions                                                            *
 307  *                                                                           *
 308 \*****************************************************************************/
 309
 310 static void sdhci_read_block_pio(struct sdhci_host *host)
 311 {
 312         unsigned long flags;
 313         size_t blksize, len, chunk;
 314         u32 uninitialized_var(scratch);
 315         u8 *buf;
 316
 317         DBG("PIO reading\n");
 318
 319         blksize = host->data->blksz;
 320         chunk = 0;
 321
 322         local_irq_save(flags);
 323
 324         while (blksize) {
 325                 if (!sg_miter_next(&host->sg_miter))
 326                         BUG();
 327
 328                 len = min(host->sg_miter.length, blksize);
 329
 330                 blksize -= len;
 331                 host->sg_miter.consumed = len;
 332
 333                 buf = host->sg_miter.addr;
 334
 335                 while (len) {
 336                         if (chunk == 0) {
 337                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 338                                 chunk = 4;
 339                         }
 340
 341                         *buf = scratch & 0xFF;
 342
 343                         buf++;
 344                         scratch >>= 8;
 345                         chunk--;
 346                         len--;
 347                 }
 348         }
 349
 350         sg_miter_stop(&host->sg_miter);
 351
 352         local_irq_restore(flags);
 353 }
 354
 355 static void sdhci_write_block_pio(struct sdhci_host *host)
 356 {
 357         unsigned long flags;
 358         size_t blksize, len, chunk;
 359         u32 scratch;
 360         u8 *buf;
 361
 362         DBG("PIO writing\n");
 363
 364         blksize = host->data->blksz;
 365         chunk = 0;
 366         scratch = 0;
 367
 368         local_irq_save(flags);
 369
 370         while (blksize) {
 371                 if (!sg_miter_next(&host->sg_miter))
 372                         BUG();
 373
 374                 len = min(host->sg_miter.length, blksize);
 375
 376                 blksize -= len;
 377                 host->sg_miter.consumed = len;
 378
 379                 buf = host->sg_miter.addr;
 380
 381                 while (len) {
 382                         scratch |= (u32)*buf << (chunk * 8);
 383
 384                         buf++;
 385                         chunk++;
 386                         len--;
 387
 388                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 389                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 390                                 chunk = 0;
 391                                 scratch = 0;
 392                         }
 393                 }
 394         }
 395
 396         sg_miter_stop(&host->sg_miter);
 397
 398         local_irq_restore(flags);
 399 }
 400
 401 static void sdhci_transfer_pio(struct sdhci_host *host)
 402 {
 403         u32 mask;
 404
 405         BUG_ON(!host->data);
 406
 407         if (host->blocks == 0)
 408                 return;
 409
 410         if (host->data->flags & MMC_DATA_READ)
 411                 mask = SDHCI_DATA_AVAILABLE;
 412         else
 413                 mask = SDHCI_SPACE_AVAILABLE;
 414
 415         /*
 416          * Some controllers (JMicron JMB38x) mess up the buffer bits
 417          * for transfers < 4 bytes. As long as it is just one block,
 418          * we can ignore the bits.
 419          */
 420         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 421                 (host->data->blocks == 1))
 422                 mask = ~0;
 423
 424         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 425                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 426                         udelay(100);
 427
 428                 if (host->data->flags & MMC_DATA_READ)
 429                         sdhci_read_block_pio(host);
 430                 else
 431                         sdhci_write_block_pio(host);
 432
 433                 host->blocks--;
 434                 if (host->blocks == 0)
 435                         break;
 436         }
 437
 438         DBG("PIO transfer complete.\n");
 439 }
 440
 441 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 442 {
 443         local_irq_save(*flags);
 444         return kmap_atomic(sg_page(sg)) + sg->offset;
 445 }
 446
 447 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 448 {
 449         kunmap_atomic(buffer);
 450         local_irq_restore(*flags);
 451 }
 452
 453 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 454 {
 455         __le32 *dataddr = (__le32 __force *)(desc + 4);
 456         __le16 *cmdlen = (__le16 __force *)desc;
 457
 458         /* SDHCI specification says ADMA descriptors should be 4 byte
 459          * aligned, so using 16 or 32bit operations should be safe. */
 460
 461         cmdlen[0] = cpu_to_le16(cmd);
 462         cmdlen[1] = cpu_to_le16(len);
 463
 464         dataddr[0] = cpu_to_le32(addr);
 465 }
 466
 467 static int sdhci_adma_table_pre(struct sdhci_host *host,
 468         struct mmc_data *data)
 469 {
 470         int direction;
 471
 472         u8 *desc;
 473         u8 *align;
 474         dma_addr_t addr;
 475         dma_addr_t align_addr;
 476         int len, offset;
 477
 478         struct scatterlist *sg;
 479         int i;
 480         char *buffer;
 481         unsigned long flags;
 482
 483         /*
 484          * The spec does not specify endianness of descriptor table.
 485          * We currently guess that it is LE.
 486          */
 487
 488         if (data->flags & MMC_DATA_READ)
 489                 direction = DMA_FROM_DEVICE;
 490         else
 491                 direction = DMA_TO_DEVICE;
 492
 493         /*
 494          * The ADMA descriptor table is mapped further down as we
 495          * need to fill it with data first.
 496          */
 497
 498         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 499                 host->align_buffer, 128 * 4, direction);
 500         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 501                 goto fail;
 502         BUG_ON(host->align_addr & 0x3);
 503
 504         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 505                 data->sg, data->sg_len, direction);
 506         if (host->sg_count == 0)
 507                 goto unmap_align;
 508
 509         desc = host->adma_desc;
 510         align = host->align_buffer;
 511
 512         align_addr = host->align_addr;
 513
 514         for_each_sg(data->sg, sg, host->sg_count, i) {
 515                 addr = sg_dma_address(sg);
 516                 len = sg_dma_len(sg);
 517
 518                 /*
 519                  * The SDHCI specification states that ADMA
 520                  * addresses must be 32-bit aligned. If they
 521                  * aren't, then we use a bounce buffer for
 522                  * the (up to three) bytes that screw up the
 523                  * alignment.
 524                  */
 525                 offset = (4 - (addr & 0x3)) & 0x3;
 526                 if (offset) {
 527                         if (data->flags & MMC_DATA_WRITE) {
 528                                 buffer = sdhci_kmap_atomic(sg, &flags);
 529                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 530                                 memcpy(align, buffer, offset);
 531                                 sdhci_kunmap_atomic(buffer, &flags);
 532                         }
 533
 534                         /* tran, valid */
 535                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 536
 537                         BUG_ON(offset > 65536);
 538
 539                         align += 4;
 540                         align_addr += 4;
 541
 542                         desc += 8;
 543
 544                         addr += offset;
 545                         len -= offset;
 546                 }
 547
 548                 BUG_ON(len > 65536);
 549
 550                 /* tran, valid */
 551                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 552                 desc += 8;
 553
 554                 /*
 555                  * If this triggers then we have a calculation bug
 556                  * somewhere. :/
 557                  */
 558                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 559         }
 560
 561         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 562                 /*
 563                 * Mark the last descriptor as the terminating descriptor
 564                 */
 565                 if (desc != host->adma_desc) {
 566                         desc -= 8;
 567                         desc[0] |= 0x2; /* end */
 568                 }
 569         } else {
 570                 /*
 571                 * Add a terminating entry.
 572                 */
 573
 574                 /* nop, end, valid */
 575                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 576         }
 577
 578         /*
 579          * Resync align buffer as we might have changed it.
 580          */
 581         if (data->flags & MMC_DATA_WRITE) {
 582                 dma_sync_single_for_device(mmc_dev(host->mmc),
 583                         host->align_addr, 128 * 4, direction);
 584         }
 585
 586         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 587                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 588         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 589                 goto unmap_entries;
 590         BUG_ON(host->adma_addr & 0x3);
 591
 592         return 0;
 593
 594 unmap_entries:
 595         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 596                 data->sg_len, direction);
 597 unmap_align:
 598         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 599                 128 * 4, direction);
 600 fail:
 601         return -EINVAL;
 602 }
 603
 604 static void sdhci_adma_table_post(struct sdhci_host *host,
 605         struct mmc_data *data)
 606 {
 607         int direction;
 608
 609         struct scatterlist *sg;
 610         int i, size;
 611         u8 *align;
 612         char *buffer;
 613         unsigned long flags;
 614
 615         if (data->flags & MMC_DATA_READ)
 616                 direction = DMA_FROM_DEVICE;
 617         else
 618                 direction = DMA_TO_DEVICE;
 619
 620         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 621                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 622
 623         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 624                 128 * 4, direction);
 625
 626         if (data->flags & MMC_DATA_READ) {
 627                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 628                         data->sg_len, direction);
 629
 630                 align = host->align_buffer;
 631
 632                 for_each_sg(data->sg, sg, host->sg_count, i) {
 633                         if (sg_dma_address(sg) & 0x3) {
 634                                 size = 4 - (sg_dma_address(sg) & 0x3);
 635
 636                                 buffer = sdhci_kmap_atomic(sg, &flags);
 637                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 638                                 memcpy(buffer, align, size);
 639                                 sdhci_kunmap_atomic(buffer, &flags);
 640
 641                                 align += 4;
 642                         }
 643                 }
 644         }
 645
 646         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 647                 data->sg_len, direction);
 648 }
 649
 650 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 651 {
 652         u8 count;
 653         struct mmc_data *data = cmd->data;
 654         unsigned target_timeout, current_timeout;
 655
 656         /*
 657          * If the host controller provides us with an incorrect timeout
 658          * value, just skip the check and use 0xE.  The hardware may take
 659          * longer to time out, but that's much better than having a too-short
 660          * timeout value.
 661          */
 662         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 663                 return 0xE;
 664
 665         /* Unspecified timeout, assume max */
 666         if (!data && !cmd->cmd_timeout_ms)
 667                 return 0xE;
 668
 669         /* timeout in us */
 670         if (!data)
 671                 target_timeout = cmd->cmd_timeout_ms * 1000;
 672         else {
 673                 target_timeout = data->timeout_ns / 1000;
 674                 if (host->clock)
 675                         target_timeout += data->timeout_clks / host->clock;
 676         }
 677
 678         /*
 679          * Figure out needed cycles.
 680          * We do this in steps in order to fit inside a 32 bit int.
 681          * The first step is the minimum timeout, which will have a
 682          * minimum resolution of 6 bits:
 683          * (1) 2^13*1000 > 2^22,
 684          * (2) host->timeout_clk < 2^16
 685          *     =>
 686          *     (1) / (2) > 2^6
 687          */
 688         count = 0;
 689         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 690         while (current_timeout < target_timeout) {
 691                 count++;
 692                 current_timeout <<= 1;
 693                 if (count >= 0xF)
 694                         break;
 695         }
 696
 697         if (count >= 0xF) {
 698                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 699                     mmc_hostname(host->mmc), count, cmd->opcode);
 700                 count = 0xE;
 701         }
 702
 703         return count;
 704 }
 705
 706 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 707 {
 708         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 709         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 710
 711         if (host->flags & SDHCI_REQ_USE_DMA)
 712                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 713         else
 714                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 715 }
 716
 717 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 718 {
 719         u8 count;
 720         u8 ctrl;
 721         struct mmc_data *data = cmd->data;
 722         int ret;
 723
 724         WARN_ON(host->data);
 725
 726         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 727                 count = sdhci_calc_timeout(host, cmd);
 728                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 729         }
 730
 731         if (!data)
 732                 return;
 733
 734         /* Sanity checks */
 735         BUG_ON(data->blksz * data->blocks > 524288);
 736         BUG_ON(data->blksz > host->mmc->max_blk_size);
 737         BUG_ON(data->blocks > 65535);
 738
 739         host->data = data;
 740         host->data_early = 0;
 741         host->data->bytes_xfered = 0;
 742
 743         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 744                 host->flags |= SDHCI_REQ_USE_DMA;
 745
 746         /*
 747          * FIXME: This doesn't account for merging when mapping the
 748          * scatterlist.
 749          */
 750         if (host->flags & SDHCI_REQ_USE_DMA) {
 751                 int broken, i;
 752                 struct scatterlist *sg;
 753
 754                 broken = 0;
 755                 if (host->flags & SDHCI_USE_ADMA) {
 756                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 757                                 broken = 1;
 758                 } else {
 759                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 760                                 broken = 1;
 761                 }
 762
 763                 if (unlikely(broken)) {
 764                         for_each_sg(data->sg, sg, data->sg_len, i) {
 765                                 if (sg->length & 0x3) {
 766                                         DBG("Reverting to PIO because of "
 767                                                 "transfer size (%d)\n",
 768                                                 sg->length);
 769                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 770                                         break;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         /*
 777          * The assumption here being that alignment is the same after
 778          * translation to device address space.
 779          */
 780         if (host->flags & SDHCI_REQ_USE_DMA) {
 781                 int broken, i;
 782                 struct scatterlist *sg;
 783
 784                 broken = 0;
 785                 if (host->flags & SDHCI_USE_ADMA) {
 786                         /*
 787                          * As we use 3 byte chunks to work around
 788                          * alignment problems, we need to check this
 789                          * quirk.
 790                          */
 791                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 792                                 broken = 1;
 793                 } else {
 794                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 795                                 broken = 1;
 796                 }
 797
 798                 if (unlikely(broken)) {
 799                         for_each_sg(data->sg, sg, data->sg_len, i) {
 800                                 if (sg->offset & 0x3) {
 801                                         DBG("Reverting to PIO because of "
 802                                                 "bad alignment\n");
 803                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 804                                         break;
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         if (host->flags & SDHCI_REQ_USE_DMA) {
 811                 if (host->flags & SDHCI_USE_ADMA) {
 812                         ret = sdhci_adma_table_pre(host, data);
 813                         if (ret) {
 814                                 /*
 815                                  * This only happens when someone fed
 816                                  * us an invalid request.
 817                                  */
 818                                 WARN_ON(1);
 819                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 820                         } else {
 821                                 sdhci_writel(host, host->adma_addr,
 822                                         SDHCI_ADMA_ADDRESS);
 823                         }
 824                 } else {
 825                         int sg_cnt;
 826
 827                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 828                                         data->sg, data->sg_len,
 829                                         (data->flags & MMC_DATA_READ) ?
 830                                                 DMA_FROM_DEVICE :
 831                                                 DMA_TO_DEVICE);
 832                         if (sg_cnt == 0) {
 833                                 /*
 834                                  * This only happens when someone fed
 835                                  * us an invalid request.
 836                                  */
 837                                 WARN_ON(1);
 838                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 839                         } else {
 840                                 WARN_ON(sg_cnt != 1);
 841                                 sdhci_writel(host, sg_dma_address(data->sg),
 842                                         SDHCI_DMA_ADDRESS);
 843                         }
 844                 }
 845         }
 846
 847         /*
 848          * Always adjust the DMA selection as some controllers
 849          * (e.g. JMicron) can't do PIO properly when the selection
 850          * is ADMA.
 851          */
 852         if (host->version >= SDHCI_SPEC_200) {
 853                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 854                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 855                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 856                         (host->flags & SDHCI_USE_ADMA))
 857                         ctrl |= SDHCI_CTRL_ADMA32;
 858                 else
 859                         ctrl |= SDHCI_CTRL_SDMA;
 860                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 861         }
 862
 863         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 864                 int flags;
 865
 866                 flags = SG_MITER_ATOMIC;
 867                 if (host->data->flags & MMC_DATA_READ)
 868                         flags |= SG_MITER_TO_SG;
 869                 else
 870                         flags |= SG_MITER_FROM_SG;
 871                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 872                 host->blocks = data->blocks;
 873         }
 874
 875         sdhci_set_transfer_irqs(host);
 876
 877         /* Set the DMA boundary value and block size */
 878         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 879                 data->blksz), SDHCI_BLOCK_SIZE);
 880         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 881 }
 882
 883 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 884         struct mmc_command *cmd)
 885 {
 886         u16 mode;
 887         struct mmc_data *data = cmd->data;
 888
 889         if (data == NULL)
 890                 return;
 891
 892         WARN_ON(!host->data);
 893
 894         mode = SDHCI_TRNS_BLK_CNT_EN;
 895         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 896                 mode |= SDHCI_TRNS_MULTI;
 897                 /*
 898                  * If we are sending CMD23, CMD12 never gets sent
 899                  * on successful completion (so no Auto-CMD12).
 900                  */
 901                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 902                         mode |= SDHCI_TRNS_AUTO_CMD12;
 903                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 904                         mode |= SDHCI_TRNS_AUTO_CMD23;
 905                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 906                 }
 907         }
 908
 909         if (data->flags & MMC_DATA_READ)
 910                 mode |= SDHCI_TRNS_READ;
 911         if (host->flags & SDHCI_REQ_USE_DMA)
 912                 mode |= SDHCI_TRNS_DMA;
 913
 914         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 915 }
 916
 917 static void sdhci_finish_data(struct sdhci_host *host)
 918 {
 919         struct mmc_data *data;
 920
 921         BUG_ON(!host->data);
 922
 923         data = host->data;
 924         host->data = NULL;
 925
 926         if (host->flags & SDHCI_REQ_USE_DMA) {
 927                 if (host->flags & SDHCI_USE_ADMA)
 928                         sdhci_adma_table_post(host, data);
 929                 else {
 930                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 931                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 932                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 933                 }
 934         }
 935
 936         /*
 937          * The specification states that the block count register must
 938          * be updated, but it does not specify at what point in the
 939          * data flow. That makes the register entirely useless to read
 940          * back so we have to assume that nothing made it to the card
 941          * in the event of an error.
 942          */
 943         if (data->error)
 944                 data->bytes_xfered = 0;
 945         else
 946                 data->bytes_xfered = data->blksz * data->blocks;
 947
 948         /*
 949          * Need to send CMD12 if -
 950          * a) open-ended multiblock transfer (no CMD23)
 951          * b) error in multiblock transfer
 952          */
 953         if (data->stop &&
 954             (data->error ||
 955              !host->mrq->sbc)) {
 956
 957                 /*
 958                  * The controller needs a reset of internal state machines
 959                  * upon error conditions.
 960                  */
 961                 if (data->error) {
 962                         sdhci_reset(host, SDHCI_RESET_CMD);
 963                         sdhci_reset(host, SDHCI_RESET_DATA);
 964                 }
 965
 966                 sdhci_send_command(host, data->stop);
 967         } else
 968                 tasklet_schedule(&host->finish_tasklet);
 969 }
 970
 971 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 972 {
 973         int flags;
 974         u32 mask;
 975         unsigned long timeout;
 976
 977         WARN_ON(host->cmd);
 978
 979         /* Wait max 10 ms */
 980         timeout = 10;
 981
 982         mask = SDHCI_CMD_INHIBIT;
 983         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 984                 mask |= SDHCI_DATA_INHIBIT;
 985
 986         /* We shouldn't wait for data inihibit for stop commands, even
 987            though they might use busy signaling */
 988         if (host->mrq->data && (cmd == host->mrq->data->stop))
 989                 mask &= ~SDHCI_DATA_INHIBIT;
 990
 991         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 992                 if (timeout == 0) {
 993                         pr_err("%s: Controller never released "
 994                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 995                         sdhci_dumpregs(host);
 996                         cmd->error = -EIO;
 997                         tasklet_schedule(&host->finish_tasklet);
 998                         return;
 999                 }
1000                 timeout--;
1001                 mdelay(1);
1002         }
1003
1004         mod_timer(&host->timer, jiffies + 10 * HZ);
1005
1006         host->cmd = cmd;
1007
1008         sdhci_prepare_data(host, cmd);
1009
1010         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1011
1012         sdhci_set_transfer_mode(host, cmd);
1013
1014         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1015                 pr_err("%s: Unsupported response type!\n",
1016                         mmc_hostname(host->mmc));
1017                 cmd->error = -EINVAL;
1018                 tasklet_schedule(&host->finish_tasklet);
1019                 return;
1020         }
1021
1022         if (!(cmd->flags & MMC_RSP_PRESENT))
1023                 flags = SDHCI_CMD_RESP_NONE;
1024         else if (cmd->flags & MMC_RSP_136)
1025                 flags = SDHCI_CMD_RESP_LONG;
1026         else if (cmd->flags & MMC_RSP_BUSY)
1027                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1028         else
1029                 flags = SDHCI_CMD_RESP_SHORT;
1030
1031         if (cmd->flags & MMC_RSP_CRC)
1032                 flags |= SDHCI_CMD_CRC;
1033         if (cmd->flags & MMC_RSP_OPCODE)
1034                 flags |= SDHCI_CMD_INDEX;
1035
1036         /* CMD19 is special in that the Data Present Select should be set */
1037         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1038             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1039                 flags |= SDHCI_CMD_DATA;
1040
1041         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1042 }
1043
1044 static void sdhci_finish_command(struct sdhci_host *host)
1045 {
1046         int i;
1047
1048         BUG_ON(host->cmd == NULL);
1049
1050         if (host->cmd->flags & MMC_RSP_PRESENT) {
1051                 if (host->cmd->flags & MMC_RSP_136) {
1052                         /* CRC is stripped so we need to do some shifting. */
1053                         for (i = 0;i < 4;i++) {
1054                                 host->cmd->resp[i] = sdhci_readl(host,
1055                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1056                                 if (i != 3)
1057                                         host->cmd->resp[i] |=
1058                                                 sdhci_readb(host,
1059                                                 SDHCI_RESPONSE + (3-i)*4-1);
1060                         }
1061                 } else {
1062                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1063                 }
1064         }
1065
1066         host->cmd->error = 0;
1067
1068         /* Finished CMD23, now send actual command. */
1069         if (host->cmd == host->mrq->sbc) {
1070                 host->cmd = NULL;
1071                 sdhci_send_command(host, host->mrq->cmd);
1072         } else {
1073
1074                 /* Processed actual command. */
1075                 if (host->data && host->data_early)
1076                         sdhci_finish_data(host);
1077
1078                 if (!host->cmd->data)
1079                         tasklet_schedule(&host->finish_tasklet);
1080
1081                 host->cmd = NULL;
1082         }
1083 }
1084
1085 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1086 {
1087         int div = 0; /* Initialized for compiler warning */
1088         int real_div = div, clk_mul = 1;
1089         u16 clk = 0;
1090         unsigned long timeout;
1091
1092         if (clock && clock == host->clock)
1093                 return;
1094
1095         host->mmc->actual_clock = 0;
1096
1097         if (host->ops->set_clock) {
1098                 host->ops->set_clock(host, clock);
1099                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1100                         return;
1101         }
1102
1103         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1104
1105         if (clock == 0)
1106                 goto out;
1107
1108         if (host->version >= SDHCI_SPEC_300) {
1109                 /*
1110                  * Check if the Host Controller supports Programmable Clock
1111                  * Mode.
1112                  */
1113                 if (host->clk_mul) {
1114                         u16 ctrl;
1115
1116                         /*
1117                          * We need to figure out whether the Host Driver needs
1118                          * to select Programmable Clock Mode, or the value can
1119                          * be set automatically by the Host Controller based on
1120                          * the Preset Value registers.
1121                          */
1122                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1123                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1124                                 for (div = 1; div <= 1024; div++) {
1125                                         if (((host->max_clk * host->clk_mul) /
1126                                               div) <= clock)
1127                                                 break;
1128                                 }
1129                                 /*
1130                                  * Set Programmable Clock Mode in the Clock
1131                                  * Control register.
1132                                  */
1133                                 clk = SDHCI_PROG_CLOCK_MODE;
1134                                 real_div = div;
1135                                 clk_mul = host->clk_mul;
1136                                 div--;
1137                         }
1138                 } else {
1139                         /* Version 3.00 divisors must be a multiple of 2. */
1140                         if (host->max_clk <= clock)
1141                                 div = 1;
1142                         else {
1143                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1144                                      div += 2) {
1145                                         if ((host->max_clk / div) <= clock)
1146                                                 break;
1147                                 }
1148                         }
1149                         real_div = div;
1150                         div >>= 1;
1151                 }
1152         } else {
1153                 /* Version 2.00 divisors must be a power of 2. */
1154                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1155                         if ((host->max_clk / div) <= clock)
1156                                 break;
1157                 }
1158                 real_div = div;
1159                 div >>= 1;
1160         }
1161
1162         if (real_div)
1163                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1164
1165         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1166         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1167                 << SDHCI_DIVIDER_HI_SHIFT;
1168         clk |= SDHCI_CLOCK_INT_EN;
1169         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1170
1171         /* Wait max 20 ms */
1172         timeout = 20;
1173         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1174                 & SDHCI_CLOCK_INT_STABLE)) {
1175                 if (timeout == 0) {
1176                         pr_err("%s: Internal clock never "
1177                                 "stabilised.\n", mmc_hostname(host->mmc));
1178                         sdhci_dumpregs(host);
1179                         return;
1180                 }
1181                 timeout--;
1182                 mdelay(1);
1183         }
1184
1185         clk |= SDHCI_CLOCK_CARD_EN;
1186         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1187
1188 out:
1189         host->clock = clock;
1190 }
1191
1192 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1193 {
1194         u8 pwr = 0;
1195
1196         if (power != (unsigned short)-1) {
1197                 switch (1 << power) {
1198                 case MMC_VDD_165_195:
1199                         pwr = SDHCI_POWER_180;
1200                         break;
1201                 case MMC_VDD_29_30:
1202                 case MMC_VDD_30_31:
1203                         pwr = SDHCI_POWER_300;
1204                         break;
1205                 case MMC_VDD_32_33:
1206                 case MMC_VDD_33_34:
1207                         pwr = SDHCI_POWER_330;
1208                         break;
1209                 default:
1210                         BUG();
1211                 }
1212         }
1213
1214         if (host->pwr == pwr)
1215                 return -1;
1216
1217         host->pwr = pwr;
1218
1219         if (pwr == 0) {
1220                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1221                 return 0;
1222         }
1223
1224         /*
1225          * Spec says that we should clear the power reg before setting
1226          * a new value. Some controllers don't seem to like this though.
1227          */
1228         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1229                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1230
1231         /*
1232          * At least the Marvell CaFe chip gets confused if we set the voltage
1233          * and set turn on power at the same time, so set the voltage first.
1234          */
1235         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1236                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1237
1238         pwr |= SDHCI_POWER_ON;
1239
1240         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1241
1242         /*
1243          * Some controllers need an extra 10ms delay of 10ms before they
1244          * can apply clock after applying power
1245          */
1246         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1247                 mdelay(10);
1248
1249         return power;
1250 }
1251
1252 /*****************************************************************************\
1253  *                                                                           *
1254  * MMC callbacks                                                             *
1255  *                                                                           *
1256 \*****************************************************************************/
1257
1258 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1259 {
1260         struct sdhci_host *host;
1261         bool present;
1262         unsigned long flags;
1263         u32 tuning_opcode;
1264
1265         host = mmc_priv(mmc);
1266
1267         sdhci_runtime_pm_get(host);
1268
1269         spin_lock_irqsave(&host->lock, flags);
1270
1271         WARN_ON(host->mrq != NULL);
1272
1273 #ifndef SDHCI_USE_LEDS_CLASS
1274         sdhci_activate_led(host);
1275 #endif
1276
1277         /*
1278          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1279          * requests if Auto-CMD12 is enabled.
1280          */
1281         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1282                 if (mrq->stop) {
1283                         mrq->data->stop = NULL;
1284                         mrq->stop = NULL;
1285                 }
1286         }
1287
1288         host->mrq = mrq;
1289
1290         /* If polling, assume that the card is always present. */
1291         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1292                 present = true;
1293         else
1294                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1295                                 SDHCI_CARD_PRESENT;
1296
1297         /* If we're using a cd-gpio, testing the presence bit might fail. */
1298         if (!present) {
1299                 int ret = mmc_gpio_get_cd(host->mmc);
1300                 if (ret > 0)
1301                         present = true;
1302         }
1303
1304         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1305                 host->mrq->cmd->error = -ENOMEDIUM;
1306                 tasklet_schedule(&host->finish_tasklet);
1307         } else {
1308                 u32 present_state;
1309
1310                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1311                 /*
1312                  * Check if the re-tuning timer has already expired and there
1313                  * is no on-going data transfer. If so, we need to execute
1314                  * tuning procedure before sending command.
1315                  */
1316                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1317                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1318                         /* eMMC uses cmd21 while sd and sdio use cmd19 */
1319                         tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1320                                 MMC_SEND_TUNING_BLOCK_HS200 :
1321                                 MMC_SEND_TUNING_BLOCK;
1322                         spin_unlock_irqrestore(&host->lock, flags);
1323                         sdhci_execute_tuning(mmc, tuning_opcode);
1324                         spin_lock_irqsave(&host->lock, flags);
1325
1326                         /* Restore original mmc_request structure */
1327                         host->mrq = mrq;
1328                 }
1329
1330                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1331                         sdhci_send_command(host, mrq->sbc);
1332                 else
1333                         sdhci_send_command(host, mrq->cmd);
1334         }
1335
1336         mmiowb();
1337         spin_unlock_irqrestore(&host->lock, flags);
1338 }
1339
1340 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1341 {
1342         unsigned long flags;
1343         int vdd_bit = -1;
1344         u8 ctrl;
1345
1346         spin_lock_irqsave(&host->lock, flags);
1347
1348         if (host->flags & SDHCI_DEVICE_DEAD) {
1349                 spin_unlock_irqrestore(&host->lock, flags);
1350                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1351                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1352                 return;
1353         }
1354
1355         /*
1356          * Reset the chip on each power off.
1357          * Should clear out any weird states.
1358          */
1359         if (ios->power_mode == MMC_POWER_OFF) {
1360                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1361                 sdhci_reinit(host);
1362         }
1363
1364         sdhci_set_clock(host, ios->clock);
1365
1366         if (ios->power_mode == MMC_POWER_OFF)
1367                 vdd_bit = sdhci_set_power(host, -1);
1368         else
1369                 vdd_bit = sdhci_set_power(host, ios->vdd);
1370
1371         if (host->vmmc && vdd_bit != -1) {
1372                 spin_unlock_irqrestore(&host->lock, flags);
1373                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1374                 spin_lock_irqsave(&host->lock, flags);
1375         }
1376
1377         if (host->ops->platform_send_init_74_clocks)
1378                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1379
1380         /*
1381          * If your platform has 8-bit width support but is not a v3 controller,
1382          * or if it requires special setup code, you should implement that in
1383          * platform_8bit_width().
1384          */
1385         if (host->ops->platform_8bit_width)
1386                 host->ops->platform_8bit_width(host, ios->bus_width);
1387         else {
1388                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1389                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1390                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1391                         if (host->version >= SDHCI_SPEC_300)
1392                                 ctrl |= SDHCI_CTRL_8BITBUS;
1393                 } else {
1394                         if (host->version >= SDHCI_SPEC_300)
1395                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1396                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1397                                 ctrl |= SDHCI_CTRL_4BITBUS;
1398                         else
1399                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1400                 }
1401                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1402         }
1403
1404         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1405
1406         if ((ios->timing == MMC_TIMING_SD_HS ||
1407              ios->timing == MMC_TIMING_MMC_HS)
1408             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1409                 ctrl |= SDHCI_CTRL_HISPD;
1410         else
1411                 ctrl &= ~SDHCI_CTRL_HISPD;
1412
1413         if (host->version >= SDHCI_SPEC_300) {
1414                 u16 clk, ctrl_2;
1415                 unsigned int clock;
1416
1417                 /* In case of UHS-I modes, set High Speed Enable */
1418                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1419                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1420                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1421                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1422                     (ios->timing == MMC_TIMING_UHS_SDR25))
1423                         ctrl |= SDHCI_CTRL_HISPD;
1424
1425                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1426                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1427                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1428                         /*
1429                          * We only need to set Driver Strength if the
1430                          * preset value enable is not set.
1431                          */
1432                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1433                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1434                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1435                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1436                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1437
1438                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1439                 } else {
1440                         /*
1441                          * According to SDHC Spec v3.00, if the Preset Value
1442                          * Enable in the Host Control 2 register is set, we
1443                          * need to reset SD Clock Enable before changing High
1444                          * Speed Enable to avoid generating clock gliches.
1445                          */
1446
1447                         /* Reset SD Clock Enable */
1448                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1449                         clk &= ~SDHCI_CLOCK_CARD_EN;
1450                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1451
1452                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1453
1454                         /* Re-enable SD Clock */
1455                         clock = host->clock;
1456                         host->clock = 0;
1457                         sdhci_set_clock(host, clock);
1458                 }
1459
1460
1461                 /* Reset SD Clock Enable */
1462                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1463                 clk &= ~SDHCI_CLOCK_CARD_EN;
1464                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1465
1466                 if (host->ops->set_uhs_signaling)
1467                         host->ops->set_uhs_signaling(host, ios->timing);
1468                 else {
1469                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1470                         /* Select Bus Speed Mode for host */
1471                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1472                         if (ios->timing == MMC_TIMING_MMC_HS200)
1473                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1474                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
1475                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1476                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1477                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1478                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1479                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1480                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1481                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1482                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1483                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1484                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1485                 }
1486
1487                 /* Re-enable SD Clock */
1488                 clock = host->clock;
1489                 host->clock = 0;
1490                 sdhci_set_clock(host, clock);
1491         } else
1492                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1493
1494         /*
1495          * Some (ENE) controllers go apeshit on some ios operation,
1496          * signalling timeout and CRC errors even on CMD0. Resetting
1497          * it on each ios seems to solve the problem.
1498          */
1499         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1500                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1501
1502         mmiowb();
1503         spin_unlock_irqrestore(&host->lock, flags);
1504 }
1505
1506 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1507 {
1508         struct sdhci_host *host = mmc_priv(mmc);
1509
1510         sdhci_runtime_pm_get(host);
1511         sdhci_do_set_ios(host, ios);
1512         sdhci_runtime_pm_put(host);
1513 }
1514
1515 static int sdhci_check_ro(struct sdhci_host *host)
1516 {
1517         unsigned long flags;
1518         int is_readonly;
1519
1520         spin_lock_irqsave(&host->lock, flags);
1521
1522         if (host->flags & SDHCI_DEVICE_DEAD)
1523                 is_readonly = 0;
1524         else if (host->ops->get_ro)
1525                 is_readonly = host->ops->get_ro(host);
1526         else
1527                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1528                                 & SDHCI_WRITE_PROTECT);
1529
1530         spin_unlock_irqrestore(&host->lock, flags);
1531
1532         /* This quirk needs to be replaced by a callback-function later */
1533         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1534                 !is_readonly : is_readonly;
1535 }
1536
1537 #define SAMPLE_COUNT    5
1538
1539 static int sdhci_do_get_ro(struct sdhci_host *host)
1540 {
1541         int i, ro_count;
1542
1543         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1544                 return sdhci_check_ro(host);
1545
1546         ro_count = 0;
1547         for (i = 0; i < SAMPLE_COUNT; i++) {
1548                 if (sdhci_check_ro(host)) {
1549                         if (++ro_count > SAMPLE_COUNT / 2)
1550                                 return 1;
1551                 }
1552                 msleep(30);
1553         }
1554         return 0;
1555 }
1556
1557 static void sdhci_hw_reset(struct mmc_host *mmc)
1558 {
1559         struct sdhci_host *host = mmc_priv(mmc);
1560
1561         if (host->ops && host->ops->hw_reset)
1562                 host->ops->hw_reset(host);
1563 }
1564
1565 static int sdhci_get_ro(struct mmc_host *mmc)
1566 {
1567         struct sdhci_host *host = mmc_priv(mmc);
1568         int ret;
1569
1570         sdhci_runtime_pm_get(host);
1571         ret = sdhci_do_get_ro(host);
1572         sdhci_runtime_pm_put(host);
1573         return ret;
1574 }
1575
1576 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1577 {
1578         if (host->flags & SDHCI_DEVICE_DEAD)
1579                 goto out;
1580
1581         if (enable)
1582                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1583         else
1584                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1585
1586         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1587         if (host->runtime_suspended)
1588                 goto out;
1589
1590         if (enable)
1591                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1592         else
1593                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1594 out:
1595         mmiowb();
1596 }
1597
1598 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1599 {
1600         struct sdhci_host *host = mmc_priv(mmc);
1601         unsigned long flags;
1602
1603         spin_lock_irqsave(&host->lock, flags);
1604         sdhci_enable_sdio_irq_nolock(host, enable);
1605         spin_unlock_irqrestore(&host->lock, flags);
1606 }
1607
1608 static int sdhci_do_3_3v_signal_voltage_switch(struct sdhci_host *host,
1609                                                 u16 ctrl)
1610 {
1611         int ret;
1612
1613         /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1614         ctrl &= ~SDHCI_CTRL_VDD_180;
1615         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1616
1617         if (host->vqmmc) {
1618                 ret = regulator_set_voltage(host->vqmmc, 3300000, 3300000);
1619                 if (ret) {
1620                         pr_warning("%s: Switching to 3.3V signalling voltage "
1621                                    " failed\n", mmc_hostname(host->mmc));
1622                         return -EIO;
1623                 }
1624         }
1625         /* Wait for 5ms */
1626         usleep_range(5000, 5500);
1627
1628         /* 3.3V regulator output should be stable within 5 ms */
1629         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1630         if (!(ctrl & SDHCI_CTRL_VDD_180))
1631                 return 0;
1632
1633         pr_warning("%s: 3.3V regulator output did not became stable\n",
1634                    mmc_hostname(host->mmc));
1635
1636         return -EIO;
1637 }
1638
1639 static int sdhci_do_1_8v_signal_voltage_switch(struct sdhci_host *host,
1640                                                 u16 ctrl)
1641 {
1642         u8 pwr;
1643         u16 clk;
1644         u32 present_state;
1645         int ret;
1646
1647         /* Stop SDCLK */
1648         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1649         clk &= ~SDHCI_CLOCK_CARD_EN;
1650         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1651
1652         /* Check whether DAT[3:0] is 0000 */
1653         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1654         if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1655                SDHCI_DATA_LVL_SHIFT)) {
1656                 /*
1657                  * Enable 1.8V Signal Enable in the Host Control2
1658                  * register
1659                  */
1660                 if (host->vqmmc)
1661                         ret = regulator_set_voltage(host->vqmmc,
1662                                 1800000, 1800000);
1663                 else
1664                         ret = 0;
1665
1666                 if (!ret) {
1667                         ctrl |= SDHCI_CTRL_VDD_180;
1668                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1669
1670                         /* Wait for 5ms */
1671                         usleep_range(5000, 5500);
1672
1673                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1674                         if (ctrl & SDHCI_CTRL_VDD_180) {
1675                                 /* Provide SDCLK again and wait for 1ms */
1676                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1677                                 clk |= SDHCI_CLOCK_CARD_EN;
1678                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1679                                 usleep_range(1000, 1500);
1680
1681                                 /*
1682                                  * If DAT[3:0] level is 1111b, then the card
1683                                  * was successfully switched to 1.8V signaling.
1684                                  */
1685                                 present_state = sdhci_readl(host,
1686                                                         SDHCI_PRESENT_STATE);
1687                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1688                                      SDHCI_DATA_LVL_MASK)
1689                                         return 0;
1690                         }
1691                 }
1692         }
1693
1694         /*
1695          * If we are here, that means the switch to 1.8V signaling
1696          * failed. We power cycle the card, and retry initialization
1697          * sequence by setting S18R to 0.
1698          */
1699         pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1700         pwr &= ~SDHCI_POWER_ON;
1701         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1702         if (host->vmmc)
1703                 regulator_disable(host->vmmc);
1704
1705         /* Wait for 1ms as per the spec */
1706         usleep_range(1000, 1500);
1707         pwr |= SDHCI_POWER_ON;
1708         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1709         if (host->vmmc)
1710                 regulator_enable(host->vmmc);
1711
1712         pr_warning("%s: Switching to 1.8V signalling voltage failed, "
1713                    "retrying with S18R set to 0\n", mmc_hostname(host->mmc));
1714
1715         return -EAGAIN;
1716 }
1717
1718 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1719                                                 struct mmc_ios *ios)
1720 {
1721         u16 ctrl;
1722
1723         /*
1724          * Signal Voltage Switching is only applicable for Host Controllers
1725          * v3.00 and above.
1726          */
1727         if (host->version < SDHCI_SPEC_300)
1728                 return 0;
1729
1730         /*
1731          * We first check whether the request is to set signalling voltage
1732          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1733          */
1734         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1735         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1736                 return sdhci_do_3_3v_signal_voltage_switch(host, ctrl);
1737         else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1738                         (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180))
1739                 return sdhci_do_1_8v_signal_voltage_switch(host, ctrl);
1740         else
1741                 /* No signal voltage switch required */
1742                 return 0;
1743 }
1744
1745 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1746         struct mmc_ios *ios)
1747 {
1748         struct sdhci_host *host = mmc_priv(mmc);
1749         int err;
1750
1751         if (host->version < SDHCI_SPEC_300)
1752                 return 0;
1753         sdhci_runtime_pm_get(host);
1754         err = sdhci_do_start_signal_voltage_switch(host, ios);
1755         sdhci_runtime_pm_put(host);
1756         return err;
1757 }
1758
1759 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1760 {
1761         struct sdhci_host *host;
1762         u16 ctrl;
1763         u32 ier;
1764         int tuning_loop_counter = MAX_TUNING_LOOP;
1765         unsigned long timeout;
1766         int err = 0;
1767         bool requires_tuning_nonuhs = false;
1768
1769         host = mmc_priv(mmc);
1770
1771         sdhci_runtime_pm_get(host);
1772         disable_irq(host->irq);
1773         spin_lock(&host->lock);
1774
1775         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1776
1777         /*
1778          * The Host Controller needs tuning only in case of SDR104 mode
1779          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1780          * Capabilities register.
1781          * If the Host Controller supports the HS200 mode then the
1782          * tuning function has to be executed.
1783          */
1784         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1785             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1786              host->flags & SDHCI_HS200_NEEDS_TUNING))
1787                 requires_tuning_nonuhs = true;
1788
1789         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1790             requires_tuning_nonuhs)
1791                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1792         else {
1793                 spin_unlock(&host->lock);
1794                 enable_irq(host->irq);
1795                 sdhci_runtime_pm_put(host);
1796                 return 0;
1797         }
1798
1799         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1800
1801         /*
1802          * As per the Host Controller spec v3.00, tuning command
1803          * generates Buffer Read Ready interrupt, so enable that.
1804          *
1805          * Note: The spec clearly says that when tuning sequence
1806          * is being performed, the controller does not generate
1807          * interrupts other than Buffer Read Ready interrupt. But
1808          * to make sure we don't hit a controller bug, we _only_
1809          * enable Buffer Read Ready interrupt here.
1810          */
1811         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1812         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1813
1814         /*
1815          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1816          * of loops reaches 40 times or a timeout of 150ms occurs.
1817          */
1818         timeout = 150;
1819         do {
1820                 struct mmc_command cmd = {0};
1821                 struct mmc_request mrq = {NULL};
1822
1823                 if (!tuning_loop_counter && !timeout)
1824                         break;
1825
1826                 cmd.opcode = opcode;
1827                 cmd.arg = 0;
1828                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1829                 cmd.retries = 0;
1830                 cmd.data = NULL;
1831                 cmd.error = 0;
1832
1833                 mrq.cmd = &cmd;
1834                 host->mrq = &mrq;
1835
1836                 /*
1837                  * In response to CMD19, the card sends 64 bytes of tuning
1838                  * block to the Host Controller. So we set the block size
1839                  * to 64 here.
1840                  */
1841                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1842                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1843                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1844                                              SDHCI_BLOCK_SIZE);
1845                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1846                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1847                                              SDHCI_BLOCK_SIZE);
1848                 } else {
1849                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1850                                      SDHCI_BLOCK_SIZE);
1851                 }
1852
1853                 /*
1854                  * The tuning block is sent by the card to the host controller.
1855                  * So we set the TRNS_READ bit in the Transfer Mode register.
1856                  * This also takes care of setting DMA Enable and Multi Block
1857                  * Select in the same register to 0.
1858                  */
1859                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1860
1861                 sdhci_send_command(host, &cmd);
1862
1863                 host->cmd = NULL;
1864                 host->mrq = NULL;
1865
1866                 spin_unlock(&host->lock);
1867                 enable_irq(host->irq);
1868
1869                 /* Wait for Buffer Read Ready interrupt */
1870                 wait_event_interruptible_timeout(host->buf_ready_int,
1871                                         (host->tuning_done == 1),
1872                                         msecs_to_jiffies(50));
1873                 disable_irq(host->irq);
1874                 spin_lock(&host->lock);
1875
1876                 if (!host->tuning_done) {
1877                         pr_info(DRIVER_NAME ": Timeout waiting for "
1878                                 "Buffer Read Ready interrupt during tuning "
1879                                 "procedure, falling back to fixed sampling "
1880                                 "clock\n");
1881                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1882                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1883                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1884                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1885
1886                         err = -EIO;
1887                         goto out;
1888                 }
1889
1890                 host->tuning_done = 0;
1891
1892                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1893                 tuning_loop_counter--;
1894                 timeout--;
1895                 mdelay(1);
1896         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1897
1898         /*
1899          * The Host Driver has exhausted the maximum number of loops allowed,
1900          * so use fixed sampling frequency.
1901          */
1902         if (!tuning_loop_counter || !timeout) {
1903                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1904                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1905         } else {
1906                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1907                         pr_info(DRIVER_NAME ": Tuning procedure"
1908                                 " failed, falling back to fixed sampling"
1909                                 " clock\n");
1910                         err = -EIO;
1911                 }
1912         }
1913
1914 out:
1915         /*
1916          * If this is the very first time we are here, we start the retuning
1917          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1918          * flag won't be set, we check this condition before actually starting
1919          * the timer.
1920          */
1921         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1922             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1923                 host->flags |= SDHCI_USING_RETUNING_TIMER;
1924                 mod_timer(&host->tuning_timer, jiffies +
1925                         host->tuning_count * HZ);
1926                 /* Tuning mode 1 limits the maximum data length to 4MB */
1927                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1928         } else {
1929                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1930                 /* Reload the new initial value for timer */
1931                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1932                         mod_timer(&host->tuning_timer, jiffies +
1933                                 host->tuning_count * HZ);
1934         }
1935
1936         /*
1937          * In case tuning fails, host controllers which support re-tuning can
1938          * try tuning again at a later time, when the re-tuning timer expires.
1939          * So for these controllers, we return 0. Since there might be other
1940          * controllers who do not have this capability, we return error for
1941          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1942          * a retuning timer to do the retuning for the card.
1943          */
1944         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
1945                 err = 0;
1946
1947         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1948         spin_unlock(&host->lock);
1949         enable_irq(host->irq);
1950         sdhci_runtime_pm_put(host);
1951
1952         return err;
1953 }
1954
1955 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1956 {
1957         u16 ctrl;
1958         unsigned long flags;
1959
1960         /* Host Controller v3.00 defines preset value registers */
1961         if (host->version < SDHCI_SPEC_300)
1962                 return;
1963
1964         spin_lock_irqsave(&host->lock, flags);
1965
1966         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1967
1968         /*
1969          * We only enable or disable Preset Value if they are not already
1970          * enabled or disabled respectively. Otherwise, we bail out.
1971          */
1972         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1973                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1974                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1975                 host->flags |= SDHCI_PV_ENABLED;
1976         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1977                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1978                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1979                 host->flags &= ~SDHCI_PV_ENABLED;
1980         }
1981
1982         spin_unlock_irqrestore(&host->lock, flags);
1983 }
1984
1985 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1986 {
1987         struct sdhci_host *host = mmc_priv(mmc);
1988
1989         sdhci_runtime_pm_get(host);
1990         sdhci_do_enable_preset_value(host, enable);
1991         sdhci_runtime_pm_put(host);
1992 }
1993
1994 static const struct mmc_host_ops sdhci_ops = {
1995         .request        = sdhci_request,
1996         .set_ios        = sdhci_set_ios,
1997         .get_ro         = sdhci_get_ro,
1998         .hw_reset       = sdhci_hw_reset,
1999         .enable_sdio_irq = sdhci_enable_sdio_irq,
2000         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2001         .execute_tuning                 = sdhci_execute_tuning,
2002         .enable_preset_value            = sdhci_enable_preset_value,
2003 };
2004
2005 /*****************************************************************************\
2006  *                                                                           *
2007  * Tasklets                                                                  *
2008  *                                                                           *
2009 \*****************************************************************************/
2010
2011 static void sdhci_tasklet_card(unsigned long param)
2012 {
2013         struct sdhci_host *host;
2014         unsigned long flags;
2015
2016         host = (struct sdhci_host*)param;
2017
2018         spin_lock_irqsave(&host->lock, flags);
2019
2020         /* Check host->mrq first in case we are runtime suspended */
2021         if (host->mrq &&
2022             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2023                 pr_err("%s: Card removed during transfer!\n",
2024                         mmc_hostname(host->mmc));
2025                 pr_err("%s: Resetting controller.\n",
2026                         mmc_hostname(host->mmc));
2027
2028                 sdhci_reset(host, SDHCI_RESET_CMD);
2029                 sdhci_reset(host, SDHCI_RESET_DATA);
2030
2031                 host->mrq->cmd->error = -ENOMEDIUM;
2032                 tasklet_schedule(&host->finish_tasklet);
2033         }
2034
2035         spin_unlock_irqrestore(&host->lock, flags);
2036
2037         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2038 }
2039
2040 static void sdhci_tasklet_finish(unsigned long param)
2041 {
2042         struct sdhci_host *host;
2043         unsigned long flags;
2044         struct mmc_request *mrq;
2045
2046         host = (struct sdhci_host*)param;
2047
2048         spin_lock_irqsave(&host->lock, flags);
2049
2050         /*
2051          * If this tasklet gets rescheduled while running, it will
2052          * be run again afterwards but without any active request.
2053          */
2054         if (!host->mrq) {
2055                 spin_unlock_irqrestore(&host->lock, flags);
2056                 return;
2057         }
2058
2059         del_timer(&host->timer);
2060
2061         mrq = host->mrq;
2062
2063         /*
2064          * The controller needs a reset of internal state machines
2065          * upon error conditions.
2066          */
2067         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2068             ((mrq->cmd && mrq->cmd->error) ||
2069                  (mrq->data && (mrq->data->error ||
2070                   (mrq->data->stop && mrq->data->stop->error))) ||
2071                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2072
2073                 /* Some controllers need this kick or reset won't work here */
2074                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2075                         unsigned int clock;
2076
2077                         /* This is to force an update */
2078                         clock = host->clock;
2079                         host->clock = 0;
2080                         sdhci_set_clock(host, clock);
2081                 }
2082
2083                 /* Spec says we should do both at the same time, but Ricoh
2084                    controllers do not like that. */
2085                 sdhci_reset(host, SDHCI_RESET_CMD);
2086                 sdhci_reset(host, SDHCI_RESET_DATA);
2087         }
2088
2089         host->mrq = NULL;
2090         host->cmd = NULL;
2091         host->data = NULL;
2092
2093 #ifndef SDHCI_USE_LEDS_CLASS
2094         sdhci_deactivate_led(host);
2095 #endif
2096
2097         mmiowb();
2098         spin_unlock_irqrestore(&host->lock, flags);
2099
2100         mmc_request_done(host->mmc, mrq);
2101         sdhci_runtime_pm_put(host);
2102 }
2103
2104 static void sdhci_timeout_timer(unsigned long data)
2105 {
2106         struct sdhci_host *host;
2107         unsigned long flags;
2108
2109         host = (struct sdhci_host*)data;
2110
2111         spin_lock_irqsave(&host->lock, flags);
2112
2113         if (host->mrq) {
2114                 pr_err("%s: Timeout waiting for hardware "
2115                         "interrupt.\n", mmc_hostname(host->mmc));
2116                 sdhci_dumpregs(host);
2117
2118                 if (host->data) {
2119                         host->data->error = -ETIMEDOUT;
2120                         sdhci_finish_data(host);
2121                 } else {
2122                         if (host->cmd)
2123                                 host->cmd->error = -ETIMEDOUT;
2124                         else
2125                                 host->mrq->cmd->error = -ETIMEDOUT;
2126
2127                         tasklet_schedule(&host->finish_tasklet);
2128                 }
2129         }
2130
2131         mmiowb();
2132         spin_unlock_irqrestore(&host->lock, flags);
2133 }
2134
2135 static void sdhci_tuning_timer(unsigned long data)
2136 {
2137         struct sdhci_host *host;
2138         unsigned long flags;
2139
2140         host = (struct sdhci_host *)data;
2141
2142         spin_lock_irqsave(&host->lock, flags);
2143
2144         host->flags |= SDHCI_NEEDS_RETUNING;
2145
2146         spin_unlock_irqrestore(&host->lock, flags);
2147 }
2148
2149 /*****************************************************************************\
2150  *                                                                           *
2151  * Interrupt handling                                                        *
2152  *                                                                           *
2153 \*****************************************************************************/
2154
2155 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2156 {
2157         BUG_ON(intmask == 0);
2158
2159         if (!host->cmd) {
2160                 pr_err("%s: Got command interrupt 0x%08x even "
2161                         "though no command operation was in progress.\n",
2162                         mmc_hostname(host->mmc), (unsigned)intmask);
2163                 sdhci_dumpregs(host);
2164                 return;
2165         }
2166
2167         if (intmask & SDHCI_INT_TIMEOUT)
2168                 host->cmd->error = -ETIMEDOUT;
2169         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2170                         SDHCI_INT_INDEX))
2171                 host->cmd->error = -EILSEQ;
2172
2173         if (host->cmd->error) {
2174                 tasklet_schedule(&host->finish_tasklet);
2175                 return;
2176         }
2177
2178         /*
2179          * The host can send and interrupt when the busy state has
2180          * ended, allowing us to wait without wasting CPU cycles.
2181          * Unfortunately this is overloaded on the "data complete"
2182          * interrupt, so we need to take some care when handling
2183          * it.
2184          *
2185          * Note: The 1.0 specification is a bit ambiguous about this
2186          *       feature so there might be some problems with older
2187          *       controllers.
2188          */
2189         if (host->cmd->flags & MMC_RSP_BUSY) {
2190                 if (host->cmd->data)
2191                         DBG("Cannot wait for busy signal when also "
2192                                 "doing a data transfer");
2193                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2194                         return;
2195
2196                 /* The controller does not support the end-of-busy IRQ,
2197                  * fall through and take the SDHCI_INT_RESPONSE */
2198         }
2199
2200         if (intmask & SDHCI_INT_RESPONSE)
2201                 sdhci_finish_command(host);
2202 }
2203
2204 #ifdef CONFIG_MMC_DEBUG
2205 static void sdhci_show_adma_error(struct sdhci_host *host)
2206 {
2207         const char *name = mmc_hostname(host->mmc);
2208         u8 *desc = host->adma_desc;
2209         __le32 *dma;
2210         __le16 *len;
2211         u8 attr;
2212
2213         sdhci_dumpregs(host);
2214
2215         while (true) {
2216                 dma = (__le32 *)(desc + 4);
2217                 len = (__le16 *)(desc + 2);
2218                 attr = *desc;
2219
2220                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2221                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2222
2223                 desc += 8;
2224
2225                 if (attr & 2)
2226                         break;
2227         }
2228 }
2229 #else
2230 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2231 #endif
2232
2233 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2234 {
2235         u32 command;
2236         BUG_ON(intmask == 0);
2237
2238         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2239         if (intmask & SDHCI_INT_DATA_AVAIL) {
2240                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2241                 if (command == MMC_SEND_TUNING_BLOCK ||
2242                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2243                         host->tuning_done = 1;
2244                         wake_up(&host->buf_ready_int);
2245                         return;
2246                 }
2247         }
2248
2249         if (!host->data) {
2250                 /*
2251                  * The "data complete" interrupt is also used to
2252                  * indicate that a busy state has ended. See comment
2253                  * above in sdhci_cmd_irq().
2254                  */
2255                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2256                         if (intmask & SDHCI_INT_DATA_END) {
2257                                 sdhci_finish_command(host);
2258                                 return;
2259                         }
2260                 }
2261
2262                 pr_err("%s: Got data interrupt 0x%08x even "
2263                         "though no data operation was in progress.\n",
2264                         mmc_hostname(host->mmc), (unsigned)intmask);
2265                 sdhci_dumpregs(host);
2266
2267                 return;
2268         }
2269
2270         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2271                 host->data->error = -ETIMEDOUT;
2272         else if (intmask & SDHCI_INT_DATA_END_BIT)
2273                 host->data->error = -EILSEQ;
2274         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2275                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2276                         != MMC_BUS_TEST_R)
2277                 host->data->error = -EILSEQ;
2278         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2279                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2280                 sdhci_show_adma_error(host);
2281                 host->data->error = -EIO;
2282         }
2283
2284         if (host->data->error)
2285                 sdhci_finish_data(host);
2286         else {
2287                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2288                         sdhci_transfer_pio(host);
2289
2290                 /*
2291                  * We currently don't do anything fancy with DMA
2292                  * boundaries, but as we can't disable the feature
2293                  * we need to at least restart the transfer.
2294                  *
2295                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2296                  * should return a valid address to continue from, but as
2297                  * some controllers are faulty, don't trust them.
2298                  */
2299                 if (intmask & SDHCI_INT_DMA_END) {
2300                         u32 dmastart, dmanow;
2301                         dmastart = sg_dma_address(host->data->sg);
2302                         dmanow = dmastart + host->data->bytes_xfered;
2303                         /*
2304                          * Force update to the next DMA block boundary.
2305                          */
2306                         dmanow = (dmanow &
2307                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2308                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2309                         host->data->bytes_xfered = dmanow - dmastart;
2310                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2311                                 " next 0x%08x\n",
2312                                 mmc_hostname(host->mmc), dmastart,
2313                                 host->data->bytes_xfered, dmanow);
2314                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2315                 }
2316
2317                 if (intmask & SDHCI_INT_DATA_END) {
2318                         if (host->cmd) {
2319                                 /*
2320                                  * Data managed to finish before the
2321                                  * command completed. Make sure we do
2322                                  * things in the proper order.
2323                                  */
2324                                 host->data_early = 1;
2325                         } else {
2326                                 sdhci_finish_data(host);
2327                         }
2328                 }
2329         }
2330 }
2331
2332 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2333 {
2334         irqreturn_t result;
2335         struct sdhci_host *host = dev_id;
2336         u32 intmask, unexpected = 0;
2337         int cardint = 0, max_loops = 16;
2338
2339         spin_lock(&host->lock);
2340
2341         if (host->runtime_suspended) {
2342                 spin_unlock(&host->lock);
2343                 pr_warning("%s: got irq while runtime suspended\n",
2344                        mmc_hostname(host->mmc));
2345                 return IRQ_HANDLED;
2346         }
2347
2348         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2349
2350         if (!intmask || intmask == 0xffffffff) {
2351                 result = IRQ_NONE;
2352                 goto out;
2353         }
2354
2355 again:
2356         DBG("*** %s got interrupt: 0x%08x\n",
2357                 mmc_hostname(host->mmc), intmask);
2358
2359         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2360                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2361                               SDHCI_CARD_PRESENT;
2362
2363                 /*
2364                  * There is a observation on i.mx esdhc.  INSERT bit will be
2365                  * immediately set again when it gets cleared, if a card is
2366                  * inserted.  We have to mask the irq to prevent interrupt
2367                  * storm which will freeze the system.  And the REMOVE gets
2368                  * the same situation.
2369                  *
2370                  * More testing are needed here to ensure it works for other
2371                  * platforms though.
2372                  */
2373                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2374                                                 SDHCI_INT_CARD_REMOVE);
2375                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2376                                                   SDHCI_INT_CARD_INSERT);
2377
2378                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2379                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2380                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2381                 tasklet_schedule(&host->card_tasklet);
2382         }
2383
2384         if (intmask & SDHCI_INT_CMD_MASK) {
2385                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2386                         SDHCI_INT_STATUS);
2387                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2388         }
2389
2390         if (intmask & SDHCI_INT_DATA_MASK) {
2391                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2392                         SDHCI_INT_STATUS);
2393                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2394         }
2395
2396         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2397
2398         intmask &= ~SDHCI_INT_ERROR;
2399
2400         if (intmask & SDHCI_INT_BUS_POWER) {
2401                 pr_err("%s: Card is consuming too much power!\n",
2402                         mmc_hostname(host->mmc));
2403                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2404         }
2405
2406         intmask &= ~SDHCI_INT_BUS_POWER;
2407
2408         if (intmask & SDHCI_INT_CARD_INT)
2409                 cardint = 1;
2410
2411         intmask &= ~SDHCI_INT_CARD_INT;
2412
2413         if (intmask) {
2414                 unexpected |= intmask;
2415                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2416         }
2417
2418         result = IRQ_HANDLED;
2419
2420         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2421         if (intmask && --max_loops)
2422                 goto again;
2423 out:
2424         spin_unlock(&host->lock);
2425
2426         if (unexpected) {
2427                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2428                            mmc_hostname(host->mmc), unexpected);
2429                 sdhci_dumpregs(host);
2430         }
2431         /*
2432          * We have to delay this as it calls back into the driver.
2433          */
2434         if (cardint)
2435                 mmc_signal_sdio_irq(host->mmc);
2436
2437         return result;
2438 }
2439
2440 /*****************************************************************************\
2441  *                                                                           *
2442  * Suspend/resume                                                            *
2443  *                                                                           *
2444 \*****************************************************************************/
2445
2446 #ifdef CONFIG_PM
2447
2448 int sdhci_suspend_host(struct sdhci_host *host)
2449 {
2450         int ret;
2451
2452         if (host->ops->platform_suspend)
2453                 host->ops->platform_suspend(host);
2454
2455         sdhci_disable_card_detection(host);
2456
2457         /* Disable tuning since we are suspending */
2458         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2459                 del_timer_sync(&host->tuning_timer);
2460                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2461         }
2462
2463         ret = mmc_suspend_host(host->mmc);
2464         if (ret) {
2465                 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2466                         host->flags |= SDHCI_NEEDS_RETUNING;
2467                         mod_timer(&host->tuning_timer, jiffies +
2468                                         host->tuning_count * HZ);
2469                 }
2470
2471                 sdhci_enable_card_detection(host);
2472
2473                 return ret;
2474         }
2475
2476         free_irq(host->irq, host);
2477
2478         return ret;
2479 }
2480
2481 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2482
2483 int sdhci_resume_host(struct sdhci_host *host)
2484 {
2485         int ret;
2486
2487         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2488                 if (host->ops->enable_dma)
2489                         host->ops->enable_dma(host);
2490         }
2491
2492         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2493                           mmc_hostname(host->mmc), host);
2494         if (ret)
2495                 return ret;
2496
2497         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2498             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2499                 /* Card keeps power but host controller does not */
2500                 sdhci_init(host, 0);
2501                 host->pwr = 0;
2502                 host->clock = 0;
2503                 sdhci_do_set_ios(host, &host->mmc->ios);
2504         } else {
2505                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2506                 mmiowb();
2507         }
2508
2509         ret = mmc_resume_host(host->mmc);
2510         sdhci_enable_card_detection(host);
2511
2512         if (host->ops->platform_resume)
2513                 host->ops->platform_resume(host);
2514
2515         /* Set the re-tuning expiration flag */
2516         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2517                 host->flags |= SDHCI_NEEDS_RETUNING;
2518
2519         return ret;
2520 }
2521
2522 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2523
2524 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2525 {
2526         u8 val;
2527         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2528         val |= SDHCI_WAKE_ON_INT;
2529         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2530 }
2531
2532 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2533
2534 #endif /* CONFIG_PM */
2535
2536 #ifdef CONFIG_PM_RUNTIME
2537
2538 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2539 {
2540         return pm_runtime_get_sync(host->mmc->parent);
2541 }
2542
2543 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2544 {
2545         pm_runtime_mark_last_busy(host->mmc->parent);
2546         return pm_runtime_put_autosuspend(host->mmc->parent);
2547 }
2548
2549 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2550 {
2551         unsigned long flags;
2552         int ret = 0;
2553
2554         /* Disable tuning since we are suspending */
2555         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2556                 del_timer_sync(&host->tuning_timer);
2557                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2558         }
2559
2560         spin_lock_irqsave(&host->lock, flags);
2561         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2562         spin_unlock_irqrestore(&host->lock, flags);
2563
2564         synchronize_irq(host->irq);
2565
2566         spin_lock_irqsave(&host->lock, flags);
2567         host->runtime_suspended = true;
2568         spin_unlock_irqrestore(&host->lock, flags);
2569
2570         return ret;
2571 }
2572 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2573
2574 int sdhci_runtime_resume_host(struct sdhci_host *host)
2575 {
2576         unsigned long flags;
2577         int ret = 0, host_flags = host->flags;
2578
2579         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2580                 if (host->ops->enable_dma)
2581                         host->ops->enable_dma(host);
2582         }
2583
2584         sdhci_init(host, 0);
2585
2586         /* Force clock and power re-program */
2587         host->pwr = 0;
2588         host->clock = 0;
2589         sdhci_do_set_ios(host, &host->mmc->ios);
2590
2591         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2592         if (host_flags & SDHCI_PV_ENABLED)
2593                 sdhci_do_enable_preset_value(host, true);
2594
2595         /* Set the re-tuning expiration flag */
2596         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2597                 host->flags |= SDHCI_NEEDS_RETUNING;
2598
2599         spin_lock_irqsave(&host->lock, flags);
2600
2601         host->runtime_suspended = false;
2602
2603         /* Enable SDIO IRQ */
2604         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2605                 sdhci_enable_sdio_irq_nolock(host, true);
2606
2607         /* Enable Card Detection */
2608         sdhci_enable_card_detection(host);
2609
2610         spin_unlock_irqrestore(&host->lock, flags);
2611
2612         return ret;
2613 }
2614 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2615
2616 #endif
2617
2618 /*****************************************************************************\
2619  *                                                                           *
2620  * Device allocation/registration                                            *
2621  *                                                                           *
2622 \*****************************************************************************/
2623
2624 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2625         size_t priv_size)
2626 {
2627         struct mmc_host *mmc;
2628         struct sdhci_host *host;
2629
2630         WARN_ON(dev == NULL);
2631
2632         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2633         if (!mmc)
2634                 return ERR_PTR(-ENOMEM);
2635
2636         host = mmc_priv(mmc);
2637         host->mmc = mmc;
2638
2639         return host;
2640 }
2641
2642 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2643
2644 int sdhci_add_host(struct sdhci_host *host)
2645 {
2646         struct mmc_host *mmc;
2647         u32 caps[2] = {0, 0};
2648         u32 max_current_caps;
2649         unsigned int ocr_avail;
2650         int ret;
2651
2652         WARN_ON(host == NULL);
2653         if (host == NULL)
2654                 return -EINVAL;
2655
2656         mmc = host->mmc;
2657
2658         if (debug_quirks)
2659                 host->quirks = debug_quirks;
2660         if (debug_quirks2)
2661                 host->quirks2 = debug_quirks2;
2662
2663         sdhci_reset(host, SDHCI_RESET_ALL);
2664
2665         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2666         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2667                                 >> SDHCI_SPEC_VER_SHIFT;
2668         if (host->version > SDHCI_SPEC_300) {
2669                 pr_err("%s: Unknown controller version (%d). "
2670                         "You may experience problems.\n", mmc_hostname(mmc),
2671                         host->version);
2672         }
2673
2674         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2675                 sdhci_readl(host, SDHCI_CAPABILITIES);
2676
2677         if (host->version >= SDHCI_SPEC_300)
2678                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2679                         host->caps1 :
2680                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2681
2682         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2683                 host->flags |= SDHCI_USE_SDMA;
2684         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2685                 DBG("Controller doesn't have SDMA capability\n");
2686         else
2687                 host->flags |= SDHCI_USE_SDMA;
2688
2689         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2690                 (host->flags & SDHCI_USE_SDMA)) {
2691                 DBG("Disabling DMA as it is marked broken\n");
2692                 host->flags &= ~SDHCI_USE_SDMA;
2693         }
2694
2695         if ((host->version >= SDHCI_SPEC_200) &&
2696                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2697                 host->flags |= SDHCI_USE_ADMA;
2698
2699         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2700                 (host->flags & SDHCI_USE_ADMA)) {
2701                 DBG("Disabling ADMA as it is marked broken\n");
2702                 host->flags &= ~SDHCI_USE_ADMA;
2703         }
2704
2705         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2706                 if (host->ops->enable_dma) {
2707                         if (host->ops->enable_dma(host)) {
2708                                 pr_warning("%s: No suitable DMA "
2709                                         "available. Falling back to PIO.\n",
2710                                         mmc_hostname(mmc));
2711                                 host->flags &=
2712                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2713                         }
2714                 }
2715         }
2716
2717         if (host->flags & SDHCI_USE_ADMA) {
2718                 /*
2719                  * We need to allocate descriptors for all sg entries
2720                  * (128) and potentially one alignment transfer for
2721                  * each of those entries.
2722                  */
2723                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2724                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2725                 if (!host->adma_desc || !host->align_buffer) {
2726                         kfree(host->adma_desc);
2727                         kfree(host->align_buffer);
2728                         pr_warning("%s: Unable to allocate ADMA "
2729                                 "buffers. Falling back to standard DMA.\n",
2730                                 mmc_hostname(mmc));
2731                         host->flags &= ~SDHCI_USE_ADMA;
2732                 }
2733         }
2734
2735         /*
2736          * If we use DMA, then it's up to the caller to set the DMA
2737          * mask, but PIO does not need the hw shim so we set a new
2738          * mask here in that case.
2739          */
2740         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2741                 host->dma_mask = DMA_BIT_MASK(64);
2742                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2743         }
2744
2745         if (host->version >= SDHCI_SPEC_300)
2746                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2747                         >> SDHCI_CLOCK_BASE_SHIFT;
2748         else
2749                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2750                         >> SDHCI_CLOCK_BASE_SHIFT;
2751
2752         host->max_clk *= 1000000;
2753         if (host->max_clk == 0 || host->quirks &
2754                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2755                 if (!host->ops->get_max_clock) {
2756                         pr_err("%s: Hardware doesn't specify base clock "
2757                                "frequency.\n", mmc_hostname(mmc));
2758                         return -ENODEV;
2759                 }
2760                 host->max_clk = host->ops->get_max_clock(host);
2761         }
2762
2763         /*
2764          * In case of Host Controller v3.00, find out whether clock
2765          * multiplier is supported.
2766          */
2767         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2768                         SDHCI_CLOCK_MUL_SHIFT;
2769
2770         /*
2771          * In case the value in Clock Multiplier is 0, then programmable
2772          * clock mode is not supported, otherwise the actual clock
2773          * multiplier is one more than the value of Clock Multiplier
2774          * in the Capabilities Register.
2775          */
2776         if (host->clk_mul)
2777                 host->clk_mul += 1;
2778
2779         /*
2780          * Set host parameters.
2781          */
2782         mmc->ops = &sdhci_ops;
2783         mmc->f_max = host->max_clk;
2784         if (host->ops->get_min_clock)
2785                 mmc->f_min = host->ops->get_min_clock(host);
2786         else if (host->version >= SDHCI_SPEC_300) {
2787                 if (host->clk_mul) {
2788                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2789                         mmc->f_max = host->max_clk * host->clk_mul;
2790                 } else
2791                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2792         } else
2793                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2794
2795         host->timeout_clk =
2796                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2797         if (host->timeout_clk == 0) {
2798                 if (host->ops->get_timeout_clock) {
2799                         host->timeout_clk = host->ops->get_timeout_clock(host);
2800                 } else if (!(host->quirks &
2801                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2802                         pr_err("%s: Hardware doesn't specify timeout clock "
2803                                "frequency.\n", mmc_hostname(mmc));
2804                         return -ENODEV;
2805                 }
2806         }
2807         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2808                 host->timeout_clk *= 1000;
2809
2810         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2811                 host->timeout_clk = mmc->f_max / 1000;
2812
2813         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2814
2815         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2816
2817         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2818                 host->flags |= SDHCI_AUTO_CMD12;
2819
2820         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2821         if ((host->version >= SDHCI_SPEC_300) &&
2822             ((host->flags & SDHCI_USE_ADMA) ||
2823              !(host->flags & SDHCI_USE_SDMA))) {
2824                 host->flags |= SDHCI_AUTO_CMD23;
2825                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2826         } else {
2827                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2828         }
2829
2830         /*
2831          * A controller may support 8-bit width, but the board itself
2832          * might not have the pins brought out.  Boards that support
2833          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2834          * their platform code before calling sdhci_add_host(), and we
2835          * won't assume 8-bit width for hosts without that CAP.
2836          */
2837         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2838                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2839
2840         if (caps[0] & SDHCI_CAN_DO_HISPD)
2841                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2842
2843         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2844             !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2845                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2846
2847         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2848         host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
2849         if (IS_ERR(host->vqmmc)) {
2850                 pr_info("%s: no vqmmc regulator found\n", mmc_hostname(mmc));
2851                 host->vqmmc = NULL;
2852         }
2853         else if (regulator_is_supported_voltage(host->vqmmc, 1800000, 1800000))
2854                 regulator_enable(host->vqmmc);
2855         else
2856                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2857                        SDHCI_SUPPORT_DDR50);
2858
2859         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2860         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2861                        SDHCI_SUPPORT_DDR50))
2862                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2863
2864         /* SDR104 supports also implies SDR50 support */
2865         if (caps[1] & SDHCI_SUPPORT_SDR104)
2866                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2867         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2868                 mmc->caps |= MMC_CAP_UHS_SDR50;
2869
2870         if (caps[1] & SDHCI_SUPPORT_DDR50)
2871                 mmc->caps |= MMC_CAP_UHS_DDR50;
2872
2873         /* Does the host need tuning for SDR50? */
2874         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2875                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2876
2877         /* Does the host need tuning for HS200? */
2878         if (mmc->caps2 & MMC_CAP2_HS200)
2879                 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2880
2881         /* Driver Type(s) (A, C, D) supported by the host */
2882         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2883                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2884         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2885                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2886         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2887                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2888
2889         /* Initial value for re-tuning timer count */
2890         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2891                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2892
2893         /*
2894          * In case Re-tuning Timer is not disabled, the actual value of
2895          * re-tuning timer will be 2 ^ (n - 1).
2896          */
2897         if (host->tuning_count)
2898                 host->tuning_count = 1 << (host->tuning_count - 1);
2899
2900         /* Re-tuning mode supported by the Host Controller */
2901         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2902                              SDHCI_RETUNING_MODE_SHIFT;
2903
2904         ocr_avail = 0;
2905
2906         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2907         if (IS_ERR(host->vmmc)) {
2908                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2909                 host->vmmc = NULL;
2910         } else
2911                 regulator_enable(host->vmmc);
2912
2913 #ifdef CONFIG_REGULATOR
2914         if (host->vmmc) {
2915                 ret = regulator_is_supported_voltage(host->vmmc, 3300000,
2916                         3300000);
2917                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2918                         caps[0] &= ~SDHCI_CAN_VDD_330;
2919                 ret = regulator_is_supported_voltage(host->vmmc, 3000000,
2920                         3000000);
2921                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2922                         caps[0] &= ~SDHCI_CAN_VDD_300;
2923                 ret = regulator_is_supported_voltage(host->vmmc, 1800000,
2924                         1800000);
2925                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2926                         caps[0] &= ~SDHCI_CAN_VDD_180;
2927         }
2928 #endif /* CONFIG_REGULATOR */
2929
2930         /*
2931          * According to SD Host Controller spec v3.00, if the Host System
2932          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2933          * the value is meaningful only if Voltage Support in the Capabilities
2934          * register is set. The actual current value is 4 times the register
2935          * value.
2936          */
2937         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2938         if (!max_current_caps && host->vmmc) {
2939                 u32 curr = regulator_get_current_limit(host->vmmc);
2940                 if (curr > 0) {
2941
2942                         /* convert to SDHCI_MAX_CURRENT format */
2943                         curr = curr/1000;  /* convert to mA */
2944                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2945
2946                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2947                         max_current_caps =
2948                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2949                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
2950                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
2951                 }
2952         }
2953
2954         if (caps[0] & SDHCI_CAN_VDD_330) {
2955                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2956
2957                 mmc->max_current_330 = ((max_current_caps &
2958                                    SDHCI_MAX_CURRENT_330_MASK) >>
2959                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2960                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2961         }
2962         if (caps[0] & SDHCI_CAN_VDD_300) {
2963                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2964
2965                 mmc->max_current_300 = ((max_current_caps &
2966                                    SDHCI_MAX_CURRENT_300_MASK) >>
2967                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2968                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2969         }
2970         if (caps[0] & SDHCI_CAN_VDD_180) {
2971                 ocr_avail |= MMC_VDD_165_195;
2972
2973                 mmc->max_current_180 = ((max_current_caps &
2974                                    SDHCI_MAX_CURRENT_180_MASK) >>
2975                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2976                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2977         }
2978
2979         mmc->ocr_avail = ocr_avail;
2980         mmc->ocr_avail_sdio = ocr_avail;
2981         if (host->ocr_avail_sdio)
2982                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2983         mmc->ocr_avail_sd = ocr_avail;
2984         if (host->ocr_avail_sd)
2985                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2986         else /* normal SD controllers don't support 1.8V */
2987                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2988         mmc->ocr_avail_mmc = ocr_avail;
2989         if (host->ocr_avail_mmc)
2990                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2991
2992         if (mmc->ocr_avail == 0) {
2993                 pr_err("%s: Hardware doesn't report any "
2994                         "support voltages.\n", mmc_hostname(mmc));
2995                 return -ENODEV;
2996         }
2997
2998         spin_lock_init(&host->lock);
2999
3000         /*
3001          * Maximum number of segments. Depends on if the hardware
3002          * can do scatter/gather or not.
3003          */
3004         if (host->flags & SDHCI_USE_ADMA)
3005                 mmc->max_segs = 128;
3006         else if (host->flags & SDHCI_USE_SDMA)
3007                 mmc->max_segs = 1;
3008         else /* PIO */
3009                 mmc->max_segs = 128;
3010
3011         /*
3012          * Maximum number of sectors in one transfer. Limited by DMA boundary
3013          * size (512KiB).
3014          */
3015         mmc->max_req_size = 524288;
3016
3017         /*
3018          * Maximum segment size. Could be one segment with the maximum number
3019          * of bytes. When doing hardware scatter/gather, each entry cannot
3020          * be larger than 64 KiB though.
3021          */
3022         if (host->flags & SDHCI_USE_ADMA) {
3023                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3024                         mmc->max_seg_size = 65535;
3025                 else
3026                         mmc->max_seg_size = 65536;
3027         } else {
3028                 mmc->max_seg_size = mmc->max_req_size;
3029         }
3030
3031         /*
3032          * Maximum block size. This varies from controller to controller and
3033          * is specified in the capabilities register.
3034          */
3035         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3036                 mmc->max_blk_size = 2;
3037         } else {
3038                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3039                                 SDHCI_MAX_BLOCK_SHIFT;
3040                 if (mmc->max_blk_size >= 3) {
3041                         pr_warning("%s: Invalid maximum block size, "
3042                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3043                         mmc->max_blk_size = 0;
3044                 }
3045         }
3046
3047         mmc->max_blk_size = 512 << mmc->max_blk_size;
3048
3049         /*
3050          * Maximum block count.
3051          */
3052         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3053
3054         /*
3055          * Init tasklets.
3056          */
3057         tasklet_init(&host->card_tasklet,
3058                 sdhci_tasklet_card, (unsigned long)host);
3059         tasklet_init(&host->finish_tasklet,
3060                 sdhci_tasklet_finish, (unsigned long)host);
3061
3062         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3063
3064         if (host->version >= SDHCI_SPEC_300) {
3065                 init_waitqueue_head(&host->buf_ready_int);
3066
3067                 /* Initialize re-tuning timer */
3068                 init_timer(&host->tuning_timer);
3069                 host->tuning_timer.data = (unsigned long)host;
3070                 host->tuning_timer.function = sdhci_tuning_timer;
3071         }
3072
3073         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3074                 mmc_hostname(mmc), host);
3075         if (ret) {
3076                 pr_err("%s: Failed to request IRQ %d: %d\n",
3077                        mmc_hostname(mmc), host->irq, ret);
3078                 goto untasklet;
3079         }
3080
3081         sdhci_init(host, 0);
3082
3083 #ifdef CONFIG_MMC_DEBUG
3084         sdhci_dumpregs(host);
3085 #endif
3086
3087 #ifdef SDHCI_USE_LEDS_CLASS
3088         snprintf(host->led_name, sizeof(host->led_name),
3089                 "%s::", mmc_hostname(mmc));
3090         host->led.name = host->led_name;
3091         host->led.brightness = LED_OFF;
3092         host->led.default_trigger = mmc_hostname(mmc);
3093         host->led.brightness_set = sdhci_led_control;
3094
3095         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3096         if (ret) {
3097                 pr_err("%s: Failed to register LED device: %d\n",
3098                        mmc_hostname(mmc), ret);
3099                 goto reset;
3100         }
3101 #endif
3102
3103         mmiowb();
3104
3105         mmc_add_host(mmc);
3106
3107         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3108                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3109                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3110                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3111
3112         sdhci_enable_card_detection(host);
3113
3114         return 0;
3115
3116 #ifdef SDHCI_USE_LEDS_CLASS
3117 reset:
3118         sdhci_reset(host, SDHCI_RESET_ALL);
3119         free_irq(host->irq, host);
3120 #endif
3121 untasklet:
3122         tasklet_kill(&host->card_tasklet);
3123         tasklet_kill(&host->finish_tasklet);
3124
3125         return ret;
3126 }
3127
3128 EXPORT_SYMBOL_GPL(sdhci_add_host);
3129
3130 void sdhci_remove_host(struct sdhci_host *host, int dead)
3131 {
3132         unsigned long flags;
3133
3134         if (dead) {
3135                 spin_lock_irqsave(&host->lock, flags);
3136
3137                 host->flags |= SDHCI_DEVICE_DEAD;
3138
3139                 if (host->mrq) {
3140                         pr_err("%s: Controller removed during "
3141                                 " transfer!\n", mmc_hostname(host->mmc));
3142
3143                         host->mrq->cmd->error = -ENOMEDIUM;
3144                         tasklet_schedule(&host->finish_tasklet);
3145                 }
3146
3147                 spin_unlock_irqrestore(&host->lock, flags);
3148         }
3149
3150         sdhci_disable_card_detection(host);
3151
3152         mmc_remove_host(host->mmc);
3153
3154 #ifdef SDHCI_USE_LEDS_CLASS
3155         led_classdev_unregister(&host->led);
3156 #endif
3157
3158         if (!dead)
3159                 sdhci_reset(host, SDHCI_RESET_ALL);
3160
3161         free_irq(host->irq, host);
3162
3163         del_timer_sync(&host->timer);
3164
3165         tasklet_kill(&host->card_tasklet);
3166         tasklet_kill(&host->finish_tasklet);
3167
3168         if (host->vmmc) {
3169                 regulator_disable(host->vmmc);
3170                 regulator_put(host->vmmc);
3171         }
3172
3173         if (host->vqmmc) {
3174                 regulator_disable(host->vqmmc);
3175                 regulator_put(host->vqmmc);
3176         }
3177
3178         kfree(host->adma_desc);
3179         kfree(host->align_buffer);
3180
3181         host->adma_desc = NULL;
3182         host->align_buffer = NULL;
3183 }
3184
3185 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3186
3187 void sdhci_free_host(struct sdhci_host *host)
3188 {
3189         mmc_free_host(host->mmc);
3190 }
3191
3192 EXPORT_SYMBOL_GPL(sdhci_free_host);
3193
3194 /*****************************************************************************\
3195  *                                                                           *
3196  * Driver init/exit                                                          *
3197  *                                                                           *
3198 \*****************************************************************************/
3199
3200 static int __init sdhci_drv_init(void)
3201 {
3202         pr_info(DRIVER_NAME
3203                 ": Secure Digital Host Controller Interface driver\n");
3204         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3205
3206         return 0;
3207 }
3208
3209 static void __exit sdhci_drv_exit(void)
3210 {
3211 }
3212
3213 module_init(sdhci_drv_init);
3214 module_exit(sdhci_drv_exit);
3215
3216 module_param(debug_quirks, uint, 0444);
3217 module_param(debug_quirks2, uint, 0444);
3218
3219 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3220 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3221 MODULE_LICENSE("GPL");
3222
3223 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3224 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");