drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/ktime.h>
  18 #include <linux/highmem.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/slab.h>
  23 #include <linux/scatterlist.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/of.h>
  27
  28 #include <linux/leds.h>
  29
  30 #include <linux/mmc/mmc.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mmc/sdio.h>
  34 #include <linux/mmc/slot-gpio.h>
  35
  36 #include "sdhci.h"
  37
  38 #define DRIVER_NAME "sdhci"
  39
  40 #define DBG(f, x...) \
  41         pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  42
  43 #define SDHCI_DUMP(f, x...) \
  44         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  54
  55 void sdhci_dumpregs(struct sdhci_host *host)
  56 {
  57         SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
  58
  59         SDHCI_DUMP("Sys addr:  0x%08x | Version:  0x%08x\n",
  60                    sdhci_readl(host, SDHCI_DMA_ADDRESS),
  61                    sdhci_readw(host, SDHCI_HOST_VERSION));
  62         SDHCI_DUMP("Blk size:  0x%08x | Blk cnt:  0x%08x\n",
  63                    sdhci_readw(host, SDHCI_BLOCK_SIZE),
  64                    sdhci_readw(host, SDHCI_BLOCK_COUNT));
  65         SDHCI_DUMP("Argument:  0x%08x | Trn mode: 0x%08x\n",
  66                    sdhci_readl(host, SDHCI_ARGUMENT),
  67                    sdhci_readw(host, SDHCI_TRANSFER_MODE));
  68         SDHCI_DUMP("Present:   0x%08x | Host ctl: 0x%08x\n",
  69                    sdhci_readl(host, SDHCI_PRESENT_STATE),
  70                    sdhci_readb(host, SDHCI_HOST_CONTROL));
  71         SDHCI_DUMP("Power:     0x%08x | Blk gap:  0x%08x\n",
  72                    sdhci_readb(host, SDHCI_POWER_CONTROL),
  73                    sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  74         SDHCI_DUMP("Wake-up:   0x%08x | Clock:    0x%08x\n",
  75                    sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  76                    sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  77         SDHCI_DUMP("Timeout:   0x%08x | Int stat: 0x%08x\n",
  78                    sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  79                    sdhci_readl(host, SDHCI_INT_STATUS));
  80         SDHCI_DUMP("Int enab:  0x%08x | Sig enab: 0x%08x\n",
  81                    sdhci_readl(host, SDHCI_INT_ENABLE),
  82                    sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  83         SDHCI_DUMP("AC12 err:  0x%08x | Slot int: 0x%08x\n",
  84                    sdhci_readw(host, SDHCI_ACMD12_ERR),
  85                    sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  86         SDHCI_DUMP("Caps:      0x%08x | Caps_1:   0x%08x\n",
  87                    sdhci_readl(host, SDHCI_CAPABILITIES),
  88                    sdhci_readl(host, SDHCI_CAPABILITIES_1));
  89         SDHCI_DUMP("Cmd:       0x%08x | Max curr: 0x%08x\n",
  90                    sdhci_readw(host, SDHCI_COMMAND),
  91                    sdhci_readl(host, SDHCI_MAX_CURRENT));
  92         SDHCI_DUMP("Resp[0]:   0x%08x | Resp[1]:  0x%08x\n",
  93                    sdhci_readl(host, SDHCI_RESPONSE),
  94                    sdhci_readl(host, SDHCI_RESPONSE + 4));
  95         SDHCI_DUMP("Resp[2]:   0x%08x | Resp[3]:  0x%08x\n",
  96                    sdhci_readl(host, SDHCI_RESPONSE + 8),
  97                    sdhci_readl(host, SDHCI_RESPONSE + 12));
  98         SDHCI_DUMP("Host ctl2: 0x%08x\n",
  99                    sdhci_readw(host, SDHCI_HOST_CONTROL2));
 100
 101         if (host->flags & SDHCI_USE_ADMA) {
 102                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
 103                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x%08x\n",
 104                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 105                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
 106                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 107                 } else {
 108                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x\n",
 109                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 110                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 111                 }
 112         }
 113
 114         SDHCI_DUMP("============================================\n");
 115 }
 116 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
 117
 118 /*****************************************************************************\
 119  *                                                                           *
 120  * Low level functions                                                       *
 121  *                                                                           *
 122 \*****************************************************************************/
 123
 124 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
 125 {
 126         return cmd->data || cmd->flags & MMC_RSP_BUSY;
 127 }
 128
 129 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 130 {
 131         u32 present;
 132
 133         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 134             !mmc_card_is_removable(host->mmc))
 135                 return;
 136
 137         if (enable) {
 138                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 139                                       SDHCI_CARD_PRESENT;
 140
 141                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 142                                        SDHCI_INT_CARD_INSERT;
 143         } else {
 144                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 145         }
 146
 147         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 148         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 149 }
 150
 151 static void sdhci_enable_card_detection(struct sdhci_host *host)
 152 {
 153         sdhci_set_card_detection(host, true);
 154 }
 155
 156 static void sdhci_disable_card_detection(struct sdhci_host *host)
 157 {
 158         sdhci_set_card_detection(host, false);
 159 }
 160
 161 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 162 {
 163         if (host->bus_on)
 164                 return;
 165         host->bus_on = true;
 166         pm_runtime_get_noresume(host->mmc->parent);
 167 }
 168
 169 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 170 {
 171         if (!host->bus_on)
 172                 return;
 173         host->bus_on = false;
 174         pm_runtime_put_noidle(host->mmc->parent);
 175 }
 176
 177 void sdhci_reset(struct sdhci_host *host, u8 mask)
 178 {
 179         ktime_t timeout;
 180
 181         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 182
 183         if (mask & SDHCI_RESET_ALL) {
 184                 host->clock = 0;
 185                 /* Reset-all turns off SD Bus Power */
 186                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 187                         sdhci_runtime_pm_bus_off(host);
 188         }
 189
 190         /* Wait max 100 ms */
 191         timeout = ktime_add_ms(ktime_get(), 100);
 192
 193         /* hw clears the bit when it's done */
 194         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 195                 if (ktime_after(ktime_get(), timeout)) {
 196                         pr_err("%s: Reset 0x%x never completed.\n",
 197                                 mmc_hostname(host->mmc), (int)mask);
 198                         sdhci_dumpregs(host);
 199                         return;
 200                 }
 201                 udelay(10);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 struct mmc_host *mmc = host->mmc;
 210
 211                 if (!mmc->ops->get_cd(mmc))
 212                         return;
 213         }
 214
 215         host->ops->reset(host, mask);
 216
 217         if (mask & SDHCI_RESET_ALL) {
 218                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 219                         if (host->ops->enable_dma)
 220                                 host->ops->enable_dma(host);
 221                 }
 222
 223                 /* Resetting the controller clears many */
 224                 host->preset_enabled = false;
 225         }
 226 }
 227
 228 static void sdhci_set_default_irqs(struct sdhci_host *host)
 229 {
 230         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 231                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 232                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 233                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 234                     SDHCI_INT_RESPONSE;
 235
 236         if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
 237             host->tuning_mode == SDHCI_TUNING_MODE_3)
 238                 host->ier |= SDHCI_INT_RETUNE;
 239
 240         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 241         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 242 }
 243
 244 static void sdhci_init(struct sdhci_host *host, int soft)
 245 {
 246         struct mmc_host *mmc = host->mmc;
 247
 248         if (soft)
 249                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 250         else
 251                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 252
 253         sdhci_set_default_irqs(host);
 254
 255         host->cqe_on = false;
 256
 257         if (soft) {
 258                 /* force clock reconfiguration */
 259                 host->clock = 0;
 260                 mmc->ops->set_ios(mmc, &mmc->ios);
 261         }
 262 }
 263
 264 static void sdhci_reinit(struct sdhci_host *host)
 265 {
 266         sdhci_init(host, 0);
 267         sdhci_enable_card_detection(host);
 268 }
 269
 270 static void __sdhci_led_activate(struct sdhci_host *host)
 271 {
 272         u8 ctrl;
 273
 274         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 275         ctrl |= SDHCI_CTRL_LED;
 276         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 277 }
 278
 279 static void __sdhci_led_deactivate(struct sdhci_host *host)
 280 {
 281         u8 ctrl;
 282
 283         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 284         ctrl &= ~SDHCI_CTRL_LED;
 285         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 286 }
 287
 288 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
 289 static void sdhci_led_control(struct led_classdev *led,
 290                               enum led_brightness brightness)
 291 {
 292         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 293         unsigned long flags;
 294
 295         spin_lock_irqsave(&host->lock, flags);
 296
 297         if (host->runtime_suspended)
 298                 goto out;
 299
 300         if (brightness == LED_OFF)
 301                 __sdhci_led_deactivate(host);
 302         else
 303                 __sdhci_led_activate(host);
 304 out:
 305         spin_unlock_irqrestore(&host->lock, flags);
 306 }
 307
 308 static int sdhci_led_register(struct sdhci_host *host)
 309 {
 310         struct mmc_host *mmc = host->mmc;
 311
 312         snprintf(host->led_name, sizeof(host->led_name),
 313                  "%s::", mmc_hostname(mmc));
 314
 315         host->led.name = host->led_name;
 316         host->led.brightness = LED_OFF;
 317         host->led.default_trigger = mmc_hostname(mmc);
 318         host->led.brightness_set = sdhci_led_control;
 319
 320         return led_classdev_register(mmc_dev(mmc), &host->led);
 321 }
 322
 323 static void sdhci_led_unregister(struct sdhci_host *host)
 324 {
 325         led_classdev_unregister(&host->led);
 326 }
 327
 328 static inline void sdhci_led_activate(struct sdhci_host *host)
 329 {
 330 }
 331
 332 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 333 {
 334 }
 335
 336 #else
 337
 338 static inline int sdhci_led_register(struct sdhci_host *host)
 339 {
 340         return 0;
 341 }
 342
 343 static inline void sdhci_led_unregister(struct sdhci_host *host)
 344 {
 345 }
 346
 347 static inline void sdhci_led_activate(struct sdhci_host *host)
 348 {
 349         __sdhci_led_activate(host);
 350 }
 351
 352 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 353 {
 354         __sdhci_led_deactivate(host);
 355 }
 356
 357 #endif
 358
 359 /*****************************************************************************\
 360  *                                                                           *
 361  * Core functions                                                            *
 362  *                                                                           *
 363 \*****************************************************************************/
 364
 365 static void sdhci_read_block_pio(struct sdhci_host *host)
 366 {
 367         unsigned long flags;
 368         size_t blksize, len, chunk;
 369         u32 uninitialized_var(scratch);
 370         u8 *buf;
 371
 372         DBG("PIO reading\n");
 373
 374         blksize = host->data->blksz;
 375         chunk = 0;
 376
 377         local_irq_save(flags);
 378
 379         while (blksize) {
 380                 BUG_ON(!sg_miter_next(&host->sg_miter));
 381
 382                 len = min(host->sg_miter.length, blksize);
 383
 384                 blksize -= len;
 385                 host->sg_miter.consumed = len;
 386
 387                 buf = host->sg_miter.addr;
 388
 389                 while (len) {
 390                         if (chunk == 0) {
 391                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 392                                 chunk = 4;
 393                         }
 394
 395                         *buf = scratch & 0xFF;
 396
 397                         buf++;
 398                         scratch >>= 8;
 399                         chunk--;
 400                         len--;
 401                 }
 402         }
 403
 404         sg_miter_stop(&host->sg_miter);
 405
 406         local_irq_restore(flags);
 407 }
 408
 409 static void sdhci_write_block_pio(struct sdhci_host *host)
 410 {
 411         unsigned long flags;
 412         size_t blksize, len, chunk;
 413         u32 scratch;
 414         u8 *buf;
 415
 416         DBG("PIO writing\n");
 417
 418         blksize = host->data->blksz;
 419         chunk = 0;
 420         scratch = 0;
 421
 422         local_irq_save(flags);
 423
 424         while (blksize) {
 425                 BUG_ON(!sg_miter_next(&host->sg_miter));
 426
 427                 len = min(host->sg_miter.length, blksize);
 428
 429                 blksize -= len;
 430                 host->sg_miter.consumed = len;
 431
 432                 buf = host->sg_miter.addr;
 433
 434                 while (len) {
 435                         scratch |= (u32)*buf << (chunk * 8);
 436
 437                         buf++;
 438                         chunk++;
 439                         len--;
 440
 441                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 442                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 443                                 chunk = 0;
 444                                 scratch = 0;
 445                         }
 446                 }
 447         }
 448
 449         sg_miter_stop(&host->sg_miter);
 450
 451         local_irq_restore(flags);
 452 }
 453
 454 static void sdhci_transfer_pio(struct sdhci_host *host)
 455 {
 456         u32 mask;
 457
 458         if (host->blocks == 0)
 459                 return;
 460
 461         if (host->data->flags & MMC_DATA_READ)
 462                 mask = SDHCI_DATA_AVAILABLE;
 463         else
 464                 mask = SDHCI_SPACE_AVAILABLE;
 465
 466         /*
 467          * Some controllers (JMicron JMB38x) mess up the buffer bits
 468          * for transfers < 4 bytes. As long as it is just one block,
 469          * we can ignore the bits.
 470          */
 471         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 472                 (host->data->blocks == 1))
 473                 mask = ~0;
 474
 475         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 476                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 477                         udelay(100);
 478
 479                 if (host->data->flags & MMC_DATA_READ)
 480                         sdhci_read_block_pio(host);
 481                 else
 482                         sdhci_write_block_pio(host);
 483
 484                 host->blocks--;
 485                 if (host->blocks == 0)
 486                         break;
 487         }
 488
 489         DBG("PIO transfer complete.\n");
 490 }
 491
 492 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 493                                   struct mmc_data *data, int cookie)
 494 {
 495         int sg_count;
 496
 497         /*
 498          * If the data buffers are already mapped, return the previous
 499          * dma_map_sg() result.
 500          */
 501         if (data->host_cookie == COOKIE_PRE_MAPPED)
 502                 return data->sg_count;
 503
 504         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 505                                 data->flags & MMC_DATA_WRITE ?
 506                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
 507
 508         if (sg_count == 0)
 509                 return -ENOSPC;
 510
 511         data->sg_count = sg_count;
 512         data->host_cookie = cookie;
 513
 514         return sg_count;
 515 }
 516
 517 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 518 {
 519         local_irq_save(*flags);
 520         return kmap_atomic(sg_page(sg)) + sg->offset;
 521 }
 522
 523 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 524 {
 525         kunmap_atomic(buffer);
 526         local_irq_restore(*flags);
 527 }
 528
 529 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 530                                   dma_addr_t addr, int len, unsigned cmd)
 531 {
 532         struct sdhci_adma2_64_desc *dma_desc = desc;
 533
 534         /* 32-bit and 64-bit descriptors have these members in same position */
 535         dma_desc->cmd = cpu_to_le16(cmd);
 536         dma_desc->len = cpu_to_le16(len);
 537         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 538
 539         if (host->flags & SDHCI_USE_64_BIT_DMA)
 540                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 541 }
 542
 543 static void sdhci_adma_mark_end(void *desc)
 544 {
 545         struct sdhci_adma2_64_desc *dma_desc = desc;
 546
 547         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 548         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 549 }
 550
 551 static void sdhci_adma_table_pre(struct sdhci_host *host,
 552         struct mmc_data *data, int sg_count)
 553 {
 554         struct scatterlist *sg;
 555         unsigned long flags;
 556         dma_addr_t addr, align_addr;
 557         void *desc, *align;
 558         char *buffer;
 559         int len, offset, i;
 560
 561         /*
 562          * The spec does not specify endianness of descriptor table.
 563          * We currently guess that it is LE.
 564          */
 565
 566         host->sg_count = sg_count;
 567
 568         desc = host->adma_table;
 569         align = host->align_buffer;
 570
 571         align_addr = host->align_addr;
 572
 573         for_each_sg(data->sg, sg, host->sg_count, i) {
 574                 addr = sg_dma_address(sg);
 575                 len = sg_dma_len(sg);
 576
 577                 /*
 578                  * The SDHCI specification states that ADMA addresses must
 579                  * be 32-bit aligned. If they aren't, then we use a bounce
 580                  * buffer for the (up to three) bytes that screw up the
 581                  * alignment.
 582                  */
 583                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 584                          SDHCI_ADMA2_MASK;
 585                 if (offset) {
 586                         if (data->flags & MMC_DATA_WRITE) {
 587                                 buffer = sdhci_kmap_atomic(sg, &flags);
 588                                 memcpy(align, buffer, offset);
 589                                 sdhci_kunmap_atomic(buffer, &flags);
 590                         }
 591
 592                         /* tran, valid */
 593                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 594                                               ADMA2_TRAN_VALID);
 595
 596                         BUG_ON(offset > 65536);
 597
 598                         align += SDHCI_ADMA2_ALIGN;
 599                         align_addr += SDHCI_ADMA2_ALIGN;
 600
 601                         desc += host->desc_sz;
 602
 603                         addr += offset;
 604                         len -= offset;
 605                 }
 606
 607                 BUG_ON(len > 65536);
 608
 609                 if (len) {
 610                         /* tran, valid */
 611                         sdhci_adma_write_desc(host, desc, addr, len,
 612                                               ADMA2_TRAN_VALID);
 613                         desc += host->desc_sz;
 614                 }
 615
 616                 /*
 617                  * If this triggers then we have a calculation bug
 618                  * somewhere. :/
 619                  */
 620                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 621         }
 622
 623         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 624                 /* Mark the last descriptor as the terminating descriptor */
 625                 if (desc != host->adma_table) {
 626                         desc -= host->desc_sz;
 627                         sdhci_adma_mark_end(desc);
 628                 }
 629         } else {
 630                 /* Add a terminating entry - nop, end, valid */
 631                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 632         }
 633 }
 634
 635 static void sdhci_adma_table_post(struct sdhci_host *host,
 636         struct mmc_data *data)
 637 {
 638         struct scatterlist *sg;
 639         int i, size;
 640         void *align;
 641         char *buffer;
 642         unsigned long flags;
 643
 644         if (data->flags & MMC_DATA_READ) {
 645                 bool has_unaligned = false;
 646
 647                 /* Do a quick scan of the SG list for any unaligned mappings */
 648                 for_each_sg(data->sg, sg, host->sg_count, i)
 649                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 650                                 has_unaligned = true;
 651                                 break;
 652                         }
 653
 654                 if (has_unaligned) {
 655                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 656                                             data->sg_len, DMA_FROM_DEVICE);
 657
 658                         align = host->align_buffer;
 659
 660                         for_each_sg(data->sg, sg, host->sg_count, i) {
 661                                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 662                                         size = SDHCI_ADMA2_ALIGN -
 663                                                (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 664
 665                                         buffer = sdhci_kmap_atomic(sg, &flags);
 666                                         memcpy(buffer, align, size);
 667                                         sdhci_kunmap_atomic(buffer, &flags);
 668
 669                                         align += SDHCI_ADMA2_ALIGN;
 670                                 }
 671                         }
 672                 }
 673         }
 674 }
 675
 676 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 677 {
 678         u8 count;
 679         struct mmc_data *data = cmd->data;
 680         unsigned target_timeout, current_timeout;
 681
 682         /*
 683          * If the host controller provides us with an incorrect timeout
 684          * value, just skip the check and use 0xE.  The hardware may take
 685          * longer to time out, but that's much better than having a too-short
 686          * timeout value.
 687          */
 688         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 689                 return 0xE;
 690
 691         /* Unspecified timeout, assume max */
 692         if (!data && !cmd->busy_timeout)
 693                 return 0xE;
 694
 695         /* timeout in us */
 696         if (!data)
 697                 target_timeout = cmd->busy_timeout * 1000;
 698         else {
 699                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
 700                 if (host->clock && data->timeout_clks) {
 701                         unsigned long long val;
 702
 703                         /*
 704                          * data->timeout_clks is in units of clock cycles.
 705                          * host->clock is in Hz.  target_timeout is in us.
 706                          * Hence, us = 1000000 * cycles / Hz.  Round up.
 707                          */
 708                         val = 1000000ULL * data->timeout_clks;
 709                         if (do_div(val, host->clock))
 710                                 target_timeout++;
 711                         target_timeout += val;
 712                 }
 713         }
 714
 715         /*
 716          * Figure out needed cycles.
 717          * We do this in steps in order to fit inside a 32 bit int.
 718          * The first step is the minimum timeout, which will have a
 719          * minimum resolution of 6 bits:
 720          * (1) 2^13*1000 > 2^22,
 721          * (2) host->timeout_clk < 2^16
 722          *     =>
 723          *     (1) / (2) > 2^6
 724          */
 725         count = 0;
 726         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 727         while (current_timeout < target_timeout) {
 728                 count++;
 729                 current_timeout <<= 1;
 730                 if (count >= 0xF)
 731                         break;
 732         }
 733
 734         if (count >= 0xF) {
 735                 DBG("Too large timeout 0x%x requested for CMD%d!\n",
 736                     count, cmd->opcode);
 737                 count = 0xE;
 738         }
 739
 740         return count;
 741 }
 742
 743 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 744 {
 745         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 746         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 747
 748         if (host->flags & SDHCI_REQ_USE_DMA)
 749                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 750         else
 751                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 752
 753         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 754         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 755 }
 756
 757 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 758 {
 759         u8 count;
 760
 761         if (host->ops->set_timeout) {
 762                 host->ops->set_timeout(host, cmd);
 763         } else {
 764                 count = sdhci_calc_timeout(host, cmd);
 765                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 766         }
 767 }
 768
 769 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 770 {
 771         u8 ctrl;
 772         struct mmc_data *data = cmd->data;
 773
 774         if (sdhci_data_line_cmd(cmd))
 775                 sdhci_set_timeout(host, cmd);
 776
 777         if (!data)
 778                 return;
 779
 780         WARN_ON(host->data);
 781
 782         /* Sanity checks */
 783         BUG_ON(data->blksz * data->blocks > 524288);
 784         BUG_ON(data->blksz > host->mmc->max_blk_size);
 785         BUG_ON(data->blocks > 65535);
 786
 787         host->data = data;
 788         host->data_early = 0;
 789         host->data->bytes_xfered = 0;
 790
 791         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 792                 struct scatterlist *sg;
 793                 unsigned int length_mask, offset_mask;
 794                 int i;
 795
 796                 host->flags |= SDHCI_REQ_USE_DMA;
 797
 798                 /*
 799                  * FIXME: This doesn't account for merging when mapping the
 800                  * scatterlist.
 801                  *
 802                  * The assumption here being that alignment and lengths are
 803                  * the same after DMA mapping to device address space.
 804                  */
 805                 length_mask = 0;
 806                 offset_mask = 0;
 807                 if (host->flags & SDHCI_USE_ADMA) {
 808                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
 809                                 length_mask = 3;
 810                                 /*
 811                                  * As we use up to 3 byte chunks to work
 812                                  * around alignment problems, we need to
 813                                  * check the offset as well.
 814                                  */
 815                                 offset_mask = 3;
 816                         }
 817                 } else {
 818                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 819                                 length_mask = 3;
 820                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 821                                 offset_mask = 3;
 822                 }
 823
 824                 if (unlikely(length_mask | offset_mask)) {
 825                         for_each_sg(data->sg, sg, data->sg_len, i) {
 826                                 if (sg->length & length_mask) {
 827                                         DBG("Reverting to PIO because of transfer size (%d)\n",
 828                                             sg->length);
 829                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 830                                         break;
 831                                 }
 832                                 if (sg->offset & offset_mask) {
 833                                         DBG("Reverting to PIO because of bad alignment\n");
 834                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 835                                         break;
 836                                 }
 837                         }
 838                 }
 839         }
 840
 841         if (host->flags & SDHCI_REQ_USE_DMA) {
 842                 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
 843
 844                 if (sg_cnt <= 0) {
 845                         /*
 846                          * This only happens when someone fed
 847                          * us an invalid request.
 848                          */
 849                         WARN_ON(1);
 850                         host->flags &= ~SDHCI_REQ_USE_DMA;
 851                 } else if (host->flags & SDHCI_USE_ADMA) {
 852                         sdhci_adma_table_pre(host, data, sg_cnt);
 853
 854                         sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
 855                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 856                                 sdhci_writel(host,
 857                                              (u64)host->adma_addr >> 32,
 858                                              SDHCI_ADMA_ADDRESS_HI);
 859                 } else {
 860                         WARN_ON(sg_cnt != 1);
 861                         sdhci_writel(host, sg_dma_address(data->sg),
 862                                 SDHCI_DMA_ADDRESS);
 863                 }
 864         }
 865
 866         /*
 867          * Always adjust the DMA selection as some controllers
 868          * (e.g. JMicron) can't do PIO properly when the selection
 869          * is ADMA.
 870          */
 871         if (host->version >= SDHCI_SPEC_200) {
 872                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 873                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 874                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 875                         (host->flags & SDHCI_USE_ADMA)) {
 876                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 877                                 ctrl |= SDHCI_CTRL_ADMA64;
 878                         else
 879                                 ctrl |= SDHCI_CTRL_ADMA32;
 880                 } else {
 881                         ctrl |= SDHCI_CTRL_SDMA;
 882                 }
 883                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 884         }
 885
 886         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 887                 int flags;
 888
 889                 flags = SG_MITER_ATOMIC;
 890                 if (host->data->flags & MMC_DATA_READ)
 891                         flags |= SG_MITER_TO_SG;
 892                 else
 893                         flags |= SG_MITER_FROM_SG;
 894                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 895                 host->blocks = data->blocks;
 896         }
 897
 898         sdhci_set_transfer_irqs(host);
 899
 900         /* Set the DMA boundary value and block size */
 901         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 902                 data->blksz), SDHCI_BLOCK_SIZE);
 903         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 904 }
 905
 906 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
 907                                     struct mmc_request *mrq)
 908 {
 909         return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 910                !mrq->cap_cmd_during_tfr;
 911 }
 912
 913 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 914         struct mmc_command *cmd)
 915 {
 916         u16 mode = 0;
 917         struct mmc_data *data = cmd->data;
 918
 919         if (data == NULL) {
 920                 if (host->quirks2 &
 921                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 922                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 923                 } else {
 924                 /* clear Auto CMD settings for no data CMDs */
 925                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 926                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 927                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 928                 }
 929                 return;
 930         }
 931
 932         WARN_ON(!host->data);
 933
 934         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 935                 mode = SDHCI_TRNS_BLK_CNT_EN;
 936
 937         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 938                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 939                 /*
 940                  * If we are sending CMD23, CMD12 never gets sent
 941                  * on successful completion (so no Auto-CMD12).
 942                  */
 943                 if (sdhci_auto_cmd12(host, cmd->mrq) &&
 944                     (cmd->opcode != SD_IO_RW_EXTENDED))
 945                         mode |= SDHCI_TRNS_AUTO_CMD12;
 946                 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 947                         mode |= SDHCI_TRNS_AUTO_CMD23;
 948                         sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
 949                 }
 950         }
 951
 952         if (data->flags & MMC_DATA_READ)
 953                 mode |= SDHCI_TRNS_READ;
 954         if (host->flags & SDHCI_REQ_USE_DMA)
 955                 mode |= SDHCI_TRNS_DMA;
 956
 957         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 958 }
 959
 960 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
 961 {
 962         return (!(host->flags & SDHCI_DEVICE_DEAD) &&
 963                 ((mrq->cmd && mrq->cmd->error) ||
 964                  (mrq->sbc && mrq->sbc->error) ||
 965                  (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
 966                                 (mrq->data->stop && mrq->data->stop->error))) ||
 967                  (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
 968 }
 969
 970 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
 971 {
 972         int i;
 973
 974         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
 975                 if (host->mrqs_done[i] == mrq) {
 976                         WARN_ON(1);
 977                         return;
 978                 }
 979         }
 980
 981         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
 982                 if (!host->mrqs_done[i]) {
 983                         host->mrqs_done[i] = mrq;
 984                         break;
 985                 }
 986         }
 987
 988         WARN_ON(i >= SDHCI_MAX_MRQS);
 989
 990         tasklet_schedule(&host->finish_tasklet);
 991 }
 992
 993 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
 994 {
 995         if (host->cmd && host->cmd->mrq == mrq)
 996                 host->cmd = NULL;
 997
 998         if (host->data_cmd && host->data_cmd->mrq == mrq)
 999                 host->data_cmd = NULL;
1000
1001         if (host->data && host->data->mrq == mrq)
1002                 host->data = NULL;
1003
1004         if (sdhci_needs_reset(host, mrq))
1005                 host->pending_reset = true;
1006
1007         __sdhci_finish_mrq(host, mrq);
1008 }
1009
1010 static void sdhci_finish_data(struct sdhci_host *host)
1011 {
1012         struct mmc_command *data_cmd = host->data_cmd;
1013         struct mmc_data *data = host->data;
1014
1015         host->data = NULL;
1016         host->data_cmd = NULL;
1017
1018         if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1019             (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1020                 sdhci_adma_table_post(host, data);
1021
1022         /*
1023          * The specification states that the block count register must
1024          * be updated, but it does not specify at what point in the
1025          * data flow. That makes the register entirely useless to read
1026          * back so we have to assume that nothing made it to the card
1027          * in the event of an error.
1028          */
1029         if (data->error)
1030                 data->bytes_xfered = 0;
1031         else
1032                 data->bytes_xfered = data->blksz * data->blocks;
1033
1034         /*
1035          * Need to send CMD12 if -
1036          * a) open-ended multiblock transfer (no CMD23)
1037          * b) error in multiblock transfer
1038          */
1039         if (data->stop &&
1040             (data->error ||
1041              !data->mrq->sbc)) {
1042
1043                 /*
1044                  * The controller needs a reset of internal state machines
1045                  * upon error conditions.
1046                  */
1047                 if (data->error) {
1048                         if (!host->cmd || host->cmd == data_cmd)
1049                                 sdhci_do_reset(host, SDHCI_RESET_CMD);
1050                         sdhci_do_reset(host, SDHCI_RESET_DATA);
1051                 }
1052
1053                 /*
1054                  * 'cap_cmd_during_tfr' request must not use the command line
1055                  * after mmc_command_done() has been called. It is upper layer's
1056                  * responsibility to send the stop command if required.
1057                  */
1058                 if (data->mrq->cap_cmd_during_tfr) {
1059                         sdhci_finish_mrq(host, data->mrq);
1060                 } else {
1061                         /* Avoid triggering warning in sdhci_send_command() */
1062                         host->cmd = NULL;
1063                         sdhci_send_command(host, data->stop);
1064                 }
1065         } else {
1066                 sdhci_finish_mrq(host, data->mrq);
1067         }
1068 }
1069
1070 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1071                             unsigned long timeout)
1072 {
1073         if (sdhci_data_line_cmd(mrq->cmd))
1074                 mod_timer(&host->data_timer, timeout);
1075         else
1076                 mod_timer(&host->timer, timeout);
1077 }
1078
1079 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1080 {
1081         if (sdhci_data_line_cmd(mrq->cmd))
1082                 del_timer(&host->data_timer);
1083         else
1084                 del_timer(&host->timer);
1085 }
1086
1087 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1088 {
1089         int flags;
1090         u32 mask;
1091         unsigned long timeout;
1092
1093         WARN_ON(host->cmd);
1094
1095         /* Initially, a command has no error */
1096         cmd->error = 0;
1097
1098         if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1099             cmd->opcode == MMC_STOP_TRANSMISSION)
1100                 cmd->flags |= MMC_RSP_BUSY;
1101
1102         /* Wait max 10 ms */
1103         timeout = 10;
1104
1105         mask = SDHCI_CMD_INHIBIT;
1106         if (sdhci_data_line_cmd(cmd))
1107                 mask |= SDHCI_DATA_INHIBIT;
1108
1109         /* We shouldn't wait for data inihibit for stop commands, even
1110            though they might use busy signaling */
1111         if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1112                 mask &= ~SDHCI_DATA_INHIBIT;
1113
1114         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1115                 if (timeout == 0) {
1116                         pr_err("%s: Controller never released inhibit bit(s).\n",
1117                                mmc_hostname(host->mmc));
1118                         sdhci_dumpregs(host);
1119                         cmd->error = -EIO;
1120                         sdhci_finish_mrq(host, cmd->mrq);
1121                         return;
1122                 }
1123                 timeout--;
1124                 mdelay(1);
1125         }
1126
1127         timeout = jiffies;
1128         if (!cmd->data && cmd->busy_timeout > 9000)
1129                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1130         else
1131                 timeout += 10 * HZ;
1132         sdhci_mod_timer(host, cmd->mrq, timeout);
1133
1134         host->cmd = cmd;
1135         if (sdhci_data_line_cmd(cmd)) {
1136                 WARN_ON(host->data_cmd);
1137                 host->data_cmd = cmd;
1138         }
1139
1140         sdhci_prepare_data(host, cmd);
1141
1142         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1143
1144         sdhci_set_transfer_mode(host, cmd);
1145
1146         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1147                 pr_err("%s: Unsupported response type!\n",
1148                         mmc_hostname(host->mmc));
1149                 cmd->error = -EINVAL;
1150                 sdhci_finish_mrq(host, cmd->mrq);
1151                 return;
1152         }
1153
1154         if (!(cmd->flags & MMC_RSP_PRESENT))
1155                 flags = SDHCI_CMD_RESP_NONE;
1156         else if (cmd->flags & MMC_RSP_136)
1157                 flags = SDHCI_CMD_RESP_LONG;
1158         else if (cmd->flags & MMC_RSP_BUSY)
1159                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1160         else
1161                 flags = SDHCI_CMD_RESP_SHORT;
1162
1163         if (cmd->flags & MMC_RSP_CRC)
1164                 flags |= SDHCI_CMD_CRC;
1165         if (cmd->flags & MMC_RSP_OPCODE)
1166                 flags |= SDHCI_CMD_INDEX;
1167
1168         /* CMD19 is special in that the Data Present Select should be set */
1169         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1170             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1171                 flags |= SDHCI_CMD_DATA;
1172
1173         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1174 }
1175 EXPORT_SYMBOL_GPL(sdhci_send_command);
1176
1177 static void sdhci_finish_command(struct sdhci_host *host)
1178 {
1179         struct mmc_command *cmd = host->cmd;
1180         int i;
1181
1182         host->cmd = NULL;
1183
1184         if (cmd->flags & MMC_RSP_PRESENT) {
1185                 if (cmd->flags & MMC_RSP_136) {
1186                         /* CRC is stripped so we need to do some shifting. */
1187                         for (i = 0;i < 4;i++) {
1188                                 cmd->resp[i] = sdhci_readl(host,
1189                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1190                                 if (i != 3)
1191                                         cmd->resp[i] |=
1192                                                 sdhci_readb(host,
1193                                                 SDHCI_RESPONSE + (3-i)*4-1);
1194                         }
1195                 } else {
1196                         cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1197                 }
1198         }
1199
1200         if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1201                 mmc_command_done(host->mmc, cmd->mrq);
1202
1203         /*
1204          * The host can send and interrupt when the busy state has
1205          * ended, allowing us to wait without wasting CPU cycles.
1206          * The busy signal uses DAT0 so this is similar to waiting
1207          * for data to complete.
1208          *
1209          * Note: The 1.0 specification is a bit ambiguous about this
1210          *       feature so there might be some problems with older
1211          *       controllers.
1212          */
1213         if (cmd->flags & MMC_RSP_BUSY) {
1214                 if (cmd->data) {
1215                         DBG("Cannot wait for busy signal when also doing a data transfer");
1216                 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1217                            cmd == host->data_cmd) {
1218                         /* Command complete before busy is ended */
1219                         return;
1220                 }
1221         }
1222
1223         /* Finished CMD23, now send actual command. */
1224         if (cmd == cmd->mrq->sbc) {
1225                 sdhci_send_command(host, cmd->mrq->cmd);
1226         } else {
1227
1228                 /* Processed actual command. */
1229                 if (host->data && host->data_early)
1230                         sdhci_finish_data(host);
1231
1232                 if (!cmd->data)
1233                         sdhci_finish_mrq(host, cmd->mrq);
1234         }
1235 }
1236
1237 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1238 {
1239         u16 preset = 0;
1240
1241         switch (host->timing) {
1242         case MMC_TIMING_UHS_SDR12:
1243                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1244                 break;
1245         case MMC_TIMING_UHS_SDR25:
1246                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1247                 break;
1248         case MMC_TIMING_UHS_SDR50:
1249                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1250                 break;
1251         case MMC_TIMING_UHS_SDR104:
1252         case MMC_TIMING_MMC_HS200:
1253                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1254                 break;
1255         case MMC_TIMING_UHS_DDR50:
1256         case MMC_TIMING_MMC_DDR52:
1257                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1258                 break;
1259         case MMC_TIMING_MMC_HS400:
1260                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1261                 break;
1262         default:
1263                 pr_warn("%s: Invalid UHS-I mode selected\n",
1264                         mmc_hostname(host->mmc));
1265                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1266                 break;
1267         }
1268         return preset;
1269 }
1270
1271 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1272                    unsigned int *actual_clock)
1273 {
1274         int div = 0; /* Initialized for compiler warning */
1275         int real_div = div, clk_mul = 1;
1276         u16 clk = 0;
1277         bool switch_base_clk = false;
1278
1279         if (host->version >= SDHCI_SPEC_300) {
1280                 if (host->preset_enabled) {
1281                         u16 pre_val;
1282
1283                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1284                         pre_val = sdhci_get_preset_value(host);
1285                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1286                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1287                         if (host->clk_mul &&
1288                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1289                                 clk = SDHCI_PROG_CLOCK_MODE;
1290                                 real_div = div + 1;
1291                                 clk_mul = host->clk_mul;
1292                         } else {
1293                                 real_div = max_t(int, 1, div << 1);
1294                         }
1295                         goto clock_set;
1296                 }
1297
1298                 /*
1299                  * Check if the Host Controller supports Programmable Clock
1300                  * Mode.
1301                  */
1302                 if (host->clk_mul) {
1303                         for (div = 1; div <= 1024; div++) {
1304                                 if ((host->max_clk * host->clk_mul / div)
1305                                         <= clock)
1306                                         break;
1307                         }
1308                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1309                                 /*
1310                                  * Set Programmable Clock Mode in the Clock
1311                                  * Control register.
1312                                  */
1313                                 clk = SDHCI_PROG_CLOCK_MODE;
1314                                 real_div = div;
1315                                 clk_mul = host->clk_mul;
1316                                 div--;
1317                         } else {
1318                                 /*
1319                                  * Divisor can be too small to reach clock
1320                                  * speed requirement. Then use the base clock.
1321                                  */
1322                                 switch_base_clk = true;
1323                         }
1324                 }
1325
1326                 if (!host->clk_mul || switch_base_clk) {
1327                         /* Version 3.00 divisors must be a multiple of 2. */
1328                         if (host->max_clk <= clock)
1329                                 div = 1;
1330                         else {
1331                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1332                                      div += 2) {
1333                                         if ((host->max_clk / div) <= clock)
1334                                                 break;
1335                                 }
1336                         }
1337                         real_div = div;
1338                         div >>= 1;
1339                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1340                                 && !div && host->max_clk <= 25000000)
1341                                 div = 1;
1342                 }
1343         } else {
1344                 /* Version 2.00 divisors must be a power of 2. */
1345                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1346                         if ((host->max_clk / div) <= clock)
1347                                 break;
1348                 }
1349                 real_div = div;
1350                 div >>= 1;
1351         }
1352
1353 clock_set:
1354         if (real_div)
1355                 *actual_clock = (host->max_clk * clk_mul) / real_div;
1356         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1357         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1358                 << SDHCI_DIVIDER_HI_SHIFT;
1359
1360         return clk;
1361 }
1362 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1363
1364 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1365 {
1366         ktime_t timeout;
1367
1368         clk |= SDHCI_CLOCK_INT_EN;
1369         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1370
1371         /* Wait max 20 ms */
1372         timeout = ktime_add_ms(ktime_get(), 20);
1373         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1374                 & SDHCI_CLOCK_INT_STABLE)) {
1375                 if (ktime_after(ktime_get(), timeout)) {
1376                         pr_err("%s: Internal clock never stabilised.\n",
1377                                mmc_hostname(host->mmc));
1378                         sdhci_dumpregs(host);
1379                         return;
1380                 }
1381                 udelay(10);
1382         }
1383
1384         clk |= SDHCI_CLOCK_CARD_EN;
1385         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1386 }
1387 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1388
1389 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1390 {
1391         u16 clk;
1392
1393         host->mmc->actual_clock = 0;
1394
1395         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1396
1397         if (clock == 0)
1398                 return;
1399
1400         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1401         sdhci_enable_clk(host, clk);
1402 }
1403 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1404
1405 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1406                                 unsigned short vdd)
1407 {
1408         struct mmc_host *mmc = host->mmc;
1409
1410         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1411
1412         if (mode != MMC_POWER_OFF)
1413                 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1414         else
1415                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1416 }
1417
1418 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1419                            unsigned short vdd)
1420 {
1421         u8 pwr = 0;
1422
1423         if (mode != MMC_POWER_OFF) {
1424                 switch (1 << vdd) {
1425                 case MMC_VDD_165_195:
1426                         pwr = SDHCI_POWER_180;
1427                         break;
1428                 case MMC_VDD_29_30:
1429                 case MMC_VDD_30_31:
1430                         pwr = SDHCI_POWER_300;
1431                         break;
1432                 case MMC_VDD_32_33:
1433                 case MMC_VDD_33_34:
1434                         pwr = SDHCI_POWER_330;
1435                         break;
1436                 default:
1437                         WARN(1, "%s: Invalid vdd %#x\n",
1438                              mmc_hostname(host->mmc), vdd);
1439                         break;
1440                 }
1441         }
1442
1443         if (host->pwr == pwr)
1444                 return;
1445
1446         host->pwr = pwr;
1447
1448         if (pwr == 0) {
1449                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1450                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1451                         sdhci_runtime_pm_bus_off(host);
1452         } else {
1453                 /*
1454                  * Spec says that we should clear the power reg before setting
1455                  * a new value. Some controllers don't seem to like this though.
1456                  */
1457                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1458                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1459
1460                 /*
1461                  * At least the Marvell CaFe chip gets confused if we set the
1462                  * voltage and set turn on power at the same time, so set the
1463                  * voltage first.
1464                  */
1465                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1466                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1467
1468                 pwr |= SDHCI_POWER_ON;
1469
1470                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1471
1472                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1473                         sdhci_runtime_pm_bus_on(host);
1474
1475                 /*
1476                  * Some controllers need an extra 10ms delay of 10ms before
1477                  * they can apply clock after applying power
1478                  */
1479                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1480                         mdelay(10);
1481         }
1482 }
1483 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1484
1485 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1486                      unsigned short vdd)
1487 {
1488         if (IS_ERR(host->mmc->supply.vmmc))
1489                 sdhci_set_power_noreg(host, mode, vdd);
1490         else
1491                 sdhci_set_power_reg(host, mode, vdd);
1492 }
1493 EXPORT_SYMBOL_GPL(sdhci_set_power);
1494
1495 /*****************************************************************************\
1496  *                                                                           *
1497  * MMC callbacks                                                             *
1498  *                                                                           *
1499 \*****************************************************************************/
1500
1501 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1502 {
1503         struct sdhci_host *host;
1504         int present;
1505         unsigned long flags;
1506
1507         host = mmc_priv(mmc);
1508
1509         /* Firstly check card presence */
1510         present = mmc->ops->get_cd(mmc);
1511
1512         spin_lock_irqsave(&host->lock, flags);
1513
1514         sdhci_led_activate(host);
1515
1516         /*
1517          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1518          * requests if Auto-CMD12 is enabled.
1519          */
1520         if (sdhci_auto_cmd12(host, mrq)) {
1521                 if (mrq->stop) {
1522                         mrq->data->stop = NULL;
1523                         mrq->stop = NULL;
1524                 }
1525         }
1526
1527         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1528                 mrq->cmd->error = -ENOMEDIUM;
1529                 sdhci_finish_mrq(host, mrq);
1530         } else {
1531                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1532                         sdhci_send_command(host, mrq->sbc);
1533                 else
1534                         sdhci_send_command(host, mrq->cmd);
1535         }
1536
1537         mmiowb();
1538         spin_unlock_irqrestore(&host->lock, flags);
1539 }
1540
1541 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1542 {
1543         u8 ctrl;
1544
1545         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1546         if (width == MMC_BUS_WIDTH_8) {
1547                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1548                 if (host->version >= SDHCI_SPEC_300)
1549                         ctrl |= SDHCI_CTRL_8BITBUS;
1550         } else {
1551                 if (host->version >= SDHCI_SPEC_300)
1552                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1553                 if (width == MMC_BUS_WIDTH_4)
1554                         ctrl |= SDHCI_CTRL_4BITBUS;
1555                 else
1556                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1557         }
1558         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1559 }
1560 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1561
1562 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1563 {
1564         u16 ctrl_2;
1565
1566         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1567         /* Select Bus Speed Mode for host */
1568         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1569         if ((timing == MMC_TIMING_MMC_HS200) ||
1570             (timing == MMC_TIMING_UHS_SDR104))
1571                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1572         else if (timing == MMC_TIMING_UHS_SDR12)
1573                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1574         else if (timing == MMC_TIMING_UHS_SDR25)
1575                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1576         else if (timing == MMC_TIMING_UHS_SDR50)
1577                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1578         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1579                  (timing == MMC_TIMING_MMC_DDR52))
1580                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1581         else if (timing == MMC_TIMING_MMC_HS400)
1582                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1583         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1584 }
1585 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1586
1587 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1588 {
1589         struct sdhci_host *host = mmc_priv(mmc);
1590         u8 ctrl;
1591
1592         if (ios->power_mode == MMC_POWER_UNDEFINED)
1593                 return;
1594
1595         if (host->flags & SDHCI_DEVICE_DEAD) {
1596                 if (!IS_ERR(mmc->supply.vmmc) &&
1597                     ios->power_mode == MMC_POWER_OFF)
1598                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1599                 return;
1600         }
1601
1602         /*
1603          * Reset the chip on each power off.
1604          * Should clear out any weird states.
1605          */
1606         if (ios->power_mode == MMC_POWER_OFF) {
1607                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1608                 sdhci_reinit(host);
1609         }
1610
1611         if (host->version >= SDHCI_SPEC_300 &&
1612                 (ios->power_mode == MMC_POWER_UP) &&
1613                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1614                 sdhci_enable_preset_value(host, false);
1615
1616         if (!ios->clock || ios->clock != host->clock) {
1617                 host->ops->set_clock(host, ios->clock);
1618                 host->clock = ios->clock;
1619
1620                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1621                     host->clock) {
1622                         host->timeout_clk = host->mmc->actual_clock ?
1623                                                 host->mmc->actual_clock / 1000 :
1624                                                 host->clock / 1000;
1625                         host->mmc->max_busy_timeout =
1626                                 host->ops->get_max_timeout_count ?
1627                                 host->ops->get_max_timeout_count(host) :
1628                                 1 << 27;
1629                         host->mmc->max_busy_timeout /= host->timeout_clk;
1630                 }
1631         }
1632
1633         if (host->ops->set_power)
1634                 host->ops->set_power(host, ios->power_mode, ios->vdd);
1635         else
1636                 sdhci_set_power(host, ios->power_mode, ios->vdd);
1637
1638         if (host->ops->platform_send_init_74_clocks)
1639                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1640
1641         host->ops->set_bus_width(host, ios->bus_width);
1642
1643         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1644
1645         if ((ios->timing == MMC_TIMING_SD_HS ||
1646              ios->timing == MMC_TIMING_MMC_HS ||
1647              ios->timing == MMC_TIMING_MMC_HS400 ||
1648              ios->timing == MMC_TIMING_MMC_HS200 ||
1649              ios->timing == MMC_TIMING_MMC_DDR52 ||
1650              ios->timing == MMC_TIMING_UHS_SDR50 ||
1651              ios->timing == MMC_TIMING_UHS_SDR104 ||
1652              ios->timing == MMC_TIMING_UHS_DDR50 ||
1653              ios->timing == MMC_TIMING_UHS_SDR25)
1654             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1655                 ctrl |= SDHCI_CTRL_HISPD;
1656         else
1657                 ctrl &= ~SDHCI_CTRL_HISPD;
1658
1659         if (host->version >= SDHCI_SPEC_300) {
1660                 u16 clk, ctrl_2;
1661
1662                 if (!host->preset_enabled) {
1663                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1664                         /*
1665                          * We only need to set Driver Strength if the
1666                          * preset value enable is not set.
1667                          */
1668                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1669                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1670                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1671                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1672                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1673                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1674                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1675                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1676                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1677                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1678                         else {
1679                                 pr_warn("%s: invalid driver type, default to driver type B\n",
1680                                         mmc_hostname(mmc));
1681                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1682                         }
1683
1684                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1685                 } else {
1686                         /*
1687                          * According to SDHC Spec v3.00, if the Preset Value
1688                          * Enable in the Host Control 2 register is set, we
1689                          * need to reset SD Clock Enable before changing High
1690                          * Speed Enable to avoid generating clock gliches.
1691                          */
1692
1693                         /* Reset SD Clock Enable */
1694                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1695                         clk &= ~SDHCI_CLOCK_CARD_EN;
1696                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1697
1698                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1699
1700                         /* Re-enable SD Clock */
1701                         host->ops->set_clock(host, host->clock);
1702                 }
1703
1704                 /* Reset SD Clock Enable */
1705                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1706                 clk &= ~SDHCI_CLOCK_CARD_EN;
1707                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1708
1709                 host->ops->set_uhs_signaling(host, ios->timing);
1710                 host->timing = ios->timing;
1711
1712                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1713                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1714                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1715                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1716                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1717                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1718                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1719                         u16 preset;
1720
1721                         sdhci_enable_preset_value(host, true);
1722                         preset = sdhci_get_preset_value(host);
1723                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1724                                 >> SDHCI_PRESET_DRV_SHIFT;
1725                 }
1726
1727                 /* Re-enable SD Clock */
1728                 host->ops->set_clock(host, host->clock);
1729         } else
1730                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1731
1732         /*
1733          * Some (ENE) controllers go apeshit on some ios operation,
1734          * signalling timeout and CRC errors even on CMD0. Resetting
1735          * it on each ios seems to solve the problem.
1736          */
1737         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1738                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1739
1740         mmiowb();
1741 }
1742
1743 static int sdhci_get_cd(struct mmc_host *mmc)
1744 {
1745         struct sdhci_host *host = mmc_priv(mmc);
1746         int gpio_cd = mmc_gpio_get_cd(mmc);
1747
1748         if (host->flags & SDHCI_DEVICE_DEAD)
1749                 return 0;
1750
1751         /* If nonremovable, assume that the card is always present. */
1752         if (!mmc_card_is_removable(host->mmc))
1753                 return 1;
1754
1755         /*
1756          * Try slot gpio detect, if defined it take precedence
1757          * over build in controller functionality
1758          */
1759         if (gpio_cd >= 0)
1760                 return !!gpio_cd;
1761
1762         /* If polling, assume that the card is always present. */
1763         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1764                 return 1;
1765
1766         /* Host native card detect */
1767         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1768 }
1769
1770 static int sdhci_check_ro(struct sdhci_host *host)
1771 {
1772         unsigned long flags;
1773         int is_readonly;
1774
1775         spin_lock_irqsave(&host->lock, flags);
1776
1777         if (host->flags & SDHCI_DEVICE_DEAD)
1778                 is_readonly = 0;
1779         else if (host->ops->get_ro)
1780                 is_readonly = host->ops->get_ro(host);
1781         else
1782                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1783                                 & SDHCI_WRITE_PROTECT);
1784
1785         spin_unlock_irqrestore(&host->lock, flags);
1786
1787         /* This quirk needs to be replaced by a callback-function later */
1788         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1789                 !is_readonly : is_readonly;
1790 }
1791
1792 #define SAMPLE_COUNT    5
1793
1794 static int sdhci_get_ro(struct mmc_host *mmc)
1795 {
1796         struct sdhci_host *host = mmc_priv(mmc);
1797         int i, ro_count;
1798
1799         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1800                 return sdhci_check_ro(host);
1801
1802         ro_count = 0;
1803         for (i = 0; i < SAMPLE_COUNT; i++) {
1804                 if (sdhci_check_ro(host)) {
1805                         if (++ro_count > SAMPLE_COUNT / 2)
1806                                 return 1;
1807                 }
1808                 msleep(30);
1809         }
1810         return 0;
1811 }
1812
1813 static void sdhci_hw_reset(struct mmc_host *mmc)
1814 {
1815         struct sdhci_host *host = mmc_priv(mmc);
1816
1817         if (host->ops && host->ops->hw_reset)
1818                 host->ops->hw_reset(host);
1819 }
1820
1821 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1822 {
1823         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1824                 if (enable)
1825                         host->ier |= SDHCI_INT_CARD_INT;
1826                 else
1827                         host->ier &= ~SDHCI_INT_CARD_INT;
1828
1829                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1830                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1831                 mmiowb();
1832         }
1833 }
1834
1835 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1836 {
1837         struct sdhci_host *host = mmc_priv(mmc);
1838         unsigned long flags;
1839
1840         if (enable)
1841                 pm_runtime_get_noresume(host->mmc->parent);
1842
1843         spin_lock_irqsave(&host->lock, flags);
1844         if (enable)
1845                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1846         else
1847                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1848
1849         sdhci_enable_sdio_irq_nolock(host, enable);
1850         spin_unlock_irqrestore(&host->lock, flags);
1851
1852         if (!enable)
1853                 pm_runtime_put_noidle(host->mmc->parent);
1854 }
1855
1856 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1857                                              struct mmc_ios *ios)
1858 {
1859         struct sdhci_host *host = mmc_priv(mmc);
1860         u16 ctrl;
1861         int ret;
1862
1863         /*
1864          * Signal Voltage Switching is only applicable for Host Controllers
1865          * v3.00 and above.
1866          */
1867         if (host->version < SDHCI_SPEC_300)
1868                 return 0;
1869
1870         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1871
1872         switch (ios->signal_voltage) {
1873         case MMC_SIGNAL_VOLTAGE_330:
1874                 if (!(host->flags & SDHCI_SIGNALING_330))
1875                         return -EINVAL;
1876                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1877                 ctrl &= ~SDHCI_CTRL_VDD_180;
1878                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1879
1880                 if (!IS_ERR(mmc->supply.vqmmc)) {
1881                         ret = mmc_regulator_set_vqmmc(mmc, ios);
1882                         if (ret) {
1883                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1884                                         mmc_hostname(mmc));
1885                                 return -EIO;
1886                         }
1887                 }
1888                 /* Wait for 5ms */
1889                 usleep_range(5000, 5500);
1890
1891                 /* 3.3V regulator output should be stable within 5 ms */
1892                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1893                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1894                         return 0;
1895
1896                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1897                         mmc_hostname(mmc));
1898
1899                 return -EAGAIN;
1900         case MMC_SIGNAL_VOLTAGE_180:
1901                 if (!(host->flags & SDHCI_SIGNALING_180))
1902                         return -EINVAL;
1903                 if (!IS_ERR(mmc->supply.vqmmc)) {
1904                         ret = mmc_regulator_set_vqmmc(mmc, ios);
1905                         if (ret) {
1906                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1907                                         mmc_hostname(mmc));
1908                                 return -EIO;
1909                         }
1910                 }
1911
1912                 /*
1913                  * Enable 1.8V Signal Enable in the Host Control2
1914                  * register
1915                  */
1916                 ctrl |= SDHCI_CTRL_VDD_180;
1917                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1918
1919                 /* Some controller need to do more when switching */
1920                 if (host->ops->voltage_switch)
1921                         host->ops->voltage_switch(host);
1922
1923                 /* 1.8V regulator output should be stable within 5 ms */
1924                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1925                 if (ctrl & SDHCI_CTRL_VDD_180)
1926                         return 0;
1927
1928                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1929                         mmc_hostname(mmc));
1930
1931                 return -EAGAIN;
1932         case MMC_SIGNAL_VOLTAGE_120:
1933                 if (!(host->flags & SDHCI_SIGNALING_120))
1934                         return -EINVAL;
1935                 if (!IS_ERR(mmc->supply.vqmmc)) {
1936                         ret = mmc_regulator_set_vqmmc(mmc, ios);
1937                         if (ret) {
1938                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1939                                         mmc_hostname(mmc));
1940                                 return -EIO;
1941                         }
1942                 }
1943                 return 0;
1944         default:
1945                 /* No signal voltage switch required */
1946                 return 0;
1947         }
1948 }
1949
1950 static int sdhci_card_busy(struct mmc_host *mmc)
1951 {
1952         struct sdhci_host *host = mmc_priv(mmc);
1953         u32 present_state;
1954
1955         /* Check whether DAT[0] is 0 */
1956         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1957
1958         return !(present_state & SDHCI_DATA_0_LVL_MASK);
1959 }
1960
1961 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1962 {
1963         struct sdhci_host *host = mmc_priv(mmc);
1964         unsigned long flags;
1965
1966         spin_lock_irqsave(&host->lock, flags);
1967         host->flags |= SDHCI_HS400_TUNING;
1968         spin_unlock_irqrestore(&host->lock, flags);
1969
1970         return 0;
1971 }
1972
1973 static void sdhci_start_tuning(struct sdhci_host *host)
1974 {
1975         u16 ctrl;
1976
1977         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1978         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1979         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1980                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1981         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1982
1983         /*
1984          * As per the Host Controller spec v3.00, tuning command
1985          * generates Buffer Read Ready interrupt, so enable that.
1986          *
1987          * Note: The spec clearly says that when tuning sequence
1988          * is being performed, the controller does not generate
1989          * interrupts other than Buffer Read Ready interrupt. But
1990          * to make sure we don't hit a controller bug, we _only_
1991          * enable Buffer Read Ready interrupt here.
1992          */
1993         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1994         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1995 }
1996
1997 static void sdhci_end_tuning(struct sdhci_host *host)
1998 {
1999         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2000         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2001 }
2002
2003 static void sdhci_reset_tuning(struct sdhci_host *host)
2004 {
2005         u16 ctrl;
2006
2007         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2008         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2009         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2010         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2011 }
2012
2013 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2014 {
2015         sdhci_reset_tuning(host);
2016
2017         sdhci_do_reset(host, SDHCI_RESET_CMD);
2018         sdhci_do_reset(host, SDHCI_RESET_DATA);
2019
2020         sdhci_end_tuning(host);
2021
2022         mmc_abort_tuning(host->mmc, opcode);
2023 }
2024
2025 /*
2026  * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2027  * tuning command does not have a data payload (or rather the hardware does it
2028  * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2029  * interrupt setup is different to other commands and there is no timeout
2030  * interrupt so special handling is needed.
2031  */
2032 static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2033 {
2034         struct mmc_host *mmc = host->mmc;
2035         struct mmc_command cmd = {};
2036         struct mmc_request mrq = {};
2037         unsigned long flags;
2038
2039         spin_lock_irqsave(&host->lock, flags);
2040
2041         cmd.opcode = opcode;
2042         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2043         cmd.mrq = &mrq;
2044
2045         mrq.cmd = &cmd;
2046         /*
2047          * In response to CMD19, the card sends 64 bytes of tuning
2048          * block to the Host Controller. So we set the block size
2049          * to 64 here.
2050          */
2051         if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2052             mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2053                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
2054         else
2055                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
2056
2057         /*
2058          * The tuning block is sent by the card to the host controller.
2059          * So we set the TRNS_READ bit in the Transfer Mode register.
2060          * This also takes care of setting DMA Enable and Multi Block
2061          * Select in the same register to 0.
2062          */
2063         sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2064
2065         sdhci_send_command(host, &cmd);
2066
2067         host->cmd = NULL;
2068
2069         sdhci_del_timer(host, &mrq);
2070
2071         host->tuning_done = 0;
2072
2073         mmiowb();
2074         spin_unlock_irqrestore(&host->lock, flags);
2075
2076         /* Wait for Buffer Read Ready interrupt */
2077         wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2078                            msecs_to_jiffies(50));
2079
2080 }
2081
2082 static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2083 {
2084         int i;
2085
2086         /*
2087          * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2088          * of loops reaches 40 times.
2089          */
2090         for (i = 0; i < MAX_TUNING_LOOP; i++) {
2091                 u16 ctrl;
2092
2093                 sdhci_send_tuning(host, opcode);
2094
2095                 if (!host->tuning_done) {
2096                         pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2097                                 mmc_hostname(host->mmc));
2098                         sdhci_abort_tuning(host, opcode);
2099                         return;
2100                 }
2101
2102                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2103                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2104                         if (ctrl & SDHCI_CTRL_TUNED_CLK)
2105                                 return; /* Success! */
2106                         break;
2107                 }
2108
2109                 /* eMMC spec does not require a delay between tuning cycles */
2110                 if (opcode == MMC_SEND_TUNING_BLOCK)
2111                         mdelay(1);
2112         }
2113
2114         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2115                 mmc_hostname(host->mmc));
2116         sdhci_reset_tuning(host);
2117 }
2118
2119 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2120 {
2121         struct sdhci_host *host = mmc_priv(mmc);
2122         int err = 0;
2123         unsigned int tuning_count = 0;
2124         bool hs400_tuning;
2125
2126         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2127
2128         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2129                 tuning_count = host->tuning_count;
2130
2131         /*
2132          * The Host Controller needs tuning in case of SDR104 and DDR50
2133          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2134          * the Capabilities register.
2135          * If the Host Controller supports the HS200 mode then the
2136          * tuning function has to be executed.
2137          */
2138         switch (host->timing) {
2139         /* HS400 tuning is done in HS200 mode */
2140         case MMC_TIMING_MMC_HS400:
2141                 err = -EINVAL;
2142                 goto out;
2143
2144         case MMC_TIMING_MMC_HS200:
2145                 /*
2146                  * Periodic re-tuning for HS400 is not expected to be needed, so
2147                  * disable it here.
2148                  */
2149                 if (hs400_tuning)
2150                         tuning_count = 0;
2151                 break;
2152
2153         case MMC_TIMING_UHS_SDR104:
2154         case MMC_TIMING_UHS_DDR50:
2155                 break;
2156
2157         case MMC_TIMING_UHS_SDR50:
2158                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2159                         break;
2160                 /* FALLTHROUGH */
2161
2162         default:
2163                 goto out;
2164         }
2165
2166         if (host->ops->platform_execute_tuning) {
2167                 err = host->ops->platform_execute_tuning(host, opcode);
2168                 goto out;
2169         }
2170
2171         host->mmc->retune_period = tuning_count;
2172
2173         sdhci_start_tuning(host);
2174
2175         __sdhci_execute_tuning(host, opcode);
2176
2177         sdhci_end_tuning(host);
2178 out:
2179         host->flags &= ~SDHCI_HS400_TUNING;
2180
2181         return err;
2182 }
2183 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2184
2185 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2186 {
2187         /* Host Controller v3.00 defines preset value registers */
2188         if (host->version < SDHCI_SPEC_300)
2189                 return;
2190
2191         /*
2192          * We only enable or disable Preset Value if they are not already
2193          * enabled or disabled respectively. Otherwise, we bail out.
2194          */
2195         if (host->preset_enabled != enable) {
2196                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2197
2198                 if (enable)
2199                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2200                 else
2201                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2202
2203                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2204
2205                 if (enable)
2206                         host->flags |= SDHCI_PV_ENABLED;
2207                 else
2208                         host->flags &= ~SDHCI_PV_ENABLED;
2209
2210                 host->preset_enabled = enable;
2211         }
2212 }
2213
2214 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2215                                 int err)
2216 {
2217         struct sdhci_host *host = mmc_priv(mmc);
2218         struct mmc_data *data = mrq->data;
2219
2220         if (data->host_cookie != COOKIE_UNMAPPED)
2221                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2222                              data->flags & MMC_DATA_WRITE ?
2223                                DMA_TO_DEVICE : DMA_FROM_DEVICE);
2224
2225         data->host_cookie = COOKIE_UNMAPPED;
2226 }
2227
2228 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2229 {
2230         struct sdhci_host *host = mmc_priv(mmc);
2231
2232         mrq->data->host_cookie = COOKIE_UNMAPPED;
2233
2234         if (host->flags & SDHCI_REQ_USE_DMA)
2235                 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2236 }
2237
2238 static inline bool sdhci_has_requests(struct sdhci_host *host)
2239 {
2240         return host->cmd || host->data_cmd;
2241 }
2242
2243 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2244 {
2245         if (host->data_cmd) {
2246                 host->data_cmd->error = err;
2247                 sdhci_finish_mrq(host, host->data_cmd->mrq);
2248         }
2249
2250         if (host->cmd) {
2251                 host->cmd->error = err;
2252                 sdhci_finish_mrq(host, host->cmd->mrq);
2253         }
2254 }
2255
2256 static void sdhci_card_event(struct mmc_host *mmc)
2257 {
2258         struct sdhci_host *host = mmc_priv(mmc);
2259         unsigned long flags;
2260         int present;
2261
2262         /* First check if client has provided their own card event */
2263         if (host->ops->card_event)
2264                 host->ops->card_event(host);
2265
2266         present = mmc->ops->get_cd(mmc);
2267
2268         spin_lock_irqsave(&host->lock, flags);
2269
2270         /* Check sdhci_has_requests() first in case we are runtime suspended */
2271         if (sdhci_has_requests(host) && !present) {
2272                 pr_err("%s: Card removed during transfer!\n",
2273                         mmc_hostname(host->mmc));
2274                 pr_err("%s: Resetting controller.\n",
2275                         mmc_hostname(host->mmc));
2276
2277                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2278                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2279
2280                 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2281         }
2282
2283         spin_unlock_irqrestore(&host->lock, flags);
2284 }
2285
2286 static const struct mmc_host_ops sdhci_ops = {
2287         .request        = sdhci_request,
2288         .post_req       = sdhci_post_req,
2289         .pre_req        = sdhci_pre_req,
2290         .set_ios        = sdhci_set_ios,
2291         .get_cd         = sdhci_get_cd,
2292         .get_ro         = sdhci_get_ro,
2293         .hw_reset       = sdhci_hw_reset,
2294         .enable_sdio_irq = sdhci_enable_sdio_irq,
2295         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2296         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2297         .execute_tuning                 = sdhci_execute_tuning,
2298         .card_event                     = sdhci_card_event,
2299         .card_busy      = sdhci_card_busy,
2300 };
2301
2302 /*****************************************************************************\
2303  *                                                                           *
2304  * Tasklets                                                                  *
2305  *                                                                           *
2306 \*****************************************************************************/
2307
2308 static bool sdhci_request_done(struct sdhci_host *host)
2309 {
2310         unsigned long flags;
2311         struct mmc_request *mrq;
2312         int i;
2313
2314         spin_lock_irqsave(&host->lock, flags);
2315
2316         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2317                 mrq = host->mrqs_done[i];
2318                 if (mrq)
2319                         break;
2320         }
2321
2322         if (!mrq) {
2323                 spin_unlock_irqrestore(&host->lock, flags);
2324                 return true;
2325         }
2326
2327         sdhci_del_timer(host, mrq);
2328
2329         /*
2330          * Always unmap the data buffers if they were mapped by
2331          * sdhci_prepare_data() whenever we finish with a request.
2332          * This avoids leaking DMA mappings on error.
2333          */
2334         if (host->flags & SDHCI_REQ_USE_DMA) {
2335                 struct mmc_data *data = mrq->data;
2336
2337                 if (data && data->host_cookie == COOKIE_MAPPED) {
2338                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2339                                      (data->flags & MMC_DATA_READ) ?
2340                                      DMA_FROM_DEVICE : DMA_TO_DEVICE);
2341                         data->host_cookie = COOKIE_UNMAPPED;
2342                 }
2343         }
2344
2345         /*
2346          * The controller needs a reset of internal state machines
2347          * upon error conditions.
2348          */
2349         if (sdhci_needs_reset(host, mrq)) {
2350                 /*
2351                  * Do not finish until command and data lines are available for
2352                  * reset. Note there can only be one other mrq, so it cannot
2353                  * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2354                  * would both be null.
2355                  */
2356                 if (host->cmd || host->data_cmd) {
2357                         spin_unlock_irqrestore(&host->lock, flags);
2358                         return true;
2359                 }
2360
2361                 /* Some controllers need this kick or reset won't work here */
2362                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2363                         /* This is to force an update */
2364                         host->ops->set_clock(host, host->clock);
2365
2366                 /* Spec says we should do both at the same time, but Ricoh
2367                    controllers do not like that. */
2368                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2369                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2370
2371                 host->pending_reset = false;
2372         }
2373
2374         if (!sdhci_has_requests(host))
2375                 sdhci_led_deactivate(host);
2376
2377         host->mrqs_done[i] = NULL;
2378
2379         mmiowb();
2380         spin_unlock_irqrestore(&host->lock, flags);
2381
2382         mmc_request_done(host->mmc, mrq);
2383
2384         return false;
2385 }
2386
2387 static void sdhci_tasklet_finish(unsigned long param)
2388 {
2389         struct sdhci_host *host = (struct sdhci_host *)param;
2390
2391         while (!sdhci_request_done(host))
2392                 ;
2393 }
2394
2395 static void sdhci_timeout_timer(unsigned long data)
2396 {
2397         struct sdhci_host *host;
2398         unsigned long flags;
2399
2400         host = (struct sdhci_host*)data;
2401
2402         spin_lock_irqsave(&host->lock, flags);
2403
2404         if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2405                 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2406                        mmc_hostname(host->mmc));
2407                 sdhci_dumpregs(host);
2408
2409                 host->cmd->error = -ETIMEDOUT;
2410                 sdhci_finish_mrq(host, host->cmd->mrq);
2411         }
2412
2413         mmiowb();
2414         spin_unlock_irqrestore(&host->lock, flags);
2415 }
2416
2417 static void sdhci_timeout_data_timer(unsigned long data)
2418 {
2419         struct sdhci_host *host;
2420         unsigned long flags;
2421
2422         host = (struct sdhci_host *)data;
2423
2424         spin_lock_irqsave(&host->lock, flags);
2425
2426         if (host->data || host->data_cmd ||
2427             (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2428                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2429                        mmc_hostname(host->mmc));
2430                 sdhci_dumpregs(host);
2431
2432                 if (host->data) {
2433                         host->data->error = -ETIMEDOUT;
2434                         sdhci_finish_data(host);
2435                 } else if (host->data_cmd) {
2436                         host->data_cmd->error = -ETIMEDOUT;
2437                         sdhci_finish_mrq(host, host->data_cmd->mrq);
2438                 } else {
2439                         host->cmd->error = -ETIMEDOUT;
2440                         sdhci_finish_mrq(host, host->cmd->mrq);
2441                 }
2442         }
2443
2444         mmiowb();
2445         spin_unlock_irqrestore(&host->lock, flags);
2446 }
2447
2448 /*****************************************************************************\
2449  *                                                                           *
2450  * Interrupt handling                                                        *
2451  *                                                                           *
2452 \*****************************************************************************/
2453
2454 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2455 {
2456         if (!host->cmd) {
2457                 /*
2458                  * SDHCI recovers from errors by resetting the cmd and data
2459                  * circuits.  Until that is done, there very well might be more
2460                  * interrupts, so ignore them in that case.
2461                  */
2462                 if (host->pending_reset)
2463                         return;
2464                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2465                        mmc_hostname(host->mmc), (unsigned)intmask);
2466                 sdhci_dumpregs(host);
2467                 return;
2468         }
2469
2470         if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2471                        SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2472                 if (intmask & SDHCI_INT_TIMEOUT)
2473                         host->cmd->error = -ETIMEDOUT;
2474                 else
2475                         host->cmd->error = -EILSEQ;
2476
2477                 /*
2478                  * If this command initiates a data phase and a response
2479                  * CRC error is signalled, the card can start transferring
2480                  * data - the card may have received the command without
2481                  * error.  We must not terminate the mmc_request early.
2482                  *
2483                  * If the card did not receive the command or returned an
2484                  * error which prevented it sending data, the data phase
2485                  * will time out.
2486                  */
2487                 if (host->cmd->data &&
2488                     (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2489                      SDHCI_INT_CRC) {
2490                         host->cmd = NULL;
2491                         return;
2492                 }
2493
2494                 sdhci_finish_mrq(host, host->cmd->mrq);
2495                 return;
2496         }
2497
2498         if (intmask & SDHCI_INT_RESPONSE)
2499                 sdhci_finish_command(host);
2500 }
2501
2502 #ifdef CONFIG_MMC_DEBUG
2503 static void sdhci_adma_show_error(struct sdhci_host *host)
2504 {
2505         void *desc = host->adma_table;
2506
2507         sdhci_dumpregs(host);
2508
2509         while (true) {
2510                 struct sdhci_adma2_64_desc *dma_desc = desc;
2511
2512                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2513                         DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2514                             desc, le32_to_cpu(dma_desc->addr_hi),
2515                             le32_to_cpu(dma_desc->addr_lo),
2516                             le16_to_cpu(dma_desc->len),
2517                             le16_to_cpu(dma_desc->cmd));
2518                 else
2519                         DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2520                             desc, le32_to_cpu(dma_desc->addr_lo),
2521                             le16_to_cpu(dma_desc->len),
2522                             le16_to_cpu(dma_desc->cmd));
2523
2524                 desc += host->desc_sz;
2525
2526                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2527                         break;
2528         }
2529 }
2530 #else
2531 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2532 #endif
2533
2534 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2535 {
2536         u32 command;
2537
2538         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2539         if (intmask & SDHCI_INT_DATA_AVAIL) {
2540                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2541                 if (command == MMC_SEND_TUNING_BLOCK ||
2542                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2543                         host->tuning_done = 1;
2544                         wake_up(&host->buf_ready_int);
2545                         return;
2546                 }
2547         }
2548
2549         if (!host->data) {
2550                 struct mmc_command *data_cmd = host->data_cmd;
2551
2552                 /*
2553                  * The "data complete" interrupt is also used to
2554                  * indicate that a busy state has ended. See comment
2555                  * above in sdhci_cmd_irq().
2556                  */
2557                 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2558                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2559                                 host->data_cmd = NULL;
2560                                 data_cmd->error = -ETIMEDOUT;
2561                                 sdhci_finish_mrq(host, data_cmd->mrq);
2562                                 return;
2563                         }
2564                         if (intmask & SDHCI_INT_DATA_END) {
2565                                 host->data_cmd = NULL;
2566                                 /*
2567                                  * Some cards handle busy-end interrupt
2568                                  * before the command completed, so make
2569                                  * sure we do things in the proper order.
2570                                  */
2571                                 if (host->cmd == data_cmd)
2572                                         return;
2573
2574                                 sdhci_finish_mrq(host, data_cmd->mrq);
2575                                 return;
2576                         }
2577                 }
2578
2579                 /*
2580                  * SDHCI recovers from errors by resetting the cmd and data
2581                  * circuits. Until that is done, there very well might be more
2582                  * interrupts, so ignore them in that case.
2583                  */
2584                 if (host->pending_reset)
2585                         return;
2586
2587                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2588                        mmc_hostname(host->mmc), (unsigned)intmask);
2589                 sdhci_dumpregs(host);
2590
2591                 return;
2592         }
2593
2594         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2595                 host->data->error = -ETIMEDOUT;
2596         else if (intmask & SDHCI_INT_DATA_END_BIT)
2597                 host->data->error = -EILSEQ;
2598         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2599                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2600                         != MMC_BUS_TEST_R)
2601                 host->data->error = -EILSEQ;
2602         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2603                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2604                 sdhci_adma_show_error(host);
2605                 host->data->error = -EIO;
2606                 if (host->ops->adma_workaround)
2607                         host->ops->adma_workaround(host, intmask);
2608         }
2609
2610         if (host->data->error)
2611                 sdhci_finish_data(host);
2612         else {
2613                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2614                         sdhci_transfer_pio(host);
2615
2616                 /*
2617                  * We currently don't do anything fancy with DMA
2618                  * boundaries, but as we can't disable the feature
2619                  * we need to at least restart the transfer.
2620                  *
2621                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2622                  * should return a valid address to continue from, but as
2623                  * some controllers are faulty, don't trust them.
2624                  */
2625                 if (intmask & SDHCI_INT_DMA_END) {
2626                         u32 dmastart, dmanow;
2627                         dmastart = sg_dma_address(host->data->sg);
2628                         dmanow = dmastart + host->data->bytes_xfered;
2629                         /*
2630                          * Force update to the next DMA block boundary.
2631                          */
2632                         dmanow = (dmanow &
2633                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2634                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2635                         host->data->bytes_xfered = dmanow - dmastart;
2636                         DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2637                             dmastart, host->data->bytes_xfered, dmanow);
2638                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2639                 }
2640
2641                 if (intmask & SDHCI_INT_DATA_END) {
2642                         if (host->cmd == host->data_cmd) {
2643                                 /*
2644                                  * Data managed to finish before the
2645                                  * command completed. Make sure we do
2646                                  * things in the proper order.
2647                                  */
2648                                 host->data_early = 1;
2649                         } else {
2650                                 sdhci_finish_data(host);
2651                         }
2652                 }
2653         }
2654 }
2655
2656 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2657 {
2658         irqreturn_t result = IRQ_NONE;
2659         struct sdhci_host *host = dev_id;
2660         u32 intmask, mask, unexpected = 0;
2661         int max_loops = 16;
2662
2663         spin_lock(&host->lock);
2664
2665         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2666                 spin_unlock(&host->lock);
2667                 return IRQ_NONE;
2668         }
2669
2670         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2671         if (!intmask || intmask == 0xffffffff) {
2672                 result = IRQ_NONE;
2673                 goto out;
2674         }
2675
2676         do {
2677                 DBG("IRQ status 0x%08x\n", intmask);
2678
2679                 if (host->ops->irq) {
2680                         intmask = host->ops->irq(host, intmask);
2681                         if (!intmask)
2682                                 goto cont;
2683                 }
2684
2685                 /* Clear selected interrupts. */
2686                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2687                                   SDHCI_INT_BUS_POWER);
2688                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2689
2690                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2691                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2692                                       SDHCI_CARD_PRESENT;
2693
2694                         /*
2695                          * There is a observation on i.mx esdhc.  INSERT
2696                          * bit will be immediately set again when it gets
2697                          * cleared, if a card is inserted.  We have to mask
2698                          * the irq to prevent interrupt storm which will
2699                          * freeze the system.  And the REMOVE gets the
2700                          * same situation.
2701                          *
2702                          * More testing are needed here to ensure it works
2703                          * for other platforms though.
2704                          */
2705                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2706                                        SDHCI_INT_CARD_REMOVE);
2707                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2708                                                SDHCI_INT_CARD_INSERT;
2709                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2710                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2711
2712                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2713                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2714
2715                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2716                                                        SDHCI_INT_CARD_REMOVE);
2717                         result = IRQ_WAKE_THREAD;
2718                 }
2719
2720                 if (intmask & SDHCI_INT_CMD_MASK)
2721                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2722
2723                 if (intmask & SDHCI_INT_DATA_MASK)
2724                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2725
2726                 if (intmask & SDHCI_INT_BUS_POWER)
2727                         pr_err("%s: Card is consuming too much power!\n",
2728                                 mmc_hostname(host->mmc));
2729
2730                 if (intmask & SDHCI_INT_RETUNE)
2731                         mmc_retune_needed(host->mmc);
2732
2733                 if ((intmask & SDHCI_INT_CARD_INT) &&
2734                     (host->ier & SDHCI_INT_CARD_INT)) {
2735                         sdhci_enable_sdio_irq_nolock(host, false);
2736                         host->thread_isr |= SDHCI_INT_CARD_INT;
2737                         result = IRQ_WAKE_THREAD;
2738                 }
2739
2740                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2741                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2742                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2743                              SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2744
2745                 if (intmask) {
2746                         unexpected |= intmask;
2747                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2748                 }
2749 cont:
2750                 if (result == IRQ_NONE)
2751                         result = IRQ_HANDLED;
2752
2753                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2754         } while (intmask && --max_loops);
2755 out:
2756         spin_unlock(&host->lock);
2757
2758         if (unexpected) {
2759                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2760                            mmc_hostname(host->mmc), unexpected);
2761                 sdhci_dumpregs(host);
2762         }
2763
2764         return result;
2765 }
2766
2767 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2768 {
2769         struct sdhci_host *host = dev_id;
2770         unsigned long flags;
2771         u32 isr;
2772
2773         spin_lock_irqsave(&host->lock, flags);
2774         isr = host->thread_isr;
2775         host->thread_isr = 0;
2776         spin_unlock_irqrestore(&host->lock, flags);
2777
2778         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2779                 struct mmc_host *mmc = host->mmc;
2780
2781                 mmc->ops->card_event(mmc);
2782                 mmc_detect_change(mmc, msecs_to_jiffies(200));
2783         }
2784
2785         if (isr & SDHCI_INT_CARD_INT) {
2786                 sdio_run_irqs(host->mmc);
2787
2788                 spin_lock_irqsave(&host->lock, flags);
2789                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2790                         sdhci_enable_sdio_irq_nolock(host, true);
2791                 spin_unlock_irqrestore(&host->lock, flags);
2792         }
2793
2794         return isr ? IRQ_HANDLED : IRQ_NONE;
2795 }
2796
2797 /*****************************************************************************\
2798  *                                                                           *
2799  * Suspend/resume                                                            *
2800  *                                                                           *
2801 \*****************************************************************************/
2802
2803 #ifdef CONFIG_PM
2804 /*
2805  * To enable wakeup events, the corresponding events have to be enabled in
2806  * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2807  * Table' in the SD Host Controller Standard Specification.
2808  * It is useless to restore SDHCI_INT_ENABLE state in
2809  * sdhci_disable_irq_wakeups() since it will be set by
2810  * sdhci_enable_card_detection() or sdhci_init().
2811  */
2812 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2813 {
2814         u8 val;
2815         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2816                         | SDHCI_WAKE_ON_INT;
2817         u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2818                       SDHCI_INT_CARD_INT;
2819
2820         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2821         val |= mask ;
2822         /* Avoid fake wake up */
2823         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2824                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2825                 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2826         }
2827         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2828         sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2829 }
2830 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2831
2832 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2833 {
2834         u8 val;
2835         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2836                         | SDHCI_WAKE_ON_INT;
2837
2838         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2839         val &= ~mask;
2840         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2841 }
2842
2843 int sdhci_suspend_host(struct sdhci_host *host)
2844 {
2845         sdhci_disable_card_detection(host);
2846
2847         mmc_retune_timer_stop(host->mmc);
2848
2849         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2850                 host->ier = 0;
2851                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2852                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2853                 free_irq(host->irq, host);
2854         } else {
2855                 sdhci_enable_irq_wakeups(host);
2856                 enable_irq_wake(host->irq);
2857         }
2858         return 0;
2859 }
2860
2861 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2862
2863 int sdhci_resume_host(struct sdhci_host *host)
2864 {
2865         struct mmc_host *mmc = host->mmc;
2866         int ret = 0;
2867
2868         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2869                 if (host->ops->enable_dma)
2870                         host->ops->enable_dma(host);
2871         }
2872
2873         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2874             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2875                 /* Card keeps power but host controller does not */
2876                 sdhci_init(host, 0);
2877                 host->pwr = 0;
2878                 host->clock = 0;
2879                 mmc->ops->set_ios(mmc, &mmc->ios);
2880         } else {
2881                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2882                 mmiowb();
2883         }
2884
2885         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2886                 ret = request_threaded_irq(host->irq, sdhci_irq,
2887                                            sdhci_thread_irq, IRQF_SHARED,
2888                                            mmc_hostname(host->mmc), host);
2889                 if (ret)
2890                         return ret;
2891         } else {
2892                 sdhci_disable_irq_wakeups(host);
2893                 disable_irq_wake(host->irq);
2894         }
2895
2896         sdhci_enable_card_detection(host);
2897
2898         return ret;
2899 }
2900
2901 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2902
2903 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2904 {
2905         unsigned long flags;
2906
2907         mmc_retune_timer_stop(host->mmc);
2908
2909         spin_lock_irqsave(&host->lock, flags);
2910         host->ier &= SDHCI_INT_CARD_INT;
2911         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2912         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2913         spin_unlock_irqrestore(&host->lock, flags);
2914
2915         synchronize_hardirq(host->irq);
2916
2917         spin_lock_irqsave(&host->lock, flags);
2918         host->runtime_suspended = true;
2919         spin_unlock_irqrestore(&host->lock, flags);
2920
2921         return 0;
2922 }
2923 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2924
2925 int sdhci_runtime_resume_host(struct sdhci_host *host)
2926 {
2927         struct mmc_host *mmc = host->mmc;
2928         unsigned long flags;
2929         int host_flags = host->flags;
2930
2931         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2932                 if (host->ops->enable_dma)
2933                         host->ops->enable_dma(host);
2934         }
2935
2936         sdhci_init(host, 0);
2937
2938         if (mmc->ios.power_mode != MMC_POWER_UNDEFINED) {
2939                 /* Force clock and power re-program */
2940                 host->pwr = 0;
2941                 host->clock = 0;
2942                 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2943                 mmc->ops->set_ios(mmc, &mmc->ios);
2944
2945                 if ((host_flags & SDHCI_PV_ENABLED) &&
2946                     !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2947                         spin_lock_irqsave(&host->lock, flags);
2948                         sdhci_enable_preset_value(host, true);
2949                         spin_unlock_irqrestore(&host->lock, flags);
2950                 }
2951
2952                 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
2953                     mmc->ops->hs400_enhanced_strobe)
2954                         mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
2955         }
2956
2957         spin_lock_irqsave(&host->lock, flags);
2958
2959         host->runtime_suspended = false;
2960
2961         /* Enable SDIO IRQ */
2962         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2963                 sdhci_enable_sdio_irq_nolock(host, true);
2964
2965         /* Enable Card Detection */
2966         sdhci_enable_card_detection(host);
2967
2968         spin_unlock_irqrestore(&host->lock, flags);
2969
2970         return 0;
2971 }
2972 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2973
2974 #endif /* CONFIG_PM */
2975
2976 /*****************************************************************************\
2977  *                                                                           *
2978  * Command Queue Engine (CQE) helpers                                        *
2979  *                                                                           *
2980 \*****************************************************************************/
2981
2982 void sdhci_cqe_enable(struct mmc_host *mmc)
2983 {
2984         struct sdhci_host *host = mmc_priv(mmc);
2985         unsigned long flags;
2986         u8 ctrl;
2987
2988         spin_lock_irqsave(&host->lock, flags);
2989
2990         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2991         ctrl &= ~SDHCI_CTRL_DMA_MASK;
2992         if (host->flags & SDHCI_USE_64_BIT_DMA)
2993                 ctrl |= SDHCI_CTRL_ADMA64;
2994         else
2995                 ctrl |= SDHCI_CTRL_ADMA32;
2996         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2997
2998         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 512),
2999                      SDHCI_BLOCK_SIZE);
3000
3001         /* Set maximum timeout */
3002         sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3003
3004         host->ier = host->cqe_ier;
3005
3006         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3007         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3008
3009         host->cqe_on = true;
3010
3011         pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3012                  mmc_hostname(mmc), host->ier,
3013                  sdhci_readl(host, SDHCI_INT_STATUS));
3014
3015         mmiowb();
3016         spin_unlock_irqrestore(&host->lock, flags);
3017 }
3018 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3019
3020 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3021 {
3022         struct sdhci_host *host = mmc_priv(mmc);
3023         unsigned long flags;
3024
3025         spin_lock_irqsave(&host->lock, flags);
3026
3027         sdhci_set_default_irqs(host);
3028
3029         host->cqe_on = false;
3030
3031         if (recovery) {
3032                 sdhci_do_reset(host, SDHCI_RESET_CMD);
3033                 sdhci_do_reset(host, SDHCI_RESET_DATA);
3034         }
3035
3036         pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3037                  mmc_hostname(mmc), host->ier,
3038                  sdhci_readl(host, SDHCI_INT_STATUS));
3039
3040         mmiowb();
3041         spin_unlock_irqrestore(&host->lock, flags);
3042 }
3043 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3044
3045 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3046                    int *data_error)
3047 {
3048         u32 mask;
3049
3050         if (!host->cqe_on)
3051                 return false;
3052
3053         if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3054                 *cmd_error = -EILSEQ;
3055         else if (intmask & SDHCI_INT_TIMEOUT)
3056                 *cmd_error = -ETIMEDOUT;
3057         else
3058                 *cmd_error = 0;
3059
3060         if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3061                 *data_error = -EILSEQ;
3062         else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3063                 *data_error = -ETIMEDOUT;
3064         else if (intmask & SDHCI_INT_ADMA_ERROR)
3065                 *data_error = -EIO;
3066         else
3067                 *data_error = 0;
3068
3069         /* Clear selected interrupts. */
3070         mask = intmask & host->cqe_ier;
3071         sdhci_writel(host, mask, SDHCI_INT_STATUS);
3072
3073         if (intmask & SDHCI_INT_BUS_POWER)
3074                 pr_err("%s: Card is consuming too much power!\n",
3075                        mmc_hostname(host->mmc));
3076
3077         intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3078         if (intmask) {
3079                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3080                 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3081                        mmc_hostname(host->mmc), intmask);
3082                 sdhci_dumpregs(host);
3083         }
3084
3085         return true;
3086 }
3087 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3088
3089 /*****************************************************************************\
3090  *                                                                           *
3091  * Device allocation/registration                                            *
3092  *                                                                           *
3093 \*****************************************************************************/
3094
3095 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3096         size_t priv_size)
3097 {
3098         struct mmc_host *mmc;
3099         struct sdhci_host *host;
3100
3101         WARN_ON(dev == NULL);
3102
3103         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3104         if (!mmc)
3105                 return ERR_PTR(-ENOMEM);
3106
3107         host = mmc_priv(mmc);
3108         host->mmc = mmc;
3109         host->mmc_host_ops = sdhci_ops;
3110         mmc->ops = &host->mmc_host_ops;
3111
3112         host->flags = SDHCI_SIGNALING_330;
3113
3114         host->cqe_ier     = SDHCI_CQE_INT_MASK;
3115         host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3116
3117         return host;
3118 }
3119
3120 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3121
3122 static int sdhci_set_dma_mask(struct sdhci_host *host)
3123 {
3124         struct mmc_host *mmc = host->mmc;
3125         struct device *dev = mmc_dev(mmc);
3126         int ret = -EINVAL;
3127
3128         if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3129                 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3130
3131         /* Try 64-bit mask if hardware is capable  of it */
3132         if (host->flags & SDHCI_USE_64_BIT_DMA) {
3133                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3134                 if (ret) {
3135                         pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3136                                 mmc_hostname(mmc));
3137                         host->flags &= ~SDHCI_USE_64_BIT_DMA;
3138                 }
3139         }
3140
3141         /* 32-bit mask as default & fallback */
3142         if (ret) {
3143                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3144                 if (ret)
3145                         pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3146                                 mmc_hostname(mmc));
3147         }
3148
3149         return ret;
3150 }
3151
3152 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3153 {
3154         u16 v;
3155         u64 dt_caps_mask = 0;
3156         u64 dt_caps = 0;
3157
3158         if (host->read_caps)
3159                 return;
3160
3161         host->read_caps = true;
3162
3163         if (debug_quirks)
3164                 host->quirks = debug_quirks;
3165
3166         if (debug_quirks2)
3167                 host->quirks2 = debug_quirks2;
3168
3169         sdhci_do_reset(host, SDHCI_RESET_ALL);
3170
3171         of_property_read_u64(mmc_dev(host->mmc)->of_node,
3172                              "sdhci-caps-mask", &dt_caps_mask);
3173         of_property_read_u64(mmc_dev(host->mmc)->of_node,
3174                              "sdhci-caps", &dt_caps);
3175
3176         v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3177         host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3178
3179         if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3180                 return;
3181
3182         if (caps) {
3183                 host->caps = *caps;
3184         } else {
3185                 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3186                 host->caps &= ~lower_32_bits(dt_caps_mask);
3187                 host->caps |= lower_32_bits(dt_caps);
3188         }
3189
3190         if (host->version < SDHCI_SPEC_300)
3191                 return;
3192
3193         if (caps1) {
3194                 host->caps1 = *caps1;
3195         } else {
3196                 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3197                 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3198                 host->caps1 |= upper_32_bits(dt_caps);
3199         }
3200 }
3201 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3202
3203 int sdhci_setup_host(struct sdhci_host *host)
3204 {
3205         struct mmc_host *mmc;
3206         u32 max_current_caps;
3207         unsigned int ocr_avail;
3208         unsigned int override_timeout_clk;
3209         u32 max_clk;
3210         int ret;
3211
3212         WARN_ON(host == NULL);
3213         if (host == NULL)
3214                 return -EINVAL;
3215
3216         mmc = host->mmc;
3217
3218         /*
3219          * If there are external regulators, get them. Note this must be done
3220          * early before resetting the host and reading the capabilities so that
3221          * the host can take the appropriate action if regulators are not
3222          * available.
3223          */
3224         ret = mmc_regulator_get_supply(mmc);
3225         if (ret == -EPROBE_DEFER)
3226                 return ret;
3227
3228         sdhci_read_caps(host);
3229
3230         override_timeout_clk = host->timeout_clk;
3231
3232         if (host->version > SDHCI_SPEC_300) {
3233                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3234                        mmc_hostname(mmc), host->version);
3235         }
3236
3237         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3238                 host->flags |= SDHCI_USE_SDMA;
3239         else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3240                 DBG("Controller doesn't have SDMA capability\n");
3241         else
3242                 host->flags |= SDHCI_USE_SDMA;
3243
3244         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3245                 (host->flags & SDHCI_USE_SDMA)) {
3246                 DBG("Disabling DMA as it is marked broken\n");
3247                 host->flags &= ~SDHCI_USE_SDMA;
3248         }
3249
3250         if ((host->version >= SDHCI_SPEC_200) &&
3251                 (host->caps & SDHCI_CAN_DO_ADMA2))
3252                 host->flags |= SDHCI_USE_ADMA;
3253
3254         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3255                 (host->flags & SDHCI_USE_ADMA)) {
3256                 DBG("Disabling ADMA as it is marked broken\n");
3257                 host->flags &= ~SDHCI_USE_ADMA;
3258         }
3259
3260         /*
3261          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3262          * and *must* do 64-bit DMA.  A driver has the opportunity to change
3263          * that during the first call to ->enable_dma().  Similarly
3264          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3265          * implement.
3266          */
3267         if (host->caps & SDHCI_CAN_64BIT)
3268                 host->flags |= SDHCI_USE_64_BIT_DMA;
3269
3270         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3271                 ret = sdhci_set_dma_mask(host);
3272
3273                 if (!ret && host->ops->enable_dma)
3274                         ret = host->ops->enable_dma(host);
3275
3276                 if (ret) {
3277                         pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3278                                 mmc_hostname(mmc));
3279                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3280
3281                         ret = 0;
3282                 }
3283         }
3284
3285         /* SDMA does not support 64-bit DMA */
3286         if (host->flags & SDHCI_USE_64_BIT_DMA)
3287                 host->flags &= ~SDHCI_USE_SDMA;
3288
3289         if (host->flags & SDHCI_USE_ADMA) {
3290                 dma_addr_t dma;
3291                 void *buf;
3292
3293                 /*
3294                  * The DMA descriptor table size is calculated as the maximum
3295                  * number of segments times 2, to allow for an alignment
3296                  * descriptor for each segment, plus 1 for a nop end descriptor,
3297                  * all multipled by the descriptor size.
3298                  */
3299                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3300                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3301                                               SDHCI_ADMA2_64_DESC_SZ;
3302                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3303                 } else {
3304                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3305                                               SDHCI_ADMA2_32_DESC_SZ;
3306                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3307                 }
3308
3309                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3310                 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3311                                          host->adma_table_sz, &dma, GFP_KERNEL);
3312                 if (!buf) {
3313                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3314                                 mmc_hostname(mmc));
3315                         host->flags &= ~SDHCI_USE_ADMA;
3316                 } else if ((dma + host->align_buffer_sz) &
3317                            (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3318                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3319                                 mmc_hostname(mmc));
3320                         host->flags &= ~SDHCI_USE_ADMA;
3321                         dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3322                                           host->adma_table_sz, buf, dma);
3323                 } else {
3324                         host->align_buffer = buf;
3325                         host->align_addr = dma;
3326
3327                         host->adma_table = buf + host->align_buffer_sz;
3328                         host->adma_addr = dma + host->align_buffer_sz;
3329                 }
3330         }
3331
3332         /*
3333          * If we use DMA, then it's up to the caller to set the DMA
3334          * mask, but PIO does not need the hw shim so we set a new
3335          * mask here in that case.
3336          */
3337         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3338                 host->dma_mask = DMA_BIT_MASK(64);
3339                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3340         }
3341
3342         if (host->version >= SDHCI_SPEC_300)
3343                 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3344                         >> SDHCI_CLOCK_BASE_SHIFT;
3345         else
3346                 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3347                         >> SDHCI_CLOCK_BASE_SHIFT;
3348
3349         host->max_clk *= 1000000;
3350         if (host->max_clk == 0 || host->quirks &
3351                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3352                 if (!host->ops->get_max_clock) {
3353                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3354                                mmc_hostname(mmc));
3355                         ret = -ENODEV;
3356                         goto undma;
3357                 }
3358                 host->max_clk = host->ops->get_max_clock(host);
3359         }
3360
3361         /*
3362          * In case of Host Controller v3.00, find out whether clock
3363          * multiplier is supported.
3364          */
3365         host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3366                         SDHCI_CLOCK_MUL_SHIFT;
3367
3368         /*
3369          * In case the value in Clock Multiplier is 0, then programmable
3370          * clock mode is not supported, otherwise the actual clock
3371          * multiplier is one more than the value of Clock Multiplier
3372          * in the Capabilities Register.
3373          */
3374         if (host->clk_mul)
3375                 host->clk_mul += 1;
3376
3377         /*
3378          * Set host parameters.
3379          */
3380         max_clk = host->max_clk;
3381
3382         if (host->ops->get_min_clock)
3383                 mmc->f_min = host->ops->get_min_clock(host);
3384         else if (host->version >= SDHCI_SPEC_300) {
3385                 if (host->clk_mul) {
3386                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3387                         max_clk = host->max_clk * host->clk_mul;
3388                 } else
3389                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3390         } else
3391                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3392
3393         if (!mmc->f_max || mmc->f_max > max_clk)
3394                 mmc->f_max = max_clk;
3395
3396         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3397                 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3398                                         SDHCI_TIMEOUT_CLK_SHIFT;
3399                 if (host->timeout_clk == 0) {
3400                         if (host->ops->get_timeout_clock) {
3401                                 host->timeout_clk =
3402                                         host->ops->get_timeout_clock(host);
3403                         } else {
3404                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3405                                         mmc_hostname(mmc));
3406                                 ret = -ENODEV;
3407                                 goto undma;
3408                         }
3409                 }
3410
3411                 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3412                         host->timeout_clk *= 1000;
3413
3414                 if (override_timeout_clk)
3415                         host->timeout_clk = override_timeout_clk;
3416
3417                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3418                         host->ops->get_max_timeout_count(host) : 1 << 27;
3419                 mmc->max_busy_timeout /= host->timeout_clk;
3420         }
3421
3422         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3423         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3424
3425         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3426                 host->flags |= SDHCI_AUTO_CMD12;
3427
3428         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3429         if ((host->version >= SDHCI_SPEC_300) &&
3430             ((host->flags & SDHCI_USE_ADMA) ||
3431              !(host->flags & SDHCI_USE_SDMA)) &&
3432              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3433                 host->flags |= SDHCI_AUTO_CMD23;
3434                 DBG("Auto-CMD23 available\n");
3435         } else {
3436                 DBG("Auto-CMD23 unavailable\n");
3437         }
3438
3439         /*
3440          * A controller may support 8-bit width, but the board itself
3441          * might not have the pins brought out.  Boards that support
3442          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3443          * their platform code before calling sdhci_add_host(), and we
3444          * won't assume 8-bit width for hosts without that CAP.
3445          */
3446         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3447                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3448
3449         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3450                 mmc->caps &= ~MMC_CAP_CMD23;
3451
3452         if (host->caps & SDHCI_CAN_DO_HISPD)
3453                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3454
3455         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3456             mmc_card_is_removable(mmc) &&
3457             mmc_gpio_get_cd(host->mmc) < 0)
3458                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3459
3460         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3461         if (!IS_ERR(mmc->supply.vqmmc)) {
3462                 ret = regulator_enable(mmc->supply.vqmmc);
3463                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3464                                                     1950000))
3465                         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3466                                          SDHCI_SUPPORT_SDR50 |
3467                                          SDHCI_SUPPORT_DDR50);
3468                 if (ret) {
3469                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3470                                 mmc_hostname(mmc), ret);
3471                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3472                 }
3473         }
3474
3475         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3476                 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3477                                  SDHCI_SUPPORT_DDR50);
3478         }
3479
3480         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3481         if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3482                            SDHCI_SUPPORT_DDR50))
3483                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3484
3485         /* SDR104 supports also implies SDR50 support */
3486         if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3487                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3488                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3489                  * field can be promoted to support HS200.
3490                  */
3491                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3492                         mmc->caps2 |= MMC_CAP2_HS200;
3493         } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3494                 mmc->caps |= MMC_CAP_UHS_SDR50;
3495         }
3496
3497         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3498             (host->caps1 & SDHCI_SUPPORT_HS400))
3499                 mmc->caps2 |= MMC_CAP2_HS400;
3500
3501         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3502             (IS_ERR(mmc->supply.vqmmc) ||
3503              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3504                                              1300000)))
3505                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3506
3507         if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3508             !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3509                 mmc->caps |= MMC_CAP_UHS_DDR50;
3510
3511         /* Does the host need tuning for SDR50? */
3512         if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3513                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3514
3515         /* Driver Type(s) (A, C, D) supported by the host */
3516         if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3517                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3518         if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3519                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3520         if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3521                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3522
3523         /* Initial value for re-tuning timer count */
3524         host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3525                              SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3526
3527         /*
3528          * In case Re-tuning Timer is not disabled, the actual value of
3529          * re-tuning timer will be 2 ^ (n - 1).
3530          */
3531         if (host->tuning_count)
3532                 host->tuning_count = 1 << (host->tuning_count - 1);
3533
3534         /* Re-tuning mode supported by the Host Controller */
3535         host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3536                              SDHCI_RETUNING_MODE_SHIFT;
3537
3538         ocr_avail = 0;
3539
3540         /*
3541          * According to SD Host Controller spec v3.00, if the Host System
3542          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3543          * the value is meaningful only if Voltage Support in the Capabilities
3544          * register is set. The actual current value is 4 times the register
3545          * value.
3546          */
3547         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3548         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3549                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3550                 if (curr > 0) {
3551
3552                         /* convert to SDHCI_MAX_CURRENT format */
3553                         curr = curr/1000;  /* convert to mA */
3554                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3555
3556                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3557                         max_current_caps =
3558                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3559                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3560                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3561                 }
3562         }
3563
3564         if (host->caps & SDHCI_CAN_VDD_330) {
3565                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3566
3567                 mmc->max_current_330 = ((max_current_caps &
3568                                    SDHCI_MAX_CURRENT_330_MASK) >>
3569                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3570                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3571         }
3572         if (host->caps & SDHCI_CAN_VDD_300) {
3573                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3574
3575                 mmc->max_current_300 = ((max_current_caps &
3576                                    SDHCI_MAX_CURRENT_300_MASK) >>
3577                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3578                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3579         }
3580         if (host->caps & SDHCI_CAN_VDD_180) {
3581                 ocr_avail |= MMC_VDD_165_195;
3582
3583                 mmc->max_current_180 = ((max_current_caps &
3584                                    SDHCI_MAX_CURRENT_180_MASK) >>
3585                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3586                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3587         }
3588
3589         /* If OCR set by host, use it instead. */
3590         if (host->ocr_mask)
3591                 ocr_avail = host->ocr_mask;
3592
3593         /* If OCR set by external regulators, give it highest prio. */
3594         if (mmc->ocr_avail)
3595                 ocr_avail = mmc->ocr_avail;
3596
3597         mmc->ocr_avail = ocr_avail;
3598         mmc->ocr_avail_sdio = ocr_avail;
3599         if (host->ocr_avail_sdio)
3600                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3601         mmc->ocr_avail_sd = ocr_avail;
3602         if (host->ocr_avail_sd)
3603                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3604         else /* normal SD controllers don't support 1.8V */
3605                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3606         mmc->ocr_avail_mmc = ocr_avail;
3607         if (host->ocr_avail_mmc)
3608                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3609
3610         if (mmc->ocr_avail == 0) {
3611                 pr_err("%s: Hardware doesn't report any support voltages.\n",
3612                        mmc_hostname(mmc));
3613                 ret = -ENODEV;
3614                 goto unreg;
3615         }
3616
3617         if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3618                           MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3619                           MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3620             (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3621                 host->flags |= SDHCI_SIGNALING_180;
3622
3623         if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3624                 host->flags |= SDHCI_SIGNALING_120;
3625
3626         spin_lock_init(&host->lock);
3627
3628         /*
3629          * Maximum number of segments. Depends on if the hardware
3630          * can do scatter/gather or not.
3631          */
3632         if (host->flags & SDHCI_USE_ADMA)
3633                 mmc->max_segs = SDHCI_MAX_SEGS;
3634         else if (host->flags & SDHCI_USE_SDMA)
3635                 mmc->max_segs = 1;
3636         else /* PIO */
3637                 mmc->max_segs = SDHCI_MAX_SEGS;
3638
3639         /*
3640          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3641          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3642          * is less anyway.
3643          */
3644         mmc->max_req_size = 524288;
3645
3646         /*
3647          * Maximum segment size. Could be one segment with the maximum number
3648          * of bytes. When doing hardware scatter/gather, each entry cannot
3649          * be larger than 64 KiB though.
3650          */
3651         if (host->flags & SDHCI_USE_ADMA) {
3652                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3653                         mmc->max_seg_size = 65535;
3654                 else
3655                         mmc->max_seg_size = 65536;
3656         } else {
3657                 mmc->max_seg_size = mmc->max_req_size;
3658         }
3659
3660         /*
3661          * Maximum block size. This varies from controller to controller and
3662          * is specified in the capabilities register.
3663          */
3664         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3665                 mmc->max_blk_size = 2;
3666         } else {
3667                 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3668                                 SDHCI_MAX_BLOCK_SHIFT;
3669                 if (mmc->max_blk_size >= 3) {
3670                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3671                                 mmc_hostname(mmc));
3672                         mmc->max_blk_size = 0;
3673                 }
3674         }
3675
3676         mmc->max_blk_size = 512 << mmc->max_blk_size;
3677
3678         /*
3679          * Maximum block count.
3680          */
3681         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3682
3683         return 0;
3684
3685 unreg:
3686         if (!IS_ERR(mmc->supply.vqmmc))
3687                 regulator_disable(mmc->supply.vqmmc);
3688 undma:
3689         if (host->align_buffer)
3690                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3691                                   host->adma_table_sz, host->align_buffer,
3692                                   host->align_addr);
3693         host->adma_table = NULL;
3694         host->align_buffer = NULL;
3695
3696         return ret;
3697 }
3698 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3699
3700 void sdhci_cleanup_host(struct sdhci_host *host)
3701 {
3702         struct mmc_host *mmc = host->mmc;
3703
3704         if (!IS_ERR(mmc->supply.vqmmc))
3705                 regulator_disable(mmc->supply.vqmmc);
3706
3707         if (host->align_buffer)
3708                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3709                                   host->adma_table_sz, host->align_buffer,
3710                                   host->align_addr);
3711         host->adma_table = NULL;
3712         host->align_buffer = NULL;
3713 }
3714 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
3715
3716 int __sdhci_add_host(struct sdhci_host *host)
3717 {
3718         struct mmc_host *mmc = host->mmc;
3719         int ret;
3720
3721         /*
3722          * Init tasklets.
3723          */
3724         tasklet_init(&host->finish_tasklet,
3725                 sdhci_tasklet_finish, (unsigned long)host);
3726
3727         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3728         setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3729                     (unsigned long)host);
3730
3731         init_waitqueue_head(&host->buf_ready_int);
3732
3733         sdhci_init(host, 0);
3734
3735         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3736                                    IRQF_SHARED, mmc_hostname(mmc), host);
3737         if (ret) {
3738                 pr_err("%s: Failed to request IRQ %d: %d\n",
3739                        mmc_hostname(mmc), host->irq, ret);
3740                 goto untasklet;
3741         }
3742
3743 #ifdef CONFIG_MMC_DEBUG
3744         sdhci_dumpregs(host);
3745 #endif
3746
3747         ret = sdhci_led_register(host);
3748         if (ret) {
3749                 pr_err("%s: Failed to register LED device: %d\n",
3750                        mmc_hostname(mmc), ret);
3751                 goto unirq;
3752         }
3753
3754         mmiowb();
3755
3756         ret = mmc_add_host(mmc);
3757         if (ret)
3758                 goto unled;
3759
3760         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3761                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3762                 (host->flags & SDHCI_USE_ADMA) ?
3763                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3764                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3765
3766         sdhci_enable_card_detection(host);
3767
3768         return 0;
3769
3770 unled:
3771         sdhci_led_unregister(host);
3772 unirq:
3773         sdhci_do_reset(host, SDHCI_RESET_ALL);
3774         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3775         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3776         free_irq(host->irq, host);
3777 untasklet:
3778         tasklet_kill(&host->finish_tasklet);
3779
3780         return ret;
3781 }
3782 EXPORT_SYMBOL_GPL(__sdhci_add_host);
3783
3784 int sdhci_add_host(struct sdhci_host *host)
3785 {
3786         int ret;
3787
3788         ret = sdhci_setup_host(host);
3789         if (ret)
3790                 return ret;
3791
3792         ret = __sdhci_add_host(host);
3793         if (ret)
3794                 goto cleanup;
3795
3796         return 0;
3797
3798 cleanup:
3799         sdhci_cleanup_host(host);
3800
3801         return ret;
3802 }
3803 EXPORT_SYMBOL_GPL(sdhci_add_host);
3804
3805 void sdhci_remove_host(struct sdhci_host *host, int dead)
3806 {
3807         struct mmc_host *mmc = host->mmc;
3808         unsigned long flags;
3809
3810         if (dead) {
3811                 spin_lock_irqsave(&host->lock, flags);
3812
3813                 host->flags |= SDHCI_DEVICE_DEAD;
3814
3815                 if (sdhci_has_requests(host)) {
3816                         pr_err("%s: Controller removed during "
3817                                 " transfer!\n", mmc_hostname(mmc));
3818                         sdhci_error_out_mrqs(host, -ENOMEDIUM);
3819                 }
3820
3821                 spin_unlock_irqrestore(&host->lock, flags);
3822         }
3823
3824         sdhci_disable_card_detection(host);
3825
3826         mmc_remove_host(mmc);
3827
3828         sdhci_led_unregister(host);
3829
3830         if (!dead)
3831                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3832
3833         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3834         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3835         free_irq(host->irq, host);
3836
3837         del_timer_sync(&host->timer);
3838         del_timer_sync(&host->data_timer);
3839
3840         tasklet_kill(&host->finish_tasklet);
3841
3842         if (!IS_ERR(mmc->supply.vqmmc))
3843                 regulator_disable(mmc->supply.vqmmc);
3844
3845         if (host->align_buffer)
3846                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3847                                   host->adma_table_sz, host->align_buffer,
3848                                   host->align_addr);
3849
3850         host->adma_table = NULL;
3851         host->align_buffer = NULL;
3852 }
3853
3854 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3855
3856 void sdhci_free_host(struct sdhci_host *host)
3857 {
3858         mmc_free_host(host->mmc);
3859 }
3860
3861 EXPORT_SYMBOL_GPL(sdhci_free_host);
3862
3863 /*****************************************************************************\
3864  *                                                                           *
3865  * Driver init/exit                                                          *
3866  *                                                                           *
3867 \*****************************************************************************/
3868
3869 static int __init sdhci_drv_init(void)
3870 {
3871         pr_info(DRIVER_NAME
3872                 ": Secure Digital Host Controller Interface driver\n");
3873         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3874
3875         return 0;
3876 }
3877
3878 static void __exit sdhci_drv_exit(void)
3879 {
3880 }
3881
3882 module_init(sdhci_drv_init);
3883 module_exit(sdhci_drv_exit);
3884
3885 module_param(debug_quirks, uint, 0444);
3886 module_param(debug_quirks2, uint, 0444);
3887
3888 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3889 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3890 MODULE_LICENSE("GPL");
3891
3892 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3893 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");