2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
50 static void sdhci_finish_data(struct sdhci_host *);
52 static void sdhci_finish_command(struct sdhci_host *);
53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54 static void sdhci_tuning_timer(unsigned long data);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
58 static int sdhci_runtime_pm_get(struct sdhci_host *host);
59 static int sdhci_runtime_pm_put(struct sdhci_host *host);
60 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
63 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79 static void sdhci_dumpregs(struct sdhci_host *host)
81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
82 mmc_hostname(host->mmc));
84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
112 sdhci_readl(host, SDHCI_CAPABILITIES),
113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
115 sdhci_readw(host, SDHCI_COMMAND),
116 sdhci_readl(host, SDHCI_MAX_CURRENT));
117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
120 if (host->flags & SDHCI_USE_ADMA) {
121 if (host->flags & SDHCI_USE_64_BIT_DMA)
122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
128 readl(host->ioaddr + SDHCI_ADMA_ERROR),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
132 pr_debug(DRIVER_NAME ": ===========================================\n");
135 /*****************************************************************************\
137 * Low level functions *
139 \*****************************************************************************/
141 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
146 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
150 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
153 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
154 SDHCI_INT_CARD_INSERT;
156 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
159 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
160 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
163 static void sdhci_enable_card_detection(struct sdhci_host *host)
165 sdhci_set_card_detection(host, true);
168 static void sdhci_disable_card_detection(struct sdhci_host *host)
170 sdhci_set_card_detection(host, false);
173 void sdhci_reset(struct sdhci_host *host, u8 mask)
175 unsigned long timeout;
177 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
179 if (mask & SDHCI_RESET_ALL) {
181 /* Reset-all turns off SD Bus Power */
182 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
183 sdhci_runtime_pm_bus_off(host);
186 /* Wait max 100 ms */
189 /* hw clears the bit when it's done */
190 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
192 pr_err("%s: Reset 0x%x never completed.\n",
193 mmc_hostname(host->mmc), (int)mask);
194 sdhci_dumpregs(host);
201 EXPORT_SYMBOL_GPL(sdhci_reset);
203 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
206 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
211 host->ops->reset(host, mask);
213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
226 static void sdhci_init(struct sdhci_host *host, int soft)
229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
231 sdhci_do_reset(host, SDHCI_RESET_ALL);
233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
243 /* force clock reconfiguration */
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
249 static void sdhci_reinit(struct sdhci_host *host)
253 * Retuning stuffs are affected by different cards inserted and only
254 * applicable to UHS-I cards. So reset these fields to their initial
255 * value when card is removed.
257 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
258 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
260 del_timer_sync(&host->tuning_timer);
261 host->flags &= ~SDHCI_NEEDS_RETUNING;
263 sdhci_enable_card_detection(host);
266 static void sdhci_activate_led(struct sdhci_host *host)
270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271 ctrl |= SDHCI_CTRL_LED;
272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
275 static void sdhci_deactivate_led(struct sdhci_host *host)
279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
280 ctrl &= ~SDHCI_CTRL_LED;
281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
284 #ifdef SDHCI_USE_LEDS_CLASS
285 static void sdhci_led_control(struct led_classdev *led,
286 enum led_brightness brightness)
288 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
291 spin_lock_irqsave(&host->lock, flags);
293 if (host->runtime_suspended)
296 if (brightness == LED_OFF)
297 sdhci_deactivate_led(host);
299 sdhci_activate_led(host);
301 spin_unlock_irqrestore(&host->lock, flags);
305 /*****************************************************************************\
309 \*****************************************************************************/
311 static void sdhci_read_block_pio(struct sdhci_host *host)
314 size_t blksize, len, chunk;
315 u32 uninitialized_var(scratch);
318 DBG("PIO reading\n");
320 blksize = host->data->blksz;
323 local_irq_save(flags);
326 if (!sg_miter_next(&host->sg_miter))
329 len = min(host->sg_miter.length, blksize);
332 host->sg_miter.consumed = len;
334 buf = host->sg_miter.addr;
338 scratch = sdhci_readl(host, SDHCI_BUFFER);
342 *buf = scratch & 0xFF;
351 sg_miter_stop(&host->sg_miter);
353 local_irq_restore(flags);
356 static void sdhci_write_block_pio(struct sdhci_host *host)
359 size_t blksize, len, chunk;
363 DBG("PIO writing\n");
365 blksize = host->data->blksz;
369 local_irq_save(flags);
372 if (!sg_miter_next(&host->sg_miter))
375 len = min(host->sg_miter.length, blksize);
378 host->sg_miter.consumed = len;
380 buf = host->sg_miter.addr;
383 scratch |= (u32)*buf << (chunk * 8);
389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
390 sdhci_writel(host, scratch, SDHCI_BUFFER);
397 sg_miter_stop(&host->sg_miter);
399 local_irq_restore(flags);
402 static void sdhci_transfer_pio(struct sdhci_host *host)
408 if (host->blocks == 0)
411 if (host->data->flags & MMC_DATA_READ)
412 mask = SDHCI_DATA_AVAILABLE;
414 mask = SDHCI_SPACE_AVAILABLE;
417 * Some controllers (JMicron JMB38x) mess up the buffer bits
418 * for transfers < 4 bytes. As long as it is just one block,
419 * we can ignore the bits.
421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
422 (host->data->blocks == 1))
425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
429 if (host->data->flags & MMC_DATA_READ)
430 sdhci_read_block_pio(host);
432 sdhci_write_block_pio(host);
435 if (host->blocks == 0)
439 DBG("PIO transfer complete.\n");
442 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
444 local_irq_save(*flags);
445 return kmap_atomic(sg_page(sg)) + sg->offset;
448 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
450 kunmap_atomic(buffer);
451 local_irq_restore(*flags);
454 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
455 dma_addr_t addr, int len, unsigned cmd)
457 struct sdhci_adma2_64_desc *dma_desc = desc;
459 /* 32-bit and 64-bit descriptors have these members in same position */
460 dma_desc->cmd = cpu_to_le16(cmd);
461 dma_desc->len = cpu_to_le16(len);
462 dma_desc->addr_lo = cpu_to_le32((u32)addr);
464 if (host->flags & SDHCI_USE_64_BIT_DMA)
465 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
468 static void sdhci_adma_mark_end(void *desc)
470 struct sdhci_adma2_64_desc *dma_desc = desc;
472 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
473 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
476 static int sdhci_adma_table_pre(struct sdhci_host *host,
477 struct mmc_data *data)
484 dma_addr_t align_addr;
487 struct scatterlist *sg;
493 * The spec does not specify endianness of descriptor table.
494 * We currently guess that it is LE.
497 if (data->flags & MMC_DATA_READ)
498 direction = DMA_FROM_DEVICE;
500 direction = DMA_TO_DEVICE;
502 host->align_addr = dma_map_single(mmc_dev(host->mmc),
503 host->align_buffer, host->align_buffer_sz, direction);
504 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
506 BUG_ON(host->align_addr & host->align_mask);
508 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
509 data->sg, data->sg_len, direction);
510 if (host->sg_count == 0)
513 desc = host->adma_table;
514 align = host->align_buffer;
516 align_addr = host->align_addr;
518 for_each_sg(data->sg, sg, host->sg_count, i) {
519 addr = sg_dma_address(sg);
520 len = sg_dma_len(sg);
523 * The SDHCI specification states that ADMA
524 * addresses must be 32-bit aligned. If they
525 * aren't, then we use a bounce buffer for
526 * the (up to three) bytes that screw up the
529 offset = (host->align_sz - (addr & host->align_mask)) &
532 if (data->flags & MMC_DATA_WRITE) {
533 buffer = sdhci_kmap_atomic(sg, &flags);
534 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
535 (PAGE_SIZE - offset));
536 memcpy(align, buffer, offset);
537 sdhci_kunmap_atomic(buffer, &flags);
541 sdhci_adma_write_desc(host, desc, align_addr, offset,
544 BUG_ON(offset > 65536);
546 align += host->align_sz;
547 align_addr += host->align_sz;
549 desc += host->desc_sz;
558 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
559 desc += host->desc_sz;
562 * If this triggers then we have a calculation bug
565 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
568 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
570 * Mark the last descriptor as the terminating descriptor
572 if (desc != host->adma_table) {
573 desc -= host->desc_sz;
574 sdhci_adma_mark_end(desc);
578 * Add a terminating entry.
581 /* nop, end, valid */
582 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
586 * Resync align buffer as we might have changed it.
588 if (data->flags & MMC_DATA_WRITE) {
589 dma_sync_single_for_device(mmc_dev(host->mmc),
590 host->align_addr, host->align_buffer_sz, direction);
596 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
597 host->align_buffer_sz, direction);
602 static void sdhci_adma_table_post(struct sdhci_host *host,
603 struct mmc_data *data)
607 struct scatterlist *sg;
614 if (data->flags & MMC_DATA_READ)
615 direction = DMA_FROM_DEVICE;
617 direction = DMA_TO_DEVICE;
619 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
620 host->align_buffer_sz, direction);
622 /* Do a quick scan of the SG list for any unaligned mappings */
623 has_unaligned = false;
624 for_each_sg(data->sg, sg, host->sg_count, i)
625 if (sg_dma_address(sg) & host->align_mask) {
626 has_unaligned = true;
630 if (has_unaligned && data->flags & MMC_DATA_READ) {
631 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
632 data->sg_len, direction);
634 align = host->align_buffer;
636 for_each_sg(data->sg, sg, host->sg_count, i) {
637 if (sg_dma_address(sg) & host->align_mask) {
638 size = host->align_sz -
639 (sg_dma_address(sg) & host->align_mask);
641 buffer = sdhci_kmap_atomic(sg, &flags);
642 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
644 memcpy(buffer, align, size);
645 sdhci_kunmap_atomic(buffer, &flags);
647 align += host->align_sz;
652 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
653 data->sg_len, direction);
656 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
659 struct mmc_data *data = cmd->data;
660 unsigned target_timeout, current_timeout;
663 * If the host controller provides us with an incorrect timeout
664 * value, just skip the check and use 0xE. The hardware may take
665 * longer to time out, but that's much better than having a too-short
668 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
671 /* Unspecified timeout, assume max */
672 if (!data && !cmd->busy_timeout)
677 target_timeout = cmd->busy_timeout * 1000;
679 target_timeout = data->timeout_ns / 1000;
681 target_timeout += data->timeout_clks / host->clock;
685 * Figure out needed cycles.
686 * We do this in steps in order to fit inside a 32 bit int.
687 * The first step is the minimum timeout, which will have a
688 * minimum resolution of 6 bits:
689 * (1) 2^13*1000 > 2^22,
690 * (2) host->timeout_clk < 2^16
695 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
696 while (current_timeout < target_timeout) {
698 current_timeout <<= 1;
704 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
705 mmc_hostname(host->mmc), count, cmd->opcode);
712 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
714 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
715 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
717 if (host->flags & SDHCI_REQ_USE_DMA)
718 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
720 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
722 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
723 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
726 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
730 if (host->ops->set_timeout) {
731 host->ops->set_timeout(host, cmd);
733 count = sdhci_calc_timeout(host, cmd);
734 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
738 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
741 struct mmc_data *data = cmd->data;
746 if (data || (cmd->flags & MMC_RSP_BUSY))
747 sdhci_set_timeout(host, cmd);
753 BUG_ON(data->blksz * data->blocks > 524288);
754 BUG_ON(data->blksz > host->mmc->max_blk_size);
755 BUG_ON(data->blocks > 65535);
758 host->data_early = 0;
759 host->data->bytes_xfered = 0;
761 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
762 host->flags |= SDHCI_REQ_USE_DMA;
765 * FIXME: This doesn't account for merging when mapping the
768 if (host->flags & SDHCI_REQ_USE_DMA) {
770 struct scatterlist *sg;
773 if (host->flags & SDHCI_USE_ADMA) {
774 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
777 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
781 if (unlikely(broken)) {
782 for_each_sg(data->sg, sg, data->sg_len, i) {
783 if (sg->length & 0x3) {
784 DBG("Reverting to PIO because of "
785 "transfer size (%d)\n",
787 host->flags &= ~SDHCI_REQ_USE_DMA;
795 * The assumption here being that alignment is the same after
796 * translation to device address space.
798 if (host->flags & SDHCI_REQ_USE_DMA) {
800 struct scatterlist *sg;
803 if (host->flags & SDHCI_USE_ADMA) {
805 * As we use 3 byte chunks to work around
806 * alignment problems, we need to check this
809 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
812 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
816 if (unlikely(broken)) {
817 for_each_sg(data->sg, sg, data->sg_len, i) {
818 if (sg->offset & 0x3) {
819 DBG("Reverting to PIO because of "
821 host->flags &= ~SDHCI_REQ_USE_DMA;
828 if (host->flags & SDHCI_REQ_USE_DMA) {
829 if (host->flags & SDHCI_USE_ADMA) {
830 ret = sdhci_adma_table_pre(host, data);
833 * This only happens when someone fed
834 * us an invalid request.
837 host->flags &= ~SDHCI_REQ_USE_DMA;
839 sdhci_writel(host, host->adma_addr,
841 if (host->flags & SDHCI_USE_64_BIT_DMA)
843 (u64)host->adma_addr >> 32,
844 SDHCI_ADMA_ADDRESS_HI);
849 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
850 data->sg, data->sg_len,
851 (data->flags & MMC_DATA_READ) ?
856 * This only happens when someone fed
857 * us an invalid request.
860 host->flags &= ~SDHCI_REQ_USE_DMA;
862 WARN_ON(sg_cnt != 1);
863 sdhci_writel(host, sg_dma_address(data->sg),
870 * Always adjust the DMA selection as some controllers
871 * (e.g. JMicron) can't do PIO properly when the selection
874 if (host->version >= SDHCI_SPEC_200) {
875 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
876 ctrl &= ~SDHCI_CTRL_DMA_MASK;
877 if ((host->flags & SDHCI_REQ_USE_DMA) &&
878 (host->flags & SDHCI_USE_ADMA)) {
879 if (host->flags & SDHCI_USE_64_BIT_DMA)
880 ctrl |= SDHCI_CTRL_ADMA64;
882 ctrl |= SDHCI_CTRL_ADMA32;
884 ctrl |= SDHCI_CTRL_SDMA;
886 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
889 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
892 flags = SG_MITER_ATOMIC;
893 if (host->data->flags & MMC_DATA_READ)
894 flags |= SG_MITER_TO_SG;
896 flags |= SG_MITER_FROM_SG;
897 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
898 host->blocks = data->blocks;
901 sdhci_set_transfer_irqs(host);
903 /* Set the DMA boundary value and block size */
904 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
905 data->blksz), SDHCI_BLOCK_SIZE);
906 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
909 static void sdhci_set_transfer_mode(struct sdhci_host *host,
910 struct mmc_command *cmd)
913 struct mmc_data *data = cmd->data;
917 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
918 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
920 /* clear Auto CMD settings for no data CMDs */
921 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
922 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
923 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
928 WARN_ON(!host->data);
930 mode = SDHCI_TRNS_BLK_CNT_EN;
931 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
932 mode |= SDHCI_TRNS_MULTI;
934 * If we are sending CMD23, CMD12 never gets sent
935 * on successful completion (so no Auto-CMD12).
937 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
938 mode |= SDHCI_TRNS_AUTO_CMD12;
939 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
940 mode |= SDHCI_TRNS_AUTO_CMD23;
941 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
945 if (data->flags & MMC_DATA_READ)
946 mode |= SDHCI_TRNS_READ;
947 if (host->flags & SDHCI_REQ_USE_DMA)
948 mode |= SDHCI_TRNS_DMA;
950 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
953 static void sdhci_finish_data(struct sdhci_host *host)
955 struct mmc_data *data;
962 if (host->flags & SDHCI_REQ_USE_DMA) {
963 if (host->flags & SDHCI_USE_ADMA)
964 sdhci_adma_table_post(host, data);
966 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
967 data->sg_len, (data->flags & MMC_DATA_READ) ?
968 DMA_FROM_DEVICE : DMA_TO_DEVICE);
973 * The specification states that the block count register must
974 * be updated, but it does not specify at what point in the
975 * data flow. That makes the register entirely useless to read
976 * back so we have to assume that nothing made it to the card
977 * in the event of an error.
980 data->bytes_xfered = 0;
982 data->bytes_xfered = data->blksz * data->blocks;
985 * Need to send CMD12 if -
986 * a) open-ended multiblock transfer (no CMD23)
987 * b) error in multiblock transfer
994 * The controller needs a reset of internal state machines
995 * upon error conditions.
998 sdhci_do_reset(host, SDHCI_RESET_CMD);
999 sdhci_do_reset(host, SDHCI_RESET_DATA);
1002 sdhci_send_command(host, data->stop);
1004 tasklet_schedule(&host->finish_tasklet);
1007 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1011 unsigned long timeout;
1015 /* Wait max 10 ms */
1018 mask = SDHCI_CMD_INHIBIT;
1019 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1020 mask |= SDHCI_DATA_INHIBIT;
1022 /* We shouldn't wait for data inihibit for stop commands, even
1023 though they might use busy signaling */
1024 if (host->mrq->data && (cmd == host->mrq->data->stop))
1025 mask &= ~SDHCI_DATA_INHIBIT;
1027 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1029 pr_err("%s: Controller never released "
1030 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1031 sdhci_dumpregs(host);
1033 tasklet_schedule(&host->finish_tasklet);
1041 if (!cmd->data && cmd->busy_timeout > 9000)
1042 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1045 mod_timer(&host->timer, timeout);
1048 host->busy_handle = 0;
1050 sdhci_prepare_data(host, cmd);
1052 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1054 sdhci_set_transfer_mode(host, cmd);
1056 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1057 pr_err("%s: Unsupported response type!\n",
1058 mmc_hostname(host->mmc));
1059 cmd->error = -EINVAL;
1060 tasklet_schedule(&host->finish_tasklet);
1064 if (!(cmd->flags & MMC_RSP_PRESENT))
1065 flags = SDHCI_CMD_RESP_NONE;
1066 else if (cmd->flags & MMC_RSP_136)
1067 flags = SDHCI_CMD_RESP_LONG;
1068 else if (cmd->flags & MMC_RSP_BUSY)
1069 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1071 flags = SDHCI_CMD_RESP_SHORT;
1073 if (cmd->flags & MMC_RSP_CRC)
1074 flags |= SDHCI_CMD_CRC;
1075 if (cmd->flags & MMC_RSP_OPCODE)
1076 flags |= SDHCI_CMD_INDEX;
1078 /* CMD19 is special in that the Data Present Select should be set */
1079 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1080 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1081 flags |= SDHCI_CMD_DATA;
1083 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1085 EXPORT_SYMBOL_GPL(sdhci_send_command);
1087 static void sdhci_finish_command(struct sdhci_host *host)
1091 BUG_ON(host->cmd == NULL);
1093 if (host->cmd->flags & MMC_RSP_PRESENT) {
1094 if (host->cmd->flags & MMC_RSP_136) {
1095 /* CRC is stripped so we need to do some shifting. */
1096 for (i = 0;i < 4;i++) {
1097 host->cmd->resp[i] = sdhci_readl(host,
1098 SDHCI_RESPONSE + (3-i)*4) << 8;
1100 host->cmd->resp[i] |=
1102 SDHCI_RESPONSE + (3-i)*4-1);
1105 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1109 host->cmd->error = 0;
1111 /* Finished CMD23, now send actual command. */
1112 if (host->cmd == host->mrq->sbc) {
1114 sdhci_send_command(host, host->mrq->cmd);
1117 /* Processed actual command. */
1118 if (host->data && host->data_early)
1119 sdhci_finish_data(host);
1121 if (!host->cmd->data)
1122 tasklet_schedule(&host->finish_tasklet);
1128 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1132 switch (host->timing) {
1133 case MMC_TIMING_UHS_SDR12:
1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1136 case MMC_TIMING_UHS_SDR25:
1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1139 case MMC_TIMING_UHS_SDR50:
1140 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1142 case MMC_TIMING_UHS_SDR104:
1143 case MMC_TIMING_MMC_HS200:
1144 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1146 case MMC_TIMING_UHS_DDR50:
1147 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1149 case MMC_TIMING_MMC_HS400:
1150 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1153 pr_warn("%s: Invalid UHS-I mode selected\n",
1154 mmc_hostname(host->mmc));
1155 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1161 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1163 int div = 0; /* Initialized for compiler warning */
1164 int real_div = div, clk_mul = 1;
1166 unsigned long timeout;
1168 host->mmc->actual_clock = 0;
1170 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1175 if (host->version >= SDHCI_SPEC_300) {
1176 if (host->preset_enabled) {
1179 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1180 pre_val = sdhci_get_preset_value(host);
1181 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1182 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1183 if (host->clk_mul &&
1184 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1185 clk = SDHCI_PROG_CLOCK_MODE;
1187 clk_mul = host->clk_mul;
1189 real_div = max_t(int, 1, div << 1);
1195 * Check if the Host Controller supports Programmable Clock
1198 if (host->clk_mul) {
1199 for (div = 1; div <= 1024; div++) {
1200 if ((host->max_clk * host->clk_mul / div)
1205 * Set Programmable Clock Mode in the Clock
1208 clk = SDHCI_PROG_CLOCK_MODE;
1210 clk_mul = host->clk_mul;
1213 /* Version 3.00 divisors must be a multiple of 2. */
1214 if (host->max_clk <= clock)
1217 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1219 if ((host->max_clk / div) <= clock)
1227 /* Version 2.00 divisors must be a power of 2. */
1228 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1229 if ((host->max_clk / div) <= clock)
1238 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1239 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1240 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1241 << SDHCI_DIVIDER_HI_SHIFT;
1242 clk |= SDHCI_CLOCK_INT_EN;
1243 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1245 /* Wait max 20 ms */
1247 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1248 & SDHCI_CLOCK_INT_STABLE)) {
1250 pr_err("%s: Internal clock never "
1251 "stabilised.\n", mmc_hostname(host->mmc));
1252 sdhci_dumpregs(host);
1259 clk |= SDHCI_CLOCK_CARD_EN;
1260 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1262 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1264 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1267 struct mmc_host *mmc = host->mmc;
1270 if (!IS_ERR(mmc->supply.vmmc)) {
1271 spin_unlock_irq(&host->lock);
1272 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1273 spin_lock_irq(&host->lock);
1277 if (mode != MMC_POWER_OFF) {
1279 case MMC_VDD_165_195:
1280 pwr = SDHCI_POWER_180;
1284 pwr = SDHCI_POWER_300;
1288 pwr = SDHCI_POWER_330;
1295 if (host->pwr == pwr)
1301 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1302 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1303 sdhci_runtime_pm_bus_off(host);
1307 * Spec says that we should clear the power reg before setting
1308 * a new value. Some controllers don't seem to like this though.
1310 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1311 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1314 * At least the Marvell CaFe chip gets confused if we set the
1315 * voltage and set turn on power at the same time, so set the
1318 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1319 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1321 pwr |= SDHCI_POWER_ON;
1323 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1325 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1326 sdhci_runtime_pm_bus_on(host);
1329 * Some controllers need an extra 10ms delay of 10ms before
1330 * they can apply clock after applying power
1332 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1337 /*****************************************************************************\
1341 \*****************************************************************************/
1343 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1345 struct sdhci_host *host;
1347 unsigned long flags;
1350 host = mmc_priv(mmc);
1352 sdhci_runtime_pm_get(host);
1354 spin_lock_irqsave(&host->lock, flags);
1356 WARN_ON(host->mrq != NULL);
1358 #ifndef SDHCI_USE_LEDS_CLASS
1359 sdhci_activate_led(host);
1363 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1364 * requests if Auto-CMD12 is enabled.
1366 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1368 mrq->data->stop = NULL;
1376 * Firstly check card presence from cd-gpio. The return could
1377 * be one of the following possibilities:
1378 * negative: cd-gpio is not available
1379 * zero: cd-gpio is used, and card is removed
1380 * one: cd-gpio is used, and card is present
1382 present = mmc_gpio_get_cd(host->mmc);
1384 /* If polling, assume that the card is always present. */
1385 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1388 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1392 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1393 host->mrq->cmd->error = -ENOMEDIUM;
1394 tasklet_schedule(&host->finish_tasklet);
1398 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1400 * Check if the re-tuning timer has already expired and there
1401 * is no on-going data transfer and DAT0 is not busy. If so,
1402 * we need to execute tuning procedure before sending command.
1404 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1405 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1406 (present_state & SDHCI_DATA_0_LVL_MASK)) {
1408 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1410 mmc->card->type == MMC_TYPE_MMC ?
1411 MMC_SEND_TUNING_BLOCK_HS200 :
1412 MMC_SEND_TUNING_BLOCK;
1414 /* Here we need to set the host->mrq to NULL,
1415 * in case the pending finish_tasklet
1416 * finishes it incorrectly.
1420 spin_unlock_irqrestore(&host->lock, flags);
1421 sdhci_execute_tuning(mmc, tuning_opcode);
1422 spin_lock_irqsave(&host->lock, flags);
1424 /* Restore original mmc_request structure */
1429 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1430 sdhci_send_command(host, mrq->sbc);
1432 sdhci_send_command(host, mrq->cmd);
1436 spin_unlock_irqrestore(&host->lock, flags);
1439 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1443 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1444 if (width == MMC_BUS_WIDTH_8) {
1445 ctrl &= ~SDHCI_CTRL_4BITBUS;
1446 if (host->version >= SDHCI_SPEC_300)
1447 ctrl |= SDHCI_CTRL_8BITBUS;
1449 if (host->version >= SDHCI_SPEC_300)
1450 ctrl &= ~SDHCI_CTRL_8BITBUS;
1451 if (width == MMC_BUS_WIDTH_4)
1452 ctrl |= SDHCI_CTRL_4BITBUS;
1454 ctrl &= ~SDHCI_CTRL_4BITBUS;
1456 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1458 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1460 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1464 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1465 /* Select Bus Speed Mode for host */
1466 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1467 if ((timing == MMC_TIMING_MMC_HS200) ||
1468 (timing == MMC_TIMING_UHS_SDR104))
1469 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1470 else if (timing == MMC_TIMING_UHS_SDR12)
1471 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1472 else if (timing == MMC_TIMING_UHS_SDR25)
1473 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1474 else if (timing == MMC_TIMING_UHS_SDR50)
1475 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1476 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1477 (timing == MMC_TIMING_MMC_DDR52))
1478 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1479 else if (timing == MMC_TIMING_MMC_HS400)
1480 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1481 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1483 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1485 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1487 unsigned long flags;
1489 struct mmc_host *mmc = host->mmc;
1491 spin_lock_irqsave(&host->lock, flags);
1493 if (host->flags & SDHCI_DEVICE_DEAD) {
1494 spin_unlock_irqrestore(&host->lock, flags);
1495 if (!IS_ERR(mmc->supply.vmmc) &&
1496 ios->power_mode == MMC_POWER_OFF)
1497 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1502 * Reset the chip on each power off.
1503 * Should clear out any weird states.
1505 if (ios->power_mode == MMC_POWER_OFF) {
1506 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1510 if (host->version >= SDHCI_SPEC_300 &&
1511 (ios->power_mode == MMC_POWER_UP) &&
1512 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1513 sdhci_enable_preset_value(host, false);
1515 if (!ios->clock || ios->clock != host->clock) {
1516 host->ops->set_clock(host, ios->clock);
1517 host->clock = ios->clock;
1519 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1521 host->timeout_clk = host->mmc->actual_clock ?
1522 host->mmc->actual_clock / 1000 :
1524 host->mmc->max_busy_timeout =
1525 host->ops->get_max_timeout_count ?
1526 host->ops->get_max_timeout_count(host) :
1528 host->mmc->max_busy_timeout /= host->timeout_clk;
1532 sdhci_set_power(host, ios->power_mode, ios->vdd);
1534 if (host->ops->platform_send_init_74_clocks)
1535 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1537 host->ops->set_bus_width(host, ios->bus_width);
1539 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1541 if ((ios->timing == MMC_TIMING_SD_HS ||
1542 ios->timing == MMC_TIMING_MMC_HS)
1543 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1544 ctrl |= SDHCI_CTRL_HISPD;
1546 ctrl &= ~SDHCI_CTRL_HISPD;
1548 if (host->version >= SDHCI_SPEC_300) {
1551 /* In case of UHS-I modes, set High Speed Enable */
1552 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1553 (ios->timing == MMC_TIMING_MMC_HS200) ||
1554 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1555 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1556 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1557 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1558 (ios->timing == MMC_TIMING_UHS_SDR25))
1559 ctrl |= SDHCI_CTRL_HISPD;
1561 if (!host->preset_enabled) {
1562 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1564 * We only need to set Driver Strength if the
1565 * preset value enable is not set.
1567 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1568 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1569 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1570 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1571 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1572 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1574 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1577 * According to SDHC Spec v3.00, if the Preset Value
1578 * Enable in the Host Control 2 register is set, we
1579 * need to reset SD Clock Enable before changing High
1580 * Speed Enable to avoid generating clock gliches.
1583 /* Reset SD Clock Enable */
1584 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1585 clk &= ~SDHCI_CLOCK_CARD_EN;
1586 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1588 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1590 /* Re-enable SD Clock */
1591 host->ops->set_clock(host, host->clock);
1594 /* Reset SD Clock Enable */
1595 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1596 clk &= ~SDHCI_CLOCK_CARD_EN;
1597 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1599 host->ops->set_uhs_signaling(host, ios->timing);
1600 host->timing = ios->timing;
1602 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1603 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1604 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1605 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1606 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1607 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1610 sdhci_enable_preset_value(host, true);
1611 preset = sdhci_get_preset_value(host);
1612 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1613 >> SDHCI_PRESET_DRV_SHIFT;
1616 /* Re-enable SD Clock */
1617 host->ops->set_clock(host, host->clock);
1619 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1622 * Some (ENE) controllers go apeshit on some ios operation,
1623 * signalling timeout and CRC errors even on CMD0. Resetting
1624 * it on each ios seems to solve the problem.
1626 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1627 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1630 spin_unlock_irqrestore(&host->lock, flags);
1633 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1635 struct sdhci_host *host = mmc_priv(mmc);
1637 sdhci_runtime_pm_get(host);
1638 sdhci_do_set_ios(host, ios);
1639 sdhci_runtime_pm_put(host);
1642 static int sdhci_do_get_cd(struct sdhci_host *host)
1644 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1646 if (host->flags & SDHCI_DEVICE_DEAD)
1649 /* If polling/nonremovable, assume that the card is always present. */
1650 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1651 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1654 /* Try slot gpio detect */
1655 if (!IS_ERR_VALUE(gpio_cd))
1658 /* Host native card detect */
1659 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1662 static int sdhci_get_cd(struct mmc_host *mmc)
1664 struct sdhci_host *host = mmc_priv(mmc);
1667 sdhci_runtime_pm_get(host);
1668 ret = sdhci_do_get_cd(host);
1669 sdhci_runtime_pm_put(host);
1673 static int sdhci_check_ro(struct sdhci_host *host)
1675 unsigned long flags;
1678 spin_lock_irqsave(&host->lock, flags);
1680 if (host->flags & SDHCI_DEVICE_DEAD)
1682 else if (host->ops->get_ro)
1683 is_readonly = host->ops->get_ro(host);
1685 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1686 & SDHCI_WRITE_PROTECT);
1688 spin_unlock_irqrestore(&host->lock, flags);
1690 /* This quirk needs to be replaced by a callback-function later */
1691 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1692 !is_readonly : is_readonly;
1695 #define SAMPLE_COUNT 5
1697 static int sdhci_do_get_ro(struct sdhci_host *host)
1701 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1702 return sdhci_check_ro(host);
1705 for (i = 0; i < SAMPLE_COUNT; i++) {
1706 if (sdhci_check_ro(host)) {
1707 if (++ro_count > SAMPLE_COUNT / 2)
1715 static void sdhci_hw_reset(struct mmc_host *mmc)
1717 struct sdhci_host *host = mmc_priv(mmc);
1719 if (host->ops && host->ops->hw_reset)
1720 host->ops->hw_reset(host);
1723 static int sdhci_get_ro(struct mmc_host *mmc)
1725 struct sdhci_host *host = mmc_priv(mmc);
1728 sdhci_runtime_pm_get(host);
1729 ret = sdhci_do_get_ro(host);
1730 sdhci_runtime_pm_put(host);
1734 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1736 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1738 host->ier |= SDHCI_INT_CARD_INT;
1740 host->ier &= ~SDHCI_INT_CARD_INT;
1742 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1743 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1748 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1750 struct sdhci_host *host = mmc_priv(mmc);
1751 unsigned long flags;
1753 sdhci_runtime_pm_get(host);
1755 spin_lock_irqsave(&host->lock, flags);
1757 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1759 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1761 sdhci_enable_sdio_irq_nolock(host, enable);
1762 spin_unlock_irqrestore(&host->lock, flags);
1764 sdhci_runtime_pm_put(host);
1767 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1768 struct mmc_ios *ios)
1770 struct mmc_host *mmc = host->mmc;
1775 * Signal Voltage Switching is only applicable for Host Controllers
1778 if (host->version < SDHCI_SPEC_300)
1781 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1783 switch (ios->signal_voltage) {
1784 case MMC_SIGNAL_VOLTAGE_330:
1785 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1786 ctrl &= ~SDHCI_CTRL_VDD_180;
1787 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1789 if (!IS_ERR(mmc->supply.vqmmc)) {
1790 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1793 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1799 usleep_range(5000, 5500);
1801 /* 3.3V regulator output should be stable within 5 ms */
1802 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1803 if (!(ctrl & SDHCI_CTRL_VDD_180))
1806 pr_warn("%s: 3.3V regulator output did not became stable\n",
1810 case MMC_SIGNAL_VOLTAGE_180:
1811 if (!IS_ERR(mmc->supply.vqmmc)) {
1812 ret = regulator_set_voltage(mmc->supply.vqmmc,
1815 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1822 * Enable 1.8V Signal Enable in the Host Control2
1825 ctrl |= SDHCI_CTRL_VDD_180;
1826 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1828 /* 1.8V regulator output should be stable within 5 ms */
1829 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1830 if (ctrl & SDHCI_CTRL_VDD_180)
1833 pr_warn("%s: 1.8V regulator output did not became stable\n",
1837 case MMC_SIGNAL_VOLTAGE_120:
1838 if (!IS_ERR(mmc->supply.vqmmc)) {
1839 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1842 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1849 /* No signal voltage switch required */
1854 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1855 struct mmc_ios *ios)
1857 struct sdhci_host *host = mmc_priv(mmc);
1860 if (host->version < SDHCI_SPEC_300)
1862 sdhci_runtime_pm_get(host);
1863 err = sdhci_do_start_signal_voltage_switch(host, ios);
1864 sdhci_runtime_pm_put(host);
1868 static int sdhci_card_busy(struct mmc_host *mmc)
1870 struct sdhci_host *host = mmc_priv(mmc);
1873 sdhci_runtime_pm_get(host);
1874 /* Check whether DAT[3:0] is 0000 */
1875 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1876 sdhci_runtime_pm_put(host);
1878 return !(present_state & SDHCI_DATA_LVL_MASK);
1881 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1883 struct sdhci_host *host = mmc_priv(mmc);
1885 int tuning_loop_counter = MAX_TUNING_LOOP;
1887 unsigned long flags;
1889 sdhci_runtime_pm_get(host);
1890 spin_lock_irqsave(&host->lock, flags);
1893 * The Host Controller needs tuning only in case of SDR104 mode
1894 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1895 * Capabilities register.
1896 * If the Host Controller supports the HS200 mode then the
1897 * tuning function has to be executed.
1899 switch (host->timing) {
1900 case MMC_TIMING_MMC_HS400:
1901 case MMC_TIMING_MMC_HS200:
1902 case MMC_TIMING_UHS_SDR104:
1905 case MMC_TIMING_UHS_SDR50:
1906 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1907 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1915 if (host->ops->platform_execute_tuning) {
1916 spin_unlock_irqrestore(&host->lock, flags);
1917 err = host->ops->platform_execute_tuning(host, opcode);
1918 sdhci_runtime_pm_put(host);
1922 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1923 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1924 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1927 * As per the Host Controller spec v3.00, tuning command
1928 * generates Buffer Read Ready interrupt, so enable that.
1930 * Note: The spec clearly says that when tuning sequence
1931 * is being performed, the controller does not generate
1932 * interrupts other than Buffer Read Ready interrupt. But
1933 * to make sure we don't hit a controller bug, we _only_
1934 * enable Buffer Read Ready interrupt here.
1936 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1937 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1940 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1941 * of loops reaches 40 times or a timeout of 150ms occurs.
1944 struct mmc_command cmd = {0};
1945 struct mmc_request mrq = {NULL};
1947 cmd.opcode = opcode;
1949 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1954 if (tuning_loop_counter-- == 0)
1961 * In response to CMD19, the card sends 64 bytes of tuning
1962 * block to the Host Controller. So we set the block size
1965 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1966 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1967 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1969 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1970 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1973 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1978 * The tuning block is sent by the card to the host controller.
1979 * So we set the TRNS_READ bit in the Transfer Mode register.
1980 * This also takes care of setting DMA Enable and Multi Block
1981 * Select in the same register to 0.
1983 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1985 sdhci_send_command(host, &cmd);
1990 spin_unlock_irqrestore(&host->lock, flags);
1991 /* Wait for Buffer Read Ready interrupt */
1992 wait_event_interruptible_timeout(host->buf_ready_int,
1993 (host->tuning_done == 1),
1994 msecs_to_jiffies(50));
1995 spin_lock_irqsave(&host->lock, flags);
1997 if (!host->tuning_done) {
1998 pr_info(DRIVER_NAME ": Timeout waiting for "
1999 "Buffer Read Ready interrupt during tuning "
2000 "procedure, falling back to fixed sampling "
2002 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2003 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2004 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2005 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2011 host->tuning_done = 0;
2013 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2015 /* eMMC spec does not require a delay between tuning cycles */
2016 if (opcode == MMC_SEND_TUNING_BLOCK)
2018 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2021 * The Host Driver has exhausted the maximum number of loops allowed,
2022 * so use fixed sampling frequency.
2024 if (tuning_loop_counter < 0) {
2025 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2026 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2028 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2029 pr_info(DRIVER_NAME ": Tuning procedure"
2030 " failed, falling back to fixed sampling"
2037 * If this is the very first time we are here, we start the retuning
2038 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2039 * flag won't be set, we check this condition before actually starting
2042 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2043 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2044 host->flags |= SDHCI_USING_RETUNING_TIMER;
2045 mod_timer(&host->tuning_timer, jiffies +
2046 host->tuning_count * HZ);
2047 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2048 host->flags &= ~SDHCI_NEEDS_RETUNING;
2049 /* Reload the new initial value for timer */
2050 mod_timer(&host->tuning_timer, jiffies +
2051 host->tuning_count * HZ);
2055 * In case tuning fails, host controllers which support re-tuning can
2056 * try tuning again at a later time, when the re-tuning timer expires.
2057 * So for these controllers, we return 0. Since there might be other
2058 * controllers who do not have this capability, we return error for
2059 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2060 * a retuning timer to do the retuning for the card.
2062 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2065 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2066 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2068 spin_unlock_irqrestore(&host->lock, flags);
2069 sdhci_runtime_pm_put(host);
2075 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2077 /* Host Controller v3.00 defines preset value registers */
2078 if (host->version < SDHCI_SPEC_300)
2082 * We only enable or disable Preset Value if they are not already
2083 * enabled or disabled respectively. Otherwise, we bail out.
2085 if (host->preset_enabled != enable) {
2086 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2089 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2091 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2093 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2096 host->flags |= SDHCI_PV_ENABLED;
2098 host->flags &= ~SDHCI_PV_ENABLED;
2100 host->preset_enabled = enable;
2104 static void sdhci_card_event(struct mmc_host *mmc)
2106 struct sdhci_host *host = mmc_priv(mmc);
2107 unsigned long flags;
2109 /* First check if client has provided their own card event */
2110 if (host->ops->card_event)
2111 host->ops->card_event(host);
2113 spin_lock_irqsave(&host->lock, flags);
2115 /* Check host->mrq first in case we are runtime suspended */
2116 if (host->mrq && !sdhci_do_get_cd(host)) {
2117 pr_err("%s: Card removed during transfer!\n",
2118 mmc_hostname(host->mmc));
2119 pr_err("%s: Resetting controller.\n",
2120 mmc_hostname(host->mmc));
2122 sdhci_do_reset(host, SDHCI_RESET_CMD);
2123 sdhci_do_reset(host, SDHCI_RESET_DATA);
2125 host->mrq->cmd->error = -ENOMEDIUM;
2126 tasklet_schedule(&host->finish_tasklet);
2129 spin_unlock_irqrestore(&host->lock, flags);
2132 static const struct mmc_host_ops sdhci_ops = {
2133 .request = sdhci_request,
2134 .set_ios = sdhci_set_ios,
2135 .get_cd = sdhci_get_cd,
2136 .get_ro = sdhci_get_ro,
2137 .hw_reset = sdhci_hw_reset,
2138 .enable_sdio_irq = sdhci_enable_sdio_irq,
2139 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2140 .execute_tuning = sdhci_execute_tuning,
2141 .card_event = sdhci_card_event,
2142 .card_busy = sdhci_card_busy,
2145 /*****************************************************************************\
2149 \*****************************************************************************/
2151 static void sdhci_tasklet_finish(unsigned long param)
2153 struct sdhci_host *host;
2154 unsigned long flags;
2155 struct mmc_request *mrq;
2157 host = (struct sdhci_host*)param;
2159 spin_lock_irqsave(&host->lock, flags);
2162 * If this tasklet gets rescheduled while running, it will
2163 * be run again afterwards but without any active request.
2166 spin_unlock_irqrestore(&host->lock, flags);
2170 del_timer(&host->timer);
2175 * The controller needs a reset of internal state machines
2176 * upon error conditions.
2178 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2179 ((mrq->cmd && mrq->cmd->error) ||
2180 (mrq->sbc && mrq->sbc->error) ||
2181 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2182 (mrq->data->stop && mrq->data->stop->error))) ||
2183 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2185 /* Some controllers need this kick or reset won't work here */
2186 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2187 /* This is to force an update */
2188 host->ops->set_clock(host, host->clock);
2190 /* Spec says we should do both at the same time, but Ricoh
2191 controllers do not like that. */
2192 sdhci_do_reset(host, SDHCI_RESET_CMD);
2193 sdhci_do_reset(host, SDHCI_RESET_DATA);
2200 #ifndef SDHCI_USE_LEDS_CLASS
2201 sdhci_deactivate_led(host);
2205 spin_unlock_irqrestore(&host->lock, flags);
2207 mmc_request_done(host->mmc, mrq);
2208 sdhci_runtime_pm_put(host);
2211 static void sdhci_timeout_timer(unsigned long data)
2213 struct sdhci_host *host;
2214 unsigned long flags;
2216 host = (struct sdhci_host*)data;
2218 spin_lock_irqsave(&host->lock, flags);
2221 pr_err("%s: Timeout waiting for hardware "
2222 "interrupt.\n", mmc_hostname(host->mmc));
2223 sdhci_dumpregs(host);
2226 host->data->error = -ETIMEDOUT;
2227 sdhci_finish_data(host);
2230 host->cmd->error = -ETIMEDOUT;
2232 host->mrq->cmd->error = -ETIMEDOUT;
2234 tasklet_schedule(&host->finish_tasklet);
2239 spin_unlock_irqrestore(&host->lock, flags);
2242 static void sdhci_tuning_timer(unsigned long data)
2244 struct sdhci_host *host;
2245 unsigned long flags;
2247 host = (struct sdhci_host *)data;
2249 spin_lock_irqsave(&host->lock, flags);
2251 host->flags |= SDHCI_NEEDS_RETUNING;
2253 spin_unlock_irqrestore(&host->lock, flags);
2256 /*****************************************************************************\
2258 * Interrupt handling *
2260 \*****************************************************************************/
2262 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2264 BUG_ON(intmask == 0);
2267 pr_err("%s: Got command interrupt 0x%08x even "
2268 "though no command operation was in progress.\n",
2269 mmc_hostname(host->mmc), (unsigned)intmask);
2270 sdhci_dumpregs(host);
2274 if (intmask & SDHCI_INT_TIMEOUT)
2275 host->cmd->error = -ETIMEDOUT;
2276 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2278 host->cmd->error = -EILSEQ;
2280 if (host->cmd->error) {
2281 tasklet_schedule(&host->finish_tasklet);
2286 * The host can send and interrupt when the busy state has
2287 * ended, allowing us to wait without wasting CPU cycles.
2288 * Unfortunately this is overloaded on the "data complete"
2289 * interrupt, so we need to take some care when handling
2292 * Note: The 1.0 specification is a bit ambiguous about this
2293 * feature so there might be some problems with older
2296 if (host->cmd->flags & MMC_RSP_BUSY) {
2297 if (host->cmd->data)
2298 DBG("Cannot wait for busy signal when also "
2299 "doing a data transfer");
2300 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2301 && !host->busy_handle) {
2302 /* Mark that command complete before busy is ended */
2303 host->busy_handle = 1;
2307 /* The controller does not support the end-of-busy IRQ,
2308 * fall through and take the SDHCI_INT_RESPONSE */
2309 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2310 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2311 *mask &= ~SDHCI_INT_DATA_END;
2314 if (intmask & SDHCI_INT_RESPONSE)
2315 sdhci_finish_command(host);
2318 #ifdef CONFIG_MMC_DEBUG
2319 static void sdhci_adma_show_error(struct sdhci_host *host)
2321 const char *name = mmc_hostname(host->mmc);
2322 void *desc = host->adma_table;
2324 sdhci_dumpregs(host);
2327 struct sdhci_adma2_64_desc *dma_desc = desc;
2329 if (host->flags & SDHCI_USE_64_BIT_DMA)
2330 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2331 name, desc, le32_to_cpu(dma_desc->addr_hi),
2332 le32_to_cpu(dma_desc->addr_lo),
2333 le16_to_cpu(dma_desc->len),
2334 le16_to_cpu(dma_desc->cmd));
2336 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2337 name, desc, le32_to_cpu(dma_desc->addr_lo),
2338 le16_to_cpu(dma_desc->len),
2339 le16_to_cpu(dma_desc->cmd));
2341 desc += host->desc_sz;
2343 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2348 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2351 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2354 BUG_ON(intmask == 0);
2356 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2357 if (intmask & SDHCI_INT_DATA_AVAIL) {
2358 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2359 if (command == MMC_SEND_TUNING_BLOCK ||
2360 command == MMC_SEND_TUNING_BLOCK_HS200) {
2361 host->tuning_done = 1;
2362 wake_up(&host->buf_ready_int);
2369 * The "data complete" interrupt is also used to
2370 * indicate that a busy state has ended. See comment
2371 * above in sdhci_cmd_irq().
2373 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2374 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2375 host->cmd->error = -ETIMEDOUT;
2376 tasklet_schedule(&host->finish_tasklet);
2379 if (intmask & SDHCI_INT_DATA_END) {
2381 * Some cards handle busy-end interrupt
2382 * before the command completed, so make
2383 * sure we do things in the proper order.
2385 if (host->busy_handle)
2386 sdhci_finish_command(host);
2388 host->busy_handle = 1;
2393 pr_err("%s: Got data interrupt 0x%08x even "
2394 "though no data operation was in progress.\n",
2395 mmc_hostname(host->mmc), (unsigned)intmask);
2396 sdhci_dumpregs(host);
2401 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2402 host->data->error = -ETIMEDOUT;
2403 else if (intmask & SDHCI_INT_DATA_END_BIT)
2404 host->data->error = -EILSEQ;
2405 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2406 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2408 host->data->error = -EILSEQ;
2409 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2410 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2411 sdhci_adma_show_error(host);
2412 host->data->error = -EIO;
2413 if (host->ops->adma_workaround)
2414 host->ops->adma_workaround(host, intmask);
2417 if (host->data->error)
2418 sdhci_finish_data(host);
2420 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2421 sdhci_transfer_pio(host);
2424 * We currently don't do anything fancy with DMA
2425 * boundaries, but as we can't disable the feature
2426 * we need to at least restart the transfer.
2428 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2429 * should return a valid address to continue from, but as
2430 * some controllers are faulty, don't trust them.
2432 if (intmask & SDHCI_INT_DMA_END) {
2433 u32 dmastart, dmanow;
2434 dmastart = sg_dma_address(host->data->sg);
2435 dmanow = dmastart + host->data->bytes_xfered;
2437 * Force update to the next DMA block boundary.
2440 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2441 SDHCI_DEFAULT_BOUNDARY_SIZE;
2442 host->data->bytes_xfered = dmanow - dmastart;
2443 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2445 mmc_hostname(host->mmc), dmastart,
2446 host->data->bytes_xfered, dmanow);
2447 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2450 if (intmask & SDHCI_INT_DATA_END) {
2453 * Data managed to finish before the
2454 * command completed. Make sure we do
2455 * things in the proper order.
2457 host->data_early = 1;
2459 sdhci_finish_data(host);
2465 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2467 irqreturn_t result = IRQ_NONE;
2468 struct sdhci_host *host = dev_id;
2469 u32 intmask, mask, unexpected = 0;
2472 spin_lock(&host->lock);
2474 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2475 spin_unlock(&host->lock);
2479 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2480 if (!intmask || intmask == 0xffffffff) {
2486 /* Clear selected interrupts. */
2487 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2488 SDHCI_INT_BUS_POWER);
2489 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2491 DBG("*** %s got interrupt: 0x%08x\n",
2492 mmc_hostname(host->mmc), intmask);
2494 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2495 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2499 * There is a observation on i.mx esdhc. INSERT
2500 * bit will be immediately set again when it gets
2501 * cleared, if a card is inserted. We have to mask
2502 * the irq to prevent interrupt storm which will
2503 * freeze the system. And the REMOVE gets the
2506 * More testing are needed here to ensure it works
2507 * for other platforms though.
2509 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2510 SDHCI_INT_CARD_REMOVE);
2511 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2512 SDHCI_INT_CARD_INSERT;
2513 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2514 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2516 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2517 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2519 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2520 SDHCI_INT_CARD_REMOVE);
2521 result = IRQ_WAKE_THREAD;
2524 if (intmask & SDHCI_INT_CMD_MASK)
2525 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2528 if (intmask & SDHCI_INT_DATA_MASK)
2529 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2531 if (intmask & SDHCI_INT_BUS_POWER)
2532 pr_err("%s: Card is consuming too much power!\n",
2533 mmc_hostname(host->mmc));
2535 if (intmask & SDHCI_INT_CARD_INT) {
2536 sdhci_enable_sdio_irq_nolock(host, false);
2537 host->thread_isr |= SDHCI_INT_CARD_INT;
2538 result = IRQ_WAKE_THREAD;
2541 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2542 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2543 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2544 SDHCI_INT_CARD_INT);
2547 unexpected |= intmask;
2548 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2551 if (result == IRQ_NONE)
2552 result = IRQ_HANDLED;
2554 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2555 } while (intmask && --max_loops);
2557 spin_unlock(&host->lock);
2560 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2561 mmc_hostname(host->mmc), unexpected);
2562 sdhci_dumpregs(host);
2568 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2570 struct sdhci_host *host = dev_id;
2571 unsigned long flags;
2574 spin_lock_irqsave(&host->lock, flags);
2575 isr = host->thread_isr;
2576 host->thread_isr = 0;
2577 spin_unlock_irqrestore(&host->lock, flags);
2579 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2580 sdhci_card_event(host->mmc);
2581 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2584 if (isr & SDHCI_INT_CARD_INT) {
2585 sdio_run_irqs(host->mmc);
2587 spin_lock_irqsave(&host->lock, flags);
2588 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2589 sdhci_enable_sdio_irq_nolock(host, true);
2590 spin_unlock_irqrestore(&host->lock, flags);
2593 return isr ? IRQ_HANDLED : IRQ_NONE;
2596 /*****************************************************************************\
2600 \*****************************************************************************/
2603 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2606 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2607 | SDHCI_WAKE_ON_INT;
2609 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2611 /* Avoid fake wake up */
2612 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2613 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2614 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2616 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2618 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2621 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2622 | SDHCI_WAKE_ON_INT;
2624 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2626 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2629 int sdhci_suspend_host(struct sdhci_host *host)
2631 sdhci_disable_card_detection(host);
2633 /* Disable tuning since we are suspending */
2634 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2635 del_timer_sync(&host->tuning_timer);
2636 host->flags &= ~SDHCI_NEEDS_RETUNING;
2639 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2641 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2642 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2643 free_irq(host->irq, host);
2645 sdhci_enable_irq_wakeups(host);
2646 enable_irq_wake(host->irq);
2651 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2653 int sdhci_resume_host(struct sdhci_host *host)
2657 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2658 if (host->ops->enable_dma)
2659 host->ops->enable_dma(host);
2662 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2663 ret = request_threaded_irq(host->irq, sdhci_irq,
2664 sdhci_thread_irq, IRQF_SHARED,
2665 mmc_hostname(host->mmc), host);
2669 sdhci_disable_irq_wakeups(host);
2670 disable_irq_wake(host->irq);
2673 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2674 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2675 /* Card keeps power but host controller does not */
2676 sdhci_init(host, 0);
2679 sdhci_do_set_ios(host, &host->mmc->ios);
2681 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2685 sdhci_enable_card_detection(host);
2687 /* Set the re-tuning expiration flag */
2688 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2689 host->flags |= SDHCI_NEEDS_RETUNING;
2694 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2696 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2698 return pm_runtime_get_sync(host->mmc->parent);
2701 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2703 pm_runtime_mark_last_busy(host->mmc->parent);
2704 return pm_runtime_put_autosuspend(host->mmc->parent);
2707 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2709 if (host->runtime_suspended || host->bus_on)
2711 host->bus_on = true;
2712 pm_runtime_get_noresume(host->mmc->parent);
2715 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2717 if (host->runtime_suspended || !host->bus_on)
2719 host->bus_on = false;
2720 pm_runtime_put_noidle(host->mmc->parent);
2723 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2725 unsigned long flags;
2727 /* Disable tuning since we are suspending */
2728 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2729 del_timer_sync(&host->tuning_timer);
2730 host->flags &= ~SDHCI_NEEDS_RETUNING;
2733 spin_lock_irqsave(&host->lock, flags);
2734 host->ier &= SDHCI_INT_CARD_INT;
2735 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2736 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2737 spin_unlock_irqrestore(&host->lock, flags);
2739 synchronize_hardirq(host->irq);
2741 spin_lock_irqsave(&host->lock, flags);
2742 host->runtime_suspended = true;
2743 spin_unlock_irqrestore(&host->lock, flags);
2747 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2749 int sdhci_runtime_resume_host(struct sdhci_host *host)
2751 unsigned long flags;
2752 int host_flags = host->flags;
2754 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2755 if (host->ops->enable_dma)
2756 host->ops->enable_dma(host);
2759 sdhci_init(host, 0);
2761 /* Force clock and power re-program */
2764 sdhci_do_set_ios(host, &host->mmc->ios);
2766 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2767 if ((host_flags & SDHCI_PV_ENABLED) &&
2768 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2769 spin_lock_irqsave(&host->lock, flags);
2770 sdhci_enable_preset_value(host, true);
2771 spin_unlock_irqrestore(&host->lock, flags);
2774 /* Set the re-tuning expiration flag */
2775 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2776 host->flags |= SDHCI_NEEDS_RETUNING;
2778 spin_lock_irqsave(&host->lock, flags);
2780 host->runtime_suspended = false;
2782 /* Enable SDIO IRQ */
2783 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2784 sdhci_enable_sdio_irq_nolock(host, true);
2786 /* Enable Card Detection */
2787 sdhci_enable_card_detection(host);
2789 spin_unlock_irqrestore(&host->lock, flags);
2793 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2795 #endif /* CONFIG_PM */
2797 /*****************************************************************************\
2799 * Device allocation/registration *
2801 \*****************************************************************************/
2803 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2806 struct mmc_host *mmc;
2807 struct sdhci_host *host;
2809 WARN_ON(dev == NULL);
2811 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2813 return ERR_PTR(-ENOMEM);
2815 host = mmc_priv(mmc);
2821 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2823 int sdhci_add_host(struct sdhci_host *host)
2825 struct mmc_host *mmc;
2826 u32 caps[2] = {0, 0};
2827 u32 max_current_caps;
2828 unsigned int ocr_avail;
2829 unsigned int override_timeout_clk;
2832 WARN_ON(host == NULL);
2839 host->quirks = debug_quirks;
2841 host->quirks2 = debug_quirks2;
2843 override_timeout_clk = host->timeout_clk;
2845 sdhci_do_reset(host, SDHCI_RESET_ALL);
2847 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2848 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2849 >> SDHCI_SPEC_VER_SHIFT;
2850 if (host->version > SDHCI_SPEC_300) {
2851 pr_err("%s: Unknown controller version (%d). "
2852 "You may experience problems.\n", mmc_hostname(mmc),
2856 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2857 sdhci_readl(host, SDHCI_CAPABILITIES);
2859 if (host->version >= SDHCI_SPEC_300)
2860 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2862 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2864 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2865 host->flags |= SDHCI_USE_SDMA;
2866 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2867 DBG("Controller doesn't have SDMA capability\n");
2869 host->flags |= SDHCI_USE_SDMA;
2871 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2872 (host->flags & SDHCI_USE_SDMA)) {
2873 DBG("Disabling DMA as it is marked broken\n");
2874 host->flags &= ~SDHCI_USE_SDMA;
2877 if ((host->version >= SDHCI_SPEC_200) &&
2878 (caps[0] & SDHCI_CAN_DO_ADMA2))
2879 host->flags |= SDHCI_USE_ADMA;
2881 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2882 (host->flags & SDHCI_USE_ADMA)) {
2883 DBG("Disabling ADMA as it is marked broken\n");
2884 host->flags &= ~SDHCI_USE_ADMA;
2888 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2889 * and *must* do 64-bit DMA. A driver has the opportunity to change
2890 * that during the first call to ->enable_dma(). Similarly
2891 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2894 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2895 host->flags |= SDHCI_USE_64_BIT_DMA;
2897 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2898 if (host->ops->enable_dma) {
2899 if (host->ops->enable_dma(host)) {
2900 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2903 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2908 /* SDMA does not support 64-bit DMA */
2909 if (host->flags & SDHCI_USE_64_BIT_DMA)
2910 host->flags &= ~SDHCI_USE_SDMA;
2912 if (host->flags & SDHCI_USE_ADMA) {
2914 * The DMA descriptor table size is calculated as the maximum
2915 * number of segments times 2, to allow for an alignment
2916 * descriptor for each segment, plus 1 for a nop end descriptor,
2917 * all multipled by the descriptor size.
2919 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2920 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2921 SDHCI_ADMA2_64_DESC_SZ;
2922 host->align_buffer_sz = SDHCI_MAX_SEGS *
2923 SDHCI_ADMA2_64_ALIGN;
2924 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2925 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2926 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2928 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2929 SDHCI_ADMA2_32_DESC_SZ;
2930 host->align_buffer_sz = SDHCI_MAX_SEGS *
2931 SDHCI_ADMA2_32_ALIGN;
2932 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2933 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2934 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2936 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2937 host->adma_table_sz,
2940 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2941 if (!host->adma_table || !host->align_buffer) {
2942 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2943 host->adma_table, host->adma_addr);
2944 kfree(host->align_buffer);
2945 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2947 host->flags &= ~SDHCI_USE_ADMA;
2948 host->adma_table = NULL;
2949 host->align_buffer = NULL;
2950 } else if (host->adma_addr & host->align_mask) {
2951 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2953 host->flags &= ~SDHCI_USE_ADMA;
2954 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2955 host->adma_table, host->adma_addr);
2956 kfree(host->align_buffer);
2957 host->adma_table = NULL;
2958 host->align_buffer = NULL;
2963 * If we use DMA, then it's up to the caller to set the DMA
2964 * mask, but PIO does not need the hw shim so we set a new
2965 * mask here in that case.
2967 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2968 host->dma_mask = DMA_BIT_MASK(64);
2969 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2972 if (host->version >= SDHCI_SPEC_300)
2973 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2974 >> SDHCI_CLOCK_BASE_SHIFT;
2976 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2977 >> SDHCI_CLOCK_BASE_SHIFT;
2979 host->max_clk *= 1000000;
2980 if (host->max_clk == 0 || host->quirks &
2981 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2982 if (!host->ops->get_max_clock) {
2983 pr_err("%s: Hardware doesn't specify base clock "
2984 "frequency.\n", mmc_hostname(mmc));
2987 host->max_clk = host->ops->get_max_clock(host);
2991 * In case of Host Controller v3.00, find out whether clock
2992 * multiplier is supported.
2994 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2995 SDHCI_CLOCK_MUL_SHIFT;
2998 * In case the value in Clock Multiplier is 0, then programmable
2999 * clock mode is not supported, otherwise the actual clock
3000 * multiplier is one more than the value of Clock Multiplier
3001 * in the Capabilities Register.
3007 * Set host parameters.
3009 mmc->ops = &sdhci_ops;
3010 mmc->f_max = host->max_clk;
3011 if (host->ops->get_min_clock)
3012 mmc->f_min = host->ops->get_min_clock(host);
3013 else if (host->version >= SDHCI_SPEC_300) {
3014 if (host->clk_mul) {
3015 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3016 mmc->f_max = host->max_clk * host->clk_mul;
3018 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3020 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3022 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3023 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3024 SDHCI_TIMEOUT_CLK_SHIFT;
3025 if (host->timeout_clk == 0) {
3026 if (host->ops->get_timeout_clock) {
3028 host->ops->get_timeout_clock(host);
3030 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3036 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3037 host->timeout_clk *= 1000;
3039 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3040 host->ops->get_max_timeout_count(host) : 1 << 27;
3041 mmc->max_busy_timeout /= host->timeout_clk;
3044 if (override_timeout_clk)
3045 host->timeout_clk = override_timeout_clk;
3047 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3048 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3050 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3051 host->flags |= SDHCI_AUTO_CMD12;
3053 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3054 if ((host->version >= SDHCI_SPEC_300) &&
3055 ((host->flags & SDHCI_USE_ADMA) ||
3056 !(host->flags & SDHCI_USE_SDMA))) {
3057 host->flags |= SDHCI_AUTO_CMD23;
3058 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3060 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3064 * A controller may support 8-bit width, but the board itself
3065 * might not have the pins brought out. Boards that support
3066 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3067 * their platform code before calling sdhci_add_host(), and we
3068 * won't assume 8-bit width for hosts without that CAP.
3070 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3071 mmc->caps |= MMC_CAP_4_BIT_DATA;
3073 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3074 mmc->caps &= ~MMC_CAP_CMD23;
3076 if (caps[0] & SDHCI_CAN_DO_HISPD)
3077 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3079 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3080 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3081 mmc->caps |= MMC_CAP_NEEDS_POLL;
3083 /* If there are external regulators, get them */
3084 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3085 return -EPROBE_DEFER;
3087 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3088 if (!IS_ERR(mmc->supply.vqmmc)) {
3089 ret = regulator_enable(mmc->supply.vqmmc);
3090 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3092 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3093 SDHCI_SUPPORT_SDR50 |
3094 SDHCI_SUPPORT_DDR50);
3096 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3097 mmc_hostname(mmc), ret);
3098 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3102 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3103 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3104 SDHCI_SUPPORT_DDR50);
3106 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3107 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3108 SDHCI_SUPPORT_DDR50))
3109 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3111 /* SDR104 supports also implies SDR50 support */
3112 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3113 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3114 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3115 * field can be promoted to support HS200.
3117 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3118 mmc->caps2 |= MMC_CAP2_HS200;
3119 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3120 mmc->caps |= MMC_CAP_UHS_SDR50;
3122 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3123 (caps[1] & SDHCI_SUPPORT_HS400))
3124 mmc->caps2 |= MMC_CAP2_HS400;
3126 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3127 (IS_ERR(mmc->supply.vqmmc) ||
3128 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3130 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3132 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3133 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3134 mmc->caps |= MMC_CAP_UHS_DDR50;
3136 /* Does the host need tuning for SDR50? */
3137 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3138 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3140 /* Does the host need tuning for SDR104 / HS200? */
3141 if (mmc->caps2 & MMC_CAP2_HS200)
3142 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3144 /* Driver Type(s) (A, C, D) supported by the host */
3145 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3146 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3147 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3148 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3149 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3150 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3152 /* Initial value for re-tuning timer count */
3153 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3154 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3157 * In case Re-tuning Timer is not disabled, the actual value of
3158 * re-tuning timer will be 2 ^ (n - 1).
3160 if (host->tuning_count)
3161 host->tuning_count = 1 << (host->tuning_count - 1);
3163 /* Re-tuning mode supported by the Host Controller */
3164 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3165 SDHCI_RETUNING_MODE_SHIFT;
3170 * According to SD Host Controller spec v3.00, if the Host System
3171 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3172 * the value is meaningful only if Voltage Support in the Capabilities
3173 * register is set. The actual current value is 4 times the register
3176 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3177 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3178 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3181 /* convert to SDHCI_MAX_CURRENT format */
3182 curr = curr/1000; /* convert to mA */
3183 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3185 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3187 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3188 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3189 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3193 if (caps[0] & SDHCI_CAN_VDD_330) {
3194 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3196 mmc->max_current_330 = ((max_current_caps &
3197 SDHCI_MAX_CURRENT_330_MASK) >>
3198 SDHCI_MAX_CURRENT_330_SHIFT) *
3199 SDHCI_MAX_CURRENT_MULTIPLIER;
3201 if (caps[0] & SDHCI_CAN_VDD_300) {
3202 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3204 mmc->max_current_300 = ((max_current_caps &
3205 SDHCI_MAX_CURRENT_300_MASK) >>
3206 SDHCI_MAX_CURRENT_300_SHIFT) *
3207 SDHCI_MAX_CURRENT_MULTIPLIER;
3209 if (caps[0] & SDHCI_CAN_VDD_180) {
3210 ocr_avail |= MMC_VDD_165_195;
3212 mmc->max_current_180 = ((max_current_caps &
3213 SDHCI_MAX_CURRENT_180_MASK) >>
3214 SDHCI_MAX_CURRENT_180_SHIFT) *
3215 SDHCI_MAX_CURRENT_MULTIPLIER;
3218 /* If OCR set by external regulators, use it instead */
3220 ocr_avail = mmc->ocr_avail;
3223 ocr_avail &= host->ocr_mask;
3225 mmc->ocr_avail = ocr_avail;
3226 mmc->ocr_avail_sdio = ocr_avail;
3227 if (host->ocr_avail_sdio)
3228 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3229 mmc->ocr_avail_sd = ocr_avail;
3230 if (host->ocr_avail_sd)
3231 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3232 else /* normal SD controllers don't support 1.8V */
3233 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3234 mmc->ocr_avail_mmc = ocr_avail;
3235 if (host->ocr_avail_mmc)
3236 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3238 if (mmc->ocr_avail == 0) {
3239 pr_err("%s: Hardware doesn't report any "
3240 "support voltages.\n", mmc_hostname(mmc));
3244 spin_lock_init(&host->lock);
3247 * Maximum number of segments. Depends on if the hardware
3248 * can do scatter/gather or not.
3250 if (host->flags & SDHCI_USE_ADMA)
3251 mmc->max_segs = SDHCI_MAX_SEGS;
3252 else if (host->flags & SDHCI_USE_SDMA)
3255 mmc->max_segs = SDHCI_MAX_SEGS;
3258 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3259 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3262 mmc->max_req_size = 524288;
3265 * Maximum segment size. Could be one segment with the maximum number
3266 * of bytes. When doing hardware scatter/gather, each entry cannot
3267 * be larger than 64 KiB though.
3269 if (host->flags & SDHCI_USE_ADMA) {
3270 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3271 mmc->max_seg_size = 65535;
3273 mmc->max_seg_size = 65536;
3275 mmc->max_seg_size = mmc->max_req_size;
3279 * Maximum block size. This varies from controller to controller and
3280 * is specified in the capabilities register.
3282 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3283 mmc->max_blk_size = 2;
3285 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3286 SDHCI_MAX_BLOCK_SHIFT;
3287 if (mmc->max_blk_size >= 3) {
3288 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3290 mmc->max_blk_size = 0;
3294 mmc->max_blk_size = 512 << mmc->max_blk_size;
3297 * Maximum block count.
3299 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3304 tasklet_init(&host->finish_tasklet,
3305 sdhci_tasklet_finish, (unsigned long)host);
3307 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3309 if (host->version >= SDHCI_SPEC_300) {
3310 init_waitqueue_head(&host->buf_ready_int);
3312 /* Initialize re-tuning timer */
3313 init_timer(&host->tuning_timer);
3314 host->tuning_timer.data = (unsigned long)host;
3315 host->tuning_timer.function = sdhci_tuning_timer;
3318 sdhci_init(host, 0);
3320 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3321 IRQF_SHARED, mmc_hostname(mmc), host);
3323 pr_err("%s: Failed to request IRQ %d: %d\n",
3324 mmc_hostname(mmc), host->irq, ret);
3328 #ifdef CONFIG_MMC_DEBUG
3329 sdhci_dumpregs(host);
3332 #ifdef SDHCI_USE_LEDS_CLASS
3333 snprintf(host->led_name, sizeof(host->led_name),
3334 "%s::", mmc_hostname(mmc));
3335 host->led.name = host->led_name;
3336 host->led.brightness = LED_OFF;
3337 host->led.default_trigger = mmc_hostname(mmc);
3338 host->led.brightness_set = sdhci_led_control;
3340 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3342 pr_err("%s: Failed to register LED device: %d\n",
3343 mmc_hostname(mmc), ret);
3352 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3353 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3354 (host->flags & SDHCI_USE_ADMA) ?
3355 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3356 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3358 sdhci_enable_card_detection(host);
3362 #ifdef SDHCI_USE_LEDS_CLASS
3364 sdhci_do_reset(host, SDHCI_RESET_ALL);
3365 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3366 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3367 free_irq(host->irq, host);
3370 tasklet_kill(&host->finish_tasklet);
3375 EXPORT_SYMBOL_GPL(sdhci_add_host);
3377 void sdhci_remove_host(struct sdhci_host *host, int dead)
3379 struct mmc_host *mmc = host->mmc;
3380 unsigned long flags;
3383 spin_lock_irqsave(&host->lock, flags);
3385 host->flags |= SDHCI_DEVICE_DEAD;
3388 pr_err("%s: Controller removed during "
3389 " transfer!\n", mmc_hostname(mmc));
3391 host->mrq->cmd->error = -ENOMEDIUM;
3392 tasklet_schedule(&host->finish_tasklet);
3395 spin_unlock_irqrestore(&host->lock, flags);
3398 sdhci_disable_card_detection(host);
3400 mmc_remove_host(mmc);
3402 #ifdef SDHCI_USE_LEDS_CLASS
3403 led_classdev_unregister(&host->led);
3407 sdhci_do_reset(host, SDHCI_RESET_ALL);
3409 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3410 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3411 free_irq(host->irq, host);
3413 del_timer_sync(&host->timer);
3415 tasklet_kill(&host->finish_tasklet);
3417 if (!IS_ERR(mmc->supply.vqmmc))
3418 regulator_disable(mmc->supply.vqmmc);
3420 if (host->adma_table)
3421 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3422 host->adma_table, host->adma_addr);
3423 kfree(host->align_buffer);
3425 host->adma_table = NULL;
3426 host->align_buffer = NULL;
3429 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3431 void sdhci_free_host(struct sdhci_host *host)
3433 mmc_free_host(host->mmc);
3436 EXPORT_SYMBOL_GPL(sdhci_free_host);
3438 /*****************************************************************************\
3440 * Driver init/exit *
3442 \*****************************************************************************/
3444 static int __init sdhci_drv_init(void)
3447 ": Secure Digital Host Controller Interface driver\n");
3448 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3453 static void __exit sdhci_drv_exit(void)
3457 module_init(sdhci_drv_init);
3458 module_exit(sdhci_drv_exit);
3460 module_param(debug_quirks, uint, 0444);
3461 module_param(debug_quirks2, uint, 0444);
3463 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3464 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3465 MODULE_LICENSE("GPL");
3467 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3468 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");