2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
23 #include <linux/leds.h>
25 #include <linux/mmc/host.h>
29 #define DRIVER_NAME "sdhci"
31 #define DBG(f, x...) \
32 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
34 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
35 defined(CONFIG_MMC_SDHCI_MODULE))
36 #define SDHCI_USE_LEDS_CLASS
39 static unsigned int debug_quirks = 0;
41 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
42 static void sdhci_finish_data(struct sdhci_host *);
44 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
45 static void sdhci_finish_command(struct sdhci_host *);
47 static void sdhci_dumpregs(struct sdhci_host *host)
49 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
51 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
52 sdhci_readl(host, SDHCI_DMA_ADDRESS),
53 sdhci_readw(host, SDHCI_HOST_VERSION));
54 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
55 sdhci_readw(host, SDHCI_BLOCK_SIZE),
56 sdhci_readw(host, SDHCI_BLOCK_COUNT));
57 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
58 sdhci_readl(host, SDHCI_ARGUMENT),
59 sdhci_readw(host, SDHCI_TRANSFER_MODE));
60 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
61 sdhci_readl(host, SDHCI_PRESENT_STATE),
62 sdhci_readb(host, SDHCI_HOST_CONTROL));
63 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
64 sdhci_readb(host, SDHCI_POWER_CONTROL),
65 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
66 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
67 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
68 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
69 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
70 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
71 sdhci_readl(host, SDHCI_INT_STATUS));
72 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
73 sdhci_readl(host, SDHCI_INT_ENABLE),
74 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
75 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
76 sdhci_readw(host, SDHCI_ACMD12_ERR),
77 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
78 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
79 sdhci_readl(host, SDHCI_CAPABILITIES),
80 sdhci_readl(host, SDHCI_MAX_CURRENT));
82 if (host->flags & SDHCI_USE_ADMA)
83 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
84 readl(host->ioaddr + SDHCI_ADMA_ERROR),
85 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
87 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
90 /*****************************************************************************\
92 * Low level functions *
94 \*****************************************************************************/
96 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
100 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
103 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
104 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
107 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
109 sdhci_clear_set_irqs(host, 0, irqs);
112 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
114 sdhci_clear_set_irqs(host, irqs, 0);
117 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
119 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
121 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
125 sdhci_unmask_irqs(host, irqs);
127 sdhci_mask_irqs(host, irqs);
130 static void sdhci_enable_card_detection(struct sdhci_host *host)
132 sdhci_set_card_detection(host, true);
135 static void sdhci_disable_card_detection(struct sdhci_host *host)
137 sdhci_set_card_detection(host, false);
140 static void sdhci_reset(struct sdhci_host *host, u8 mask)
142 unsigned long timeout;
143 u32 uninitialized_var(ier);
145 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
146 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
151 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
152 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
154 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
156 if (mask & SDHCI_RESET_ALL)
159 /* Wait max 100 ms */
162 /* hw clears the bit when it's done */
163 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
165 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
166 mmc_hostname(host->mmc), (int)mask);
167 sdhci_dumpregs(host);
174 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
175 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
178 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
180 static void sdhci_init(struct sdhci_host *host, int soft)
183 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
185 sdhci_reset(host, SDHCI_RESET_ALL);
187 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
188 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
189 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
190 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
191 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
194 /* force clock reconfiguration */
196 sdhci_set_ios(host->mmc, &host->mmc->ios);
200 static void sdhci_reinit(struct sdhci_host *host)
203 sdhci_enable_card_detection(host);
206 static void sdhci_activate_led(struct sdhci_host *host)
210 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
211 ctrl |= SDHCI_CTRL_LED;
212 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
215 static void sdhci_deactivate_led(struct sdhci_host *host)
219 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
220 ctrl &= ~SDHCI_CTRL_LED;
221 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
224 #ifdef SDHCI_USE_LEDS_CLASS
225 static void sdhci_led_control(struct led_classdev *led,
226 enum led_brightness brightness)
228 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
231 spin_lock_irqsave(&host->lock, flags);
233 if (brightness == LED_OFF)
234 sdhci_deactivate_led(host);
236 sdhci_activate_led(host);
238 spin_unlock_irqrestore(&host->lock, flags);
242 /*****************************************************************************\
246 \*****************************************************************************/
248 static void sdhci_read_block_pio(struct sdhci_host *host)
251 size_t blksize, len, chunk;
252 u32 uninitialized_var(scratch);
255 DBG("PIO reading\n");
257 blksize = host->data->blksz;
260 local_irq_save(flags);
263 if (!sg_miter_next(&host->sg_miter))
266 len = min(host->sg_miter.length, blksize);
269 host->sg_miter.consumed = len;
271 buf = host->sg_miter.addr;
275 scratch = sdhci_readl(host, SDHCI_BUFFER);
279 *buf = scratch & 0xFF;
288 sg_miter_stop(&host->sg_miter);
290 local_irq_restore(flags);
293 static void sdhci_write_block_pio(struct sdhci_host *host)
296 size_t blksize, len, chunk;
300 DBG("PIO writing\n");
302 blksize = host->data->blksz;
306 local_irq_save(flags);
309 if (!sg_miter_next(&host->sg_miter))
312 len = min(host->sg_miter.length, blksize);
315 host->sg_miter.consumed = len;
317 buf = host->sg_miter.addr;
320 scratch |= (u32)*buf << (chunk * 8);
326 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
327 sdhci_writel(host, scratch, SDHCI_BUFFER);
334 sg_miter_stop(&host->sg_miter);
336 local_irq_restore(flags);
339 static void sdhci_transfer_pio(struct sdhci_host *host)
345 if (host->blocks == 0)
348 if (host->data->flags & MMC_DATA_READ)
349 mask = SDHCI_DATA_AVAILABLE;
351 mask = SDHCI_SPACE_AVAILABLE;
354 * Some controllers (JMicron JMB38x) mess up the buffer bits
355 * for transfers < 4 bytes. As long as it is just one block,
356 * we can ignore the bits.
358 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
359 (host->data->blocks == 1))
362 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
363 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
366 if (host->data->flags & MMC_DATA_READ)
367 sdhci_read_block_pio(host);
369 sdhci_write_block_pio(host);
372 if (host->blocks == 0)
376 DBG("PIO transfer complete.\n");
379 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
381 local_irq_save(*flags);
382 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
385 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
387 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
388 local_irq_restore(*flags);
391 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
393 __le32 *dataddr = (__le32 __force *)(desc + 4);
394 __le16 *cmdlen = (__le16 __force *)desc;
396 /* SDHCI specification says ADMA descriptors should be 4 byte
397 * aligned, so using 16 or 32bit operations should be safe. */
399 cmdlen[0] = cpu_to_le16(cmd);
400 cmdlen[1] = cpu_to_le16(len);
402 dataddr[0] = cpu_to_le32(addr);
405 static int sdhci_adma_table_pre(struct sdhci_host *host,
406 struct mmc_data *data)
413 dma_addr_t align_addr;
416 struct scatterlist *sg;
422 * The spec does not specify endianness of descriptor table.
423 * We currently guess that it is LE.
426 if (data->flags & MMC_DATA_READ)
427 direction = DMA_FROM_DEVICE;
429 direction = DMA_TO_DEVICE;
432 * The ADMA descriptor table is mapped further down as we
433 * need to fill it with data first.
436 host->align_addr = dma_map_single(mmc_dev(host->mmc),
437 host->align_buffer, 128 * 4, direction);
438 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
440 BUG_ON(host->align_addr & 0x3);
442 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
443 data->sg, data->sg_len, direction);
444 if (host->sg_count == 0)
447 desc = host->adma_desc;
448 align = host->align_buffer;
450 align_addr = host->align_addr;
452 for_each_sg(data->sg, sg, host->sg_count, i) {
453 addr = sg_dma_address(sg);
454 len = sg_dma_len(sg);
457 * The SDHCI specification states that ADMA
458 * addresses must be 32-bit aligned. If they
459 * aren't, then we use a bounce buffer for
460 * the (up to three) bytes that screw up the
463 offset = (4 - (addr & 0x3)) & 0x3;
465 if (data->flags & MMC_DATA_WRITE) {
466 buffer = sdhci_kmap_atomic(sg, &flags);
467 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
468 memcpy(align, buffer, offset);
469 sdhci_kunmap_atomic(buffer, &flags);
473 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
475 BUG_ON(offset > 65536);
489 sdhci_set_adma_desc(desc, addr, len, 0x21);
493 * If this triggers then we have a calculation bug
496 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
499 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
501 * Mark the last descriptor as the terminating descriptor
503 if (desc != host->adma_desc) {
505 desc[0] |= 0x2; /* end */
509 * Add a terminating entry.
512 /* nop, end, valid */
513 sdhci_set_adma_desc(desc, 0, 0, 0x3);
517 * Resync align buffer as we might have changed it.
519 if (data->flags & MMC_DATA_WRITE) {
520 dma_sync_single_for_device(mmc_dev(host->mmc),
521 host->align_addr, 128 * 4, direction);
524 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
525 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
526 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
528 BUG_ON(host->adma_addr & 0x3);
533 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
534 data->sg_len, direction);
536 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
542 static void sdhci_adma_table_post(struct sdhci_host *host,
543 struct mmc_data *data)
547 struct scatterlist *sg;
553 if (data->flags & MMC_DATA_READ)
554 direction = DMA_FROM_DEVICE;
556 direction = DMA_TO_DEVICE;
558 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
559 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
561 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
564 if (data->flags & MMC_DATA_READ) {
565 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
566 data->sg_len, direction);
568 align = host->align_buffer;
570 for_each_sg(data->sg, sg, host->sg_count, i) {
571 if (sg_dma_address(sg) & 0x3) {
572 size = 4 - (sg_dma_address(sg) & 0x3);
574 buffer = sdhci_kmap_atomic(sg, &flags);
575 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
576 memcpy(buffer, align, size);
577 sdhci_kunmap_atomic(buffer, &flags);
584 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
585 data->sg_len, direction);
588 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
591 unsigned target_timeout, current_timeout;
594 * If the host controller provides us with an incorrect timeout
595 * value, just skip the check and use 0xE. The hardware may take
596 * longer to time out, but that's much better than having a too-short
599 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
603 target_timeout = data->timeout_ns / 1000 +
604 data->timeout_clks / host->clock;
606 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
607 host->timeout_clk = host->clock / 1000;
610 * Figure out needed cycles.
611 * We do this in steps in order to fit inside a 32 bit int.
612 * The first step is the minimum timeout, which will have a
613 * minimum resolution of 6 bits:
614 * (1) 2^13*1000 > 2^22,
615 * (2) host->timeout_clk < 2^16
620 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
621 while (current_timeout < target_timeout) {
623 current_timeout <<= 1;
629 printk(KERN_WARNING "%s: Too large timeout requested!\n",
630 mmc_hostname(host->mmc));
637 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
639 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
640 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
642 if (host->flags & SDHCI_REQ_USE_DMA)
643 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
645 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
648 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
660 BUG_ON(data->blksz * data->blocks > 524288);
661 BUG_ON(data->blksz > host->mmc->max_blk_size);
662 BUG_ON(data->blocks > 65535);
665 host->data_early = 0;
667 count = sdhci_calc_timeout(host, data);
668 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
670 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
671 host->flags |= SDHCI_REQ_USE_DMA;
674 * FIXME: This doesn't account for merging when mapping the
677 if (host->flags & SDHCI_REQ_USE_DMA) {
679 struct scatterlist *sg;
682 if (host->flags & SDHCI_USE_ADMA) {
683 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
686 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
690 if (unlikely(broken)) {
691 for_each_sg(data->sg, sg, data->sg_len, i) {
692 if (sg->length & 0x3) {
693 DBG("Reverting to PIO because of "
694 "transfer size (%d)\n",
696 host->flags &= ~SDHCI_REQ_USE_DMA;
704 * The assumption here being that alignment is the same after
705 * translation to device address space.
707 if (host->flags & SDHCI_REQ_USE_DMA) {
709 struct scatterlist *sg;
712 if (host->flags & SDHCI_USE_ADMA) {
714 * As we use 3 byte chunks to work around
715 * alignment problems, we need to check this
718 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
721 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
725 if (unlikely(broken)) {
726 for_each_sg(data->sg, sg, data->sg_len, i) {
727 if (sg->offset & 0x3) {
728 DBG("Reverting to PIO because of "
730 host->flags &= ~SDHCI_REQ_USE_DMA;
737 if (host->flags & SDHCI_REQ_USE_DMA) {
738 if (host->flags & SDHCI_USE_ADMA) {
739 ret = sdhci_adma_table_pre(host, data);
742 * This only happens when someone fed
743 * us an invalid request.
746 host->flags &= ~SDHCI_REQ_USE_DMA;
748 sdhci_writel(host, host->adma_addr,
754 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
755 data->sg, data->sg_len,
756 (data->flags & MMC_DATA_READ) ?
761 * This only happens when someone fed
762 * us an invalid request.
765 host->flags &= ~SDHCI_REQ_USE_DMA;
767 WARN_ON(sg_cnt != 1);
768 sdhci_writel(host, sg_dma_address(data->sg),
775 * Always adjust the DMA selection as some controllers
776 * (e.g. JMicron) can't do PIO properly when the selection
779 if (host->version >= SDHCI_SPEC_200) {
780 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
781 ctrl &= ~SDHCI_CTRL_DMA_MASK;
782 if ((host->flags & SDHCI_REQ_USE_DMA) &&
783 (host->flags & SDHCI_USE_ADMA))
784 ctrl |= SDHCI_CTRL_ADMA32;
786 ctrl |= SDHCI_CTRL_SDMA;
787 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
790 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
793 flags = SG_MITER_ATOMIC;
794 if (host->data->flags & MMC_DATA_READ)
795 flags |= SG_MITER_TO_SG;
797 flags |= SG_MITER_FROM_SG;
798 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
799 host->blocks = data->blocks;
802 sdhci_set_transfer_irqs(host);
804 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
805 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
806 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
809 static void sdhci_set_transfer_mode(struct sdhci_host *host,
810 struct mmc_data *data)
817 WARN_ON(!host->data);
819 mode = SDHCI_TRNS_BLK_CNT_EN;
820 if (data->blocks > 1)
821 mode |= SDHCI_TRNS_MULTI;
822 if (data->flags & MMC_DATA_READ)
823 mode |= SDHCI_TRNS_READ;
824 if (host->flags & SDHCI_REQ_USE_DMA)
825 mode |= SDHCI_TRNS_DMA;
827 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
830 static void sdhci_finish_data(struct sdhci_host *host)
832 struct mmc_data *data;
839 if (host->flags & SDHCI_REQ_USE_DMA) {
840 if (host->flags & SDHCI_USE_ADMA)
841 sdhci_adma_table_post(host, data);
843 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
844 data->sg_len, (data->flags & MMC_DATA_READ) ?
845 DMA_FROM_DEVICE : DMA_TO_DEVICE);
850 * The specification states that the block count register must
851 * be updated, but it does not specify at what point in the
852 * data flow. That makes the register entirely useless to read
853 * back so we have to assume that nothing made it to the card
854 * in the event of an error.
857 data->bytes_xfered = 0;
859 data->bytes_xfered = data->blksz * data->blocks;
863 * The controller needs a reset of internal state machines
864 * upon error conditions.
867 sdhci_reset(host, SDHCI_RESET_CMD);
868 sdhci_reset(host, SDHCI_RESET_DATA);
871 sdhci_send_command(host, data->stop);
873 tasklet_schedule(&host->finish_tasklet);
876 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
880 unsigned long timeout;
887 mask = SDHCI_CMD_INHIBIT;
888 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
889 mask |= SDHCI_DATA_INHIBIT;
891 /* We shouldn't wait for data inihibit for stop commands, even
892 though they might use busy signaling */
893 if (host->mrq->data && (cmd == host->mrq->data->stop))
894 mask &= ~SDHCI_DATA_INHIBIT;
896 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
898 printk(KERN_ERR "%s: Controller never released "
899 "inhibit bit(s).\n", mmc_hostname(host->mmc));
900 sdhci_dumpregs(host);
902 tasklet_schedule(&host->finish_tasklet);
909 mod_timer(&host->timer, jiffies + 10 * HZ);
913 sdhci_prepare_data(host, cmd->data);
915 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
917 sdhci_set_transfer_mode(host, cmd->data);
919 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
920 printk(KERN_ERR "%s: Unsupported response type!\n",
921 mmc_hostname(host->mmc));
922 cmd->error = -EINVAL;
923 tasklet_schedule(&host->finish_tasklet);
927 if (!(cmd->flags & MMC_RSP_PRESENT))
928 flags = SDHCI_CMD_RESP_NONE;
929 else if (cmd->flags & MMC_RSP_136)
930 flags = SDHCI_CMD_RESP_LONG;
931 else if (cmd->flags & MMC_RSP_BUSY)
932 flags = SDHCI_CMD_RESP_SHORT_BUSY;
934 flags = SDHCI_CMD_RESP_SHORT;
936 if (cmd->flags & MMC_RSP_CRC)
937 flags |= SDHCI_CMD_CRC;
938 if (cmd->flags & MMC_RSP_OPCODE)
939 flags |= SDHCI_CMD_INDEX;
941 flags |= SDHCI_CMD_DATA;
943 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
946 static void sdhci_finish_command(struct sdhci_host *host)
950 BUG_ON(host->cmd == NULL);
952 if (host->cmd->flags & MMC_RSP_PRESENT) {
953 if (host->cmd->flags & MMC_RSP_136) {
954 /* CRC is stripped so we need to do some shifting. */
955 for (i = 0;i < 4;i++) {
956 host->cmd->resp[i] = sdhci_readl(host,
957 SDHCI_RESPONSE + (3-i)*4) << 8;
959 host->cmd->resp[i] |=
961 SDHCI_RESPONSE + (3-i)*4-1);
964 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
968 host->cmd->error = 0;
970 if (host->data && host->data_early)
971 sdhci_finish_data(host);
973 if (!host->cmd->data)
974 tasklet_schedule(&host->finish_tasklet);
979 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
983 unsigned long timeout;
985 if (clock == host->clock)
988 if (host->ops->set_clock) {
989 host->ops->set_clock(host, clock);
990 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
994 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
999 for (div = 1;div < 256;div *= 2) {
1000 if ((host->max_clk / div) <= clock)
1005 clk = div << SDHCI_DIVIDER_SHIFT;
1006 clk |= SDHCI_CLOCK_INT_EN;
1007 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1009 /* Wait max 20 ms */
1011 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1012 & SDHCI_CLOCK_INT_STABLE)) {
1014 printk(KERN_ERR "%s: Internal clock never "
1015 "stabilised.\n", mmc_hostname(host->mmc));
1016 sdhci_dumpregs(host);
1023 clk |= SDHCI_CLOCK_CARD_EN;
1024 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1027 host->clock = clock;
1030 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1034 if (power == (unsigned short)-1)
1037 switch (1 << power) {
1038 case MMC_VDD_165_195:
1039 pwr = SDHCI_POWER_180;
1043 pwr = SDHCI_POWER_300;
1047 pwr = SDHCI_POWER_330;
1054 if (host->pwr == pwr)
1060 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1065 * Spec says that we should clear the power reg before setting
1066 * a new value. Some controllers don't seem to like this though.
1068 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1069 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1072 * At least the Marvell CaFe chip gets confused if we set the voltage
1073 * and set turn on power at the same time, so set the voltage first.
1075 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1076 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1078 pwr |= SDHCI_POWER_ON;
1080 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1083 * Some controllers need an extra 10ms delay of 10ms before they
1084 * can apply clock after applying power
1086 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1090 /*****************************************************************************\
1094 \*****************************************************************************/
1096 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1098 struct sdhci_host *host;
1100 unsigned long flags;
1102 host = mmc_priv(mmc);
1104 spin_lock_irqsave(&host->lock, flags);
1106 WARN_ON(host->mrq != NULL);
1108 #ifndef SDHCI_USE_LEDS_CLASS
1109 sdhci_activate_led(host);
1114 /* If polling, assume that the card is always present. */
1115 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1118 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1121 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1122 host->mrq->cmd->error = -ENOMEDIUM;
1123 tasklet_schedule(&host->finish_tasklet);
1125 sdhci_send_command(host, mrq->cmd);
1128 spin_unlock_irqrestore(&host->lock, flags);
1131 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1133 struct sdhci_host *host;
1134 unsigned long flags;
1137 host = mmc_priv(mmc);
1139 spin_lock_irqsave(&host->lock, flags);
1141 if (host->flags & SDHCI_DEVICE_DEAD)
1145 * Reset the chip on each power off.
1146 * Should clear out any weird states.
1148 if (ios->power_mode == MMC_POWER_OFF) {
1149 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1153 sdhci_set_clock(host, ios->clock);
1155 if (ios->power_mode == MMC_POWER_OFF)
1156 sdhci_set_power(host, -1);
1158 sdhci_set_power(host, ios->vdd);
1160 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1162 if (ios->bus_width == MMC_BUS_WIDTH_8)
1163 ctrl |= SDHCI_CTRL_8BITBUS;
1165 ctrl &= ~SDHCI_CTRL_8BITBUS;
1167 if (ios->bus_width == MMC_BUS_WIDTH_4)
1168 ctrl |= SDHCI_CTRL_4BITBUS;
1170 ctrl &= ~SDHCI_CTRL_4BITBUS;
1172 if (ios->timing == MMC_TIMING_SD_HS)
1173 ctrl |= SDHCI_CTRL_HISPD;
1175 ctrl &= ~SDHCI_CTRL_HISPD;
1177 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1180 * Some (ENE) controllers go apeshit on some ios operation,
1181 * signalling timeout and CRC errors even on CMD0. Resetting
1182 * it on each ios seems to solve the problem.
1184 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1185 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1189 spin_unlock_irqrestore(&host->lock, flags);
1192 static int sdhci_get_ro(struct mmc_host *mmc)
1194 struct sdhci_host *host;
1195 unsigned long flags;
1198 host = mmc_priv(mmc);
1200 spin_lock_irqsave(&host->lock, flags);
1202 if (host->flags & SDHCI_DEVICE_DEAD)
1205 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1207 spin_unlock_irqrestore(&host->lock, flags);
1209 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1210 return !!(present & SDHCI_WRITE_PROTECT);
1211 return !(present & SDHCI_WRITE_PROTECT);
1214 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1216 struct sdhci_host *host;
1217 unsigned long flags;
1219 host = mmc_priv(mmc);
1221 spin_lock_irqsave(&host->lock, flags);
1223 if (host->flags & SDHCI_DEVICE_DEAD)
1227 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1229 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1233 spin_unlock_irqrestore(&host->lock, flags);
1236 static const struct mmc_host_ops sdhci_ops = {
1237 .request = sdhci_request,
1238 .set_ios = sdhci_set_ios,
1239 .get_ro = sdhci_get_ro,
1240 .enable_sdio_irq = sdhci_enable_sdio_irq,
1243 /*****************************************************************************\
1247 \*****************************************************************************/
1249 static void sdhci_tasklet_card(unsigned long param)
1251 struct sdhci_host *host;
1252 unsigned long flags;
1254 host = (struct sdhci_host*)param;
1256 spin_lock_irqsave(&host->lock, flags);
1258 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1260 printk(KERN_ERR "%s: Card removed during transfer!\n",
1261 mmc_hostname(host->mmc));
1262 printk(KERN_ERR "%s: Resetting controller.\n",
1263 mmc_hostname(host->mmc));
1265 sdhci_reset(host, SDHCI_RESET_CMD);
1266 sdhci_reset(host, SDHCI_RESET_DATA);
1268 host->mrq->cmd->error = -ENOMEDIUM;
1269 tasklet_schedule(&host->finish_tasklet);
1273 spin_unlock_irqrestore(&host->lock, flags);
1275 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1278 static void sdhci_tasklet_finish(unsigned long param)
1280 struct sdhci_host *host;
1281 unsigned long flags;
1282 struct mmc_request *mrq;
1284 host = (struct sdhci_host*)param;
1286 spin_lock_irqsave(&host->lock, flags);
1288 del_timer(&host->timer);
1293 * The controller needs a reset of internal state machines
1294 * upon error conditions.
1296 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1298 (mrq->data && (mrq->data->error ||
1299 (mrq->data->stop && mrq->data->stop->error))) ||
1300 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1302 /* Some controllers need this kick or reset won't work here */
1303 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1306 /* This is to force an update */
1307 clock = host->clock;
1309 sdhci_set_clock(host, clock);
1312 /* Spec says we should do both at the same time, but Ricoh
1313 controllers do not like that. */
1314 sdhci_reset(host, SDHCI_RESET_CMD);
1315 sdhci_reset(host, SDHCI_RESET_DATA);
1322 #ifndef SDHCI_USE_LEDS_CLASS
1323 sdhci_deactivate_led(host);
1327 spin_unlock_irqrestore(&host->lock, flags);
1329 mmc_request_done(host->mmc, mrq);
1332 static void sdhci_timeout_timer(unsigned long data)
1334 struct sdhci_host *host;
1335 unsigned long flags;
1337 host = (struct sdhci_host*)data;
1339 spin_lock_irqsave(&host->lock, flags);
1342 printk(KERN_ERR "%s: Timeout waiting for hardware "
1343 "interrupt.\n", mmc_hostname(host->mmc));
1344 sdhci_dumpregs(host);
1347 host->data->error = -ETIMEDOUT;
1348 sdhci_finish_data(host);
1351 host->cmd->error = -ETIMEDOUT;
1353 host->mrq->cmd->error = -ETIMEDOUT;
1355 tasklet_schedule(&host->finish_tasklet);
1360 spin_unlock_irqrestore(&host->lock, flags);
1363 /*****************************************************************************\
1365 * Interrupt handling *
1367 \*****************************************************************************/
1369 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1371 BUG_ON(intmask == 0);
1374 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1375 "though no command operation was in progress.\n",
1376 mmc_hostname(host->mmc), (unsigned)intmask);
1377 sdhci_dumpregs(host);
1381 if (intmask & SDHCI_INT_TIMEOUT)
1382 host->cmd->error = -ETIMEDOUT;
1383 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1385 host->cmd->error = -EILSEQ;
1387 if (host->cmd->error) {
1388 tasklet_schedule(&host->finish_tasklet);
1393 * The host can send and interrupt when the busy state has
1394 * ended, allowing us to wait without wasting CPU cycles.
1395 * Unfortunately this is overloaded on the "data complete"
1396 * interrupt, so we need to take some care when handling
1399 * Note: The 1.0 specification is a bit ambiguous about this
1400 * feature so there might be some problems with older
1403 if (host->cmd->flags & MMC_RSP_BUSY) {
1404 if (host->cmd->data)
1405 DBG("Cannot wait for busy signal when also "
1406 "doing a data transfer");
1407 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1410 /* The controller does not support the end-of-busy IRQ,
1411 * fall through and take the SDHCI_INT_RESPONSE */
1414 if (intmask & SDHCI_INT_RESPONSE)
1415 sdhci_finish_command(host);
1419 static void sdhci_show_adma_error(struct sdhci_host *host)
1421 const char *name = mmc_hostname(host->mmc);
1422 u8 *desc = host->adma_desc;
1427 sdhci_dumpregs(host);
1430 dma = (__le32 *)(desc + 4);
1431 len = (__le16 *)(desc + 2);
1434 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1435 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1444 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1447 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1449 BUG_ON(intmask == 0);
1453 * The "data complete" interrupt is also used to
1454 * indicate that a busy state has ended. See comment
1455 * above in sdhci_cmd_irq().
1457 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1458 if (intmask & SDHCI_INT_DATA_END) {
1459 sdhci_finish_command(host);
1464 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1465 "though no data operation was in progress.\n",
1466 mmc_hostname(host->mmc), (unsigned)intmask);
1467 sdhci_dumpregs(host);
1472 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1473 host->data->error = -ETIMEDOUT;
1474 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1475 host->data->error = -EILSEQ;
1476 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1477 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1478 sdhci_show_adma_error(host);
1479 host->data->error = -EIO;
1482 if (host->data->error)
1483 sdhci_finish_data(host);
1485 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1486 sdhci_transfer_pio(host);
1489 * We currently don't do anything fancy with DMA
1490 * boundaries, but as we can't disable the feature
1491 * we need to at least restart the transfer.
1493 if (intmask & SDHCI_INT_DMA_END)
1494 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1497 if (intmask & SDHCI_INT_DATA_END) {
1500 * Data managed to finish before the
1501 * command completed. Make sure we do
1502 * things in the proper order.
1504 host->data_early = 1;
1506 sdhci_finish_data(host);
1512 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1515 struct sdhci_host* host = dev_id;
1519 spin_lock(&host->lock);
1521 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1523 if (!intmask || intmask == 0xffffffff) {
1528 DBG("*** %s got interrupt: 0x%08x\n",
1529 mmc_hostname(host->mmc), intmask);
1531 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1532 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1533 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1534 tasklet_schedule(&host->card_tasklet);
1537 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1539 if (intmask & SDHCI_INT_CMD_MASK) {
1540 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1542 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1545 if (intmask & SDHCI_INT_DATA_MASK) {
1546 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1548 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1551 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1553 intmask &= ~SDHCI_INT_ERROR;
1555 if (intmask & SDHCI_INT_BUS_POWER) {
1556 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1557 mmc_hostname(host->mmc));
1558 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1561 intmask &= ~SDHCI_INT_BUS_POWER;
1563 if (intmask & SDHCI_INT_CARD_INT)
1566 intmask &= ~SDHCI_INT_CARD_INT;
1569 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1570 mmc_hostname(host->mmc), intmask);
1571 sdhci_dumpregs(host);
1573 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1576 result = IRQ_HANDLED;
1580 spin_unlock(&host->lock);
1583 * We have to delay this as it calls back into the driver.
1586 mmc_signal_sdio_irq(host->mmc);
1591 /*****************************************************************************\
1595 \*****************************************************************************/
1599 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1603 sdhci_disable_card_detection(host);
1605 ret = mmc_suspend_host(host->mmc);
1609 free_irq(host->irq, host);
1614 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1616 int sdhci_resume_host(struct sdhci_host *host)
1620 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1621 if (host->ops->enable_dma)
1622 host->ops->enable_dma(host);
1625 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1626 mmc_hostname(host->mmc), host);
1630 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1633 ret = mmc_resume_host(host->mmc);
1634 sdhci_enable_card_detection(host);
1639 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1641 #endif /* CONFIG_PM */
1643 /*****************************************************************************\
1645 * Device allocation/registration *
1647 \*****************************************************************************/
1649 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1652 struct mmc_host *mmc;
1653 struct sdhci_host *host;
1655 WARN_ON(dev == NULL);
1657 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1659 return ERR_PTR(-ENOMEM);
1661 host = mmc_priv(mmc);
1667 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1669 int sdhci_add_host(struct sdhci_host *host)
1671 struct mmc_host *mmc;
1675 WARN_ON(host == NULL);
1682 host->quirks = debug_quirks;
1684 sdhci_reset(host, SDHCI_RESET_ALL);
1686 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1687 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1688 >> SDHCI_SPEC_VER_SHIFT;
1689 if (host->version > SDHCI_SPEC_200) {
1690 printk(KERN_ERR "%s: Unknown controller version (%d). "
1691 "You may experience problems.\n", mmc_hostname(mmc),
1695 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1696 sdhci_readl(host, SDHCI_CAPABILITIES);
1698 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1699 host->flags |= SDHCI_USE_SDMA;
1700 else if (!(caps & SDHCI_CAN_DO_SDMA))
1701 DBG("Controller doesn't have SDMA capability\n");
1703 host->flags |= SDHCI_USE_SDMA;
1705 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1706 (host->flags & SDHCI_USE_SDMA)) {
1707 DBG("Disabling DMA as it is marked broken\n");
1708 host->flags &= ~SDHCI_USE_SDMA;
1711 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1712 host->flags |= SDHCI_USE_ADMA;
1714 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1715 (host->flags & SDHCI_USE_ADMA)) {
1716 DBG("Disabling ADMA as it is marked broken\n");
1717 host->flags &= ~SDHCI_USE_ADMA;
1720 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1721 if (host->ops->enable_dma) {
1722 if (host->ops->enable_dma(host)) {
1723 printk(KERN_WARNING "%s: No suitable DMA "
1724 "available. Falling back to PIO.\n",
1727 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1732 if (host->flags & SDHCI_USE_ADMA) {
1734 * We need to allocate descriptors for all sg entries
1735 * (128) and potentially one alignment transfer for
1736 * each of those entries.
1738 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1739 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1740 if (!host->adma_desc || !host->align_buffer) {
1741 kfree(host->adma_desc);
1742 kfree(host->align_buffer);
1743 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1744 "buffers. Falling back to standard DMA.\n",
1746 host->flags &= ~SDHCI_USE_ADMA;
1751 * If we use DMA, then it's up to the caller to set the DMA
1752 * mask, but PIO does not need the hw shim so we set a new
1753 * mask here in that case.
1755 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1756 host->dma_mask = DMA_BIT_MASK(64);
1757 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1761 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1762 host->max_clk *= 1000000;
1763 if (host->max_clk == 0 || host->quirks &
1764 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1765 if (!host->ops->get_max_clock) {
1767 "%s: Hardware doesn't specify base clock "
1768 "frequency.\n", mmc_hostname(mmc));
1771 host->max_clk = host->ops->get_max_clock(host);
1775 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1776 if (host->timeout_clk == 0) {
1777 if (host->ops->get_timeout_clock) {
1778 host->timeout_clk = host->ops->get_timeout_clock(host);
1779 } else if (!(host->quirks &
1780 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1782 "%s: Hardware doesn't specify timeout clock "
1783 "frequency.\n", mmc_hostname(mmc));
1787 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1788 host->timeout_clk *= 1000;
1791 * Set host parameters.
1793 mmc->ops = &sdhci_ops;
1794 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
1795 host->ops->get_min_clock)
1796 mmc->f_min = host->ops->get_min_clock(host);
1798 mmc->f_min = host->max_clk / 256;
1799 mmc->f_max = host->max_clk;
1800 mmc->caps = MMC_CAP_SDIO_IRQ;
1802 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1803 mmc->caps |= MMC_CAP_4_BIT_DATA;
1805 if (caps & SDHCI_CAN_DO_HISPD)
1806 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1808 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1809 mmc->caps |= MMC_CAP_NEEDS_POLL;
1812 if (caps & SDHCI_CAN_VDD_330)
1813 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1814 if (caps & SDHCI_CAN_VDD_300)
1815 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1816 if (caps & SDHCI_CAN_VDD_180)
1817 mmc->ocr_avail |= MMC_VDD_165_195;
1819 if (mmc->ocr_avail == 0) {
1820 printk(KERN_ERR "%s: Hardware doesn't report any "
1821 "support voltages.\n", mmc_hostname(mmc));
1825 spin_lock_init(&host->lock);
1828 * Maximum number of segments. Depends on if the hardware
1829 * can do scatter/gather or not.
1831 if (host->flags & SDHCI_USE_ADMA)
1832 mmc->max_hw_segs = 128;
1833 else if (host->flags & SDHCI_USE_SDMA)
1834 mmc->max_hw_segs = 1;
1836 mmc->max_hw_segs = 128;
1837 mmc->max_phys_segs = 128;
1840 * Maximum number of sectors in one transfer. Limited by DMA boundary
1843 mmc->max_req_size = 524288;
1846 * Maximum segment size. Could be one segment with the maximum number
1847 * of bytes. When doing hardware scatter/gather, each entry cannot
1848 * be larger than 64 KiB though.
1850 if (host->flags & SDHCI_USE_ADMA)
1851 mmc->max_seg_size = 65536;
1853 mmc->max_seg_size = mmc->max_req_size;
1856 * Maximum block size. This varies from controller to controller and
1857 * is specified in the capabilities register.
1859 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1860 mmc->max_blk_size = 2;
1862 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1863 SDHCI_MAX_BLOCK_SHIFT;
1864 if (mmc->max_blk_size >= 3) {
1865 printk(KERN_WARNING "%s: Invalid maximum block size, "
1866 "assuming 512 bytes\n", mmc_hostname(mmc));
1867 mmc->max_blk_size = 0;
1871 mmc->max_blk_size = 512 << mmc->max_blk_size;
1874 * Maximum block count.
1876 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1881 tasklet_init(&host->card_tasklet,
1882 sdhci_tasklet_card, (unsigned long)host);
1883 tasklet_init(&host->finish_tasklet,
1884 sdhci_tasklet_finish, (unsigned long)host);
1886 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1888 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1889 mmc_hostname(mmc), host);
1893 sdhci_init(host, 0);
1895 #ifdef CONFIG_MMC_DEBUG
1896 sdhci_dumpregs(host);
1899 #ifdef SDHCI_USE_LEDS_CLASS
1900 snprintf(host->led_name, sizeof(host->led_name),
1901 "%s::", mmc_hostname(mmc));
1902 host->led.name = host->led_name;
1903 host->led.brightness = LED_OFF;
1904 host->led.default_trigger = mmc_hostname(mmc);
1905 host->led.brightness_set = sdhci_led_control;
1907 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1916 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1917 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1918 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1919 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1921 sdhci_enable_card_detection(host);
1925 #ifdef SDHCI_USE_LEDS_CLASS
1927 sdhci_reset(host, SDHCI_RESET_ALL);
1928 free_irq(host->irq, host);
1931 tasklet_kill(&host->card_tasklet);
1932 tasklet_kill(&host->finish_tasklet);
1937 EXPORT_SYMBOL_GPL(sdhci_add_host);
1939 void sdhci_remove_host(struct sdhci_host *host, int dead)
1941 unsigned long flags;
1944 spin_lock_irqsave(&host->lock, flags);
1946 host->flags |= SDHCI_DEVICE_DEAD;
1949 printk(KERN_ERR "%s: Controller removed during "
1950 " transfer!\n", mmc_hostname(host->mmc));
1952 host->mrq->cmd->error = -ENOMEDIUM;
1953 tasklet_schedule(&host->finish_tasklet);
1956 spin_unlock_irqrestore(&host->lock, flags);
1959 sdhci_disable_card_detection(host);
1961 mmc_remove_host(host->mmc);
1963 #ifdef SDHCI_USE_LEDS_CLASS
1964 led_classdev_unregister(&host->led);
1968 sdhci_reset(host, SDHCI_RESET_ALL);
1970 free_irq(host->irq, host);
1972 del_timer_sync(&host->timer);
1974 tasklet_kill(&host->card_tasklet);
1975 tasklet_kill(&host->finish_tasklet);
1977 kfree(host->adma_desc);
1978 kfree(host->align_buffer);
1980 host->adma_desc = NULL;
1981 host->align_buffer = NULL;
1984 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1986 void sdhci_free_host(struct sdhci_host *host)
1988 mmc_free_host(host->mmc);
1991 EXPORT_SYMBOL_GPL(sdhci_free_host);
1993 /*****************************************************************************\
1995 * Driver init/exit *
1997 \*****************************************************************************/
1999 static int __init sdhci_drv_init(void)
2001 printk(KERN_INFO DRIVER_NAME
2002 ": Secure Digital Host Controller Interface driver\n");
2003 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2008 static void __exit sdhci_drv_exit(void)
2012 module_init(sdhci_drv_init);
2013 module_exit(sdhci_drv_exit);
2015 module_param(debug_quirks, uint, 0444);
2017 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2018 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2019 MODULE_LICENSE("GPL");
2021 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");