drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31
  32 #include "sdhci.h"
  33
  34 #define DRIVER_NAME "sdhci"
  35
  36 #define DBG(f, x...) \
  37         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  38
  39 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  40         defined(CONFIG_MMC_SDHCI_MODULE))
  41 #define SDHCI_USE_LEDS_CLASS
  42 #endif
  43
  44 #define MAX_TUNING_LOOP 40
  45
  46 static unsigned int debug_quirks = 0;
  47 static unsigned int debug_quirks2;
  48
  49 static void sdhci_finish_data(struct sdhci_host *);
  50
  51 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  52 static void sdhci_finish_command(struct sdhci_host *);
  53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  54 static void sdhci_tuning_timer(unsigned long data);
  55
  56 #ifdef CONFIG_PM_RUNTIME
  57 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  58 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  59 #else
  60 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  61 {
  62         return 0;
  63 }
  64 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  65 {
  66         return 0;
  67 }
  68 #endif
  69
  70 static void sdhci_dumpregs(struct sdhci_host *host)
  71 {
  72         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  73                 mmc_hostname(host->mmc));
  74
  75         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  76                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  77                 sdhci_readw(host, SDHCI_HOST_VERSION));
  78         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  79                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  80                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  81         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  82                 sdhci_readl(host, SDHCI_ARGUMENT),
  83                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  84         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  85                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  86                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  87         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  88                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  89                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  90         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  91                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  92                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  93         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  94                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  95                 sdhci_readl(host, SDHCI_INT_STATUS));
  96         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_INT_ENABLE),
  98                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  99         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 100                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 101                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 102         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 103                 sdhci_readl(host, SDHCI_CAPABILITIES),
 104                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 105         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 106                 sdhci_readw(host, SDHCI_COMMAND),
 107                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 108         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 109                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 110
 111         if (host->flags & SDHCI_USE_ADMA)
 112                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 113                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 114                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 115
 116         pr_debug(DRIVER_NAME ": ===========================================\n");
 117 }
 118
 119 /*****************************************************************************\
 120  *                                                                           *
 121  * Low level functions                                                       *
 122  *                                                                           *
 123 \*****************************************************************************/
 124
 125 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 126 {
 127         u32 ier;
 128
 129         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 130         ier &= ~clear;
 131         ier |= set;
 132         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 133         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 134 }
 135
 136 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 137 {
 138         sdhci_clear_set_irqs(host, 0, irqs);
 139 }
 140
 141 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 142 {
 143         sdhci_clear_set_irqs(host, irqs, 0);
 144 }
 145
 146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 147 {
 148         u32 present, irqs;
 149
 150         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 151             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 152                 return;
 153
 154         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 155                               SDHCI_CARD_PRESENT;
 156         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 157
 158         if (enable)
 159                 sdhci_unmask_irqs(host, irqs);
 160         else
 161                 sdhci_mask_irqs(host, irqs);
 162 }
 163
 164 static void sdhci_enable_card_detection(struct sdhci_host *host)
 165 {
 166         sdhci_set_card_detection(host, true);
 167 }
 168
 169 static void sdhci_disable_card_detection(struct sdhci_host *host)
 170 {
 171         sdhci_set_card_detection(host, false);
 172 }
 173
 174 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 175 {
 176         unsigned long timeout;
 177         u32 uninitialized_var(ier);
 178
 179         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 180                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 181                         SDHCI_CARD_PRESENT))
 182                         return;
 183         }
 184
 185         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 186                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 187
 188         if (host->ops->platform_reset_enter)
 189                 host->ops->platform_reset_enter(host, mask);
 190
 191         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 192
 193         if (mask & SDHCI_RESET_ALL)
 194                 host->clock = 0;
 195
 196         /* Wait max 100 ms */
 197         timeout = 100;
 198
 199         /* hw clears the bit when it's done */
 200         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 201                 if (timeout == 0) {
 202                         pr_err("%s: Reset 0x%x never completed.\n",
 203                                 mmc_hostname(host->mmc), (int)mask);
 204                         sdhci_dumpregs(host);
 205                         return;
 206                 }
 207                 timeout--;
 208                 mdelay(1);
 209         }
 210
 211         if (host->ops->platform_reset_exit)
 212                 host->ops->platform_reset_exit(host, mask);
 213
 214         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 215                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 216
 217         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 218                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
 219                         host->ops->enable_dma(host);
 220         }
 221 }
 222
 223 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 224
 225 static void sdhci_init(struct sdhci_host *host, int soft)
 226 {
 227         if (soft)
 228                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 229         else
 230                 sdhci_reset(host, SDHCI_RESET_ALL);
 231
 232         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 233                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 234                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 235                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 236                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 237
 238         if (soft) {
 239                 /* force clock reconfiguration */
 240                 host->clock = 0;
 241                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 242         }
 243 }
 244
 245 static void sdhci_reinit(struct sdhci_host *host)
 246 {
 247         sdhci_init(host, 0);
 248         /*
 249          * Retuning stuffs are affected by different cards inserted and only
 250          * applicable to UHS-I cards. So reset these fields to their initial
 251          * value when card is removed.
 252          */
 253         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 254                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 255
 256                 del_timer_sync(&host->tuning_timer);
 257                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 258                 host->mmc->max_blk_count =
 259                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 260         }
 261         sdhci_enable_card_detection(host);
 262 }
 263
 264 static void sdhci_activate_led(struct sdhci_host *host)
 265 {
 266         u8 ctrl;
 267
 268         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 269         ctrl |= SDHCI_CTRL_LED;
 270         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 271 }
 272
 273 static void sdhci_deactivate_led(struct sdhci_host *host)
 274 {
 275         u8 ctrl;
 276
 277         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 278         ctrl &= ~SDHCI_CTRL_LED;
 279         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 280 }
 281
 282 #ifdef SDHCI_USE_LEDS_CLASS
 283 static void sdhci_led_control(struct led_classdev *led,
 284         enum led_brightness brightness)
 285 {
 286         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 287         unsigned long flags;
 288
 289         spin_lock_irqsave(&host->lock, flags);
 290
 291         if (host->runtime_suspended)
 292                 goto out;
 293
 294         if (brightness == LED_OFF)
 295                 sdhci_deactivate_led(host);
 296         else
 297                 sdhci_activate_led(host);
 298 out:
 299         spin_unlock_irqrestore(&host->lock, flags);
 300 }
 301 #endif
 302
 303 /*****************************************************************************\
 304  *                                                                           *
 305  * Core functions                                                            *
 306  *                                                                           *
 307 \*****************************************************************************/
 308
 309 static void sdhci_read_block_pio(struct sdhci_host *host)
 310 {
 311         unsigned long flags;
 312         size_t blksize, len, chunk;
 313         u32 uninitialized_var(scratch);
 314         u8 *buf;
 315
 316         DBG("PIO reading\n");
 317
 318         blksize = host->data->blksz;
 319         chunk = 0;
 320
 321         local_irq_save(flags);
 322
 323         while (blksize) {
 324                 if (!sg_miter_next(&host->sg_miter))
 325                         BUG();
 326
 327                 len = min(host->sg_miter.length, blksize);
 328
 329                 blksize -= len;
 330                 host->sg_miter.consumed = len;
 331
 332                 buf = host->sg_miter.addr;
 333
 334                 while (len) {
 335                         if (chunk == 0) {
 336                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 337                                 chunk = 4;
 338                         }
 339
 340                         *buf = scratch & 0xFF;
 341
 342                         buf++;
 343                         scratch >>= 8;
 344                         chunk--;
 345                         len--;
 346                 }
 347         }
 348
 349         sg_miter_stop(&host->sg_miter);
 350
 351         local_irq_restore(flags);
 352 }
 353
 354 static void sdhci_write_block_pio(struct sdhci_host *host)
 355 {
 356         unsigned long flags;
 357         size_t blksize, len, chunk;
 358         u32 scratch;
 359         u8 *buf;
 360
 361         DBG("PIO writing\n");
 362
 363         blksize = host->data->blksz;
 364         chunk = 0;
 365         scratch = 0;
 366
 367         local_irq_save(flags);
 368
 369         while (blksize) {
 370                 if (!sg_miter_next(&host->sg_miter))
 371                         BUG();
 372
 373                 len = min(host->sg_miter.length, blksize);
 374
 375                 blksize -= len;
 376                 host->sg_miter.consumed = len;
 377
 378                 buf = host->sg_miter.addr;
 379
 380                 while (len) {
 381                         scratch |= (u32)*buf << (chunk * 8);
 382
 383                         buf++;
 384                         chunk++;
 385                         len--;
 386
 387                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 388                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 389                                 chunk = 0;
 390                                 scratch = 0;
 391                         }
 392                 }
 393         }
 394
 395         sg_miter_stop(&host->sg_miter);
 396
 397         local_irq_restore(flags);
 398 }
 399
 400 static void sdhci_transfer_pio(struct sdhci_host *host)
 401 {
 402         u32 mask;
 403
 404         BUG_ON(!host->data);
 405
 406         if (host->blocks == 0)
 407                 return;
 408
 409         if (host->data->flags & MMC_DATA_READ)
 410                 mask = SDHCI_DATA_AVAILABLE;
 411         else
 412                 mask = SDHCI_SPACE_AVAILABLE;
 413
 414         /*
 415          * Some controllers (JMicron JMB38x) mess up the buffer bits
 416          * for transfers < 4 bytes. As long as it is just one block,
 417          * we can ignore the bits.
 418          */
 419         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 420                 (host->data->blocks == 1))
 421                 mask = ~0;
 422
 423         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 424                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 425                         udelay(100);
 426
 427                 if (host->data->flags & MMC_DATA_READ)
 428                         sdhci_read_block_pio(host);
 429                 else
 430                         sdhci_write_block_pio(host);
 431
 432                 host->blocks--;
 433                 if (host->blocks == 0)
 434                         break;
 435         }
 436
 437         DBG("PIO transfer complete.\n");
 438 }
 439
 440 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 441 {
 442         local_irq_save(*flags);
 443         return kmap_atomic(sg_page(sg)) + sg->offset;
 444 }
 445
 446 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 447 {
 448         kunmap_atomic(buffer);
 449         local_irq_restore(*flags);
 450 }
 451
 452 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 453 {
 454         __le32 *dataddr = (__le32 __force *)(desc + 4);
 455         __le16 *cmdlen = (__le16 __force *)desc;
 456
 457         /* SDHCI specification says ADMA descriptors should be 4 byte
 458          * aligned, so using 16 or 32bit operations should be safe. */
 459
 460         cmdlen[0] = cpu_to_le16(cmd);
 461         cmdlen[1] = cpu_to_le16(len);
 462
 463         dataddr[0] = cpu_to_le32(addr);
 464 }
 465
 466 static int sdhci_adma_table_pre(struct sdhci_host *host,
 467         struct mmc_data *data)
 468 {
 469         int direction;
 470
 471         u8 *desc;
 472         u8 *align;
 473         dma_addr_t addr;
 474         dma_addr_t align_addr;
 475         int len, offset;
 476
 477         struct scatterlist *sg;
 478         int i;
 479         char *buffer;
 480         unsigned long flags;
 481
 482         /*
 483          * The spec does not specify endianness of descriptor table.
 484          * We currently guess that it is LE.
 485          */
 486
 487         if (data->flags & MMC_DATA_READ)
 488                 direction = DMA_FROM_DEVICE;
 489         else
 490                 direction = DMA_TO_DEVICE;
 491
 492         /*
 493          * The ADMA descriptor table is mapped further down as we
 494          * need to fill it with data first.
 495          */
 496
 497         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 498                 host->align_buffer, 128 * 4, direction);
 499         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 500                 goto fail;
 501         BUG_ON(host->align_addr & 0x3);
 502
 503         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 504                 data->sg, data->sg_len, direction);
 505         if (host->sg_count == 0)
 506                 goto unmap_align;
 507
 508         desc = host->adma_desc;
 509         align = host->align_buffer;
 510
 511         align_addr = host->align_addr;
 512
 513         for_each_sg(data->sg, sg, host->sg_count, i) {
 514                 addr = sg_dma_address(sg);
 515                 len = sg_dma_len(sg);
 516
 517                 /*
 518                  * The SDHCI specification states that ADMA
 519                  * addresses must be 32-bit aligned. If they
 520                  * aren't, then we use a bounce buffer for
 521                  * the (up to three) bytes that screw up the
 522                  * alignment.
 523                  */
 524                 offset = (4 - (addr & 0x3)) & 0x3;
 525                 if (offset) {
 526                         if (data->flags & MMC_DATA_WRITE) {
 527                                 buffer = sdhci_kmap_atomic(sg, &flags);
 528                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 529                                 memcpy(align, buffer, offset);
 530                                 sdhci_kunmap_atomic(buffer, &flags);
 531                         }
 532
 533                         /* tran, valid */
 534                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 535
 536                         BUG_ON(offset > 65536);
 537
 538                         align += 4;
 539                         align_addr += 4;
 540
 541                         desc += 8;
 542
 543                         addr += offset;
 544                         len -= offset;
 545                 }
 546
 547                 BUG_ON(len > 65536);
 548
 549                 /* tran, valid */
 550                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 551                 desc += 8;
 552
 553                 /*
 554                  * If this triggers then we have a calculation bug
 555                  * somewhere. :/
 556                  */
 557                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 558         }
 559
 560         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 561                 /*
 562                 * Mark the last descriptor as the terminating descriptor
 563                 */
 564                 if (desc != host->adma_desc) {
 565                         desc -= 8;
 566                         desc[0] |= 0x2; /* end */
 567                 }
 568         } else {
 569                 /*
 570                 * Add a terminating entry.
 571                 */
 572
 573                 /* nop, end, valid */
 574                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 575         }
 576
 577         /*
 578          * Resync align buffer as we might have changed it.
 579          */
 580         if (data->flags & MMC_DATA_WRITE) {
 581                 dma_sync_single_for_device(mmc_dev(host->mmc),
 582                         host->align_addr, 128 * 4, direction);
 583         }
 584
 585         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 586                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 587         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 588                 goto unmap_entries;
 589         BUG_ON(host->adma_addr & 0x3);
 590
 591         return 0;
 592
 593 unmap_entries:
 594         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 595                 data->sg_len, direction);
 596 unmap_align:
 597         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 598                 128 * 4, direction);
 599 fail:
 600         return -EINVAL;
 601 }
 602
 603 static void sdhci_adma_table_post(struct sdhci_host *host,
 604         struct mmc_data *data)
 605 {
 606         int direction;
 607
 608         struct scatterlist *sg;
 609         int i, size;
 610         u8 *align;
 611         char *buffer;
 612         unsigned long flags;
 613
 614         if (data->flags & MMC_DATA_READ)
 615                 direction = DMA_FROM_DEVICE;
 616         else
 617                 direction = DMA_TO_DEVICE;
 618
 619         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 620                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 621
 622         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 623                 128 * 4, direction);
 624
 625         if (data->flags & MMC_DATA_READ) {
 626                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 627                         data->sg_len, direction);
 628
 629                 align = host->align_buffer;
 630
 631                 for_each_sg(data->sg, sg, host->sg_count, i) {
 632                         if (sg_dma_address(sg) & 0x3) {
 633                                 size = 4 - (sg_dma_address(sg) & 0x3);
 634
 635                                 buffer = sdhci_kmap_atomic(sg, &flags);
 636                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 637                                 memcpy(buffer, align, size);
 638                                 sdhci_kunmap_atomic(buffer, &flags);
 639
 640                                 align += 4;
 641                         }
 642                 }
 643         }
 644
 645         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 646                 data->sg_len, direction);
 647 }
 648
 649 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 650 {
 651         u8 count;
 652         struct mmc_data *data = cmd->data;
 653         unsigned target_timeout, current_timeout;
 654
 655         /*
 656          * If the host controller provides us with an incorrect timeout
 657          * value, just skip the check and use 0xE.  The hardware may take
 658          * longer to time out, but that's much better than having a too-short
 659          * timeout value.
 660          */
 661         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 662                 return 0xE;
 663
 664         /* Unspecified timeout, assume max */
 665         if (!data && !cmd->cmd_timeout_ms)
 666                 return 0xE;
 667
 668         /* timeout in us */
 669         if (!data)
 670                 target_timeout = cmd->cmd_timeout_ms * 1000;
 671         else {
 672                 target_timeout = data->timeout_ns / 1000;
 673                 if (host->clock)
 674                         target_timeout += data->timeout_clks / host->clock;
 675         }
 676
 677         /*
 678          * Figure out needed cycles.
 679          * We do this in steps in order to fit inside a 32 bit int.
 680          * The first step is the minimum timeout, which will have a
 681          * minimum resolution of 6 bits:
 682          * (1) 2^13*1000 > 2^22,
 683          * (2) host->timeout_clk < 2^16
 684          *     =>
 685          *     (1) / (2) > 2^6
 686          */
 687         count = 0;
 688         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 689         while (current_timeout < target_timeout) {
 690                 count++;
 691                 current_timeout <<= 1;
 692                 if (count >= 0xF)
 693                         break;
 694         }
 695
 696         if (count >= 0xF) {
 697                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 698                     mmc_hostname(host->mmc), count, cmd->opcode);
 699                 count = 0xE;
 700         }
 701
 702         return count;
 703 }
 704
 705 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 706 {
 707         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 708         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 709
 710         if (host->flags & SDHCI_REQ_USE_DMA)
 711                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 712         else
 713                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 714 }
 715
 716 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 717 {
 718         u8 count;
 719         u8 ctrl;
 720         struct mmc_data *data = cmd->data;
 721         int ret;
 722
 723         WARN_ON(host->data);
 724
 725         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 726                 count = sdhci_calc_timeout(host, cmd);
 727                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 728         }
 729
 730         if (!data)
 731                 return;
 732
 733         /* Sanity checks */
 734         BUG_ON(data->blksz * data->blocks > 524288);
 735         BUG_ON(data->blksz > host->mmc->max_blk_size);
 736         BUG_ON(data->blocks > 65535);
 737
 738         host->data = data;
 739         host->data_early = 0;
 740         host->data->bytes_xfered = 0;
 741
 742         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 743                 host->flags |= SDHCI_REQ_USE_DMA;
 744
 745         /*
 746          * FIXME: This doesn't account for merging when mapping the
 747          * scatterlist.
 748          */
 749         if (host->flags & SDHCI_REQ_USE_DMA) {
 750                 int broken, i;
 751                 struct scatterlist *sg;
 752
 753                 broken = 0;
 754                 if (host->flags & SDHCI_USE_ADMA) {
 755                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 756                                 broken = 1;
 757                 } else {
 758                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 759                                 broken = 1;
 760                 }
 761
 762                 if (unlikely(broken)) {
 763                         for_each_sg(data->sg, sg, data->sg_len, i) {
 764                                 if (sg->length & 0x3) {
 765                                         DBG("Reverting to PIO because of "
 766                                                 "transfer size (%d)\n",
 767                                                 sg->length);
 768                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 769                                         break;
 770                                 }
 771                         }
 772                 }
 773         }
 774
 775         /*
 776          * The assumption here being that alignment is the same after
 777          * translation to device address space.
 778          */
 779         if (host->flags & SDHCI_REQ_USE_DMA) {
 780                 int broken, i;
 781                 struct scatterlist *sg;
 782
 783                 broken = 0;
 784                 if (host->flags & SDHCI_USE_ADMA) {
 785                         /*
 786                          * As we use 3 byte chunks to work around
 787                          * alignment problems, we need to check this
 788                          * quirk.
 789                          */
 790                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 791                                 broken = 1;
 792                 } else {
 793                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 794                                 broken = 1;
 795                 }
 796
 797                 if (unlikely(broken)) {
 798                         for_each_sg(data->sg, sg, data->sg_len, i) {
 799                                 if (sg->offset & 0x3) {
 800                                         DBG("Reverting to PIO because of "
 801                                                 "bad alignment\n");
 802                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 803                                         break;
 804                                 }
 805                         }
 806                 }
 807         }
 808
 809         if (host->flags & SDHCI_REQ_USE_DMA) {
 810                 if (host->flags & SDHCI_USE_ADMA) {
 811                         ret = sdhci_adma_table_pre(host, data);
 812                         if (ret) {
 813                                 /*
 814                                  * This only happens when someone fed
 815                                  * us an invalid request.
 816                                  */
 817                                 WARN_ON(1);
 818                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 819                         } else {
 820                                 sdhci_writel(host, host->adma_addr,
 821                                         SDHCI_ADMA_ADDRESS);
 822                         }
 823                 } else {
 824                         int sg_cnt;
 825
 826                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 827                                         data->sg, data->sg_len,
 828                                         (data->flags & MMC_DATA_READ) ?
 829                                                 DMA_FROM_DEVICE :
 830                                                 DMA_TO_DEVICE);
 831                         if (sg_cnt == 0) {
 832                                 /*
 833                                  * This only happens when someone fed
 834                                  * us an invalid request.
 835                                  */
 836                                 WARN_ON(1);
 837                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 838                         } else {
 839                                 WARN_ON(sg_cnt != 1);
 840                                 sdhci_writel(host, sg_dma_address(data->sg),
 841                                         SDHCI_DMA_ADDRESS);
 842                         }
 843                 }
 844         }
 845
 846         /*
 847          * Always adjust the DMA selection as some controllers
 848          * (e.g. JMicron) can't do PIO properly when the selection
 849          * is ADMA.
 850          */
 851         if (host->version >= SDHCI_SPEC_200) {
 852                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 853                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 854                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 855                         (host->flags & SDHCI_USE_ADMA))
 856                         ctrl |= SDHCI_CTRL_ADMA32;
 857                 else
 858                         ctrl |= SDHCI_CTRL_SDMA;
 859                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 860         }
 861
 862         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 863                 int flags;
 864
 865                 flags = SG_MITER_ATOMIC;
 866                 if (host->data->flags & MMC_DATA_READ)
 867                         flags |= SG_MITER_TO_SG;
 868                 else
 869                         flags |= SG_MITER_FROM_SG;
 870                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 871                 host->blocks = data->blocks;
 872         }
 873
 874         sdhci_set_transfer_irqs(host);
 875
 876         /* Set the DMA boundary value and block size */
 877         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 878                 data->blksz), SDHCI_BLOCK_SIZE);
 879         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 880 }
 881
 882 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 883         struct mmc_command *cmd)
 884 {
 885         u16 mode;
 886         struct mmc_data *data = cmd->data;
 887
 888         if (data == NULL)
 889                 return;
 890
 891         WARN_ON(!host->data);
 892
 893         mode = SDHCI_TRNS_BLK_CNT_EN;
 894         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 895                 mode |= SDHCI_TRNS_MULTI;
 896                 /*
 897                  * If we are sending CMD23, CMD12 never gets sent
 898                  * on successful completion (so no Auto-CMD12).
 899                  */
 900                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 901                         mode |= SDHCI_TRNS_AUTO_CMD12;
 902                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 903                         mode |= SDHCI_TRNS_AUTO_CMD23;
 904                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 905                 }
 906         }
 907
 908         if (data->flags & MMC_DATA_READ)
 909                 mode |= SDHCI_TRNS_READ;
 910         if (host->flags & SDHCI_REQ_USE_DMA)
 911                 mode |= SDHCI_TRNS_DMA;
 912
 913         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 914 }
 915
 916 static void sdhci_finish_data(struct sdhci_host *host)
 917 {
 918         struct mmc_data *data;
 919
 920         BUG_ON(!host->data);
 921
 922         data = host->data;
 923         host->data = NULL;
 924
 925         if (host->flags & SDHCI_REQ_USE_DMA) {
 926                 if (host->flags & SDHCI_USE_ADMA)
 927                         sdhci_adma_table_post(host, data);
 928                 else {
 929                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 930                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 931                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 932                 }
 933         }
 934
 935         /*
 936          * The specification states that the block count register must
 937          * be updated, but it does not specify at what point in the
 938          * data flow. That makes the register entirely useless to read
 939          * back so we have to assume that nothing made it to the card
 940          * in the event of an error.
 941          */
 942         if (data->error)
 943                 data->bytes_xfered = 0;
 944         else
 945                 data->bytes_xfered = data->blksz * data->blocks;
 946
 947         /*
 948          * Need to send CMD12 if -
 949          * a) open-ended multiblock transfer (no CMD23)
 950          * b) error in multiblock transfer
 951          */
 952         if (data->stop &&
 953             (data->error ||
 954              !host->mrq->sbc)) {
 955
 956                 /*
 957                  * The controller needs a reset of internal state machines
 958                  * upon error conditions.
 959                  */
 960                 if (data->error) {
 961                         sdhci_reset(host, SDHCI_RESET_CMD);
 962                         sdhci_reset(host, SDHCI_RESET_DATA);
 963                 }
 964
 965                 sdhci_send_command(host, data->stop);
 966         } else
 967                 tasklet_schedule(&host->finish_tasklet);
 968 }
 969
 970 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 971 {
 972         int flags;
 973         u32 mask;
 974         unsigned long timeout;
 975
 976         WARN_ON(host->cmd);
 977
 978         /* Wait max 10 ms */
 979         timeout = 10;
 980
 981         mask = SDHCI_CMD_INHIBIT;
 982         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 983                 mask |= SDHCI_DATA_INHIBIT;
 984
 985         /* We shouldn't wait for data inihibit for stop commands, even
 986            though they might use busy signaling */
 987         if (host->mrq->data && (cmd == host->mrq->data->stop))
 988                 mask &= ~SDHCI_DATA_INHIBIT;
 989
 990         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 991                 if (timeout == 0) {
 992                         pr_err("%s: Controller never released "
 993                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 994                         sdhci_dumpregs(host);
 995                         cmd->error = -EIO;
 996                         tasklet_schedule(&host->finish_tasklet);
 997                         return;
 998                 }
 999                 timeout--;
1000                 mdelay(1);
1001         }
1002
1003         mod_timer(&host->timer, jiffies + 10 * HZ);
1004
1005         host->cmd = cmd;
1006
1007         sdhci_prepare_data(host, cmd);
1008
1009         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1010
1011         sdhci_set_transfer_mode(host, cmd);
1012
1013         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1014                 pr_err("%s: Unsupported response type!\n",
1015                         mmc_hostname(host->mmc));
1016                 cmd->error = -EINVAL;
1017                 tasklet_schedule(&host->finish_tasklet);
1018                 return;
1019         }
1020
1021         if (!(cmd->flags & MMC_RSP_PRESENT))
1022                 flags = SDHCI_CMD_RESP_NONE;
1023         else if (cmd->flags & MMC_RSP_136)
1024                 flags = SDHCI_CMD_RESP_LONG;
1025         else if (cmd->flags & MMC_RSP_BUSY)
1026                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1027         else
1028                 flags = SDHCI_CMD_RESP_SHORT;
1029
1030         if (cmd->flags & MMC_RSP_CRC)
1031                 flags |= SDHCI_CMD_CRC;
1032         if (cmd->flags & MMC_RSP_OPCODE)
1033                 flags |= SDHCI_CMD_INDEX;
1034
1035         /* CMD19 is special in that the Data Present Select should be set */
1036         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1037             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1038                 flags |= SDHCI_CMD_DATA;
1039
1040         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1041 }
1042
1043 static void sdhci_finish_command(struct sdhci_host *host)
1044 {
1045         int i;
1046
1047         BUG_ON(host->cmd == NULL);
1048
1049         if (host->cmd->flags & MMC_RSP_PRESENT) {
1050                 if (host->cmd->flags & MMC_RSP_136) {
1051                         /* CRC is stripped so we need to do some shifting. */
1052                         for (i = 0;i < 4;i++) {
1053                                 host->cmd->resp[i] = sdhci_readl(host,
1054                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1055                                 if (i != 3)
1056                                         host->cmd->resp[i] |=
1057                                                 sdhci_readb(host,
1058                                                 SDHCI_RESPONSE + (3-i)*4-1);
1059                         }
1060                 } else {
1061                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1062                 }
1063         }
1064
1065         host->cmd->error = 0;
1066
1067         /* Finished CMD23, now send actual command. */
1068         if (host->cmd == host->mrq->sbc) {
1069                 host->cmd = NULL;
1070                 sdhci_send_command(host, host->mrq->cmd);
1071         } else {
1072
1073                 /* Processed actual command. */
1074                 if (host->data && host->data_early)
1075                         sdhci_finish_data(host);
1076
1077                 if (!host->cmd->data)
1078                         tasklet_schedule(&host->finish_tasklet);
1079
1080                 host->cmd = NULL;
1081         }
1082 }
1083
1084 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1085 {
1086         int div = 0; /* Initialized for compiler warning */
1087         int real_div = div, clk_mul = 1;
1088         u16 clk = 0;
1089         unsigned long timeout;
1090
1091         if (clock && clock == host->clock)
1092                 return;
1093
1094         host->mmc->actual_clock = 0;
1095
1096         if (host->ops->set_clock) {
1097                 host->ops->set_clock(host, clock);
1098                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1099                         return;
1100         }
1101
1102         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1103
1104         if (clock == 0)
1105                 goto out;
1106
1107         if (host->version >= SDHCI_SPEC_300) {
1108                 /*
1109                  * Check if the Host Controller supports Programmable Clock
1110                  * Mode.
1111                  */
1112                 if (host->clk_mul) {
1113                         u16 ctrl;
1114
1115                         /*
1116                          * We need to figure out whether the Host Driver needs
1117                          * to select Programmable Clock Mode, or the value can
1118                          * be set automatically by the Host Controller based on
1119                          * the Preset Value registers.
1120                          */
1121                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1122                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1123                                 for (div = 1; div <= 1024; div++) {
1124                                         if (((host->max_clk * host->clk_mul) /
1125                                               div) <= clock)
1126                                                 break;
1127                                 }
1128                                 /*
1129                                  * Set Programmable Clock Mode in the Clock
1130                                  * Control register.
1131                                  */
1132                                 clk = SDHCI_PROG_CLOCK_MODE;
1133                                 real_div = div;
1134                                 clk_mul = host->clk_mul;
1135                                 div--;
1136                         }
1137                 } else {
1138                         /* Version 3.00 divisors must be a multiple of 2. */
1139                         if (host->max_clk <= clock)
1140                                 div = 1;
1141                         else {
1142                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1143                                      div += 2) {
1144                                         if ((host->max_clk / div) <= clock)
1145                                                 break;
1146                                 }
1147                         }
1148                         real_div = div;
1149                         div >>= 1;
1150                 }
1151         } else {
1152                 /* Version 2.00 divisors must be a power of 2. */
1153                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1154                         if ((host->max_clk / div) <= clock)
1155                                 break;
1156                 }
1157                 real_div = div;
1158                 div >>= 1;
1159         }
1160
1161         if (real_div)
1162                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1163
1164         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1165         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1166                 << SDHCI_DIVIDER_HI_SHIFT;
1167         clk |= SDHCI_CLOCK_INT_EN;
1168         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1169
1170         /* Wait max 20 ms */
1171         timeout = 20;
1172         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1173                 & SDHCI_CLOCK_INT_STABLE)) {
1174                 if (timeout == 0) {
1175                         pr_err("%s: Internal clock never "
1176                                 "stabilised.\n", mmc_hostname(host->mmc));
1177                         sdhci_dumpregs(host);
1178                         return;
1179                 }
1180                 timeout--;
1181                 mdelay(1);
1182         }
1183
1184         clk |= SDHCI_CLOCK_CARD_EN;
1185         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1186
1187 out:
1188         host->clock = clock;
1189 }
1190
1191 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1192 {
1193         u8 pwr = 0;
1194
1195         if (power != (unsigned short)-1) {
1196                 switch (1 << power) {
1197                 case MMC_VDD_165_195:
1198                         pwr = SDHCI_POWER_180;
1199                         break;
1200                 case MMC_VDD_29_30:
1201                 case MMC_VDD_30_31:
1202                         pwr = SDHCI_POWER_300;
1203                         break;
1204                 case MMC_VDD_32_33:
1205                 case MMC_VDD_33_34:
1206                         pwr = SDHCI_POWER_330;
1207                         break;
1208                 default:
1209                         BUG();
1210                 }
1211         }
1212
1213         if (host->pwr == pwr)
1214                 return -1;
1215
1216         host->pwr = pwr;
1217
1218         if (pwr == 0) {
1219                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1220                 return 0;
1221         }
1222
1223         /*
1224          * Spec says that we should clear the power reg before setting
1225          * a new value. Some controllers don't seem to like this though.
1226          */
1227         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1228                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1229
1230         /*
1231          * At least the Marvell CaFe chip gets confused if we set the voltage
1232          * and set turn on power at the same time, so set the voltage first.
1233          */
1234         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1235                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1236
1237         pwr |= SDHCI_POWER_ON;
1238
1239         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1240
1241         /*
1242          * Some controllers need an extra 10ms delay of 10ms before they
1243          * can apply clock after applying power
1244          */
1245         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1246                 mdelay(10);
1247
1248         return power;
1249 }
1250
1251 /*****************************************************************************\
1252  *                                                                           *
1253  * MMC callbacks                                                             *
1254  *                                                                           *
1255 \*****************************************************************************/
1256
1257 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1258 {
1259         struct sdhci_host *host;
1260         bool present;
1261         unsigned long flags;
1262         u32 tuning_opcode;
1263
1264         host = mmc_priv(mmc);
1265
1266         sdhci_runtime_pm_get(host);
1267
1268         spin_lock_irqsave(&host->lock, flags);
1269
1270         WARN_ON(host->mrq != NULL);
1271
1272 #ifndef SDHCI_USE_LEDS_CLASS
1273         sdhci_activate_led(host);
1274 #endif
1275
1276         /*
1277          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1278          * requests if Auto-CMD12 is enabled.
1279          */
1280         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1281                 if (mrq->stop) {
1282                         mrq->data->stop = NULL;
1283                         mrq->stop = NULL;
1284                 }
1285         }
1286
1287         host->mrq = mrq;
1288
1289         /* If polling, assume that the card is always present. */
1290         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1291                 present = true;
1292         else
1293                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1294                                 SDHCI_CARD_PRESENT;
1295
1296         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1297                 host->mrq->cmd->error = -ENOMEDIUM;
1298                 tasklet_schedule(&host->finish_tasklet);
1299         } else {
1300                 u32 present_state;
1301
1302                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1303                 /*
1304                  * Check if the re-tuning timer has already expired and there
1305                  * is no on-going data transfer. If so, we need to execute
1306                  * tuning procedure before sending command.
1307                  */
1308                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1309                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1310                         /* eMMC uses cmd21 while sd and sdio use cmd19 */
1311                         tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1312                                 MMC_SEND_TUNING_BLOCK_HS200 :
1313                                 MMC_SEND_TUNING_BLOCK;
1314                         spin_unlock_irqrestore(&host->lock, flags);
1315                         sdhci_execute_tuning(mmc, tuning_opcode);
1316                         spin_lock_irqsave(&host->lock, flags);
1317
1318                         /* Restore original mmc_request structure */
1319                         host->mrq = mrq;
1320                 }
1321
1322                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1323                         sdhci_send_command(host, mrq->sbc);
1324                 else
1325                         sdhci_send_command(host, mrq->cmd);
1326         }
1327
1328         mmiowb();
1329         spin_unlock_irqrestore(&host->lock, flags);
1330 }
1331
1332 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1333 {
1334         unsigned long flags;
1335         int vdd_bit = -1;
1336         u8 ctrl;
1337
1338         spin_lock_irqsave(&host->lock, flags);
1339
1340         if (host->flags & SDHCI_DEVICE_DEAD) {
1341                 spin_unlock_irqrestore(&host->lock, flags);
1342                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1343                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1344                 return;
1345         }
1346
1347         /*
1348          * Reset the chip on each power off.
1349          * Should clear out any weird states.
1350          */
1351         if (ios->power_mode == MMC_POWER_OFF) {
1352                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1353                 sdhci_reinit(host);
1354         }
1355
1356         sdhci_set_clock(host, ios->clock);
1357
1358         if (ios->power_mode == MMC_POWER_OFF)
1359                 vdd_bit = sdhci_set_power(host, -1);
1360         else
1361                 vdd_bit = sdhci_set_power(host, ios->vdd);
1362
1363         if (host->vmmc && vdd_bit != -1) {
1364                 spin_unlock_irqrestore(&host->lock, flags);
1365                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1366                 spin_lock_irqsave(&host->lock, flags);
1367         }
1368
1369         if (host->ops->platform_send_init_74_clocks)
1370                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1371
1372         /*
1373          * If your platform has 8-bit width support but is not a v3 controller,
1374          * or if it requires special setup code, you should implement that in
1375          * platform_8bit_width().
1376          */
1377         if (host->ops->platform_8bit_width)
1378                 host->ops->platform_8bit_width(host, ios->bus_width);
1379         else {
1380                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1381                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1382                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1383                         if (host->version >= SDHCI_SPEC_300)
1384                                 ctrl |= SDHCI_CTRL_8BITBUS;
1385                 } else {
1386                         if (host->version >= SDHCI_SPEC_300)
1387                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1388                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1389                                 ctrl |= SDHCI_CTRL_4BITBUS;
1390                         else
1391                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1392                 }
1393                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1394         }
1395
1396         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1397
1398         if ((ios->timing == MMC_TIMING_SD_HS ||
1399              ios->timing == MMC_TIMING_MMC_HS)
1400             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1401                 ctrl |= SDHCI_CTRL_HISPD;
1402         else
1403                 ctrl &= ~SDHCI_CTRL_HISPD;
1404
1405         if (host->version >= SDHCI_SPEC_300) {
1406                 u16 clk, ctrl_2;
1407                 unsigned int clock;
1408
1409                 /* In case of UHS-I modes, set High Speed Enable */
1410                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1411                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1412                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1413                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1414                     (ios->timing == MMC_TIMING_UHS_SDR25))
1415                         ctrl |= SDHCI_CTRL_HISPD;
1416
1417                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1418                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1419                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1420                         /*
1421                          * We only need to set Driver Strength if the
1422                          * preset value enable is not set.
1423                          */
1424                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1425                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1426                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1427                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1428                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1429
1430                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1431                 } else {
1432                         /*
1433                          * According to SDHC Spec v3.00, if the Preset Value
1434                          * Enable in the Host Control 2 register is set, we
1435                          * need to reset SD Clock Enable before changing High
1436                          * Speed Enable to avoid generating clock gliches.
1437                          */
1438
1439                         /* Reset SD Clock Enable */
1440                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1441                         clk &= ~SDHCI_CLOCK_CARD_EN;
1442                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1443
1444                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1445
1446                         /* Re-enable SD Clock */
1447                         clock = host->clock;
1448                         host->clock = 0;
1449                         sdhci_set_clock(host, clock);
1450                 }
1451
1452
1453                 /* Reset SD Clock Enable */
1454                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1455                 clk &= ~SDHCI_CLOCK_CARD_EN;
1456                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1457
1458                 if (host->ops->set_uhs_signaling)
1459                         host->ops->set_uhs_signaling(host, ios->timing);
1460                 else {
1461                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1462                         /* Select Bus Speed Mode for host */
1463                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1464                         if (ios->timing == MMC_TIMING_MMC_HS200)
1465                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1466                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
1467                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1468                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1469                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1470                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1471                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1472                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1473                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1474                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1475                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1476                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1477                 }
1478
1479                 /* Re-enable SD Clock */
1480                 clock = host->clock;
1481                 host->clock = 0;
1482                 sdhci_set_clock(host, clock);
1483         } else
1484                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1485
1486         /*
1487          * Some (ENE) controllers go apeshit on some ios operation,
1488          * signalling timeout and CRC errors even on CMD0. Resetting
1489          * it on each ios seems to solve the problem.
1490          */
1491         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1492                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1493
1494         mmiowb();
1495         spin_unlock_irqrestore(&host->lock, flags);
1496 }
1497
1498 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1499 {
1500         struct sdhci_host *host = mmc_priv(mmc);
1501
1502         sdhci_runtime_pm_get(host);
1503         sdhci_do_set_ios(host, ios);
1504         sdhci_runtime_pm_put(host);
1505 }
1506
1507 static int sdhci_check_ro(struct sdhci_host *host)
1508 {
1509         unsigned long flags;
1510         int is_readonly;
1511
1512         spin_lock_irqsave(&host->lock, flags);
1513
1514         if (host->flags & SDHCI_DEVICE_DEAD)
1515                 is_readonly = 0;
1516         else if (host->ops->get_ro)
1517                 is_readonly = host->ops->get_ro(host);
1518         else
1519                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1520                                 & SDHCI_WRITE_PROTECT);
1521
1522         spin_unlock_irqrestore(&host->lock, flags);
1523
1524         /* This quirk needs to be replaced by a callback-function later */
1525         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1526                 !is_readonly : is_readonly;
1527 }
1528
1529 #define SAMPLE_COUNT    5
1530
1531 static int sdhci_do_get_ro(struct sdhci_host *host)
1532 {
1533         int i, ro_count;
1534
1535         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1536                 return sdhci_check_ro(host);
1537
1538         ro_count = 0;
1539         for (i = 0; i < SAMPLE_COUNT; i++) {
1540                 if (sdhci_check_ro(host)) {
1541                         if (++ro_count > SAMPLE_COUNT / 2)
1542                                 return 1;
1543                 }
1544                 msleep(30);
1545         }
1546         return 0;
1547 }
1548
1549 static void sdhci_hw_reset(struct mmc_host *mmc)
1550 {
1551         struct sdhci_host *host = mmc_priv(mmc);
1552
1553         if (host->ops && host->ops->hw_reset)
1554                 host->ops->hw_reset(host);
1555 }
1556
1557 static int sdhci_get_ro(struct mmc_host *mmc)
1558 {
1559         struct sdhci_host *host = mmc_priv(mmc);
1560         int ret;
1561
1562         sdhci_runtime_pm_get(host);
1563         ret = sdhci_do_get_ro(host);
1564         sdhci_runtime_pm_put(host);
1565         return ret;
1566 }
1567
1568 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1569 {
1570         if (host->flags & SDHCI_DEVICE_DEAD)
1571                 goto out;
1572
1573         if (enable)
1574                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1575         else
1576                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1577
1578         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1579         if (host->runtime_suspended)
1580                 goto out;
1581
1582         if (enable)
1583                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1584         else
1585                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1586 out:
1587         mmiowb();
1588 }
1589
1590 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1591 {
1592         struct sdhci_host *host = mmc_priv(mmc);
1593         unsigned long flags;
1594
1595         spin_lock_irqsave(&host->lock, flags);
1596         sdhci_enable_sdio_irq_nolock(host, enable);
1597         spin_unlock_irqrestore(&host->lock, flags);
1598 }
1599
1600 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1601                                                 struct mmc_ios *ios)
1602 {
1603         u8 pwr;
1604         u16 clk, ctrl;
1605         u32 present_state;
1606
1607         /*
1608          * Signal Voltage Switching is only applicable for Host Controllers
1609          * v3.00 and above.
1610          */
1611         if (host->version < SDHCI_SPEC_300)
1612                 return 0;
1613
1614         /*
1615          * We first check whether the request is to set signalling voltage
1616          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1617          */
1618         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1619         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1620                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1621                 ctrl &= ~SDHCI_CTRL_VDD_180;
1622                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1623
1624                 /* Wait for 5ms */
1625                 usleep_range(5000, 5500);
1626
1627                 /* 3.3V regulator output should be stable within 5 ms */
1628                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1629                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1630                         return 0;
1631                 else {
1632                         pr_info(DRIVER_NAME ": Switching to 3.3V "
1633                                 "signalling voltage failed\n");
1634                         return -EIO;
1635                 }
1636         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1637                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1638                 /* Stop SDCLK */
1639                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1640                 clk &= ~SDHCI_CLOCK_CARD_EN;
1641                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1642
1643                 /* Check whether DAT[3:0] is 0000 */
1644                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1645                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1646                        SDHCI_DATA_LVL_SHIFT)) {
1647                         /*
1648                          * Enable 1.8V Signal Enable in the Host Control2
1649                          * register
1650                          */
1651                         ctrl |= SDHCI_CTRL_VDD_180;
1652                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1653
1654                         /* Wait for 5ms */
1655                         usleep_range(5000, 5500);
1656
1657                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1658                         if (ctrl & SDHCI_CTRL_VDD_180) {
1659                                 /* Provide SDCLK again and wait for 1ms*/
1660                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1661                                 clk |= SDHCI_CLOCK_CARD_EN;
1662                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1663                                 usleep_range(1000, 1500);
1664
1665                                 /*
1666                                  * If DAT[3:0] level is 1111b, then the card
1667                                  * was successfully switched to 1.8V signaling.
1668                                  */
1669                                 present_state = sdhci_readl(host,
1670                                                         SDHCI_PRESENT_STATE);
1671                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1672                                      SDHCI_DATA_LVL_MASK)
1673                                         return 0;
1674                         }
1675                 }
1676
1677                 /*
1678                  * If we are here, that means the switch to 1.8V signaling
1679                  * failed. We power cycle the card, and retry initialization
1680                  * sequence by setting S18R to 0.
1681                  */
1682                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1683                 pwr &= ~SDHCI_POWER_ON;
1684                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1685                 if (host->vmmc)
1686                         regulator_disable(host->vmmc);
1687
1688                 /* Wait for 1ms as per the spec */
1689                 usleep_range(1000, 1500);
1690                 pwr |= SDHCI_POWER_ON;
1691                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1692                 if (host->vmmc)
1693                         regulator_enable(host->vmmc);
1694
1695                 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1696                         "voltage failed, retrying with S18R set to 0\n");
1697                 return -EAGAIN;
1698         } else
1699                 /* No signal voltage switch required */
1700                 return 0;
1701 }
1702
1703 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1704         struct mmc_ios *ios)
1705 {
1706         struct sdhci_host *host = mmc_priv(mmc);
1707         int err;
1708
1709         if (host->version < SDHCI_SPEC_300)
1710                 return 0;
1711         sdhci_runtime_pm_get(host);
1712         err = sdhci_do_start_signal_voltage_switch(host, ios);
1713         sdhci_runtime_pm_put(host);
1714         return err;
1715 }
1716
1717 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1718 {
1719         struct sdhci_host *host;
1720         u16 ctrl;
1721         u32 ier;
1722         int tuning_loop_counter = MAX_TUNING_LOOP;
1723         unsigned long timeout;
1724         int err = 0;
1725         bool requires_tuning_nonuhs = false;
1726
1727         host = mmc_priv(mmc);
1728
1729         sdhci_runtime_pm_get(host);
1730         disable_irq(host->irq);
1731         spin_lock(&host->lock);
1732
1733         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1734
1735         /*
1736          * The Host Controller needs tuning only in case of SDR104 mode
1737          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1738          * Capabilities register.
1739          * If the Host Controller supports the HS200 mode then the
1740          * tuning function has to be executed.
1741          */
1742         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1743             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1744              host->flags & SDHCI_HS200_NEEDS_TUNING))
1745                 requires_tuning_nonuhs = true;
1746
1747         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1748             requires_tuning_nonuhs)
1749                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1750         else {
1751                 spin_unlock(&host->lock);
1752                 enable_irq(host->irq);
1753                 sdhci_runtime_pm_put(host);
1754                 return 0;
1755         }
1756
1757         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1758
1759         /*
1760          * As per the Host Controller spec v3.00, tuning command
1761          * generates Buffer Read Ready interrupt, so enable that.
1762          *
1763          * Note: The spec clearly says that when tuning sequence
1764          * is being performed, the controller does not generate
1765          * interrupts other than Buffer Read Ready interrupt. But
1766          * to make sure we don't hit a controller bug, we _only_
1767          * enable Buffer Read Ready interrupt here.
1768          */
1769         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1770         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1771
1772         /*
1773          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1774          * of loops reaches 40 times or a timeout of 150ms occurs.
1775          */
1776         timeout = 150;
1777         do {
1778                 struct mmc_command cmd = {0};
1779                 struct mmc_request mrq = {NULL};
1780
1781                 if (!tuning_loop_counter && !timeout)
1782                         break;
1783
1784                 cmd.opcode = opcode;
1785                 cmd.arg = 0;
1786                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1787                 cmd.retries = 0;
1788                 cmd.data = NULL;
1789                 cmd.error = 0;
1790
1791                 mrq.cmd = &cmd;
1792                 host->mrq = &mrq;
1793
1794                 /*
1795                  * In response to CMD19, the card sends 64 bytes of tuning
1796                  * block to the Host Controller. So we set the block size
1797                  * to 64 here.
1798                  */
1799                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1800                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1801                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1802                                              SDHCI_BLOCK_SIZE);
1803                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1804                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1805                                              SDHCI_BLOCK_SIZE);
1806                 } else {
1807                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1808                                      SDHCI_BLOCK_SIZE);
1809                 }
1810
1811                 /*
1812                  * The tuning block is sent by the card to the host controller.
1813                  * So we set the TRNS_READ bit in the Transfer Mode register.
1814                  * This also takes care of setting DMA Enable and Multi Block
1815                  * Select in the same register to 0.
1816                  */
1817                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1818
1819                 sdhci_send_command(host, &cmd);
1820
1821                 host->cmd = NULL;
1822                 host->mrq = NULL;
1823
1824                 spin_unlock(&host->lock);
1825                 enable_irq(host->irq);
1826
1827                 /* Wait for Buffer Read Ready interrupt */
1828                 wait_event_interruptible_timeout(host->buf_ready_int,
1829                                         (host->tuning_done == 1),
1830                                         msecs_to_jiffies(50));
1831                 disable_irq(host->irq);
1832                 spin_lock(&host->lock);
1833
1834                 if (!host->tuning_done) {
1835                         pr_info(DRIVER_NAME ": Timeout waiting for "
1836                                 "Buffer Read Ready interrupt during tuning "
1837                                 "procedure, falling back to fixed sampling "
1838                                 "clock\n");
1839                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1840                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1841                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1842                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1843
1844                         err = -EIO;
1845                         goto out;
1846                 }
1847
1848                 host->tuning_done = 0;
1849
1850                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1851                 tuning_loop_counter--;
1852                 timeout--;
1853                 mdelay(1);
1854         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1855
1856         /*
1857          * The Host Driver has exhausted the maximum number of loops allowed,
1858          * so use fixed sampling frequency.
1859          */
1860         if (!tuning_loop_counter || !timeout) {
1861                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1862                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1863         } else {
1864                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1865                         pr_info(DRIVER_NAME ": Tuning procedure"
1866                                 " failed, falling back to fixed sampling"
1867                                 " clock\n");
1868                         err = -EIO;
1869                 }
1870         }
1871
1872 out:
1873         /*
1874          * If this is the very first time we are here, we start the retuning
1875          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1876          * flag won't be set, we check this condition before actually starting
1877          * the timer.
1878          */
1879         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1880             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1881                 host->flags |= SDHCI_USING_RETUNING_TIMER;
1882                 mod_timer(&host->tuning_timer, jiffies +
1883                         host->tuning_count * HZ);
1884                 /* Tuning mode 1 limits the maximum data length to 4MB */
1885                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1886         } else {
1887                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1888                 /* Reload the new initial value for timer */
1889                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1890                         mod_timer(&host->tuning_timer, jiffies +
1891                                 host->tuning_count * HZ);
1892         }
1893
1894         /*
1895          * In case tuning fails, host controllers which support re-tuning can
1896          * try tuning again at a later time, when the re-tuning timer expires.
1897          * So for these controllers, we return 0. Since there might be other
1898          * controllers who do not have this capability, we return error for
1899          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1900          * a retuning timer to do the retuning for the card.
1901          */
1902         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
1903                 err = 0;
1904
1905         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1906         spin_unlock(&host->lock);
1907         enable_irq(host->irq);
1908         sdhci_runtime_pm_put(host);
1909
1910         return err;
1911 }
1912
1913 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1914 {
1915         u16 ctrl;
1916         unsigned long flags;
1917
1918         /* Host Controller v3.00 defines preset value registers */
1919         if (host->version < SDHCI_SPEC_300)
1920                 return;
1921
1922         spin_lock_irqsave(&host->lock, flags);
1923
1924         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1925
1926         /*
1927          * We only enable or disable Preset Value if they are not already
1928          * enabled or disabled respectively. Otherwise, we bail out.
1929          */
1930         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1931                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1932                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1933                 host->flags |= SDHCI_PV_ENABLED;
1934         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1935                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1936                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1937                 host->flags &= ~SDHCI_PV_ENABLED;
1938         }
1939
1940         spin_unlock_irqrestore(&host->lock, flags);
1941 }
1942
1943 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1944 {
1945         struct sdhci_host *host = mmc_priv(mmc);
1946
1947         sdhci_runtime_pm_get(host);
1948         sdhci_do_enable_preset_value(host, enable);
1949         sdhci_runtime_pm_put(host);
1950 }
1951
1952 static const struct mmc_host_ops sdhci_ops = {
1953         .request        = sdhci_request,
1954         .set_ios        = sdhci_set_ios,
1955         .get_ro         = sdhci_get_ro,
1956         .hw_reset       = sdhci_hw_reset,
1957         .enable_sdio_irq = sdhci_enable_sdio_irq,
1958         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1959         .execute_tuning                 = sdhci_execute_tuning,
1960         .enable_preset_value            = sdhci_enable_preset_value,
1961 };
1962
1963 /*****************************************************************************\
1964  *                                                                           *
1965  * Tasklets                                                                  *
1966  *                                                                           *
1967 \*****************************************************************************/
1968
1969 static void sdhci_tasklet_card(unsigned long param)
1970 {
1971         struct sdhci_host *host;
1972         unsigned long flags;
1973
1974         host = (struct sdhci_host*)param;
1975
1976         spin_lock_irqsave(&host->lock, flags);
1977
1978         /* Check host->mrq first in case we are runtime suspended */
1979         if (host->mrq &&
1980             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1981                 pr_err("%s: Card removed during transfer!\n",
1982                         mmc_hostname(host->mmc));
1983                 pr_err("%s: Resetting controller.\n",
1984                         mmc_hostname(host->mmc));
1985
1986                 sdhci_reset(host, SDHCI_RESET_CMD);
1987                 sdhci_reset(host, SDHCI_RESET_DATA);
1988
1989                 host->mrq->cmd->error = -ENOMEDIUM;
1990                 tasklet_schedule(&host->finish_tasklet);
1991         }
1992
1993         spin_unlock_irqrestore(&host->lock, flags);
1994
1995         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1996 }
1997
1998 static void sdhci_tasklet_finish(unsigned long param)
1999 {
2000         struct sdhci_host *host;
2001         unsigned long flags;
2002         struct mmc_request *mrq;
2003
2004         host = (struct sdhci_host*)param;
2005
2006         spin_lock_irqsave(&host->lock, flags);
2007
2008         /*
2009          * If this tasklet gets rescheduled while running, it will
2010          * be run again afterwards but without any active request.
2011          */
2012         if (!host->mrq) {
2013                 spin_unlock_irqrestore(&host->lock, flags);
2014                 return;
2015         }
2016
2017         del_timer(&host->timer);
2018
2019         mrq = host->mrq;
2020
2021         /*
2022          * The controller needs a reset of internal state machines
2023          * upon error conditions.
2024          */
2025         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2026             ((mrq->cmd && mrq->cmd->error) ||
2027                  (mrq->data && (mrq->data->error ||
2028                   (mrq->data->stop && mrq->data->stop->error))) ||
2029                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2030
2031                 /* Some controllers need this kick or reset won't work here */
2032                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2033                         unsigned int clock;
2034
2035                         /* This is to force an update */
2036                         clock = host->clock;
2037                         host->clock = 0;
2038                         sdhci_set_clock(host, clock);
2039                 }
2040
2041                 /* Spec says we should do both at the same time, but Ricoh
2042                    controllers do not like that. */
2043                 sdhci_reset(host, SDHCI_RESET_CMD);
2044                 sdhci_reset(host, SDHCI_RESET_DATA);
2045         }
2046
2047         host->mrq = NULL;
2048         host->cmd = NULL;
2049         host->data = NULL;
2050
2051 #ifndef SDHCI_USE_LEDS_CLASS
2052         sdhci_deactivate_led(host);
2053 #endif
2054
2055         mmiowb();
2056         spin_unlock_irqrestore(&host->lock, flags);
2057
2058         mmc_request_done(host->mmc, mrq);
2059         sdhci_runtime_pm_put(host);
2060 }
2061
2062 static void sdhci_timeout_timer(unsigned long data)
2063 {
2064         struct sdhci_host *host;
2065         unsigned long flags;
2066
2067         host = (struct sdhci_host*)data;
2068
2069         spin_lock_irqsave(&host->lock, flags);
2070
2071         if (host->mrq) {
2072                 pr_err("%s: Timeout waiting for hardware "
2073                         "interrupt.\n", mmc_hostname(host->mmc));
2074                 sdhci_dumpregs(host);
2075
2076                 if (host->data) {
2077                         host->data->error = -ETIMEDOUT;
2078                         sdhci_finish_data(host);
2079                 } else {
2080                         if (host->cmd)
2081                                 host->cmd->error = -ETIMEDOUT;
2082                         else
2083                                 host->mrq->cmd->error = -ETIMEDOUT;
2084
2085                         tasklet_schedule(&host->finish_tasklet);
2086                 }
2087         }
2088
2089         mmiowb();
2090         spin_unlock_irqrestore(&host->lock, flags);
2091 }
2092
2093 static void sdhci_tuning_timer(unsigned long data)
2094 {
2095         struct sdhci_host *host;
2096         unsigned long flags;
2097
2098         host = (struct sdhci_host *)data;
2099
2100         spin_lock_irqsave(&host->lock, flags);
2101
2102         host->flags |= SDHCI_NEEDS_RETUNING;
2103
2104         spin_unlock_irqrestore(&host->lock, flags);
2105 }
2106
2107 /*****************************************************************************\
2108  *                                                                           *
2109  * Interrupt handling                                                        *
2110  *                                                                           *
2111 \*****************************************************************************/
2112
2113 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2114 {
2115         BUG_ON(intmask == 0);
2116
2117         if (!host->cmd) {
2118                 pr_err("%s: Got command interrupt 0x%08x even "
2119                         "though no command operation was in progress.\n",
2120                         mmc_hostname(host->mmc), (unsigned)intmask);
2121                 sdhci_dumpregs(host);
2122                 return;
2123         }
2124
2125         if (intmask & SDHCI_INT_TIMEOUT)
2126                 host->cmd->error = -ETIMEDOUT;
2127         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2128                         SDHCI_INT_INDEX))
2129                 host->cmd->error = -EILSEQ;
2130
2131         if (host->cmd->error) {
2132                 tasklet_schedule(&host->finish_tasklet);
2133                 return;
2134         }
2135
2136         /*
2137          * The host can send and interrupt when the busy state has
2138          * ended, allowing us to wait without wasting CPU cycles.
2139          * Unfortunately this is overloaded on the "data complete"
2140          * interrupt, so we need to take some care when handling
2141          * it.
2142          *
2143          * Note: The 1.0 specification is a bit ambiguous about this
2144          *       feature so there might be some problems with older
2145          *       controllers.
2146          */
2147         if (host->cmd->flags & MMC_RSP_BUSY) {
2148                 if (host->cmd->data)
2149                         DBG("Cannot wait for busy signal when also "
2150                                 "doing a data transfer");
2151                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2152                         return;
2153
2154                 /* The controller does not support the end-of-busy IRQ,
2155                  * fall through and take the SDHCI_INT_RESPONSE */
2156         }
2157
2158         if (intmask & SDHCI_INT_RESPONSE)
2159                 sdhci_finish_command(host);
2160 }
2161
2162 #ifdef CONFIG_MMC_DEBUG
2163 static void sdhci_show_adma_error(struct sdhci_host *host)
2164 {
2165         const char *name = mmc_hostname(host->mmc);
2166         u8 *desc = host->adma_desc;
2167         __le32 *dma;
2168         __le16 *len;
2169         u8 attr;
2170
2171         sdhci_dumpregs(host);
2172
2173         while (true) {
2174                 dma = (__le32 *)(desc + 4);
2175                 len = (__le16 *)(desc + 2);
2176                 attr = *desc;
2177
2178                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2179                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2180
2181                 desc += 8;
2182
2183                 if (attr & 2)
2184                         break;
2185         }
2186 }
2187 #else
2188 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2189 #endif
2190
2191 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2192 {
2193         u32 command;
2194         BUG_ON(intmask == 0);
2195
2196         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2197         if (intmask & SDHCI_INT_DATA_AVAIL) {
2198                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2199                 if (command == MMC_SEND_TUNING_BLOCK ||
2200                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2201                         host->tuning_done = 1;
2202                         wake_up(&host->buf_ready_int);
2203                         return;
2204                 }
2205         }
2206
2207         if (!host->data) {
2208                 /*
2209                  * The "data complete" interrupt is also used to
2210                  * indicate that a busy state has ended. See comment
2211                  * above in sdhci_cmd_irq().
2212                  */
2213                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2214                         if (intmask & SDHCI_INT_DATA_END) {
2215                                 sdhci_finish_command(host);
2216                                 return;
2217                         }
2218                 }
2219
2220                 pr_err("%s: Got data interrupt 0x%08x even "
2221                         "though no data operation was in progress.\n",
2222                         mmc_hostname(host->mmc), (unsigned)intmask);
2223                 sdhci_dumpregs(host);
2224
2225                 return;
2226         }
2227
2228         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2229                 host->data->error = -ETIMEDOUT;
2230         else if (intmask & SDHCI_INT_DATA_END_BIT)
2231                 host->data->error = -EILSEQ;
2232         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2233                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2234                         != MMC_BUS_TEST_R)
2235                 host->data->error = -EILSEQ;
2236         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2237                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2238                 sdhci_show_adma_error(host);
2239                 host->data->error = -EIO;
2240         }
2241
2242         if (host->data->error)
2243                 sdhci_finish_data(host);
2244         else {
2245                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2246                         sdhci_transfer_pio(host);
2247
2248                 /*
2249                  * We currently don't do anything fancy with DMA
2250                  * boundaries, but as we can't disable the feature
2251                  * we need to at least restart the transfer.
2252                  *
2253                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2254                  * should return a valid address to continue from, but as
2255                  * some controllers are faulty, don't trust them.
2256                  */
2257                 if (intmask & SDHCI_INT_DMA_END) {
2258                         u32 dmastart, dmanow;
2259                         dmastart = sg_dma_address(host->data->sg);
2260                         dmanow = dmastart + host->data->bytes_xfered;
2261                         /*
2262                          * Force update to the next DMA block boundary.
2263                          */
2264                         dmanow = (dmanow &
2265                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2266                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2267                         host->data->bytes_xfered = dmanow - dmastart;
2268                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2269                                 " next 0x%08x\n",
2270                                 mmc_hostname(host->mmc), dmastart,
2271                                 host->data->bytes_xfered, dmanow);
2272                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2273                 }
2274
2275                 if (intmask & SDHCI_INT_DATA_END) {
2276                         if (host->cmd) {
2277                                 /*
2278                                  * Data managed to finish before the
2279                                  * command completed. Make sure we do
2280                                  * things in the proper order.
2281                                  */
2282                                 host->data_early = 1;
2283                         } else {
2284                                 sdhci_finish_data(host);
2285                         }
2286                 }
2287         }
2288 }
2289
2290 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2291 {
2292         irqreturn_t result;
2293         struct sdhci_host *host = dev_id;
2294         u32 intmask, unexpected = 0;
2295         int cardint = 0, max_loops = 16;
2296
2297         spin_lock(&host->lock);
2298
2299         if (host->runtime_suspended) {
2300                 spin_unlock(&host->lock);
2301                 pr_warning("%s: got irq while runtime suspended\n",
2302                        mmc_hostname(host->mmc));
2303                 return IRQ_HANDLED;
2304         }
2305
2306         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2307
2308         if (!intmask || intmask == 0xffffffff) {
2309                 result = IRQ_NONE;
2310                 goto out;
2311         }
2312
2313 again:
2314         DBG("*** %s got interrupt: 0x%08x\n",
2315                 mmc_hostname(host->mmc), intmask);
2316
2317         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2318                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2319                               SDHCI_CARD_PRESENT;
2320
2321                 /*
2322                  * There is a observation on i.mx esdhc.  INSERT bit will be
2323                  * immediately set again when it gets cleared, if a card is
2324                  * inserted.  We have to mask the irq to prevent interrupt
2325                  * storm which will freeze the system.  And the REMOVE gets
2326                  * the same situation.
2327                  *
2328                  * More testing are needed here to ensure it works for other
2329                  * platforms though.
2330                  */
2331                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2332                                                 SDHCI_INT_CARD_REMOVE);
2333                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2334                                                   SDHCI_INT_CARD_INSERT);
2335
2336                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2337                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2338                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2339                 tasklet_schedule(&host->card_tasklet);
2340         }
2341
2342         if (intmask & SDHCI_INT_CMD_MASK) {
2343                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2344                         SDHCI_INT_STATUS);
2345                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2346         }
2347
2348         if (intmask & SDHCI_INT_DATA_MASK) {
2349                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2350                         SDHCI_INT_STATUS);
2351                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2352         }
2353
2354         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2355
2356         intmask &= ~SDHCI_INT_ERROR;
2357
2358         if (intmask & SDHCI_INT_BUS_POWER) {
2359                 pr_err("%s: Card is consuming too much power!\n",
2360                         mmc_hostname(host->mmc));
2361                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2362         }
2363
2364         intmask &= ~SDHCI_INT_BUS_POWER;
2365
2366         if (intmask & SDHCI_INT_CARD_INT)
2367                 cardint = 1;
2368
2369         intmask &= ~SDHCI_INT_CARD_INT;
2370
2371         if (intmask) {
2372                 unexpected |= intmask;
2373                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2374         }
2375
2376         result = IRQ_HANDLED;
2377
2378         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2379         if (intmask && --max_loops)
2380                 goto again;
2381 out:
2382         spin_unlock(&host->lock);
2383
2384         if (unexpected) {
2385                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2386                            mmc_hostname(host->mmc), unexpected);
2387                 sdhci_dumpregs(host);
2388         }
2389         /*
2390          * We have to delay this as it calls back into the driver.
2391          */
2392         if (cardint)
2393                 mmc_signal_sdio_irq(host->mmc);
2394
2395         return result;
2396 }
2397
2398 /*****************************************************************************\
2399  *                                                                           *
2400  * Suspend/resume                                                            *
2401  *                                                                           *
2402 \*****************************************************************************/
2403
2404 #ifdef CONFIG_PM
2405
2406 int sdhci_suspend_host(struct sdhci_host *host)
2407 {
2408         int ret;
2409
2410         if (host->ops->platform_suspend)
2411                 host->ops->platform_suspend(host);
2412
2413         sdhci_disable_card_detection(host);
2414
2415         /* Disable tuning since we are suspending */
2416         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2417                 del_timer_sync(&host->tuning_timer);
2418                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2419         }
2420
2421         ret = mmc_suspend_host(host->mmc);
2422         if (ret) {
2423                 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2424                         host->flags |= SDHCI_NEEDS_RETUNING;
2425                         mod_timer(&host->tuning_timer, jiffies +
2426                                         host->tuning_count * HZ);
2427                 }
2428
2429                 sdhci_enable_card_detection(host);
2430
2431                 return ret;
2432         }
2433
2434         free_irq(host->irq, host);
2435
2436         return ret;
2437 }
2438
2439 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2440
2441 int sdhci_resume_host(struct sdhci_host *host)
2442 {
2443         int ret;
2444
2445         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2446                 if (host->ops->enable_dma)
2447                         host->ops->enable_dma(host);
2448         }
2449
2450         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2451                           mmc_hostname(host->mmc), host);
2452         if (ret)
2453                 return ret;
2454
2455         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2456             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2457                 /* Card keeps power but host controller does not */
2458                 sdhci_init(host, 0);
2459                 host->pwr = 0;
2460                 host->clock = 0;
2461                 sdhci_do_set_ios(host, &host->mmc->ios);
2462         } else {
2463                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2464                 mmiowb();
2465         }
2466
2467         ret = mmc_resume_host(host->mmc);
2468         sdhci_enable_card_detection(host);
2469
2470         if (host->ops->platform_resume)
2471                 host->ops->platform_resume(host);
2472
2473         /* Set the re-tuning expiration flag */
2474         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2475                 host->flags |= SDHCI_NEEDS_RETUNING;
2476
2477         return ret;
2478 }
2479
2480 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2481
2482 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2483 {
2484         u8 val;
2485         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2486         val |= SDHCI_WAKE_ON_INT;
2487         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2488 }
2489
2490 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2491
2492 #endif /* CONFIG_PM */
2493
2494 #ifdef CONFIG_PM_RUNTIME
2495
2496 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2497 {
2498         return pm_runtime_get_sync(host->mmc->parent);
2499 }
2500
2501 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2502 {
2503         pm_runtime_mark_last_busy(host->mmc->parent);
2504         return pm_runtime_put_autosuspend(host->mmc->parent);
2505 }
2506
2507 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2508 {
2509         unsigned long flags;
2510         int ret = 0;
2511
2512         /* Disable tuning since we are suspending */
2513         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2514                 del_timer_sync(&host->tuning_timer);
2515                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2516         }
2517
2518         spin_lock_irqsave(&host->lock, flags);
2519         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2520         spin_unlock_irqrestore(&host->lock, flags);
2521
2522         synchronize_irq(host->irq);
2523
2524         spin_lock_irqsave(&host->lock, flags);
2525         host->runtime_suspended = true;
2526         spin_unlock_irqrestore(&host->lock, flags);
2527
2528         return ret;
2529 }
2530 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2531
2532 int sdhci_runtime_resume_host(struct sdhci_host *host)
2533 {
2534         unsigned long flags;
2535         int ret = 0, host_flags = host->flags;
2536
2537         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2538                 if (host->ops->enable_dma)
2539                         host->ops->enable_dma(host);
2540         }
2541
2542         sdhci_init(host, 0);
2543
2544         /* Force clock and power re-program */
2545         host->pwr = 0;
2546         host->clock = 0;
2547         sdhci_do_set_ios(host, &host->mmc->ios);
2548
2549         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2550         if (host_flags & SDHCI_PV_ENABLED)
2551                 sdhci_do_enable_preset_value(host, true);
2552
2553         /* Set the re-tuning expiration flag */
2554         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2555                 host->flags |= SDHCI_NEEDS_RETUNING;
2556
2557         spin_lock_irqsave(&host->lock, flags);
2558
2559         host->runtime_suspended = false;
2560
2561         /* Enable SDIO IRQ */
2562         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2563                 sdhci_enable_sdio_irq_nolock(host, true);
2564
2565         /* Enable Card Detection */
2566         sdhci_enable_card_detection(host);
2567
2568         spin_unlock_irqrestore(&host->lock, flags);
2569
2570         return ret;
2571 }
2572 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2573
2574 #endif
2575
2576 /*****************************************************************************\
2577  *                                                                           *
2578  * Device allocation/registration                                            *
2579  *                                                                           *
2580 \*****************************************************************************/
2581
2582 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2583         size_t priv_size)
2584 {
2585         struct mmc_host *mmc;
2586         struct sdhci_host *host;
2587
2588         WARN_ON(dev == NULL);
2589
2590         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2591         if (!mmc)
2592                 return ERR_PTR(-ENOMEM);
2593
2594         host = mmc_priv(mmc);
2595         host->mmc = mmc;
2596
2597         return host;
2598 }
2599
2600 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2601
2602 int sdhci_add_host(struct sdhci_host *host)
2603 {
2604         struct mmc_host *mmc;
2605         u32 caps[2] = {0, 0};
2606         u32 max_current_caps;
2607         unsigned int ocr_avail;
2608         int ret;
2609
2610         WARN_ON(host == NULL);
2611         if (host == NULL)
2612                 return -EINVAL;
2613
2614         mmc = host->mmc;
2615
2616         if (debug_quirks)
2617                 host->quirks = debug_quirks;
2618         if (debug_quirks2)
2619                 host->quirks2 = debug_quirks2;
2620
2621         sdhci_reset(host, SDHCI_RESET_ALL);
2622
2623         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2624         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2625                                 >> SDHCI_SPEC_VER_SHIFT;
2626         if (host->version > SDHCI_SPEC_300) {
2627                 pr_err("%s: Unknown controller version (%d). "
2628                         "You may experience problems.\n", mmc_hostname(mmc),
2629                         host->version);
2630         }
2631
2632         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2633                 sdhci_readl(host, SDHCI_CAPABILITIES);
2634
2635         if (host->version >= SDHCI_SPEC_300)
2636                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2637                         host->caps1 :
2638                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2639
2640         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2641                 host->flags |= SDHCI_USE_SDMA;
2642         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2643                 DBG("Controller doesn't have SDMA capability\n");
2644         else
2645                 host->flags |= SDHCI_USE_SDMA;
2646
2647         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2648                 (host->flags & SDHCI_USE_SDMA)) {
2649                 DBG("Disabling DMA as it is marked broken\n");
2650                 host->flags &= ~SDHCI_USE_SDMA;
2651         }
2652
2653         if ((host->version >= SDHCI_SPEC_200) &&
2654                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2655                 host->flags |= SDHCI_USE_ADMA;
2656
2657         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2658                 (host->flags & SDHCI_USE_ADMA)) {
2659                 DBG("Disabling ADMA as it is marked broken\n");
2660                 host->flags &= ~SDHCI_USE_ADMA;
2661         }
2662
2663         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2664                 if (host->ops->enable_dma) {
2665                         if (host->ops->enable_dma(host)) {
2666                                 pr_warning("%s: No suitable DMA "
2667                                         "available. Falling back to PIO.\n",
2668                                         mmc_hostname(mmc));
2669                                 host->flags &=
2670                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2671                         }
2672                 }
2673         }
2674
2675         if (host->flags & SDHCI_USE_ADMA) {
2676                 /*
2677                  * We need to allocate descriptors for all sg entries
2678                  * (128) and potentially one alignment transfer for
2679                  * each of those entries.
2680                  */
2681                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2682                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2683                 if (!host->adma_desc || !host->align_buffer) {
2684                         kfree(host->adma_desc);
2685                         kfree(host->align_buffer);
2686                         pr_warning("%s: Unable to allocate ADMA "
2687                                 "buffers. Falling back to standard DMA.\n",
2688                                 mmc_hostname(mmc));
2689                         host->flags &= ~SDHCI_USE_ADMA;
2690                 }
2691         }
2692
2693         /*
2694          * If we use DMA, then it's up to the caller to set the DMA
2695          * mask, but PIO does not need the hw shim so we set a new
2696          * mask here in that case.
2697          */
2698         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2699                 host->dma_mask = DMA_BIT_MASK(64);
2700                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2701         }
2702
2703         if (host->version >= SDHCI_SPEC_300)
2704                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2705                         >> SDHCI_CLOCK_BASE_SHIFT;
2706         else
2707                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2708                         >> SDHCI_CLOCK_BASE_SHIFT;
2709
2710         host->max_clk *= 1000000;
2711         if (host->max_clk == 0 || host->quirks &
2712                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2713                 if (!host->ops->get_max_clock) {
2714                         pr_err("%s: Hardware doesn't specify base clock "
2715                                "frequency.\n", mmc_hostname(mmc));
2716                         return -ENODEV;
2717                 }
2718                 host->max_clk = host->ops->get_max_clock(host);
2719         }
2720
2721         /*
2722          * In case of Host Controller v3.00, find out whether clock
2723          * multiplier is supported.
2724          */
2725         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2726                         SDHCI_CLOCK_MUL_SHIFT;
2727
2728         /*
2729          * In case the value in Clock Multiplier is 0, then programmable
2730          * clock mode is not supported, otherwise the actual clock
2731          * multiplier is one more than the value of Clock Multiplier
2732          * in the Capabilities Register.
2733          */
2734         if (host->clk_mul)
2735                 host->clk_mul += 1;
2736
2737         /*
2738          * Set host parameters.
2739          */
2740         mmc->ops = &sdhci_ops;
2741         mmc->f_max = host->max_clk;
2742         if (host->ops->get_min_clock)
2743                 mmc->f_min = host->ops->get_min_clock(host);
2744         else if (host->version >= SDHCI_SPEC_300) {
2745                 if (host->clk_mul) {
2746                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2747                         mmc->f_max = host->max_clk * host->clk_mul;
2748                 } else
2749                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2750         } else
2751                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2752
2753         host->timeout_clk =
2754                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2755         if (host->timeout_clk == 0) {
2756                 if (host->ops->get_timeout_clock) {
2757                         host->timeout_clk = host->ops->get_timeout_clock(host);
2758                 } else if (!(host->quirks &
2759                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2760                         pr_err("%s: Hardware doesn't specify timeout clock "
2761                                "frequency.\n", mmc_hostname(mmc));
2762                         return -ENODEV;
2763                 }
2764         }
2765         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2766                 host->timeout_clk *= 1000;
2767
2768         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2769                 host->timeout_clk = mmc->f_max / 1000;
2770
2771         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2772
2773         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2774
2775         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2776                 host->flags |= SDHCI_AUTO_CMD12;
2777
2778         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2779         if ((host->version >= SDHCI_SPEC_300) &&
2780             ((host->flags & SDHCI_USE_ADMA) ||
2781              !(host->flags & SDHCI_USE_SDMA))) {
2782                 host->flags |= SDHCI_AUTO_CMD23;
2783                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2784         } else {
2785                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2786         }
2787
2788         /*
2789          * A controller may support 8-bit width, but the board itself
2790          * might not have the pins brought out.  Boards that support
2791          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2792          * their platform code before calling sdhci_add_host(), and we
2793          * won't assume 8-bit width for hosts without that CAP.
2794          */
2795         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2796                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2797
2798         if (caps[0] & SDHCI_CAN_DO_HISPD)
2799                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2800
2801         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2802             !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2803                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2804
2805         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2806         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2807                        SDHCI_SUPPORT_DDR50))
2808                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2809
2810         /* SDR104 supports also implies SDR50 support */
2811         if (caps[1] & SDHCI_SUPPORT_SDR104)
2812                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2813         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2814                 mmc->caps |= MMC_CAP_UHS_SDR50;
2815
2816         if (caps[1] & SDHCI_SUPPORT_DDR50)
2817                 mmc->caps |= MMC_CAP_UHS_DDR50;
2818
2819         /* Does the host need tuning for SDR50? */
2820         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2821                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2822
2823         /* Does the host need tuning for HS200? */
2824         if (mmc->caps2 & MMC_CAP2_HS200)
2825                 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2826
2827         /* Driver Type(s) (A, C, D) supported by the host */
2828         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2829                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2830         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2831                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2832         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2833                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2834
2835         /*
2836          * If Power Off Notify capability is enabled by the host,
2837          * set notify to short power off notify timeout value.
2838          */
2839         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2840                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2841         else
2842                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2843
2844         /* Initial value for re-tuning timer count */
2845         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2846                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2847
2848         /*
2849          * In case Re-tuning Timer is not disabled, the actual value of
2850          * re-tuning timer will be 2 ^ (n - 1).
2851          */
2852         if (host->tuning_count)
2853                 host->tuning_count = 1 << (host->tuning_count - 1);
2854
2855         /* Re-tuning mode supported by the Host Controller */
2856         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2857                              SDHCI_RETUNING_MODE_SHIFT;
2858
2859         ocr_avail = 0;
2860
2861         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2862         if (IS_ERR(host->vmmc)) {
2863                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2864                 host->vmmc = NULL;
2865         }
2866
2867 #ifdef CONFIG_REGULATOR
2868         if (host->vmmc) {
2869                 ret = regulator_is_supported_voltage(host->vmmc, 3300000,
2870                         3300000);
2871                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2872                         caps[0] &= ~SDHCI_CAN_VDD_330;
2873                 ret = regulator_is_supported_voltage(host->vmmc, 3000000,
2874                         3000000);
2875                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2876                         caps[0] &= ~SDHCI_CAN_VDD_300;
2877                 ret = regulator_is_supported_voltage(host->vmmc, 1800000,
2878                         1800000);
2879                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2880                         caps[0] &= ~SDHCI_CAN_VDD_180;
2881         }
2882 #endif /* CONFIG_REGULATOR */
2883
2884         /*
2885          * According to SD Host Controller spec v3.00, if the Host System
2886          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2887          * the value is meaningful only if Voltage Support in the Capabilities
2888          * register is set. The actual current value is 4 times the register
2889          * value.
2890          */
2891         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2892         if (!max_current_caps && host->vmmc) {
2893                 u32 curr = regulator_get_current_limit(host->vmmc);
2894                 if (curr > 0) {
2895
2896                         /* convert to SDHCI_MAX_CURRENT format */
2897                         curr = curr/1000;  /* convert to mA */
2898                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2899
2900                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2901                         max_current_caps =
2902                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2903                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
2904                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
2905                 }
2906         }
2907
2908         if (caps[0] & SDHCI_CAN_VDD_330) {
2909                 int max_current_330;
2910
2911                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2912
2913                 max_current_330 = ((max_current_caps &
2914                                    SDHCI_MAX_CURRENT_330_MASK) >>
2915                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2916                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2917
2918                 if (max_current_330 > 150)
2919                         mmc->caps |= MMC_CAP_SET_XPC_330;
2920         }
2921         if (caps[0] & SDHCI_CAN_VDD_300) {
2922                 int max_current_300;
2923
2924                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2925
2926                 max_current_300 = ((max_current_caps &
2927                                    SDHCI_MAX_CURRENT_300_MASK) >>
2928                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2929                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2930
2931                 if (max_current_300 > 150)
2932                         mmc->caps |= MMC_CAP_SET_XPC_300;
2933         }
2934         if (caps[0] & SDHCI_CAN_VDD_180) {
2935                 int max_current_180;
2936
2937                 ocr_avail |= MMC_VDD_165_195;
2938
2939                 max_current_180 = ((max_current_caps &
2940                                    SDHCI_MAX_CURRENT_180_MASK) >>
2941                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2942                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2943
2944                 if (max_current_180 > 150)
2945                         mmc->caps |= MMC_CAP_SET_XPC_180;
2946
2947                 /* Maximum current capabilities of the host at 1.8V */
2948                 if (max_current_180 >= 800)
2949                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2950                 else if (max_current_180 >= 600)
2951                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2952                 else if (max_current_180 >= 400)
2953                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2954                 else if (max_current_180 >= 200)
2955                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2956         }
2957
2958         mmc->ocr_avail = ocr_avail;
2959         mmc->ocr_avail_sdio = ocr_avail;
2960         if (host->ocr_avail_sdio)
2961                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2962         mmc->ocr_avail_sd = ocr_avail;
2963         if (host->ocr_avail_sd)
2964                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2965         else /* normal SD controllers don't support 1.8V */
2966                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2967         mmc->ocr_avail_mmc = ocr_avail;
2968         if (host->ocr_avail_mmc)
2969                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2970
2971         if (mmc->ocr_avail == 0) {
2972                 pr_err("%s: Hardware doesn't report any "
2973                         "support voltages.\n", mmc_hostname(mmc));
2974                 return -ENODEV;
2975         }
2976
2977         spin_lock_init(&host->lock);
2978
2979         /*
2980          * Maximum number of segments. Depends on if the hardware
2981          * can do scatter/gather or not.
2982          */
2983         if (host->flags & SDHCI_USE_ADMA)
2984                 mmc->max_segs = 128;
2985         else if (host->flags & SDHCI_USE_SDMA)
2986                 mmc->max_segs = 1;
2987         else /* PIO */
2988                 mmc->max_segs = 128;
2989
2990         /*
2991          * Maximum number of sectors in one transfer. Limited by DMA boundary
2992          * size (512KiB).
2993          */
2994         mmc->max_req_size = 524288;
2995
2996         /*
2997          * Maximum segment size. Could be one segment with the maximum number
2998          * of bytes. When doing hardware scatter/gather, each entry cannot
2999          * be larger than 64 KiB though.
3000          */
3001         if (host->flags & SDHCI_USE_ADMA) {
3002                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3003                         mmc->max_seg_size = 65535;
3004                 else
3005                         mmc->max_seg_size = 65536;
3006         } else {
3007                 mmc->max_seg_size = mmc->max_req_size;
3008         }
3009
3010         /*
3011          * Maximum block size. This varies from controller to controller and
3012          * is specified in the capabilities register.
3013          */
3014         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3015                 mmc->max_blk_size = 2;
3016         } else {
3017                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3018                                 SDHCI_MAX_BLOCK_SHIFT;
3019                 if (mmc->max_blk_size >= 3) {
3020                         pr_warning("%s: Invalid maximum block size, "
3021                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3022                         mmc->max_blk_size = 0;
3023                 }
3024         }
3025
3026         mmc->max_blk_size = 512 << mmc->max_blk_size;
3027
3028         /*
3029          * Maximum block count.
3030          */
3031         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3032
3033         /*
3034          * Init tasklets.
3035          */
3036         tasklet_init(&host->card_tasklet,
3037                 sdhci_tasklet_card, (unsigned long)host);
3038         tasklet_init(&host->finish_tasklet,
3039                 sdhci_tasklet_finish, (unsigned long)host);
3040
3041         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3042
3043         if (host->version >= SDHCI_SPEC_300) {
3044                 init_waitqueue_head(&host->buf_ready_int);
3045
3046                 /* Initialize re-tuning timer */
3047                 init_timer(&host->tuning_timer);
3048                 host->tuning_timer.data = (unsigned long)host;
3049                 host->tuning_timer.function = sdhci_tuning_timer;
3050         }
3051
3052         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3053                 mmc_hostname(mmc), host);
3054         if (ret) {
3055                 pr_err("%s: Failed to request IRQ %d: %d\n",
3056                        mmc_hostname(mmc), host->irq, ret);
3057                 goto untasklet;
3058         }
3059
3060         sdhci_init(host, 0);
3061
3062 #ifdef CONFIG_MMC_DEBUG
3063         sdhci_dumpregs(host);
3064 #endif
3065
3066 #ifdef SDHCI_USE_LEDS_CLASS
3067         snprintf(host->led_name, sizeof(host->led_name),
3068                 "%s::", mmc_hostname(mmc));
3069         host->led.name = host->led_name;
3070         host->led.brightness = LED_OFF;
3071         host->led.default_trigger = mmc_hostname(mmc);
3072         host->led.brightness_set = sdhci_led_control;
3073
3074         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3075         if (ret) {
3076                 pr_err("%s: Failed to register LED device: %d\n",
3077                        mmc_hostname(mmc), ret);
3078                 goto reset;
3079         }
3080 #endif
3081
3082         mmiowb();
3083
3084         mmc_add_host(mmc);
3085
3086         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3087                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3088                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3089                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3090
3091         sdhci_enable_card_detection(host);
3092
3093         return 0;
3094
3095 #ifdef SDHCI_USE_LEDS_CLASS
3096 reset:
3097         sdhci_reset(host, SDHCI_RESET_ALL);
3098         free_irq(host->irq, host);
3099 #endif
3100 untasklet:
3101         tasklet_kill(&host->card_tasklet);
3102         tasklet_kill(&host->finish_tasklet);
3103
3104         return ret;
3105 }
3106
3107 EXPORT_SYMBOL_GPL(sdhci_add_host);
3108
3109 void sdhci_remove_host(struct sdhci_host *host, int dead)
3110 {
3111         unsigned long flags;
3112
3113         if (dead) {
3114                 spin_lock_irqsave(&host->lock, flags);
3115
3116                 host->flags |= SDHCI_DEVICE_DEAD;
3117
3118                 if (host->mrq) {
3119                         pr_err("%s: Controller removed during "
3120                                 " transfer!\n", mmc_hostname(host->mmc));
3121
3122                         host->mrq->cmd->error = -ENOMEDIUM;
3123                         tasklet_schedule(&host->finish_tasklet);
3124                 }
3125
3126                 spin_unlock_irqrestore(&host->lock, flags);
3127         }
3128
3129         sdhci_disable_card_detection(host);
3130
3131         mmc_remove_host(host->mmc);
3132
3133 #ifdef SDHCI_USE_LEDS_CLASS
3134         led_classdev_unregister(&host->led);
3135 #endif
3136
3137         if (!dead)
3138                 sdhci_reset(host, SDHCI_RESET_ALL);
3139
3140         free_irq(host->irq, host);
3141
3142         del_timer_sync(&host->timer);
3143
3144         tasklet_kill(&host->card_tasklet);
3145         tasklet_kill(&host->finish_tasklet);
3146
3147         if (host->vmmc)
3148                 regulator_put(host->vmmc);
3149
3150         kfree(host->adma_desc);
3151         kfree(host->align_buffer);
3152
3153         host->adma_desc = NULL;
3154         host->align_buffer = NULL;
3155 }
3156
3157 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3158
3159 void sdhci_free_host(struct sdhci_host *host)
3160 {
3161         mmc_free_host(host->mmc);
3162 }
3163
3164 EXPORT_SYMBOL_GPL(sdhci_free_host);
3165
3166 /*****************************************************************************\
3167  *                                                                           *
3168  * Driver init/exit                                                          *
3169  *                                                                           *
3170 \*****************************************************************************/
3171
3172 static int __init sdhci_drv_init(void)
3173 {
3174         pr_info(DRIVER_NAME
3175                 ": Secure Digital Host Controller Interface driver\n");
3176         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3177
3178         return 0;
3179 }
3180
3181 static void __exit sdhci_drv_exit(void)
3182 {
3183 }
3184
3185 module_init(sdhci_drv_init);
3186 module_exit(sdhci_drv_exit);
3187
3188 module_param(debug_quirks, uint, 0444);
3189 module_param(debug_quirks2, uint, 0444);
3190
3191 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3192 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3193 MODULE_LICENSE("GPL");
3194
3195 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3196 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");