2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
34 #define DRIVER_NAME "sdhci"
36 #define DBG(f, x...) \
37 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
40 defined(CONFIG_MMC_SDHCI_MODULE))
41 #define SDHCI_USE_LEDS_CLASS
44 #define MAX_TUNING_LOOP 40
46 static unsigned int debug_quirks = 0;
47 static unsigned int debug_quirks2;
49 static void sdhci_finish_data(struct sdhci_host *);
51 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
52 static void sdhci_finish_command(struct sdhci_host *);
53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54 static void sdhci_tuning_timer(unsigned long data);
56 #ifdef CONFIG_PM_RUNTIME
57 static int sdhci_runtime_pm_get(struct sdhci_host *host);
58 static int sdhci_runtime_pm_put(struct sdhci_host *host);
60 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70 static void sdhci_dumpregs(struct sdhci_host *host)
72 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
73 mmc_hostname(host->mmc));
75 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
76 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77 sdhci_readw(host, SDHCI_HOST_VERSION));
78 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
79 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80 sdhci_readw(host, SDHCI_BLOCK_COUNT));
81 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
82 sdhci_readl(host, SDHCI_ARGUMENT),
83 sdhci_readw(host, SDHCI_TRANSFER_MODE));
84 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
85 sdhci_readl(host, SDHCI_PRESENT_STATE),
86 sdhci_readb(host, SDHCI_HOST_CONTROL));
87 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
88 sdhci_readb(host, SDHCI_POWER_CONTROL),
89 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
90 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
91 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
93 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
94 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95 sdhci_readl(host, SDHCI_INT_STATUS));
96 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
97 sdhci_readl(host, SDHCI_INT_ENABLE),
98 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
99 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
100 sdhci_readw(host, SDHCI_ACMD12_ERR),
101 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
102 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
103 sdhci_readl(host, SDHCI_CAPABILITIES),
104 sdhci_readl(host, SDHCI_CAPABILITIES_1));
105 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
106 sdhci_readw(host, SDHCI_COMMAND),
107 sdhci_readl(host, SDHCI_MAX_CURRENT));
108 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
109 sdhci_readw(host, SDHCI_HOST_CONTROL2));
111 if (host->flags & SDHCI_USE_ADMA)
112 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
113 readl(host->ioaddr + SDHCI_ADMA_ERROR),
114 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
116 pr_debug(DRIVER_NAME ": ===========================================\n");
119 /*****************************************************************************\
121 * Low level functions *
123 \*****************************************************************************/
125 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
129 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
132 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
133 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
136 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
138 sdhci_clear_set_irqs(host, 0, irqs);
141 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
143 sdhci_clear_set_irqs(host, irqs, 0);
146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
159 sdhci_unmask_irqs(host, irqs);
161 sdhci_mask_irqs(host, irqs);
164 static void sdhci_enable_card_detection(struct sdhci_host *host)
166 sdhci_set_card_detection(host, true);
169 static void sdhci_disable_card_detection(struct sdhci_host *host)
171 sdhci_set_card_detection(host, false);
174 static void sdhci_reset(struct sdhci_host *host, u8 mask)
176 unsigned long timeout;
177 u32 uninitialized_var(ier);
179 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
180 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
185 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
186 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
188 if (host->ops->platform_reset_enter)
189 host->ops->platform_reset_enter(host, mask);
191 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
193 if (mask & SDHCI_RESET_ALL)
196 /* Wait max 100 ms */
199 /* hw clears the bit when it's done */
200 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
202 pr_err("%s: Reset 0x%x never completed.\n",
203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
211 if (host->ops->platform_reset_exit)
212 host->ops->platform_reset_exit(host, mask);
214 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
215 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
219 host->ops->enable_dma(host);
223 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225 static void sdhci_init(struct sdhci_host *host, int soft)
228 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
230 sdhci_reset(host, SDHCI_RESET_ALL);
232 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
233 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
236 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
239 /* force clock reconfiguration */
241 sdhci_set_ios(host->mmc, &host->mmc->ios);
245 static void sdhci_reinit(struct sdhci_host *host)
249 * Retuning stuffs are affected by different cards inserted and only
250 * applicable to UHS-I cards. So reset these fields to their initial
251 * value when card is removed.
253 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
254 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
256 del_timer_sync(&host->tuning_timer);
257 host->flags &= ~SDHCI_NEEDS_RETUNING;
258 host->mmc->max_blk_count =
259 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
261 sdhci_enable_card_detection(host);
264 static void sdhci_activate_led(struct sdhci_host *host)
268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
269 ctrl |= SDHCI_CTRL_LED;
270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
273 static void sdhci_deactivate_led(struct sdhci_host *host)
277 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
278 ctrl &= ~SDHCI_CTRL_LED;
279 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
282 #ifdef SDHCI_USE_LEDS_CLASS
283 static void sdhci_led_control(struct led_classdev *led,
284 enum led_brightness brightness)
286 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
289 spin_lock_irqsave(&host->lock, flags);
291 if (host->runtime_suspended)
294 if (brightness == LED_OFF)
295 sdhci_deactivate_led(host);
297 sdhci_activate_led(host);
299 spin_unlock_irqrestore(&host->lock, flags);
303 /*****************************************************************************\
307 \*****************************************************************************/
309 static void sdhci_read_block_pio(struct sdhci_host *host)
312 size_t blksize, len, chunk;
313 u32 uninitialized_var(scratch);
316 DBG("PIO reading\n");
318 blksize = host->data->blksz;
321 local_irq_save(flags);
324 if (!sg_miter_next(&host->sg_miter))
327 len = min(host->sg_miter.length, blksize);
330 host->sg_miter.consumed = len;
332 buf = host->sg_miter.addr;
336 scratch = sdhci_readl(host, SDHCI_BUFFER);
340 *buf = scratch & 0xFF;
349 sg_miter_stop(&host->sg_miter);
351 local_irq_restore(flags);
354 static void sdhci_write_block_pio(struct sdhci_host *host)
357 size_t blksize, len, chunk;
361 DBG("PIO writing\n");
363 blksize = host->data->blksz;
367 local_irq_save(flags);
370 if (!sg_miter_next(&host->sg_miter))
373 len = min(host->sg_miter.length, blksize);
376 host->sg_miter.consumed = len;
378 buf = host->sg_miter.addr;
381 scratch |= (u32)*buf << (chunk * 8);
387 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
388 sdhci_writel(host, scratch, SDHCI_BUFFER);
395 sg_miter_stop(&host->sg_miter);
397 local_irq_restore(flags);
400 static void sdhci_transfer_pio(struct sdhci_host *host)
406 if (host->blocks == 0)
409 if (host->data->flags & MMC_DATA_READ)
410 mask = SDHCI_DATA_AVAILABLE;
412 mask = SDHCI_SPACE_AVAILABLE;
415 * Some controllers (JMicron JMB38x) mess up the buffer bits
416 * for transfers < 4 bytes. As long as it is just one block,
417 * we can ignore the bits.
419 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
420 (host->data->blocks == 1))
423 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
424 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
427 if (host->data->flags & MMC_DATA_READ)
428 sdhci_read_block_pio(host);
430 sdhci_write_block_pio(host);
433 if (host->blocks == 0)
437 DBG("PIO transfer complete.\n");
440 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
442 local_irq_save(*flags);
443 return kmap_atomic(sg_page(sg)) + sg->offset;
446 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
448 kunmap_atomic(buffer);
449 local_irq_restore(*flags);
452 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
454 __le32 *dataddr = (__le32 __force *)(desc + 4);
455 __le16 *cmdlen = (__le16 __force *)desc;
457 /* SDHCI specification says ADMA descriptors should be 4 byte
458 * aligned, so using 16 or 32bit operations should be safe. */
460 cmdlen[0] = cpu_to_le16(cmd);
461 cmdlen[1] = cpu_to_le16(len);
463 dataddr[0] = cpu_to_le32(addr);
466 static int sdhci_adma_table_pre(struct sdhci_host *host,
467 struct mmc_data *data)
474 dma_addr_t align_addr;
477 struct scatterlist *sg;
483 * The spec does not specify endianness of descriptor table.
484 * We currently guess that it is LE.
487 if (data->flags & MMC_DATA_READ)
488 direction = DMA_FROM_DEVICE;
490 direction = DMA_TO_DEVICE;
493 * The ADMA descriptor table is mapped further down as we
494 * need to fill it with data first.
497 host->align_addr = dma_map_single(mmc_dev(host->mmc),
498 host->align_buffer, 128 * 4, direction);
499 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
501 BUG_ON(host->align_addr & 0x3);
503 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
504 data->sg, data->sg_len, direction);
505 if (host->sg_count == 0)
508 desc = host->adma_desc;
509 align = host->align_buffer;
511 align_addr = host->align_addr;
513 for_each_sg(data->sg, sg, host->sg_count, i) {
514 addr = sg_dma_address(sg);
515 len = sg_dma_len(sg);
518 * The SDHCI specification states that ADMA
519 * addresses must be 32-bit aligned. If they
520 * aren't, then we use a bounce buffer for
521 * the (up to three) bytes that screw up the
524 offset = (4 - (addr & 0x3)) & 0x3;
526 if (data->flags & MMC_DATA_WRITE) {
527 buffer = sdhci_kmap_atomic(sg, &flags);
528 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
529 memcpy(align, buffer, offset);
530 sdhci_kunmap_atomic(buffer, &flags);
534 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
536 BUG_ON(offset > 65536);
550 sdhci_set_adma_desc(desc, addr, len, 0x21);
554 * If this triggers then we have a calculation bug
557 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
562 * Mark the last descriptor as the terminating descriptor
564 if (desc != host->adma_desc) {
566 desc[0] |= 0x2; /* end */
570 * Add a terminating entry.
573 /* nop, end, valid */
574 sdhci_set_adma_desc(desc, 0, 0, 0x3);
578 * Resync align buffer as we might have changed it.
580 if (data->flags & MMC_DATA_WRITE) {
581 dma_sync_single_for_device(mmc_dev(host->mmc),
582 host->align_addr, 128 * 4, direction);
585 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
586 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
587 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
589 BUG_ON(host->adma_addr & 0x3);
594 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
595 data->sg_len, direction);
597 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
603 static void sdhci_adma_table_post(struct sdhci_host *host,
604 struct mmc_data *data)
608 struct scatterlist *sg;
614 if (data->flags & MMC_DATA_READ)
615 direction = DMA_FROM_DEVICE;
617 direction = DMA_TO_DEVICE;
619 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
620 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
622 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
625 if (data->flags & MMC_DATA_READ) {
626 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
627 data->sg_len, direction);
629 align = host->align_buffer;
631 for_each_sg(data->sg, sg, host->sg_count, i) {
632 if (sg_dma_address(sg) & 0x3) {
633 size = 4 - (sg_dma_address(sg) & 0x3);
635 buffer = sdhci_kmap_atomic(sg, &flags);
636 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
637 memcpy(buffer, align, size);
638 sdhci_kunmap_atomic(buffer, &flags);
645 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
646 data->sg_len, direction);
649 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
652 struct mmc_data *data = cmd->data;
653 unsigned target_timeout, current_timeout;
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
661 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
664 /* Unspecified timeout, assume max */
665 if (!data && !cmd->cmd_timeout_ms)
670 target_timeout = cmd->cmd_timeout_ms * 1000;
672 target_timeout = data->timeout_ns / 1000;
674 target_timeout += data->timeout_clks / host->clock;
678 * Figure out needed cycles.
679 * We do this in steps in order to fit inside a 32 bit int.
680 * The first step is the minimum timeout, which will have a
681 * minimum resolution of 6 bits:
682 * (1) 2^13*1000 > 2^22,
683 * (2) host->timeout_clk < 2^16
688 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
689 while (current_timeout < target_timeout) {
691 current_timeout <<= 1;
697 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
698 mmc_hostname(host->mmc), count, cmd->opcode);
705 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
707 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
708 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
710 if (host->flags & SDHCI_REQ_USE_DMA)
711 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
713 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
716 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
720 struct mmc_data *data = cmd->data;
725 if (data || (cmd->flags & MMC_RSP_BUSY)) {
726 count = sdhci_calc_timeout(host, cmd);
727 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
734 BUG_ON(data->blksz * data->blocks > 524288);
735 BUG_ON(data->blksz > host->mmc->max_blk_size);
736 BUG_ON(data->blocks > 65535);
739 host->data_early = 0;
740 host->data->bytes_xfered = 0;
742 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
743 host->flags |= SDHCI_REQ_USE_DMA;
746 * FIXME: This doesn't account for merging when mapping the
749 if (host->flags & SDHCI_REQ_USE_DMA) {
751 struct scatterlist *sg;
754 if (host->flags & SDHCI_USE_ADMA) {
755 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
758 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
762 if (unlikely(broken)) {
763 for_each_sg(data->sg, sg, data->sg_len, i) {
764 if (sg->length & 0x3) {
765 DBG("Reverting to PIO because of "
766 "transfer size (%d)\n",
768 host->flags &= ~SDHCI_REQ_USE_DMA;
776 * The assumption here being that alignment is the same after
777 * translation to device address space.
779 if (host->flags & SDHCI_REQ_USE_DMA) {
781 struct scatterlist *sg;
784 if (host->flags & SDHCI_USE_ADMA) {
786 * As we use 3 byte chunks to work around
787 * alignment problems, we need to check this
790 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
793 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
797 if (unlikely(broken)) {
798 for_each_sg(data->sg, sg, data->sg_len, i) {
799 if (sg->offset & 0x3) {
800 DBG("Reverting to PIO because of "
802 host->flags &= ~SDHCI_REQ_USE_DMA;
809 if (host->flags & SDHCI_REQ_USE_DMA) {
810 if (host->flags & SDHCI_USE_ADMA) {
811 ret = sdhci_adma_table_pre(host, data);
814 * This only happens when someone fed
815 * us an invalid request.
818 host->flags &= ~SDHCI_REQ_USE_DMA;
820 sdhci_writel(host, host->adma_addr,
826 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
827 data->sg, data->sg_len,
828 (data->flags & MMC_DATA_READ) ?
833 * This only happens when someone fed
834 * us an invalid request.
837 host->flags &= ~SDHCI_REQ_USE_DMA;
839 WARN_ON(sg_cnt != 1);
840 sdhci_writel(host, sg_dma_address(data->sg),
847 * Always adjust the DMA selection as some controllers
848 * (e.g. JMicron) can't do PIO properly when the selection
851 if (host->version >= SDHCI_SPEC_200) {
852 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
853 ctrl &= ~SDHCI_CTRL_DMA_MASK;
854 if ((host->flags & SDHCI_REQ_USE_DMA) &&
855 (host->flags & SDHCI_USE_ADMA))
856 ctrl |= SDHCI_CTRL_ADMA32;
858 ctrl |= SDHCI_CTRL_SDMA;
859 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
862 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
865 flags = SG_MITER_ATOMIC;
866 if (host->data->flags & MMC_DATA_READ)
867 flags |= SG_MITER_TO_SG;
869 flags |= SG_MITER_FROM_SG;
870 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
871 host->blocks = data->blocks;
874 sdhci_set_transfer_irqs(host);
876 /* Set the DMA boundary value and block size */
877 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
878 data->blksz), SDHCI_BLOCK_SIZE);
879 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
882 static void sdhci_set_transfer_mode(struct sdhci_host *host,
883 struct mmc_command *cmd)
886 struct mmc_data *data = cmd->data;
891 WARN_ON(!host->data);
893 mode = SDHCI_TRNS_BLK_CNT_EN;
894 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
895 mode |= SDHCI_TRNS_MULTI;
897 * If we are sending CMD23, CMD12 never gets sent
898 * on successful completion (so no Auto-CMD12).
900 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
901 mode |= SDHCI_TRNS_AUTO_CMD12;
902 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
903 mode |= SDHCI_TRNS_AUTO_CMD23;
904 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
908 if (data->flags & MMC_DATA_READ)
909 mode |= SDHCI_TRNS_READ;
910 if (host->flags & SDHCI_REQ_USE_DMA)
911 mode |= SDHCI_TRNS_DMA;
913 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
916 static void sdhci_finish_data(struct sdhci_host *host)
918 struct mmc_data *data;
925 if (host->flags & SDHCI_REQ_USE_DMA) {
926 if (host->flags & SDHCI_USE_ADMA)
927 sdhci_adma_table_post(host, data);
929 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
930 data->sg_len, (data->flags & MMC_DATA_READ) ?
931 DMA_FROM_DEVICE : DMA_TO_DEVICE);
936 * The specification states that the block count register must
937 * be updated, but it does not specify at what point in the
938 * data flow. That makes the register entirely useless to read
939 * back so we have to assume that nothing made it to the card
940 * in the event of an error.
943 data->bytes_xfered = 0;
945 data->bytes_xfered = data->blksz * data->blocks;
948 * Need to send CMD12 if -
949 * a) open-ended multiblock transfer (no CMD23)
950 * b) error in multiblock transfer
957 * The controller needs a reset of internal state machines
958 * upon error conditions.
961 sdhci_reset(host, SDHCI_RESET_CMD);
962 sdhci_reset(host, SDHCI_RESET_DATA);
965 sdhci_send_command(host, data->stop);
967 tasklet_schedule(&host->finish_tasklet);
970 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
974 unsigned long timeout;
981 mask = SDHCI_CMD_INHIBIT;
982 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
983 mask |= SDHCI_DATA_INHIBIT;
985 /* We shouldn't wait for data inihibit for stop commands, even
986 though they might use busy signaling */
987 if (host->mrq->data && (cmd == host->mrq->data->stop))
988 mask &= ~SDHCI_DATA_INHIBIT;
990 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
992 pr_err("%s: Controller never released "
993 "inhibit bit(s).\n", mmc_hostname(host->mmc));
994 sdhci_dumpregs(host);
996 tasklet_schedule(&host->finish_tasklet);
1003 mod_timer(&host->timer, jiffies + 10 * HZ);
1007 sdhci_prepare_data(host, cmd);
1009 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1011 sdhci_set_transfer_mode(host, cmd);
1013 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1014 pr_err("%s: Unsupported response type!\n",
1015 mmc_hostname(host->mmc));
1016 cmd->error = -EINVAL;
1017 tasklet_schedule(&host->finish_tasklet);
1021 if (!(cmd->flags & MMC_RSP_PRESENT))
1022 flags = SDHCI_CMD_RESP_NONE;
1023 else if (cmd->flags & MMC_RSP_136)
1024 flags = SDHCI_CMD_RESP_LONG;
1025 else if (cmd->flags & MMC_RSP_BUSY)
1026 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1028 flags = SDHCI_CMD_RESP_SHORT;
1030 if (cmd->flags & MMC_RSP_CRC)
1031 flags |= SDHCI_CMD_CRC;
1032 if (cmd->flags & MMC_RSP_OPCODE)
1033 flags |= SDHCI_CMD_INDEX;
1035 /* CMD19 is special in that the Data Present Select should be set */
1036 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1037 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1038 flags |= SDHCI_CMD_DATA;
1040 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1043 static void sdhci_finish_command(struct sdhci_host *host)
1047 BUG_ON(host->cmd == NULL);
1049 if (host->cmd->flags & MMC_RSP_PRESENT) {
1050 if (host->cmd->flags & MMC_RSP_136) {
1051 /* CRC is stripped so we need to do some shifting. */
1052 for (i = 0;i < 4;i++) {
1053 host->cmd->resp[i] = sdhci_readl(host,
1054 SDHCI_RESPONSE + (3-i)*4) << 8;
1056 host->cmd->resp[i] |=
1058 SDHCI_RESPONSE + (3-i)*4-1);
1061 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1065 host->cmd->error = 0;
1067 /* Finished CMD23, now send actual command. */
1068 if (host->cmd == host->mrq->sbc) {
1070 sdhci_send_command(host, host->mrq->cmd);
1073 /* Processed actual command. */
1074 if (host->data && host->data_early)
1075 sdhci_finish_data(host);
1077 if (!host->cmd->data)
1078 tasklet_schedule(&host->finish_tasklet);
1084 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1086 int div = 0; /* Initialized for compiler warning */
1087 int real_div = div, clk_mul = 1;
1089 unsigned long timeout;
1091 if (clock && clock == host->clock)
1094 host->mmc->actual_clock = 0;
1096 if (host->ops->set_clock) {
1097 host->ops->set_clock(host, clock);
1098 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1102 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1107 if (host->version >= SDHCI_SPEC_300) {
1109 * Check if the Host Controller supports Programmable Clock
1112 if (host->clk_mul) {
1116 * We need to figure out whether the Host Driver needs
1117 * to select Programmable Clock Mode, or the value can
1118 * be set automatically by the Host Controller based on
1119 * the Preset Value registers.
1121 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1122 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1123 for (div = 1; div <= 1024; div++) {
1124 if (((host->max_clk * host->clk_mul) /
1129 * Set Programmable Clock Mode in the Clock
1132 clk = SDHCI_PROG_CLOCK_MODE;
1134 clk_mul = host->clk_mul;
1138 /* Version 3.00 divisors must be a multiple of 2. */
1139 if (host->max_clk <= clock)
1142 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1144 if ((host->max_clk / div) <= clock)
1152 /* Version 2.00 divisors must be a power of 2. */
1153 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1154 if ((host->max_clk / div) <= clock)
1162 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1164 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1165 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1166 << SDHCI_DIVIDER_HI_SHIFT;
1167 clk |= SDHCI_CLOCK_INT_EN;
1168 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1170 /* Wait max 20 ms */
1172 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1173 & SDHCI_CLOCK_INT_STABLE)) {
1175 pr_err("%s: Internal clock never "
1176 "stabilised.\n", mmc_hostname(host->mmc));
1177 sdhci_dumpregs(host);
1184 clk |= SDHCI_CLOCK_CARD_EN;
1185 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1188 host->clock = clock;
1191 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1195 if (power != (unsigned short)-1) {
1196 switch (1 << power) {
1197 case MMC_VDD_165_195:
1198 pwr = SDHCI_POWER_180;
1202 pwr = SDHCI_POWER_300;
1206 pwr = SDHCI_POWER_330;
1213 if (host->pwr == pwr)
1219 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1224 * Spec says that we should clear the power reg before setting
1225 * a new value. Some controllers don't seem to like this though.
1227 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1228 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1231 * At least the Marvell CaFe chip gets confused if we set the voltage
1232 * and set turn on power at the same time, so set the voltage first.
1234 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1235 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1237 pwr |= SDHCI_POWER_ON;
1239 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1242 * Some controllers need an extra 10ms delay of 10ms before they
1243 * can apply clock after applying power
1245 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1251 /*****************************************************************************\
1255 \*****************************************************************************/
1257 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1259 struct sdhci_host *host;
1261 unsigned long flags;
1264 host = mmc_priv(mmc);
1266 sdhci_runtime_pm_get(host);
1268 spin_lock_irqsave(&host->lock, flags);
1270 WARN_ON(host->mrq != NULL);
1272 #ifndef SDHCI_USE_LEDS_CLASS
1273 sdhci_activate_led(host);
1277 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1278 * requests if Auto-CMD12 is enabled.
1280 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1282 mrq->data->stop = NULL;
1289 /* If polling, assume that the card is always present. */
1290 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1293 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1296 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1297 host->mrq->cmd->error = -ENOMEDIUM;
1298 tasklet_schedule(&host->finish_tasklet);
1302 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1304 * Check if the re-tuning timer has already expired and there
1305 * is no on-going data transfer. If so, we need to execute
1306 * tuning procedure before sending command.
1308 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1309 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1310 /* eMMC uses cmd21 while sd and sdio use cmd19 */
1311 tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1312 MMC_SEND_TUNING_BLOCK_HS200 :
1313 MMC_SEND_TUNING_BLOCK;
1314 spin_unlock_irqrestore(&host->lock, flags);
1315 sdhci_execute_tuning(mmc, tuning_opcode);
1316 spin_lock_irqsave(&host->lock, flags);
1318 /* Restore original mmc_request structure */
1322 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1323 sdhci_send_command(host, mrq->sbc);
1325 sdhci_send_command(host, mrq->cmd);
1329 spin_unlock_irqrestore(&host->lock, flags);
1332 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1334 unsigned long flags;
1338 spin_lock_irqsave(&host->lock, flags);
1340 if (host->flags & SDHCI_DEVICE_DEAD) {
1341 spin_unlock_irqrestore(&host->lock, flags);
1342 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1343 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1348 * Reset the chip on each power off.
1349 * Should clear out any weird states.
1351 if (ios->power_mode == MMC_POWER_OFF) {
1352 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1356 sdhci_set_clock(host, ios->clock);
1358 if (ios->power_mode == MMC_POWER_OFF)
1359 vdd_bit = sdhci_set_power(host, -1);
1361 vdd_bit = sdhci_set_power(host, ios->vdd);
1363 if (host->vmmc && vdd_bit != -1) {
1364 spin_unlock_irqrestore(&host->lock, flags);
1365 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1366 spin_lock_irqsave(&host->lock, flags);
1369 if (host->ops->platform_send_init_74_clocks)
1370 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1373 * If your platform has 8-bit width support but is not a v3 controller,
1374 * or if it requires special setup code, you should implement that in
1375 * platform_8bit_width().
1377 if (host->ops->platform_8bit_width)
1378 host->ops->platform_8bit_width(host, ios->bus_width);
1380 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1381 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1382 ctrl &= ~SDHCI_CTRL_4BITBUS;
1383 if (host->version >= SDHCI_SPEC_300)
1384 ctrl |= SDHCI_CTRL_8BITBUS;
1386 if (host->version >= SDHCI_SPEC_300)
1387 ctrl &= ~SDHCI_CTRL_8BITBUS;
1388 if (ios->bus_width == MMC_BUS_WIDTH_4)
1389 ctrl |= SDHCI_CTRL_4BITBUS;
1391 ctrl &= ~SDHCI_CTRL_4BITBUS;
1393 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1396 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1398 if ((ios->timing == MMC_TIMING_SD_HS ||
1399 ios->timing == MMC_TIMING_MMC_HS)
1400 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1401 ctrl |= SDHCI_CTRL_HISPD;
1403 ctrl &= ~SDHCI_CTRL_HISPD;
1405 if (host->version >= SDHCI_SPEC_300) {
1409 /* In case of UHS-I modes, set High Speed Enable */
1410 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1411 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1412 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1413 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1414 (ios->timing == MMC_TIMING_UHS_SDR25))
1415 ctrl |= SDHCI_CTRL_HISPD;
1417 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1418 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1419 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1421 * We only need to set Driver Strength if the
1422 * preset value enable is not set.
1424 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1425 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1426 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1427 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1428 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1430 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1433 * According to SDHC Spec v3.00, if the Preset Value
1434 * Enable in the Host Control 2 register is set, we
1435 * need to reset SD Clock Enable before changing High
1436 * Speed Enable to avoid generating clock gliches.
1439 /* Reset SD Clock Enable */
1440 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1441 clk &= ~SDHCI_CLOCK_CARD_EN;
1442 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1444 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1446 /* Re-enable SD Clock */
1447 clock = host->clock;
1449 sdhci_set_clock(host, clock);
1453 /* Reset SD Clock Enable */
1454 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1455 clk &= ~SDHCI_CLOCK_CARD_EN;
1456 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1458 if (host->ops->set_uhs_signaling)
1459 host->ops->set_uhs_signaling(host, ios->timing);
1461 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1462 /* Select Bus Speed Mode for host */
1463 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1464 if (ios->timing == MMC_TIMING_MMC_HS200)
1465 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1466 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1467 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1468 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1469 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1470 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1471 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1472 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1473 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1474 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1475 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1476 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1479 /* Re-enable SD Clock */
1480 clock = host->clock;
1482 sdhci_set_clock(host, clock);
1484 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1487 * Some (ENE) controllers go apeshit on some ios operation,
1488 * signalling timeout and CRC errors even on CMD0. Resetting
1489 * it on each ios seems to solve the problem.
1491 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1492 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1495 spin_unlock_irqrestore(&host->lock, flags);
1498 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1500 struct sdhci_host *host = mmc_priv(mmc);
1502 sdhci_runtime_pm_get(host);
1503 sdhci_do_set_ios(host, ios);
1504 sdhci_runtime_pm_put(host);
1507 static int sdhci_check_ro(struct sdhci_host *host)
1509 unsigned long flags;
1512 spin_lock_irqsave(&host->lock, flags);
1514 if (host->flags & SDHCI_DEVICE_DEAD)
1516 else if (host->ops->get_ro)
1517 is_readonly = host->ops->get_ro(host);
1519 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1520 & SDHCI_WRITE_PROTECT);
1522 spin_unlock_irqrestore(&host->lock, flags);
1524 /* This quirk needs to be replaced by a callback-function later */
1525 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1526 !is_readonly : is_readonly;
1529 #define SAMPLE_COUNT 5
1531 static int sdhci_do_get_ro(struct sdhci_host *host)
1535 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1536 return sdhci_check_ro(host);
1539 for (i = 0; i < SAMPLE_COUNT; i++) {
1540 if (sdhci_check_ro(host)) {
1541 if (++ro_count > SAMPLE_COUNT / 2)
1549 static void sdhci_hw_reset(struct mmc_host *mmc)
1551 struct sdhci_host *host = mmc_priv(mmc);
1553 if (host->ops && host->ops->hw_reset)
1554 host->ops->hw_reset(host);
1557 static int sdhci_get_ro(struct mmc_host *mmc)
1559 struct sdhci_host *host = mmc_priv(mmc);
1562 sdhci_runtime_pm_get(host);
1563 ret = sdhci_do_get_ro(host);
1564 sdhci_runtime_pm_put(host);
1568 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1570 if (host->flags & SDHCI_DEVICE_DEAD)
1574 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1576 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1578 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1579 if (host->runtime_suspended)
1583 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1585 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1590 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1592 struct sdhci_host *host = mmc_priv(mmc);
1593 unsigned long flags;
1595 spin_lock_irqsave(&host->lock, flags);
1596 sdhci_enable_sdio_irq_nolock(host, enable);
1597 spin_unlock_irqrestore(&host->lock, flags);
1600 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1601 struct mmc_ios *ios)
1608 * Signal Voltage Switching is only applicable for Host Controllers
1611 if (host->version < SDHCI_SPEC_300)
1615 * We first check whether the request is to set signalling voltage
1616 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1618 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1619 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1620 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1621 ctrl &= ~SDHCI_CTRL_VDD_180;
1622 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1625 usleep_range(5000, 5500);
1627 /* 3.3V regulator output should be stable within 5 ms */
1628 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1629 if (!(ctrl & SDHCI_CTRL_VDD_180))
1632 pr_info(DRIVER_NAME ": Switching to 3.3V "
1633 "signalling voltage failed\n");
1636 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1637 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1639 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1640 clk &= ~SDHCI_CLOCK_CARD_EN;
1641 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1643 /* Check whether DAT[3:0] is 0000 */
1644 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1645 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1646 SDHCI_DATA_LVL_SHIFT)) {
1648 * Enable 1.8V Signal Enable in the Host Control2
1651 ctrl |= SDHCI_CTRL_VDD_180;
1652 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1655 usleep_range(5000, 5500);
1657 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1658 if (ctrl & SDHCI_CTRL_VDD_180) {
1659 /* Provide SDCLK again and wait for 1ms*/
1660 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1661 clk |= SDHCI_CLOCK_CARD_EN;
1662 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1663 usleep_range(1000, 1500);
1666 * If DAT[3:0] level is 1111b, then the card
1667 * was successfully switched to 1.8V signaling.
1669 present_state = sdhci_readl(host,
1670 SDHCI_PRESENT_STATE);
1671 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1672 SDHCI_DATA_LVL_MASK)
1678 * If we are here, that means the switch to 1.8V signaling
1679 * failed. We power cycle the card, and retry initialization
1680 * sequence by setting S18R to 0.
1682 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1683 pwr &= ~SDHCI_POWER_ON;
1684 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1686 regulator_disable(host->vmmc);
1688 /* Wait for 1ms as per the spec */
1689 usleep_range(1000, 1500);
1690 pwr |= SDHCI_POWER_ON;
1691 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1693 regulator_enable(host->vmmc);
1695 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1696 "voltage failed, retrying with S18R set to 0\n");
1699 /* No signal voltage switch required */
1703 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1704 struct mmc_ios *ios)
1706 struct sdhci_host *host = mmc_priv(mmc);
1709 if (host->version < SDHCI_SPEC_300)
1711 sdhci_runtime_pm_get(host);
1712 err = sdhci_do_start_signal_voltage_switch(host, ios);
1713 sdhci_runtime_pm_put(host);
1717 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1719 struct sdhci_host *host;
1722 int tuning_loop_counter = MAX_TUNING_LOOP;
1723 unsigned long timeout;
1725 bool requires_tuning_nonuhs = false;
1727 host = mmc_priv(mmc);
1729 sdhci_runtime_pm_get(host);
1730 disable_irq(host->irq);
1731 spin_lock(&host->lock);
1733 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1736 * The Host Controller needs tuning only in case of SDR104 mode
1737 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1738 * Capabilities register.
1739 * If the Host Controller supports the HS200 mode then the
1740 * tuning function has to be executed.
1742 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1743 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1744 host->flags & SDHCI_HS200_NEEDS_TUNING))
1745 requires_tuning_nonuhs = true;
1747 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1748 requires_tuning_nonuhs)
1749 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1751 spin_unlock(&host->lock);
1752 enable_irq(host->irq);
1753 sdhci_runtime_pm_put(host);
1757 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1760 * As per the Host Controller spec v3.00, tuning command
1761 * generates Buffer Read Ready interrupt, so enable that.
1763 * Note: The spec clearly says that when tuning sequence
1764 * is being performed, the controller does not generate
1765 * interrupts other than Buffer Read Ready interrupt. But
1766 * to make sure we don't hit a controller bug, we _only_
1767 * enable Buffer Read Ready interrupt here.
1769 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1770 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1773 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1774 * of loops reaches 40 times or a timeout of 150ms occurs.
1778 struct mmc_command cmd = {0};
1779 struct mmc_request mrq = {NULL};
1781 if (!tuning_loop_counter && !timeout)
1784 cmd.opcode = opcode;
1786 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1795 * In response to CMD19, the card sends 64 bytes of tuning
1796 * block to the Host Controller. So we set the block size
1799 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1800 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1801 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1803 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1804 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1807 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1812 * The tuning block is sent by the card to the host controller.
1813 * So we set the TRNS_READ bit in the Transfer Mode register.
1814 * This also takes care of setting DMA Enable and Multi Block
1815 * Select in the same register to 0.
1817 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1819 sdhci_send_command(host, &cmd);
1824 spin_unlock(&host->lock);
1825 enable_irq(host->irq);
1827 /* Wait for Buffer Read Ready interrupt */
1828 wait_event_interruptible_timeout(host->buf_ready_int,
1829 (host->tuning_done == 1),
1830 msecs_to_jiffies(50));
1831 disable_irq(host->irq);
1832 spin_lock(&host->lock);
1834 if (!host->tuning_done) {
1835 pr_info(DRIVER_NAME ": Timeout waiting for "
1836 "Buffer Read Ready interrupt during tuning "
1837 "procedure, falling back to fixed sampling "
1839 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1840 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1841 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1842 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1848 host->tuning_done = 0;
1850 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1851 tuning_loop_counter--;
1854 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1857 * The Host Driver has exhausted the maximum number of loops allowed,
1858 * so use fixed sampling frequency.
1860 if (!tuning_loop_counter || !timeout) {
1861 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1862 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1864 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1865 pr_info(DRIVER_NAME ": Tuning procedure"
1866 " failed, falling back to fixed sampling"
1874 * If this is the very first time we are here, we start the retuning
1875 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1876 * flag won't be set, we check this condition before actually starting
1879 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1880 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1881 host->flags |= SDHCI_USING_RETUNING_TIMER;
1882 mod_timer(&host->tuning_timer, jiffies +
1883 host->tuning_count * HZ);
1884 /* Tuning mode 1 limits the maximum data length to 4MB */
1885 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1887 host->flags &= ~SDHCI_NEEDS_RETUNING;
1888 /* Reload the new initial value for timer */
1889 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1890 mod_timer(&host->tuning_timer, jiffies +
1891 host->tuning_count * HZ);
1895 * In case tuning fails, host controllers which support re-tuning can
1896 * try tuning again at a later time, when the re-tuning timer expires.
1897 * So for these controllers, we return 0. Since there might be other
1898 * controllers who do not have this capability, we return error for
1899 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1900 * a retuning timer to do the retuning for the card.
1902 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
1905 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1906 spin_unlock(&host->lock);
1907 enable_irq(host->irq);
1908 sdhci_runtime_pm_put(host);
1913 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1916 unsigned long flags;
1918 /* Host Controller v3.00 defines preset value registers */
1919 if (host->version < SDHCI_SPEC_300)
1922 spin_lock_irqsave(&host->lock, flags);
1924 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1927 * We only enable or disable Preset Value if they are not already
1928 * enabled or disabled respectively. Otherwise, we bail out.
1930 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1931 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1932 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1933 host->flags |= SDHCI_PV_ENABLED;
1934 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1935 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1936 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1937 host->flags &= ~SDHCI_PV_ENABLED;
1940 spin_unlock_irqrestore(&host->lock, flags);
1943 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1945 struct sdhci_host *host = mmc_priv(mmc);
1947 sdhci_runtime_pm_get(host);
1948 sdhci_do_enable_preset_value(host, enable);
1949 sdhci_runtime_pm_put(host);
1952 static const struct mmc_host_ops sdhci_ops = {
1953 .request = sdhci_request,
1954 .set_ios = sdhci_set_ios,
1955 .get_ro = sdhci_get_ro,
1956 .hw_reset = sdhci_hw_reset,
1957 .enable_sdio_irq = sdhci_enable_sdio_irq,
1958 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
1959 .execute_tuning = sdhci_execute_tuning,
1960 .enable_preset_value = sdhci_enable_preset_value,
1963 /*****************************************************************************\
1967 \*****************************************************************************/
1969 static void sdhci_tasklet_card(unsigned long param)
1971 struct sdhci_host *host;
1972 unsigned long flags;
1974 host = (struct sdhci_host*)param;
1976 spin_lock_irqsave(&host->lock, flags);
1978 /* Check host->mrq first in case we are runtime suspended */
1980 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1981 pr_err("%s: Card removed during transfer!\n",
1982 mmc_hostname(host->mmc));
1983 pr_err("%s: Resetting controller.\n",
1984 mmc_hostname(host->mmc));
1986 sdhci_reset(host, SDHCI_RESET_CMD);
1987 sdhci_reset(host, SDHCI_RESET_DATA);
1989 host->mrq->cmd->error = -ENOMEDIUM;
1990 tasklet_schedule(&host->finish_tasklet);
1993 spin_unlock_irqrestore(&host->lock, flags);
1995 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1998 static void sdhci_tasklet_finish(unsigned long param)
2000 struct sdhci_host *host;
2001 unsigned long flags;
2002 struct mmc_request *mrq;
2004 host = (struct sdhci_host*)param;
2006 spin_lock_irqsave(&host->lock, flags);
2009 * If this tasklet gets rescheduled while running, it will
2010 * be run again afterwards but without any active request.
2013 spin_unlock_irqrestore(&host->lock, flags);
2017 del_timer(&host->timer);
2022 * The controller needs a reset of internal state machines
2023 * upon error conditions.
2025 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2026 ((mrq->cmd && mrq->cmd->error) ||
2027 (mrq->data && (mrq->data->error ||
2028 (mrq->data->stop && mrq->data->stop->error))) ||
2029 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2031 /* Some controllers need this kick or reset won't work here */
2032 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2035 /* This is to force an update */
2036 clock = host->clock;
2038 sdhci_set_clock(host, clock);
2041 /* Spec says we should do both at the same time, but Ricoh
2042 controllers do not like that. */
2043 sdhci_reset(host, SDHCI_RESET_CMD);
2044 sdhci_reset(host, SDHCI_RESET_DATA);
2051 #ifndef SDHCI_USE_LEDS_CLASS
2052 sdhci_deactivate_led(host);
2056 spin_unlock_irqrestore(&host->lock, flags);
2058 mmc_request_done(host->mmc, mrq);
2059 sdhci_runtime_pm_put(host);
2062 static void sdhci_timeout_timer(unsigned long data)
2064 struct sdhci_host *host;
2065 unsigned long flags;
2067 host = (struct sdhci_host*)data;
2069 spin_lock_irqsave(&host->lock, flags);
2072 pr_err("%s: Timeout waiting for hardware "
2073 "interrupt.\n", mmc_hostname(host->mmc));
2074 sdhci_dumpregs(host);
2077 host->data->error = -ETIMEDOUT;
2078 sdhci_finish_data(host);
2081 host->cmd->error = -ETIMEDOUT;
2083 host->mrq->cmd->error = -ETIMEDOUT;
2085 tasklet_schedule(&host->finish_tasklet);
2090 spin_unlock_irqrestore(&host->lock, flags);
2093 static void sdhci_tuning_timer(unsigned long data)
2095 struct sdhci_host *host;
2096 unsigned long flags;
2098 host = (struct sdhci_host *)data;
2100 spin_lock_irqsave(&host->lock, flags);
2102 host->flags |= SDHCI_NEEDS_RETUNING;
2104 spin_unlock_irqrestore(&host->lock, flags);
2107 /*****************************************************************************\
2109 * Interrupt handling *
2111 \*****************************************************************************/
2113 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2115 BUG_ON(intmask == 0);
2118 pr_err("%s: Got command interrupt 0x%08x even "
2119 "though no command operation was in progress.\n",
2120 mmc_hostname(host->mmc), (unsigned)intmask);
2121 sdhci_dumpregs(host);
2125 if (intmask & SDHCI_INT_TIMEOUT)
2126 host->cmd->error = -ETIMEDOUT;
2127 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2129 host->cmd->error = -EILSEQ;
2131 if (host->cmd->error) {
2132 tasklet_schedule(&host->finish_tasklet);
2137 * The host can send and interrupt when the busy state has
2138 * ended, allowing us to wait without wasting CPU cycles.
2139 * Unfortunately this is overloaded on the "data complete"
2140 * interrupt, so we need to take some care when handling
2143 * Note: The 1.0 specification is a bit ambiguous about this
2144 * feature so there might be some problems with older
2147 if (host->cmd->flags & MMC_RSP_BUSY) {
2148 if (host->cmd->data)
2149 DBG("Cannot wait for busy signal when also "
2150 "doing a data transfer");
2151 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2154 /* The controller does not support the end-of-busy IRQ,
2155 * fall through and take the SDHCI_INT_RESPONSE */
2158 if (intmask & SDHCI_INT_RESPONSE)
2159 sdhci_finish_command(host);
2162 #ifdef CONFIG_MMC_DEBUG
2163 static void sdhci_show_adma_error(struct sdhci_host *host)
2165 const char *name = mmc_hostname(host->mmc);
2166 u8 *desc = host->adma_desc;
2171 sdhci_dumpregs(host);
2174 dma = (__le32 *)(desc + 4);
2175 len = (__le16 *)(desc + 2);
2178 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2179 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2188 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2191 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2194 BUG_ON(intmask == 0);
2196 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2197 if (intmask & SDHCI_INT_DATA_AVAIL) {
2198 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2199 if (command == MMC_SEND_TUNING_BLOCK ||
2200 command == MMC_SEND_TUNING_BLOCK_HS200) {
2201 host->tuning_done = 1;
2202 wake_up(&host->buf_ready_int);
2209 * The "data complete" interrupt is also used to
2210 * indicate that a busy state has ended. See comment
2211 * above in sdhci_cmd_irq().
2213 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2214 if (intmask & SDHCI_INT_DATA_END) {
2215 sdhci_finish_command(host);
2220 pr_err("%s: Got data interrupt 0x%08x even "
2221 "though no data operation was in progress.\n",
2222 mmc_hostname(host->mmc), (unsigned)intmask);
2223 sdhci_dumpregs(host);
2228 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2229 host->data->error = -ETIMEDOUT;
2230 else if (intmask & SDHCI_INT_DATA_END_BIT)
2231 host->data->error = -EILSEQ;
2232 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2233 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2235 host->data->error = -EILSEQ;
2236 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2237 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2238 sdhci_show_adma_error(host);
2239 host->data->error = -EIO;
2242 if (host->data->error)
2243 sdhci_finish_data(host);
2245 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2246 sdhci_transfer_pio(host);
2249 * We currently don't do anything fancy with DMA
2250 * boundaries, but as we can't disable the feature
2251 * we need to at least restart the transfer.
2253 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2254 * should return a valid address to continue from, but as
2255 * some controllers are faulty, don't trust them.
2257 if (intmask & SDHCI_INT_DMA_END) {
2258 u32 dmastart, dmanow;
2259 dmastart = sg_dma_address(host->data->sg);
2260 dmanow = dmastart + host->data->bytes_xfered;
2262 * Force update to the next DMA block boundary.
2265 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2266 SDHCI_DEFAULT_BOUNDARY_SIZE;
2267 host->data->bytes_xfered = dmanow - dmastart;
2268 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2270 mmc_hostname(host->mmc), dmastart,
2271 host->data->bytes_xfered, dmanow);
2272 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2275 if (intmask & SDHCI_INT_DATA_END) {
2278 * Data managed to finish before the
2279 * command completed. Make sure we do
2280 * things in the proper order.
2282 host->data_early = 1;
2284 sdhci_finish_data(host);
2290 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2293 struct sdhci_host *host = dev_id;
2294 u32 intmask, unexpected = 0;
2295 int cardint = 0, max_loops = 16;
2297 spin_lock(&host->lock);
2299 if (host->runtime_suspended) {
2300 spin_unlock(&host->lock);
2301 pr_warning("%s: got irq while runtime suspended\n",
2302 mmc_hostname(host->mmc));
2306 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2308 if (!intmask || intmask == 0xffffffff) {
2314 DBG("*** %s got interrupt: 0x%08x\n",
2315 mmc_hostname(host->mmc), intmask);
2317 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2318 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2322 * There is a observation on i.mx esdhc. INSERT bit will be
2323 * immediately set again when it gets cleared, if a card is
2324 * inserted. We have to mask the irq to prevent interrupt
2325 * storm which will freeze the system. And the REMOVE gets
2326 * the same situation.
2328 * More testing are needed here to ensure it works for other
2331 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2332 SDHCI_INT_CARD_REMOVE);
2333 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2334 SDHCI_INT_CARD_INSERT);
2336 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2337 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2338 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2339 tasklet_schedule(&host->card_tasklet);
2342 if (intmask & SDHCI_INT_CMD_MASK) {
2343 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2345 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2348 if (intmask & SDHCI_INT_DATA_MASK) {
2349 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2351 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2354 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2356 intmask &= ~SDHCI_INT_ERROR;
2358 if (intmask & SDHCI_INT_BUS_POWER) {
2359 pr_err("%s: Card is consuming too much power!\n",
2360 mmc_hostname(host->mmc));
2361 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2364 intmask &= ~SDHCI_INT_BUS_POWER;
2366 if (intmask & SDHCI_INT_CARD_INT)
2369 intmask &= ~SDHCI_INT_CARD_INT;
2372 unexpected |= intmask;
2373 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2376 result = IRQ_HANDLED;
2378 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2379 if (intmask && --max_loops)
2382 spin_unlock(&host->lock);
2385 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2386 mmc_hostname(host->mmc), unexpected);
2387 sdhci_dumpregs(host);
2390 * We have to delay this as it calls back into the driver.
2393 mmc_signal_sdio_irq(host->mmc);
2398 /*****************************************************************************\
2402 \*****************************************************************************/
2406 int sdhci_suspend_host(struct sdhci_host *host)
2410 if (host->ops->platform_suspend)
2411 host->ops->platform_suspend(host);
2413 sdhci_disable_card_detection(host);
2415 /* Disable tuning since we are suspending */
2416 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2417 del_timer_sync(&host->tuning_timer);
2418 host->flags &= ~SDHCI_NEEDS_RETUNING;
2421 ret = mmc_suspend_host(host->mmc);
2423 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2424 host->flags |= SDHCI_NEEDS_RETUNING;
2425 mod_timer(&host->tuning_timer, jiffies +
2426 host->tuning_count * HZ);
2429 sdhci_enable_card_detection(host);
2434 free_irq(host->irq, host);
2439 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2441 int sdhci_resume_host(struct sdhci_host *host)
2445 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2446 if (host->ops->enable_dma)
2447 host->ops->enable_dma(host);
2450 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2451 mmc_hostname(host->mmc), host);
2455 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2456 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2457 /* Card keeps power but host controller does not */
2458 sdhci_init(host, 0);
2461 sdhci_do_set_ios(host, &host->mmc->ios);
2463 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2467 ret = mmc_resume_host(host->mmc);
2468 sdhci_enable_card_detection(host);
2470 if (host->ops->platform_resume)
2471 host->ops->platform_resume(host);
2473 /* Set the re-tuning expiration flag */
2474 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2475 host->flags |= SDHCI_NEEDS_RETUNING;
2480 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2482 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2485 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2486 val |= SDHCI_WAKE_ON_INT;
2487 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2490 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2492 #endif /* CONFIG_PM */
2494 #ifdef CONFIG_PM_RUNTIME
2496 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2498 return pm_runtime_get_sync(host->mmc->parent);
2501 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2503 pm_runtime_mark_last_busy(host->mmc->parent);
2504 return pm_runtime_put_autosuspend(host->mmc->parent);
2507 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2509 unsigned long flags;
2512 /* Disable tuning since we are suspending */
2513 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2514 del_timer_sync(&host->tuning_timer);
2515 host->flags &= ~SDHCI_NEEDS_RETUNING;
2518 spin_lock_irqsave(&host->lock, flags);
2519 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2520 spin_unlock_irqrestore(&host->lock, flags);
2522 synchronize_irq(host->irq);
2524 spin_lock_irqsave(&host->lock, flags);
2525 host->runtime_suspended = true;
2526 spin_unlock_irqrestore(&host->lock, flags);
2530 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2532 int sdhci_runtime_resume_host(struct sdhci_host *host)
2534 unsigned long flags;
2535 int ret = 0, host_flags = host->flags;
2537 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2538 if (host->ops->enable_dma)
2539 host->ops->enable_dma(host);
2542 sdhci_init(host, 0);
2544 /* Force clock and power re-program */
2547 sdhci_do_set_ios(host, &host->mmc->ios);
2549 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2550 if (host_flags & SDHCI_PV_ENABLED)
2551 sdhci_do_enable_preset_value(host, true);
2553 /* Set the re-tuning expiration flag */
2554 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2555 host->flags |= SDHCI_NEEDS_RETUNING;
2557 spin_lock_irqsave(&host->lock, flags);
2559 host->runtime_suspended = false;
2561 /* Enable SDIO IRQ */
2562 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2563 sdhci_enable_sdio_irq_nolock(host, true);
2565 /* Enable Card Detection */
2566 sdhci_enable_card_detection(host);
2568 spin_unlock_irqrestore(&host->lock, flags);
2572 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2576 /*****************************************************************************\
2578 * Device allocation/registration *
2580 \*****************************************************************************/
2582 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2585 struct mmc_host *mmc;
2586 struct sdhci_host *host;
2588 WARN_ON(dev == NULL);
2590 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2592 return ERR_PTR(-ENOMEM);
2594 host = mmc_priv(mmc);
2600 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2602 int sdhci_add_host(struct sdhci_host *host)
2604 struct mmc_host *mmc;
2605 u32 caps[2] = {0, 0};
2606 u32 max_current_caps;
2607 unsigned int ocr_avail;
2610 WARN_ON(host == NULL);
2617 host->quirks = debug_quirks;
2619 host->quirks2 = debug_quirks2;
2621 sdhci_reset(host, SDHCI_RESET_ALL);
2623 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2624 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2625 >> SDHCI_SPEC_VER_SHIFT;
2626 if (host->version > SDHCI_SPEC_300) {
2627 pr_err("%s: Unknown controller version (%d). "
2628 "You may experience problems.\n", mmc_hostname(mmc),
2632 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2633 sdhci_readl(host, SDHCI_CAPABILITIES);
2635 if (host->version >= SDHCI_SPEC_300)
2636 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2638 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2640 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2641 host->flags |= SDHCI_USE_SDMA;
2642 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2643 DBG("Controller doesn't have SDMA capability\n");
2645 host->flags |= SDHCI_USE_SDMA;
2647 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2648 (host->flags & SDHCI_USE_SDMA)) {
2649 DBG("Disabling DMA as it is marked broken\n");
2650 host->flags &= ~SDHCI_USE_SDMA;
2653 if ((host->version >= SDHCI_SPEC_200) &&
2654 (caps[0] & SDHCI_CAN_DO_ADMA2))
2655 host->flags |= SDHCI_USE_ADMA;
2657 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2658 (host->flags & SDHCI_USE_ADMA)) {
2659 DBG("Disabling ADMA as it is marked broken\n");
2660 host->flags &= ~SDHCI_USE_ADMA;
2663 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2664 if (host->ops->enable_dma) {
2665 if (host->ops->enable_dma(host)) {
2666 pr_warning("%s: No suitable DMA "
2667 "available. Falling back to PIO.\n",
2670 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2675 if (host->flags & SDHCI_USE_ADMA) {
2677 * We need to allocate descriptors for all sg entries
2678 * (128) and potentially one alignment transfer for
2679 * each of those entries.
2681 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2682 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2683 if (!host->adma_desc || !host->align_buffer) {
2684 kfree(host->adma_desc);
2685 kfree(host->align_buffer);
2686 pr_warning("%s: Unable to allocate ADMA "
2687 "buffers. Falling back to standard DMA.\n",
2689 host->flags &= ~SDHCI_USE_ADMA;
2694 * If we use DMA, then it's up to the caller to set the DMA
2695 * mask, but PIO does not need the hw shim so we set a new
2696 * mask here in that case.
2698 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2699 host->dma_mask = DMA_BIT_MASK(64);
2700 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2703 if (host->version >= SDHCI_SPEC_300)
2704 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2705 >> SDHCI_CLOCK_BASE_SHIFT;
2707 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2708 >> SDHCI_CLOCK_BASE_SHIFT;
2710 host->max_clk *= 1000000;
2711 if (host->max_clk == 0 || host->quirks &
2712 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2713 if (!host->ops->get_max_clock) {
2714 pr_err("%s: Hardware doesn't specify base clock "
2715 "frequency.\n", mmc_hostname(mmc));
2718 host->max_clk = host->ops->get_max_clock(host);
2722 * In case of Host Controller v3.00, find out whether clock
2723 * multiplier is supported.
2725 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2726 SDHCI_CLOCK_MUL_SHIFT;
2729 * In case the value in Clock Multiplier is 0, then programmable
2730 * clock mode is not supported, otherwise the actual clock
2731 * multiplier is one more than the value of Clock Multiplier
2732 * in the Capabilities Register.
2738 * Set host parameters.
2740 mmc->ops = &sdhci_ops;
2741 mmc->f_max = host->max_clk;
2742 if (host->ops->get_min_clock)
2743 mmc->f_min = host->ops->get_min_clock(host);
2744 else if (host->version >= SDHCI_SPEC_300) {
2745 if (host->clk_mul) {
2746 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2747 mmc->f_max = host->max_clk * host->clk_mul;
2749 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2751 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2754 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2755 if (host->timeout_clk == 0) {
2756 if (host->ops->get_timeout_clock) {
2757 host->timeout_clk = host->ops->get_timeout_clock(host);
2758 } else if (!(host->quirks &
2759 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2760 pr_err("%s: Hardware doesn't specify timeout clock "
2761 "frequency.\n", mmc_hostname(mmc));
2765 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2766 host->timeout_clk *= 1000;
2768 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2769 host->timeout_clk = mmc->f_max / 1000;
2771 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2773 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2775 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2776 host->flags |= SDHCI_AUTO_CMD12;
2778 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2779 if ((host->version >= SDHCI_SPEC_300) &&
2780 ((host->flags & SDHCI_USE_ADMA) ||
2781 !(host->flags & SDHCI_USE_SDMA))) {
2782 host->flags |= SDHCI_AUTO_CMD23;
2783 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2785 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2789 * A controller may support 8-bit width, but the board itself
2790 * might not have the pins brought out. Boards that support
2791 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2792 * their platform code before calling sdhci_add_host(), and we
2793 * won't assume 8-bit width for hosts without that CAP.
2795 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2796 mmc->caps |= MMC_CAP_4_BIT_DATA;
2798 if (caps[0] & SDHCI_CAN_DO_HISPD)
2799 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2801 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2802 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2803 mmc->caps |= MMC_CAP_NEEDS_POLL;
2805 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2806 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2807 SDHCI_SUPPORT_DDR50))
2808 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2810 /* SDR104 supports also implies SDR50 support */
2811 if (caps[1] & SDHCI_SUPPORT_SDR104)
2812 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2813 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2814 mmc->caps |= MMC_CAP_UHS_SDR50;
2816 if (caps[1] & SDHCI_SUPPORT_DDR50)
2817 mmc->caps |= MMC_CAP_UHS_DDR50;
2819 /* Does the host need tuning for SDR50? */
2820 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2821 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2823 /* Does the host need tuning for HS200? */
2824 if (mmc->caps2 & MMC_CAP2_HS200)
2825 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2827 /* Driver Type(s) (A, C, D) supported by the host */
2828 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2829 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2830 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2831 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2832 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2833 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2836 * If Power Off Notify capability is enabled by the host,
2837 * set notify to short power off notify timeout value.
2839 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2840 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2842 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2844 /* Initial value for re-tuning timer count */
2845 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2846 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2849 * In case Re-tuning Timer is not disabled, the actual value of
2850 * re-tuning timer will be 2 ^ (n - 1).
2852 if (host->tuning_count)
2853 host->tuning_count = 1 << (host->tuning_count - 1);
2855 /* Re-tuning mode supported by the Host Controller */
2856 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2857 SDHCI_RETUNING_MODE_SHIFT;
2861 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2862 if (IS_ERR(host->vmmc)) {
2863 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2867 #ifdef CONFIG_REGULATOR
2869 ret = regulator_is_supported_voltage(host->vmmc, 3300000,
2871 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2872 caps[0] &= ~SDHCI_CAN_VDD_330;
2873 ret = regulator_is_supported_voltage(host->vmmc, 3000000,
2875 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2876 caps[0] &= ~SDHCI_CAN_VDD_300;
2877 ret = regulator_is_supported_voltage(host->vmmc, 1800000,
2879 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2880 caps[0] &= ~SDHCI_CAN_VDD_180;
2882 #endif /* CONFIG_REGULATOR */
2885 * According to SD Host Controller spec v3.00, if the Host System
2886 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2887 * the value is meaningful only if Voltage Support in the Capabilities
2888 * register is set. The actual current value is 4 times the register
2891 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2892 if (!max_current_caps && host->vmmc) {
2893 u32 curr = regulator_get_current_limit(host->vmmc);
2896 /* convert to SDHCI_MAX_CURRENT format */
2897 curr = curr/1000; /* convert to mA */
2898 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2900 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2902 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2903 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
2904 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
2908 if (caps[0] & SDHCI_CAN_VDD_330) {
2909 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2911 mmc->max_current_330 = ((max_current_caps &
2912 SDHCI_MAX_CURRENT_330_MASK) >>
2913 SDHCI_MAX_CURRENT_330_SHIFT) *
2914 SDHCI_MAX_CURRENT_MULTIPLIER;
2916 if (caps[0] & SDHCI_CAN_VDD_300) {
2917 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2919 mmc->max_current_300 = ((max_current_caps &
2920 SDHCI_MAX_CURRENT_300_MASK) >>
2921 SDHCI_MAX_CURRENT_300_SHIFT) *
2922 SDHCI_MAX_CURRENT_MULTIPLIER;
2924 if (caps[0] & SDHCI_CAN_VDD_180) {
2925 ocr_avail |= MMC_VDD_165_195;
2927 mmc->max_current_180 = ((max_current_caps &
2928 SDHCI_MAX_CURRENT_180_MASK) >>
2929 SDHCI_MAX_CURRENT_180_SHIFT) *
2930 SDHCI_MAX_CURRENT_MULTIPLIER;
2933 mmc->ocr_avail = ocr_avail;
2934 mmc->ocr_avail_sdio = ocr_avail;
2935 if (host->ocr_avail_sdio)
2936 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2937 mmc->ocr_avail_sd = ocr_avail;
2938 if (host->ocr_avail_sd)
2939 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2940 else /* normal SD controllers don't support 1.8V */
2941 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2942 mmc->ocr_avail_mmc = ocr_avail;
2943 if (host->ocr_avail_mmc)
2944 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2946 if (mmc->ocr_avail == 0) {
2947 pr_err("%s: Hardware doesn't report any "
2948 "support voltages.\n", mmc_hostname(mmc));
2952 spin_lock_init(&host->lock);
2955 * Maximum number of segments. Depends on if the hardware
2956 * can do scatter/gather or not.
2958 if (host->flags & SDHCI_USE_ADMA)
2959 mmc->max_segs = 128;
2960 else if (host->flags & SDHCI_USE_SDMA)
2963 mmc->max_segs = 128;
2966 * Maximum number of sectors in one transfer. Limited by DMA boundary
2969 mmc->max_req_size = 524288;
2972 * Maximum segment size. Could be one segment with the maximum number
2973 * of bytes. When doing hardware scatter/gather, each entry cannot
2974 * be larger than 64 KiB though.
2976 if (host->flags & SDHCI_USE_ADMA) {
2977 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2978 mmc->max_seg_size = 65535;
2980 mmc->max_seg_size = 65536;
2982 mmc->max_seg_size = mmc->max_req_size;
2986 * Maximum block size. This varies from controller to controller and
2987 * is specified in the capabilities register.
2989 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2990 mmc->max_blk_size = 2;
2992 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2993 SDHCI_MAX_BLOCK_SHIFT;
2994 if (mmc->max_blk_size >= 3) {
2995 pr_warning("%s: Invalid maximum block size, "
2996 "assuming 512 bytes\n", mmc_hostname(mmc));
2997 mmc->max_blk_size = 0;
3001 mmc->max_blk_size = 512 << mmc->max_blk_size;
3004 * Maximum block count.
3006 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3011 tasklet_init(&host->card_tasklet,
3012 sdhci_tasklet_card, (unsigned long)host);
3013 tasklet_init(&host->finish_tasklet,
3014 sdhci_tasklet_finish, (unsigned long)host);
3016 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3018 if (host->version >= SDHCI_SPEC_300) {
3019 init_waitqueue_head(&host->buf_ready_int);
3021 /* Initialize re-tuning timer */
3022 init_timer(&host->tuning_timer);
3023 host->tuning_timer.data = (unsigned long)host;
3024 host->tuning_timer.function = sdhci_tuning_timer;
3027 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3028 mmc_hostname(mmc), host);
3030 pr_err("%s: Failed to request IRQ %d: %d\n",
3031 mmc_hostname(mmc), host->irq, ret);
3035 sdhci_init(host, 0);
3037 #ifdef CONFIG_MMC_DEBUG
3038 sdhci_dumpregs(host);
3041 #ifdef SDHCI_USE_LEDS_CLASS
3042 snprintf(host->led_name, sizeof(host->led_name),
3043 "%s::", mmc_hostname(mmc));
3044 host->led.name = host->led_name;
3045 host->led.brightness = LED_OFF;
3046 host->led.default_trigger = mmc_hostname(mmc);
3047 host->led.brightness_set = sdhci_led_control;
3049 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3051 pr_err("%s: Failed to register LED device: %d\n",
3052 mmc_hostname(mmc), ret);
3061 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3062 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3063 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3064 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3066 sdhci_enable_card_detection(host);
3070 #ifdef SDHCI_USE_LEDS_CLASS
3072 sdhci_reset(host, SDHCI_RESET_ALL);
3073 free_irq(host->irq, host);
3076 tasklet_kill(&host->card_tasklet);
3077 tasklet_kill(&host->finish_tasklet);
3082 EXPORT_SYMBOL_GPL(sdhci_add_host);
3084 void sdhci_remove_host(struct sdhci_host *host, int dead)
3086 unsigned long flags;
3089 spin_lock_irqsave(&host->lock, flags);
3091 host->flags |= SDHCI_DEVICE_DEAD;
3094 pr_err("%s: Controller removed during "
3095 " transfer!\n", mmc_hostname(host->mmc));
3097 host->mrq->cmd->error = -ENOMEDIUM;
3098 tasklet_schedule(&host->finish_tasklet);
3101 spin_unlock_irqrestore(&host->lock, flags);
3104 sdhci_disable_card_detection(host);
3106 mmc_remove_host(host->mmc);
3108 #ifdef SDHCI_USE_LEDS_CLASS
3109 led_classdev_unregister(&host->led);
3113 sdhci_reset(host, SDHCI_RESET_ALL);
3115 free_irq(host->irq, host);
3117 del_timer_sync(&host->timer);
3119 tasklet_kill(&host->card_tasklet);
3120 tasklet_kill(&host->finish_tasklet);
3123 regulator_put(host->vmmc);
3125 kfree(host->adma_desc);
3126 kfree(host->align_buffer);
3128 host->adma_desc = NULL;
3129 host->align_buffer = NULL;
3132 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3134 void sdhci_free_host(struct sdhci_host *host)
3136 mmc_free_host(host->mmc);
3139 EXPORT_SYMBOL_GPL(sdhci_free_host);
3141 /*****************************************************************************\
3143 * Driver init/exit *
3145 \*****************************************************************************/
3147 static int __init sdhci_drv_init(void)
3150 ": Secure Digital Host Controller Interface driver\n");
3151 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3156 static void __exit sdhci_drv_exit(void)
3160 module_init(sdhci_drv_init);
3161 module_exit(sdhci_drv_exit);
3163 module_param(debug_quirks, uint, 0444);
3164 module_param(debug_quirks2, uint, 0444);
3166 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3167 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3168 MODULE_LICENSE("GPL");
3170 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3171 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");