2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
13 * Controller registers
16 #define SDHCI_DMA_ADDRESS 0x00
18 #define SDHCI_BLOCK_SIZE 0x04
19 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
21 #define SDHCI_BLOCK_COUNT 0x06
23 #define SDHCI_ARGUMENT 0x08
25 #define SDHCI_TRANSFER_MODE 0x0C
26 #define SDHCI_TRNS_DMA 0x01
27 #define SDHCI_TRNS_BLK_CNT_EN 0x02
28 #define SDHCI_TRNS_ACMD12 0x04
29 #define SDHCI_TRNS_READ 0x10
30 #define SDHCI_TRNS_MULTI 0x20
32 #define SDHCI_COMMAND 0x0E
33 #define SDHCI_CMD_RESP_MASK 0x03
34 #define SDHCI_CMD_CRC 0x08
35 #define SDHCI_CMD_INDEX 0x10
36 #define SDHCI_CMD_DATA 0x20
38 #define SDHCI_CMD_RESP_NONE 0x00
39 #define SDHCI_CMD_RESP_LONG 0x01
40 #define SDHCI_CMD_RESP_SHORT 0x02
41 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
43 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
45 #define SDHCI_RESPONSE 0x10
47 #define SDHCI_BUFFER 0x20
49 #define SDHCI_PRESENT_STATE 0x24
50 #define SDHCI_CMD_INHIBIT 0x00000001
51 #define SDHCI_DATA_INHIBIT 0x00000002
52 #define SDHCI_DOING_WRITE 0x00000100
53 #define SDHCI_DOING_READ 0x00000200
54 #define SDHCI_SPACE_AVAILABLE 0x00000400
55 #define SDHCI_DATA_AVAILABLE 0x00000800
56 #define SDHCI_CARD_PRESENT 0x00010000
57 #define SDHCI_WRITE_PROTECT 0x00080000
59 #define SDHCI_HOST_CONTROL 0x28
60 #define SDHCI_CTRL_LED 0x01
61 #define SDHCI_CTRL_4BITBUS 0x02
62 #define SDHCI_CTRL_HISPD 0x04
63 #define SDHCI_CTRL_DMA_MASK 0x18
64 #define SDHCI_CTRL_SDMA 0x00
65 #define SDHCI_CTRL_ADMA1 0x08
66 #define SDHCI_CTRL_ADMA32 0x10
67 #define SDHCI_CTRL_ADMA64 0x18
69 #define SDHCI_POWER_CONTROL 0x29
70 #define SDHCI_POWER_ON 0x01
71 #define SDHCI_POWER_180 0x0A
72 #define SDHCI_POWER_300 0x0C
73 #define SDHCI_POWER_330 0x0E
75 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
77 #define SDHCI_WAKE_UP_CONTROL 0x2B
79 #define SDHCI_CLOCK_CONTROL 0x2C
80 #define SDHCI_DIVIDER_SHIFT 8
81 #define SDHCI_CLOCK_CARD_EN 0x0004
82 #define SDHCI_CLOCK_INT_STABLE 0x0002
83 #define SDHCI_CLOCK_INT_EN 0x0001
85 #define SDHCI_TIMEOUT_CONTROL 0x2E
87 #define SDHCI_SOFTWARE_RESET 0x2F
88 #define SDHCI_RESET_ALL 0x01
89 #define SDHCI_RESET_CMD 0x02
90 #define SDHCI_RESET_DATA 0x04
92 #define SDHCI_INT_STATUS 0x30
93 #define SDHCI_INT_ENABLE 0x34
94 #define SDHCI_SIGNAL_ENABLE 0x38
95 #define SDHCI_INT_RESPONSE 0x00000001
96 #define SDHCI_INT_DATA_END 0x00000002
97 #define SDHCI_INT_DMA_END 0x00000008
98 #define SDHCI_INT_SPACE_AVAIL 0x00000010
99 #define SDHCI_INT_DATA_AVAIL 0x00000020
100 #define SDHCI_INT_CARD_INSERT 0x00000040
101 #define SDHCI_INT_CARD_REMOVE 0x00000080
102 #define SDHCI_INT_CARD_INT 0x00000100
103 #define SDHCI_INT_ERROR 0x00008000
104 #define SDHCI_INT_TIMEOUT 0x00010000
105 #define SDHCI_INT_CRC 0x00020000
106 #define SDHCI_INT_END_BIT 0x00040000
107 #define SDHCI_INT_INDEX 0x00080000
108 #define SDHCI_INT_DATA_TIMEOUT 0x00100000
109 #define SDHCI_INT_DATA_CRC 0x00200000
110 #define SDHCI_INT_DATA_END_BIT 0x00400000
111 #define SDHCI_INT_BUS_POWER 0x00800000
112 #define SDHCI_INT_ACMD12ERR 0x01000000
113 #define SDHCI_INT_ADMA_ERROR 0x02000000
115 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
116 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
118 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
119 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
120 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
121 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
122 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
123 SDHCI_INT_DATA_END_BIT)
125 #define SDHCI_ACMD12_ERR 0x3C
129 #define SDHCI_CAPABILITIES 0x40
130 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
131 #define SDHCI_TIMEOUT_CLK_SHIFT 0
132 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
133 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
134 #define SDHCI_CLOCK_BASE_SHIFT 8
135 #define SDHCI_MAX_BLOCK_MASK 0x00030000
136 #define SDHCI_MAX_BLOCK_SHIFT 16
137 #define SDHCI_CAN_DO_ADMA2 0x00080000
138 #define SDHCI_CAN_DO_ADMA1 0x00100000
139 #define SDHCI_CAN_DO_HISPD 0x00200000
140 #define SDHCI_CAN_DO_DMA 0x00400000
141 #define SDHCI_CAN_VDD_330 0x01000000
142 #define SDHCI_CAN_VDD_300 0x02000000
143 #define SDHCI_CAN_VDD_180 0x04000000
144 #define SDHCI_CAN_64BIT 0x10000000
146 /* 44-47 reserved for more caps */
148 #define SDHCI_MAX_CURRENT 0x48
150 /* 4C-4F reserved for more max current */
152 #define SDHCI_SET_ACMD12_ERROR 0x50
153 #define SDHCI_SET_INT_ERROR 0x52
155 #define SDHCI_ADMA_ERROR 0x54
159 #define SDHCI_ADMA_ADDRESS 0x58
163 #define SDHCI_SLOT_INT_STATUS 0xFC
165 #define SDHCI_HOST_VERSION 0xFE
166 #define SDHCI_VENDOR_VER_MASK 0xFF00
167 #define SDHCI_VENDOR_VER_SHIFT 8
168 #define SDHCI_SPEC_VER_MASK 0x00FF
169 #define SDHCI_SPEC_VER_SHIFT 0
170 #define SDHCI_SPEC_100 0
171 #define SDHCI_SPEC_200 1
176 /* Data set by hardware interface driver */
177 const char *hw_name; /* Hardware bus name */
179 unsigned int quirks; /* Deviations from spec. */
181 /* Controller doesn't honor resets unless we touch the clock register */
182 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
183 /* Controller has bad caps bits, but really supports DMA */
184 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
185 /* Controller doesn't like to be reset when there is no card inserted. */
186 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
187 /* Controller doesn't like clearing the power reg before a change */
188 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
189 /* Controller has flaky internal state so reset it on each ios change */
190 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
191 /* Controller has an unusable DMA engine */
192 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
193 /* Controller has an unusable ADMA engine */
194 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
195 /* Controller can only DMA from 32-bit aligned addresses */
196 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
197 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
198 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
199 /* Controller can only ADMA chunks that are a multiple of 32 bits */
200 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
201 /* Controller needs to be reset after each request to stay stable */
202 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
203 /* Controller needs voltage and power writes to happen separately */
204 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
205 /* Controller provides an incorrect timeout value for transfers */
206 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
208 int irq; /* Device IRQ */
209 void __iomem * ioaddr; /* Mapped address */
211 const struct sdhci_ops *ops; /* Low level hw interface */
214 struct mmc_host *mmc; /* MMC structure */
216 #ifdef CONFIG_LEDS_CLASS
217 struct led_classdev led; /* LED control */
220 spinlock_t lock; /* Mutex */
222 int flags; /* Host attributes */
223 #define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
224 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
225 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
226 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
228 unsigned int version; /* SDHCI spec. version */
230 unsigned int max_clk; /* Max possible freq (MHz) */
231 unsigned int timeout_clk; /* Timeout freq (KHz) */
233 unsigned int clock; /* Current clock (MHz) */
234 unsigned short power; /* Current voltage */
236 struct mmc_request *mrq; /* Current request */
237 struct mmc_command *cmd; /* Current command */
238 struct mmc_data *data; /* Current data request */
239 unsigned int data_early:1; /* Data finished before cmd */
241 struct scatterlist *cur_sg; /* We're working on this */
242 int num_sg; /* Entries left */
243 int offset; /* Offset into current sg */
244 int remain; /* Bytes left in current */
246 int sg_count; /* Mapped sg entries */
248 u8 *adma_desc; /* ADMA descriptor table */
249 u8 *align_buffer; /* Bounce buffer */
251 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
252 dma_addr_t align_addr; /* Mapped bounce buffer */
254 struct tasklet_struct card_tasklet; /* Tasklet structures */
255 struct tasklet_struct finish_tasklet;
257 struct timer_list timer; /* Timer for timeouts */
259 unsigned long private[0] ____cacheline_aligned;
264 int (*enable_dma)(struct sdhci_host *host);
268 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
270 extern void sdhci_free_host(struct sdhci_host *host);
272 static inline void *sdhci_priv(struct sdhci_host *host)
274 return (void *)host->private;
277 extern int sdhci_add_host(struct sdhci_host *host);
278 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
281 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
282 extern int sdhci_resume_host(struct sdhci_host *host);