2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
14 #include <linux/scatterlist.h>
15 #include <linux/compiler.h>
16 #include <linux/types.h>
20 * Controller registers
23 #define SDHCI_DMA_ADDRESS 0x00
25 #define SDHCI_BLOCK_SIZE 0x04
26 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
28 #define SDHCI_BLOCK_COUNT 0x06
30 #define SDHCI_ARGUMENT 0x08
32 #define SDHCI_TRANSFER_MODE 0x0C
33 #define SDHCI_TRNS_DMA 0x01
34 #define SDHCI_TRNS_BLK_CNT_EN 0x02
35 #define SDHCI_TRNS_ACMD12 0x04
36 #define SDHCI_TRNS_READ 0x10
37 #define SDHCI_TRNS_MULTI 0x20
39 #define SDHCI_COMMAND 0x0E
40 #define SDHCI_CMD_RESP_MASK 0x03
41 #define SDHCI_CMD_CRC 0x08
42 #define SDHCI_CMD_INDEX 0x10
43 #define SDHCI_CMD_DATA 0x20
45 #define SDHCI_CMD_RESP_NONE 0x00
46 #define SDHCI_CMD_RESP_LONG 0x01
47 #define SDHCI_CMD_RESP_SHORT 0x02
48 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
50 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
52 #define SDHCI_RESPONSE 0x10
54 #define SDHCI_BUFFER 0x20
56 #define SDHCI_PRESENT_STATE 0x24
57 #define SDHCI_CMD_INHIBIT 0x00000001
58 #define SDHCI_DATA_INHIBIT 0x00000002
59 #define SDHCI_DOING_WRITE 0x00000100
60 #define SDHCI_DOING_READ 0x00000200
61 #define SDHCI_SPACE_AVAILABLE 0x00000400
62 #define SDHCI_DATA_AVAILABLE 0x00000800
63 #define SDHCI_CARD_PRESENT 0x00010000
64 #define SDHCI_WRITE_PROTECT 0x00080000
66 #define SDHCI_HOST_CONTROL 0x28
67 #define SDHCI_CTRL_LED 0x01
68 #define SDHCI_CTRL_4BITBUS 0x02
69 #define SDHCI_CTRL_HISPD 0x04
70 #define SDHCI_CTRL_DMA_MASK 0x18
71 #define SDHCI_CTRL_SDMA 0x00
72 #define SDHCI_CTRL_ADMA1 0x08
73 #define SDHCI_CTRL_ADMA32 0x10
74 #define SDHCI_CTRL_ADMA64 0x18
75 #define SDHCI_CTRL_8BITBUS 0x20
77 #define SDHCI_POWER_CONTROL 0x29
78 #define SDHCI_POWER_ON 0x01
79 #define SDHCI_POWER_180 0x0A
80 #define SDHCI_POWER_300 0x0C
81 #define SDHCI_POWER_330 0x0E
83 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
85 #define SDHCI_WAKE_UP_CONTROL 0x2B
87 #define SDHCI_CLOCK_CONTROL 0x2C
88 #define SDHCI_DIVIDER_SHIFT 8
89 #define SDHCI_DIVIDER_HI_SHIFT 6
90 #define SDHCI_DIV_MASK 0xFF
91 #define SDHCI_DIV_MASK_LEN 8
92 #define SDHCI_DIV_HI_MASK 0x300
93 #define SDHCI_CLOCK_CARD_EN 0x0004
94 #define SDHCI_CLOCK_INT_STABLE 0x0002
95 #define SDHCI_CLOCK_INT_EN 0x0001
97 #define SDHCI_TIMEOUT_CONTROL 0x2E
99 #define SDHCI_SOFTWARE_RESET 0x2F
100 #define SDHCI_RESET_ALL 0x01
101 #define SDHCI_RESET_CMD 0x02
102 #define SDHCI_RESET_DATA 0x04
104 #define SDHCI_INT_STATUS 0x30
105 #define SDHCI_INT_ENABLE 0x34
106 #define SDHCI_SIGNAL_ENABLE 0x38
107 #define SDHCI_INT_RESPONSE 0x00000001
108 #define SDHCI_INT_DATA_END 0x00000002
109 #define SDHCI_INT_DMA_END 0x00000008
110 #define SDHCI_INT_SPACE_AVAIL 0x00000010
111 #define SDHCI_INT_DATA_AVAIL 0x00000020
112 #define SDHCI_INT_CARD_INSERT 0x00000040
113 #define SDHCI_INT_CARD_REMOVE 0x00000080
114 #define SDHCI_INT_CARD_INT 0x00000100
115 #define SDHCI_INT_ERROR 0x00008000
116 #define SDHCI_INT_TIMEOUT 0x00010000
117 #define SDHCI_INT_CRC 0x00020000
118 #define SDHCI_INT_END_BIT 0x00040000
119 #define SDHCI_INT_INDEX 0x00080000
120 #define SDHCI_INT_DATA_TIMEOUT 0x00100000
121 #define SDHCI_INT_DATA_CRC 0x00200000
122 #define SDHCI_INT_DATA_END_BIT 0x00400000
123 #define SDHCI_INT_BUS_POWER 0x00800000
124 #define SDHCI_INT_ACMD12ERR 0x01000000
125 #define SDHCI_INT_ADMA_ERROR 0x02000000
127 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
128 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
130 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
131 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
132 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
133 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
134 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
135 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
136 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
138 #define SDHCI_ACMD12_ERR 0x3C
142 #define SDHCI_CAPABILITIES 0x40
143 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
144 #define SDHCI_TIMEOUT_CLK_SHIFT 0
145 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
146 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
147 #define SDHCI_CLOCK_BASE_SHIFT 8
148 #define SDHCI_MAX_BLOCK_MASK 0x00030000
149 #define SDHCI_MAX_BLOCK_SHIFT 16
150 #define SDHCI_CAN_DO_ADMA2 0x00080000
151 #define SDHCI_CAN_DO_ADMA1 0x00100000
152 #define SDHCI_CAN_DO_HISPD 0x00200000
153 #define SDHCI_CAN_DO_SDMA 0x00400000
154 #define SDHCI_CAN_VDD_330 0x01000000
155 #define SDHCI_CAN_VDD_300 0x02000000
156 #define SDHCI_CAN_VDD_180 0x04000000
157 #define SDHCI_CAN_64BIT 0x10000000
159 /* 44-47 reserved for more caps */
161 #define SDHCI_MAX_CURRENT 0x48
163 /* 4C-4F reserved for more max current */
165 #define SDHCI_SET_ACMD12_ERROR 0x50
166 #define SDHCI_SET_INT_ERROR 0x52
168 #define SDHCI_ADMA_ERROR 0x54
172 #define SDHCI_ADMA_ADDRESS 0x58
176 #define SDHCI_SLOT_INT_STATUS 0xFC
178 #define SDHCI_HOST_VERSION 0xFE
179 #define SDHCI_VENDOR_VER_MASK 0xFF00
180 #define SDHCI_VENDOR_VER_SHIFT 8
181 #define SDHCI_SPEC_VER_MASK 0x00FF
182 #define SDHCI_SPEC_VER_SHIFT 0
183 #define SDHCI_SPEC_100 0
184 #define SDHCI_SPEC_200 1
185 #define SDHCI_SPEC_300 2
190 /* Data set by hardware interface driver */
191 const char *hw_name; /* Hardware bus name */
193 unsigned int quirks; /* Deviations from spec. */
195 /* Controller doesn't honor resets unless we touch the clock register */
196 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
197 /* Controller has bad caps bits, but really supports DMA */
198 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
199 /* Controller doesn't like to be reset when there is no card inserted. */
200 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
201 /* Controller doesn't like clearing the power reg before a change */
202 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
203 /* Controller has flaky internal state so reset it on each ios change */
204 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
205 /* Controller has an unusable DMA engine */
206 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
207 /* Controller has an unusable ADMA engine */
208 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
209 /* Controller can only DMA from 32-bit aligned addresses */
210 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
211 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
212 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
213 /* Controller can only ADMA chunks that are a multiple of 32 bits */
214 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
215 /* Controller needs to be reset after each request to stay stable */
216 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
217 /* Controller needs voltage and power writes to happen separately */
218 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
219 /* Controller provides an incorrect timeout value for transfers */
220 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
221 /* Controller has an issue with buffer bits for small transfers */
222 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
223 /* Controller does not provide transfer-complete interrupt when not busy */
224 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
225 /* Controller has unreliable card detection */
226 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
227 /* Controller reports inverted write-protect state */
228 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
229 /* Controller has nonstandard clock management */
230 #define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
231 /* Controller does not like fast PIO transfers */
232 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
233 /* Controller losing signal/interrupt enable states after reset */
234 #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
235 /* Controller has to be forced to use block size of 2048 bytes */
236 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
237 /* Controller cannot do multi-block transfers */
238 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
239 /* Controller can only handle 1-bit data transfers */
240 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
241 /* Controller needs 10ms delay between applying power and clock */
242 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
243 /* Controller uses SDCLK instead of TMCLK for data timeouts */
244 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
245 /* Controller reports wrong base clock capability */
246 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
247 /* Controller cannot support End Attribute in NOP ADMA descriptor */
248 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
249 /* Controller is missing device caps. Use caps provided by host */
250 #define SDHCI_QUIRK_MISSING_CAPS (1<<27)
251 /* Controller uses Auto CMD12 command to stop the transfer */
252 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
253 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
254 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
256 int irq; /* Device IRQ */
257 void __iomem * ioaddr; /* Mapped address */
259 const struct sdhci_ops *ops; /* Low level hw interface */
261 struct regulator *vmmc; /* Power regulator */
264 struct mmc_host *mmc; /* MMC structure */
265 u64 dma_mask; /* custom DMA mask */
267 #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
268 struct led_classdev led; /* LED control */
272 spinlock_t lock; /* Mutex */
274 int flags; /* Host attributes */
275 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
276 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
277 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
278 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
280 unsigned int version; /* SDHCI spec. version */
282 unsigned int max_clk; /* Max possible freq (MHz) */
283 unsigned int timeout_clk; /* Timeout freq (KHz) */
285 unsigned int clock; /* Current clock (MHz) */
286 u8 pwr; /* Current voltage */
288 struct mmc_request *mrq; /* Current request */
289 struct mmc_command *cmd; /* Current command */
290 struct mmc_data *data; /* Current data request */
291 unsigned int data_early:1; /* Data finished before cmd */
293 struct sg_mapping_iter sg_miter; /* SG state for PIO */
294 unsigned int blocks; /* remaining PIO blocks */
296 int sg_count; /* Mapped sg entries */
298 u8 *adma_desc; /* ADMA descriptor table */
299 u8 *align_buffer; /* Bounce buffer */
301 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
302 dma_addr_t align_addr; /* Mapped bounce buffer */
304 struct tasklet_struct card_tasklet; /* Tasklet structures */
305 struct tasklet_struct finish_tasklet;
307 struct timer_list timer; /* Timer for timeouts */
309 unsigned int caps; /* Alternative capabilities */
311 unsigned long private[0] ____cacheline_aligned;
316 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
317 u32 (*read_l)(struct sdhci_host *host, int reg);
318 u16 (*read_w)(struct sdhci_host *host, int reg);
319 u8 (*read_b)(struct sdhci_host *host, int reg);
320 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
321 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
322 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
325 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
327 int (*enable_dma)(struct sdhci_host *host);
328 unsigned int (*get_max_clock)(struct sdhci_host *host);
329 unsigned int (*get_min_clock)(struct sdhci_host *host);
330 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
333 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
335 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
337 if (unlikely(host->ops->write_l))
338 host->ops->write_l(host, val, reg);
340 writel(val, host->ioaddr + reg);
343 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
345 if (unlikely(host->ops->write_w))
346 host->ops->write_w(host, val, reg);
348 writew(val, host->ioaddr + reg);
351 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
353 if (unlikely(host->ops->write_b))
354 host->ops->write_b(host, val, reg);
356 writeb(val, host->ioaddr + reg);
359 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
361 if (unlikely(host->ops->read_l))
362 return host->ops->read_l(host, reg);
364 return readl(host->ioaddr + reg);
367 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
369 if (unlikely(host->ops->read_w))
370 return host->ops->read_w(host, reg);
372 return readw(host->ioaddr + reg);
375 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
377 if (unlikely(host->ops->read_b))
378 return host->ops->read_b(host, reg);
380 return readb(host->ioaddr + reg);
385 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
387 writel(val, host->ioaddr + reg);
390 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
392 writew(val, host->ioaddr + reg);
395 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
397 writeb(val, host->ioaddr + reg);
400 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
402 return readl(host->ioaddr + reg);
405 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
407 return readw(host->ioaddr + reg);
410 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
412 return readb(host->ioaddr + reg);
415 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
417 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
419 extern void sdhci_free_host(struct sdhci_host *host);
421 static inline void *sdhci_priv(struct sdhci_host *host)
423 return (void *)host->private;
426 extern void sdhci_card_detect(struct sdhci_host *host);
427 extern int sdhci_add_host(struct sdhci_host *host);
428 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
431 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
432 extern int sdhci_resume_host(struct sdhci_host *host);
435 #endif /* __SDHCI_H */