drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/pagemap.h>
  58 #include <linux/platform_device.h>
  59 #include <linux/pm_runtime.h>
  60 #include <linux/spinlock.h>
  61 #include <linux/module.h>
  62
  63 #define DRIVER_NAME     "sh_mmcif"
  64 #define DRIVER_VERSION  "2010-04-28"
  65
  66 /* CE_CMD_SET */
  67 #define CMD_MASK                0x3f000000
  68 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  69 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  70 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  71 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  72 #define CMD_SET_CCSEN           (1 << 20)
  73 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  74 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  75 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  76 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  77 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  78 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  79 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  80 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  81 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  82 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  83 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  84 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  85 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  86 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  87 #define CMD_SET_CCSH            (1 << 5)
  88 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  89 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  90 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  91
  92 /* CE_CMD_CTRL */
  93 #define CMD_CTRL_BREAK          (1 << 0)
  94
  95 /* CE_BLOCK_SET */
  96 #define BLOCK_SIZE_MASK         0x0000ffff
  97
  98 /* CE_INT */
  99 #define INT_CCSDE               (1 << 29)
 100 #define INT_CMD12DRE            (1 << 26)
 101 #define INT_CMD12RBE            (1 << 25)
 102 #define INT_CMD12CRE            (1 << 24)
 103 #define INT_DTRANE              (1 << 23)
 104 #define INT_BUFRE               (1 << 22)
 105 #define INT_BUFWEN              (1 << 21)
 106 #define INT_BUFREN              (1 << 20)
 107 #define INT_CCSRCV              (1 << 19)
 108 #define INT_RBSYE               (1 << 17)
 109 #define INT_CRSPE               (1 << 16)
 110 #define INT_CMDVIO              (1 << 15)
 111 #define INT_BUFVIO              (1 << 14)
 112 #define INT_WDATERR             (1 << 11)
 113 #define INT_RDATERR             (1 << 10)
 114 #define INT_RIDXERR             (1 << 9)
 115 #define INT_RSPERR              (1 << 8)
 116 #define INT_CCSTO               (1 << 5)
 117 #define INT_CRCSTO              (1 << 4)
 118 #define INT_WDATTO              (1 << 3)
 119 #define INT_RDATTO              (1 << 2)
 120 #define INT_RBSYTO              (1 << 1)
 121 #define INT_RSPTO               (1 << 0)
 122 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 123                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 124                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 125                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 126
 127 /* CE_INT_MASK */
 128 #define MASK_ALL                0x00000000
 129 #define MASK_MCCSDE             (1 << 29)
 130 #define MASK_MCMD12DRE          (1 << 26)
 131 #define MASK_MCMD12RBE          (1 << 25)
 132 #define MASK_MCMD12CRE          (1 << 24)
 133 #define MASK_MDTRANE            (1 << 23)
 134 #define MASK_MBUFRE             (1 << 22)
 135 #define MASK_MBUFWEN            (1 << 21)
 136 #define MASK_MBUFREN            (1 << 20)
 137 #define MASK_MCCSRCV            (1 << 19)
 138 #define MASK_MRBSYE             (1 << 17)
 139 #define MASK_MCRSPE             (1 << 16)
 140 #define MASK_MCMDVIO            (1 << 15)
 141 #define MASK_MBUFVIO            (1 << 14)
 142 #define MASK_MWDATERR           (1 << 11)
 143 #define MASK_MRDATERR           (1 << 10)
 144 #define MASK_MRIDXERR           (1 << 9)
 145 #define MASK_MRSPERR            (1 << 8)
 146 #define MASK_MCCSTO             (1 << 5)
 147 #define MASK_MCRCSTO            (1 << 4)
 148 #define MASK_MWDATTO            (1 << 3)
 149 #define MASK_MRDATTO            (1 << 2)
 150 #define MASK_MRBSYTO            (1 << 1)
 151 #define MASK_MRSPTO             (1 << 0)
 152
 153 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 154                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 155                                  MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
 156                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 157
 158 /* CE_HOST_STS1 */
 159 #define STS1_CMDSEQ             (1 << 31)
 160
 161 /* CE_HOST_STS2 */
 162 #define STS2_CRCSTE             (1 << 31)
 163 #define STS2_CRC16E             (1 << 30)
 164 #define STS2_AC12CRCE           (1 << 29)
 165 #define STS2_RSPCRC7E           (1 << 28)
 166 #define STS2_CRCSTEBE           (1 << 27)
 167 #define STS2_RDATEBE            (1 << 26)
 168 #define STS2_AC12REBE           (1 << 25)
 169 #define STS2_RSPEBE             (1 << 24)
 170 #define STS2_AC12IDXE           (1 << 23)
 171 #define STS2_RSPIDXE            (1 << 22)
 172 #define STS2_CCSTO              (1 << 15)
 173 #define STS2_RDATTO             (1 << 14)
 174 #define STS2_DATBSYTO           (1 << 13)
 175 #define STS2_CRCSTTO            (1 << 12)
 176 #define STS2_AC12BSYTO          (1 << 11)
 177 #define STS2_RSPBSYTO           (1 << 10)
 178 #define STS2_AC12RSPTO          (1 << 9)
 179 #define STS2_RSPTO              (1 << 8)
 180 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 181                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 182 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 183                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 184                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 185                                  STS2_AC12RSPTO | STS2_RSPTO)
 186
 187 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 188 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 189 #define CLKDEV_INIT             400000   /* 400 KHz */
 190
 191 enum mmcif_state {
 192         STATE_IDLE,
 193         STATE_REQUEST,
 194         STATE_IOS,
 195 };
 196
 197 enum mmcif_wait_for {
 198         MMCIF_WAIT_FOR_REQUEST,
 199         MMCIF_WAIT_FOR_CMD,
 200         MMCIF_WAIT_FOR_MREAD,
 201         MMCIF_WAIT_FOR_MWRITE,
 202         MMCIF_WAIT_FOR_READ,
 203         MMCIF_WAIT_FOR_WRITE,
 204         MMCIF_WAIT_FOR_READ_END,
 205         MMCIF_WAIT_FOR_WRITE_END,
 206         MMCIF_WAIT_FOR_STOP,
 207 };
 208
 209 struct sh_mmcif_host {
 210         struct mmc_host *mmc;
 211         struct mmc_data *data;
 212         struct mmc_request *mrq;
 213         struct platform_device *pd;
 214         struct sh_dmae_slave dma_slave_tx;
 215         struct sh_dmae_slave dma_slave_rx;
 216         struct clk *hclk;
 217         unsigned int clk;
 218         int bus_width;
 219         bool sd_error;
 220         bool dying;
 221         long timeout;
 222         void __iomem *addr;
 223         u32 *pio_ptr;
 224         spinlock_t lock;                /* protect sh_mmcif_host::state */
 225         enum mmcif_state state;
 226         enum mmcif_wait_for wait_for;
 227         struct delayed_work timeout_work;
 228         size_t blocksize;
 229         int sg_idx;
 230         int sg_blkidx;
 231         bool power;
 232         bool card_present;
 233
 234         /* DMA support */
 235         struct dma_chan         *chan_rx;
 236         struct dma_chan         *chan_tx;
 237         struct completion       dma_complete;
 238         bool                    dma_active;
 239 };
 240
 241 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 242                                         unsigned int reg, u32 val)
 243 {
 244         writel(val | readl(host->addr + reg), host->addr + reg);
 245 }
 246
 247 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 248                                         unsigned int reg, u32 val)
 249 {
 250         writel(~val & readl(host->addr + reg), host->addr + reg);
 251 }
 252
 253 static void mmcif_dma_complete(void *arg)
 254 {
 255         struct sh_mmcif_host *host = arg;
 256         dev_dbg(&host->pd->dev, "Command completed\n");
 257
 258         if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
 259                  dev_name(&host->pd->dev)))
 260                 return;
 261
 262         if (host->data->flags & MMC_DATA_READ)
 263                 dma_unmap_sg(host->chan_rx->device->dev,
 264                              host->data->sg, host->data->sg_len,
 265                              DMA_FROM_DEVICE);
 266         else
 267                 dma_unmap_sg(host->chan_tx->device->dev,
 268                              host->data->sg, host->data->sg_len,
 269                              DMA_TO_DEVICE);
 270
 271         complete(&host->dma_complete);
 272 }
 273
 274 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 275 {
 276         struct scatterlist *sg = host->data->sg;
 277         struct dma_async_tx_descriptor *desc = NULL;
 278         struct dma_chan *chan = host->chan_rx;
 279         dma_cookie_t cookie = -EINVAL;
 280         int ret;
 281
 282         ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
 283                          DMA_FROM_DEVICE);
 284         if (ret > 0) {
 285                 host->dma_active = true;
 286                 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
 287                         DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 288         }
 289
 290         if (desc) {
 291                 desc->callback = mmcif_dma_complete;
 292                 desc->callback_param = host;
 293                 cookie = dmaengine_submit(desc);
 294                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 295                 dma_async_issue_pending(chan);
 296         }
 297         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 298                 __func__, host->data->sg_len, ret, cookie);
 299
 300         if (!desc) {
 301                 /* DMA failed, fall back to PIO */
 302                 if (ret >= 0)
 303                         ret = -EIO;
 304                 host->chan_rx = NULL;
 305                 host->dma_active = false;
 306                 dma_release_channel(chan);
 307                 /* Free the Tx channel too */
 308                 chan = host->chan_tx;
 309                 if (chan) {
 310                         host->chan_tx = NULL;
 311                         dma_release_channel(chan);
 312                 }
 313                 dev_warn(&host->pd->dev,
 314                          "DMA failed: %d, falling back to PIO\n", ret);
 315                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 316         }
 317
 318         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 319                 desc, cookie, host->data->sg_len);
 320 }
 321
 322 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 323 {
 324         struct scatterlist *sg = host->data->sg;
 325         struct dma_async_tx_descriptor *desc = NULL;
 326         struct dma_chan *chan = host->chan_tx;
 327         dma_cookie_t cookie = -EINVAL;
 328         int ret;
 329
 330         ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
 331                          DMA_TO_DEVICE);
 332         if (ret > 0) {
 333                 host->dma_active = true;
 334                 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
 335                         DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 336         }
 337
 338         if (desc) {
 339                 desc->callback = mmcif_dma_complete;
 340                 desc->callback_param = host;
 341                 cookie = dmaengine_submit(desc);
 342                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 343                 dma_async_issue_pending(chan);
 344         }
 345         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 346                 __func__, host->data->sg_len, ret, cookie);
 347
 348         if (!desc) {
 349                 /* DMA failed, fall back to PIO */
 350                 if (ret >= 0)
 351                         ret = -EIO;
 352                 host->chan_tx = NULL;
 353                 host->dma_active = false;
 354                 dma_release_channel(chan);
 355                 /* Free the Rx channel too */
 356                 chan = host->chan_rx;
 357                 if (chan) {
 358                         host->chan_rx = NULL;
 359                         dma_release_channel(chan);
 360                 }
 361                 dev_warn(&host->pd->dev,
 362                          "DMA failed: %d, falling back to PIO\n", ret);
 363                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 364         }
 365
 366         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 367                 desc, cookie);
 368 }
 369
 370 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
 371 {
 372         dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
 373         chan->private = arg;
 374         return true;
 375 }
 376
 377 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 378                                  struct sh_mmcif_plat_data *pdata)
 379 {
 380         struct sh_dmae_slave *tx, *rx;
 381         host->dma_active = false;
 382
 383         /* We can only either use DMA for both Tx and Rx or not use it at all */
 384         if (pdata->dma) {
 385                 dev_warn(&host->pd->dev,
 386                          "Update your platform to use embedded DMA slave IDs\n");
 387                 tx = &pdata->dma->chan_priv_tx;
 388                 rx = &pdata->dma->chan_priv_rx;
 389         } else {
 390                 tx = &host->dma_slave_tx;
 391                 tx->slave_id = pdata->slave_id_tx;
 392                 rx = &host->dma_slave_rx;
 393                 rx->slave_id = pdata->slave_id_rx;
 394         }
 395         if (tx->slave_id > 0 && rx->slave_id > 0) {
 396                 dma_cap_mask_t mask;
 397
 398                 dma_cap_zero(mask);
 399                 dma_cap_set(DMA_SLAVE, mask);
 400
 401                 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx);
 402                 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
 403                         host->chan_tx);
 404
 405                 if (!host->chan_tx)
 406                         return;
 407
 408                 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx);
 409                 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
 410                         host->chan_rx);
 411
 412                 if (!host->chan_rx) {
 413                         dma_release_channel(host->chan_tx);
 414                         host->chan_tx = NULL;
 415                         return;
 416                 }
 417
 418                 init_completion(&host->dma_complete);
 419         }
 420 }
 421
 422 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 423 {
 424         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 425         /* Descriptors are freed automatically */
 426         if (host->chan_tx) {
 427                 struct dma_chan *chan = host->chan_tx;
 428                 host->chan_tx = NULL;
 429                 dma_release_channel(chan);
 430         }
 431         if (host->chan_rx) {
 432                 struct dma_chan *chan = host->chan_rx;
 433                 host->chan_rx = NULL;
 434                 dma_release_channel(chan);
 435         }
 436
 437         host->dma_active = false;
 438 }
 439
 440 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 441 {
 442         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 443
 444         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 445         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 446
 447         if (!clk)
 448                 return;
 449         if (p->sup_pclk && clk == host->clk)
 450                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 451         else
 452                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 453                                 ((fls(host->clk / clk) - 1) << 16));
 454
 455         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 456 }
 457
 458 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 459 {
 460         u32 tmp;
 461
 462         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 463
 464         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 465         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 466         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 467                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 468         /* byte swap on */
 469         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 470 }
 471
 472 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 473 {
 474         u32 state1, state2;
 475         int ret, timeout;
 476
 477         host->sd_error = false;
 478
 479         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 480         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 481         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 482         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 483
 484         if (state1 & STS1_CMDSEQ) {
 485                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 486                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 487                 for (timeout = 10000000; timeout; timeout--) {
 488                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 489                               & STS1_CMDSEQ))
 490                                 break;
 491                         mdelay(1);
 492                 }
 493                 if (!timeout) {
 494                         dev_err(&host->pd->dev,
 495                                 "Forced end of command sequence timeout err\n");
 496                         return -EIO;
 497                 }
 498                 sh_mmcif_sync_reset(host);
 499                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 500                 return -EIO;
 501         }
 502
 503         if (state2 & STS2_CRC_ERR) {
 504                 dev_dbg(&host->pd->dev, ": CRC error\n");
 505                 ret = -EIO;
 506         } else if (state2 & STS2_TIMEOUT_ERR) {
 507                 dev_dbg(&host->pd->dev, ": Timeout\n");
 508                 ret = -ETIMEDOUT;
 509         } else {
 510                 dev_dbg(&host->pd->dev, ": End/Index error\n");
 511                 ret = -EIO;
 512         }
 513         return ret;
 514 }
 515
 516 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 517 {
 518         struct mmc_data *data = host->mrq->data;
 519
 520         host->sg_blkidx += host->blocksize;
 521
 522         /* data->sg->length must be a multiple of host->blocksize? */
 523         BUG_ON(host->sg_blkidx > data->sg->length);
 524
 525         if (host->sg_blkidx == data->sg->length) {
 526                 host->sg_blkidx = 0;
 527                 if (++host->sg_idx < data->sg_len)
 528                         host->pio_ptr = sg_virt(++data->sg);
 529         } else {
 530                 host->pio_ptr = p;
 531         }
 532
 533         if (host->sg_idx == data->sg_len)
 534                 return false;
 535
 536         return true;
 537 }
 538
 539 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 540                                  struct mmc_request *mrq)
 541 {
 542         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 543                            BLOCK_SIZE_MASK) + 3;
 544
 545         host->wait_for = MMCIF_WAIT_FOR_READ;
 546         schedule_delayed_work(&host->timeout_work, host->timeout);
 547
 548         /* buf read enable */
 549         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 550 }
 551
 552 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 553 {
 554         struct mmc_data *data = host->mrq->data;
 555         u32 *p = sg_virt(data->sg);
 556         int i;
 557
 558         if (host->sd_error) {
 559                 data->error = sh_mmcif_error_manage(host);
 560                 return false;
 561         }
 562
 563         for (i = 0; i < host->blocksize / 4; i++)
 564                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 565
 566         /* buffer read end */
 567         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 568         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 569
 570         return true;
 571 }
 572
 573 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 574                                 struct mmc_request *mrq)
 575 {
 576         struct mmc_data *data = mrq->data;
 577
 578         if (!data->sg_len || !data->sg->length)
 579                 return;
 580
 581         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 582                 BLOCK_SIZE_MASK;
 583
 584         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 585         host->sg_idx = 0;
 586         host->sg_blkidx = 0;
 587         host->pio_ptr = sg_virt(data->sg);
 588         schedule_delayed_work(&host->timeout_work, host->timeout);
 589         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 590 }
 591
 592 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 593 {
 594         struct mmc_data *data = host->mrq->data;
 595         u32 *p = host->pio_ptr;
 596         int i;
 597
 598         if (host->sd_error) {
 599                 data->error = sh_mmcif_error_manage(host);
 600                 return false;
 601         }
 602
 603         BUG_ON(!data->sg->length);
 604
 605         for (i = 0; i < host->blocksize / 4; i++)
 606                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 607
 608         if (!sh_mmcif_next_block(host, p))
 609                 return false;
 610
 611         schedule_delayed_work(&host->timeout_work, host->timeout);
 612         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 613
 614         return true;
 615 }
 616
 617 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 618                                         struct mmc_request *mrq)
 619 {
 620         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 621                            BLOCK_SIZE_MASK) + 3;
 622
 623         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 624         schedule_delayed_work(&host->timeout_work, host->timeout);
 625
 626         /* buf write enable */
 627         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 628 }
 629
 630 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 631 {
 632         struct mmc_data *data = host->mrq->data;
 633         u32 *p = sg_virt(data->sg);
 634         int i;
 635
 636         if (host->sd_error) {
 637                 data->error = sh_mmcif_error_manage(host);
 638                 return false;
 639         }
 640
 641         for (i = 0; i < host->blocksize / 4; i++)
 642                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 643
 644         /* buffer write end */
 645         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 646         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 647
 648         return true;
 649 }
 650
 651 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 652                                 struct mmc_request *mrq)
 653 {
 654         struct mmc_data *data = mrq->data;
 655
 656         if (!data->sg_len || !data->sg->length)
 657                 return;
 658
 659         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 660                 BLOCK_SIZE_MASK;
 661
 662         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 663         host->sg_idx = 0;
 664         host->sg_blkidx = 0;
 665         host->pio_ptr = sg_virt(data->sg);
 666         schedule_delayed_work(&host->timeout_work, host->timeout);
 667         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 668 }
 669
 670 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 671 {
 672         struct mmc_data *data = host->mrq->data;
 673         u32 *p = host->pio_ptr;
 674         int i;
 675
 676         if (host->sd_error) {
 677                 data->error = sh_mmcif_error_manage(host);
 678                 return false;
 679         }
 680
 681         BUG_ON(!data->sg->length);
 682
 683         for (i = 0; i < host->blocksize / 4; i++)
 684                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 685
 686         if (!sh_mmcif_next_block(host, p))
 687                 return false;
 688
 689         schedule_delayed_work(&host->timeout_work, host->timeout);
 690         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 691
 692         return true;
 693 }
 694
 695 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 696                                                 struct mmc_command *cmd)
 697 {
 698         if (cmd->flags & MMC_RSP_136) {
 699                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 700                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 701                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 702                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 703         } else
 704                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 705 }
 706
 707 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 708                                                 struct mmc_command *cmd)
 709 {
 710         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 711 }
 712
 713 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 714                 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
 715 {
 716         u32 tmp = 0;
 717
 718         /* Response Type check */
 719         switch (mmc_resp_type(cmd)) {
 720         case MMC_RSP_NONE:
 721                 tmp |= CMD_SET_RTYP_NO;
 722                 break;
 723         case MMC_RSP_R1:
 724         case MMC_RSP_R1B:
 725         case MMC_RSP_R3:
 726                 tmp |= CMD_SET_RTYP_6B;
 727                 break;
 728         case MMC_RSP_R2:
 729                 tmp |= CMD_SET_RTYP_17B;
 730                 break;
 731         default:
 732                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 733                 break;
 734         }
 735         switch (opc) {
 736         /* RBSY */
 737         case MMC_SWITCH:
 738         case MMC_STOP_TRANSMISSION:
 739         case MMC_SET_WRITE_PROT:
 740         case MMC_CLR_WRITE_PROT:
 741         case MMC_ERASE:
 742         case MMC_GEN_CMD:
 743                 tmp |= CMD_SET_RBSY;
 744                 break;
 745         }
 746         /* WDAT / DATW */
 747         if (host->data) {
 748                 tmp |= CMD_SET_WDAT;
 749                 switch (host->bus_width) {
 750                 case MMC_BUS_WIDTH_1:
 751                         tmp |= CMD_SET_DATW_1;
 752                         break;
 753                 case MMC_BUS_WIDTH_4:
 754                         tmp |= CMD_SET_DATW_4;
 755                         break;
 756                 case MMC_BUS_WIDTH_8:
 757                         tmp |= CMD_SET_DATW_8;
 758                         break;
 759                 default:
 760                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 761                         break;
 762                 }
 763         }
 764         /* DWEN */
 765         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 766                 tmp |= CMD_SET_DWEN;
 767         /* CMLTE/CMD12EN */
 768         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 769                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 770                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 771                                         mrq->data->blocks << 16);
 772         }
 773         /* RIDXC[1:0] check bits */
 774         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 775             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 776                 tmp |= CMD_SET_RIDXC_BITS;
 777         /* RCRC7C[1:0] check bits */
 778         if (opc == MMC_SEND_OP_COND)
 779                 tmp |= CMD_SET_CRC7C_BITS;
 780         /* RCRC7C[1:0] internal CRC7 */
 781         if (opc == MMC_ALL_SEND_CID ||
 782                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 783                 tmp |= CMD_SET_CRC7C_INTERNAL;
 784
 785         return opc = ((opc << 24) | tmp);
 786 }
 787
 788 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 789                                struct mmc_request *mrq, u32 opc)
 790 {
 791         switch (opc) {
 792         case MMC_READ_MULTIPLE_BLOCK:
 793                 sh_mmcif_multi_read(host, mrq);
 794                 return 0;
 795         case MMC_WRITE_MULTIPLE_BLOCK:
 796                 sh_mmcif_multi_write(host, mrq);
 797                 return 0;
 798         case MMC_WRITE_BLOCK:
 799                 sh_mmcif_single_write(host, mrq);
 800                 return 0;
 801         case MMC_READ_SINGLE_BLOCK:
 802         case MMC_SEND_EXT_CSD:
 803                 sh_mmcif_single_read(host, mrq);
 804                 return 0;
 805         default:
 806                 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
 807                 return -EINVAL;
 808         }
 809 }
 810
 811 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 812                                struct mmc_request *mrq)
 813 {
 814         struct mmc_command *cmd = mrq->cmd;
 815         u32 opc = cmd->opcode;
 816         u32 mask;
 817
 818         switch (opc) {
 819         /* response busy check */
 820         case MMC_SWITCH:
 821         case MMC_STOP_TRANSMISSION:
 822         case MMC_SET_WRITE_PROT:
 823         case MMC_CLR_WRITE_PROT:
 824         case MMC_ERASE:
 825         case MMC_GEN_CMD:
 826                 mask = MASK_START_CMD | MASK_MRBSYE;
 827                 break;
 828         default:
 829                 mask = MASK_START_CMD | MASK_MCRSPE;
 830                 break;
 831         }
 832
 833         if (host->data) {
 834                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 835                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 836                                 mrq->data->blksz);
 837         }
 838         opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
 839
 840         sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 841         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 842         /* set arg */
 843         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 844         /* set cmd */
 845         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 846
 847         host->wait_for = MMCIF_WAIT_FOR_CMD;
 848         schedule_delayed_work(&host->timeout_work, host->timeout);
 849 }
 850
 851 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 852                               struct mmc_request *mrq)
 853 {
 854         struct mmc_command *cmd = mrq->stop;
 855
 856         if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
 857                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 858         else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
 859                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 860         else {
 861                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 862                 cmd->error = sh_mmcif_error_manage(host);
 863                 return;
 864         }
 865
 866         host->wait_for = MMCIF_WAIT_FOR_STOP;
 867         schedule_delayed_work(&host->timeout_work, host->timeout);
 868 }
 869
 870 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 871 {
 872         struct sh_mmcif_host *host = mmc_priv(mmc);
 873         unsigned long flags;
 874
 875         spin_lock_irqsave(&host->lock, flags);
 876         if (host->state != STATE_IDLE) {
 877                 spin_unlock_irqrestore(&host->lock, flags);
 878                 mrq->cmd->error = -EAGAIN;
 879                 mmc_request_done(mmc, mrq);
 880                 return;
 881         }
 882
 883         host->state = STATE_REQUEST;
 884         spin_unlock_irqrestore(&host->lock, flags);
 885
 886         switch (mrq->cmd->opcode) {
 887         /* MMCIF does not support SD/SDIO command */
 888         case SD_IO_SEND_OP_COND:
 889         case MMC_APP_CMD:
 890                 host->state = STATE_IDLE;
 891                 mrq->cmd->error = -ETIMEDOUT;
 892                 mmc_request_done(mmc, mrq);
 893                 return;
 894         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 895                 if (!mrq->data) {
 896                         /* send_if_cond cmd (not support) */
 897                         host->state = STATE_IDLE;
 898                         mrq->cmd->error = -ETIMEDOUT;
 899                         mmc_request_done(mmc, mrq);
 900                         return;
 901                 }
 902                 break;
 903         default:
 904                 break;
 905         }
 906
 907         host->mrq = mrq;
 908         host->data = mrq->data;
 909
 910         sh_mmcif_start_cmd(host, mrq);
 911 }
 912
 913 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 914 {
 915         struct sh_mmcif_host *host = mmc_priv(mmc);
 916         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 917         unsigned long flags;
 918
 919         spin_lock_irqsave(&host->lock, flags);
 920         if (host->state != STATE_IDLE) {
 921                 spin_unlock_irqrestore(&host->lock, flags);
 922                 return;
 923         }
 924
 925         host->state = STATE_IOS;
 926         spin_unlock_irqrestore(&host->lock, flags);
 927
 928         if (ios->power_mode == MMC_POWER_UP) {
 929                 if (!host->card_present) {
 930                         /* See if we also get DMA */
 931                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
 932                         host->card_present = true;
 933                 }
 934         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
 935                 /* clock stop */
 936                 sh_mmcif_clock_control(host, 0);
 937                 if (ios->power_mode == MMC_POWER_OFF) {
 938                         if (host->card_present) {
 939                                 sh_mmcif_release_dma(host);
 940                                 host->card_present = false;
 941                         }
 942                 }
 943                 if (host->power) {
 944                         pm_runtime_put(&host->pd->dev);
 945                         host->power = false;
 946                         if (p->down_pwr && ios->power_mode == MMC_POWER_OFF)
 947                                 p->down_pwr(host->pd);
 948                 }
 949                 host->state = STATE_IDLE;
 950                 return;
 951         }
 952
 953         if (ios->clock) {
 954                 if (!host->power) {
 955                         if (p->set_pwr)
 956                                 p->set_pwr(host->pd, ios->power_mode);
 957                         pm_runtime_get_sync(&host->pd->dev);
 958                         host->power = true;
 959                         sh_mmcif_sync_reset(host);
 960                 }
 961                 sh_mmcif_clock_control(host, ios->clock);
 962         }
 963
 964         host->bus_width = ios->bus_width;
 965         host->state = STATE_IDLE;
 966 }
 967
 968 static int sh_mmcif_get_cd(struct mmc_host *mmc)
 969 {
 970         struct sh_mmcif_host *host = mmc_priv(mmc);
 971         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 972
 973         if (!p->get_cd)
 974                 return -ENOSYS;
 975         else
 976                 return p->get_cd(host->pd);
 977 }
 978
 979 static struct mmc_host_ops sh_mmcif_ops = {
 980         .request        = sh_mmcif_request,
 981         .set_ios        = sh_mmcif_set_ios,
 982         .get_cd         = sh_mmcif_get_cd,
 983 };
 984
 985 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
 986 {
 987         struct mmc_command *cmd = host->mrq->cmd;
 988         long time;
 989
 990         if (host->sd_error) {
 991                 switch (cmd->opcode) {
 992                 case MMC_ALL_SEND_CID:
 993                 case MMC_SELECT_CARD:
 994                 case MMC_APP_CMD:
 995                         cmd->error = -ETIMEDOUT;
 996                         host->sd_error = false;
 997                         break;
 998                 default:
 999                         cmd->error = sh_mmcif_error_manage(host);
1000                         dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1001                                 cmd->opcode, cmd->error);
1002                         break;
1003                 }
1004                 return false;
1005         }
1006         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1007                 cmd->error = 0;
1008                 return false;
1009         }
1010
1011         sh_mmcif_get_response(host, cmd);
1012
1013         if (!host->data)
1014                 return false;
1015
1016         if (host->mrq->data->flags & MMC_DATA_READ) {
1017                 if (host->chan_rx)
1018                         sh_mmcif_start_dma_rx(host);
1019         } else {
1020                 if (host->chan_tx)
1021                         sh_mmcif_start_dma_tx(host);
1022         }
1023
1024         if (!host->dma_active) {
1025                 host->data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1026                 if (!host->data->error)
1027                         return true;
1028                 return false;
1029         }
1030
1031         /* Running in the IRQ thread, can sleep */
1032         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1033                                                          host->timeout);
1034         if (host->sd_error) {
1035                 dev_err(host->mmc->parent,
1036                         "Error IRQ while waiting for DMA completion!\n");
1037                 /* Woken up by an error IRQ: abort DMA */
1038                 if (host->data->flags & MMC_DATA_READ)
1039                         dmaengine_terminate_all(host->chan_rx);
1040                 else
1041                         dmaengine_terminate_all(host->chan_tx);
1042                 host->data->error = sh_mmcif_error_manage(host);
1043         } else if (!time) {
1044                 host->data->error = -ETIMEDOUT;
1045         } else if (time < 0) {
1046                 host->data->error = time;
1047         }
1048         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1049                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1050         host->dma_active = false;
1051
1052         if (host->data->error)
1053                 host->data->bytes_xfered = 0;
1054
1055         return false;
1056 }
1057
1058 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1059 {
1060         struct sh_mmcif_host *host = dev_id;
1061         struct mmc_request *mrq = host->mrq;
1062
1063         cancel_delayed_work_sync(&host->timeout_work);
1064
1065         /*
1066          * All handlers return true, if processing continues, and false, if the
1067          * request has to be completed - successfully or not
1068          */
1069         switch (host->wait_for) {
1070         case MMCIF_WAIT_FOR_REQUEST:
1071                 /* We're too late, the timeout has already kicked in */
1072                 return IRQ_HANDLED;
1073         case MMCIF_WAIT_FOR_CMD:
1074                 if (sh_mmcif_end_cmd(host))
1075                         /* Wait for data */
1076                         return IRQ_HANDLED;
1077                 break;
1078         case MMCIF_WAIT_FOR_MREAD:
1079                 if (sh_mmcif_mread_block(host))
1080                         /* Wait for more data */
1081                         return IRQ_HANDLED;
1082                 break;
1083         case MMCIF_WAIT_FOR_READ:
1084                 if (sh_mmcif_read_block(host))
1085                         /* Wait for data end */
1086                         return IRQ_HANDLED;
1087                 break;
1088         case MMCIF_WAIT_FOR_MWRITE:
1089                 if (sh_mmcif_mwrite_block(host))
1090                         /* Wait data to write */
1091                         return IRQ_HANDLED;
1092                 break;
1093         case MMCIF_WAIT_FOR_WRITE:
1094                 if (sh_mmcif_write_block(host))
1095                         /* Wait for data end */
1096                         return IRQ_HANDLED;
1097                 break;
1098         case MMCIF_WAIT_FOR_STOP:
1099                 if (host->sd_error) {
1100                         mrq->stop->error = sh_mmcif_error_manage(host);
1101                         break;
1102                 }
1103                 sh_mmcif_get_cmd12response(host, mrq->stop);
1104                 mrq->stop->error = 0;
1105                 break;
1106         case MMCIF_WAIT_FOR_READ_END:
1107         case MMCIF_WAIT_FOR_WRITE_END:
1108                 if (host->sd_error)
1109                         mrq->data->error = sh_mmcif_error_manage(host);
1110                 break;
1111         default:
1112                 BUG();
1113         }
1114
1115         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1116                 host->data = NULL;
1117
1118                 if (!mrq->cmd->error && mrq->data && !mrq->data->error)
1119                         mrq->data->bytes_xfered =
1120                                 mrq->data->blocks * mrq->data->blksz;
1121
1122                 if (mrq->stop && !mrq->cmd->error && (!mrq->data || !mrq->data->error)) {
1123                         sh_mmcif_stop_cmd(host, mrq);
1124                         if (!mrq->stop->error)
1125                                 return IRQ_HANDLED;
1126                 }
1127         }
1128
1129         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1130         host->state = STATE_IDLE;
1131         mmc_request_done(host->mmc, mrq);
1132
1133         return IRQ_HANDLED;
1134 }
1135
1136 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1137 {
1138         struct sh_mmcif_host *host = dev_id;
1139         u32 state;
1140         int err = 0;
1141
1142         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1143
1144         if (state & INT_ERR_STS) {
1145                 /* error interrupts - process first */
1146                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1147                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1148                 err = 1;
1149         } else if (state & INT_RBSYE) {
1150                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1151                                 ~(INT_RBSYE | INT_CRSPE));
1152                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1153         } else if (state & INT_CRSPE) {
1154                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
1155                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1156         } else if (state & INT_BUFREN) {
1157                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
1158                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1159         } else if (state & INT_BUFWEN) {
1160                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
1161                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1162         } else if (state & INT_CMD12DRE) {
1163                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1164                         ~(INT_CMD12DRE | INT_CMD12RBE |
1165                           INT_CMD12CRE | INT_BUFRE));
1166                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1167         } else if (state & INT_BUFRE) {
1168                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
1169                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1170         } else if (state & INT_DTRANE) {
1171                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
1172                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1173         } else if (state & INT_CMD12RBE) {
1174                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1175                                 ~(INT_CMD12RBE | INT_CMD12CRE));
1176                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
1177         } else {
1178                 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
1179                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1180                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1181                 err = 1;
1182         }
1183         if (err) {
1184                 host->sd_error = true;
1185                 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
1186         }
1187         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1188                 if (!host->dma_active)
1189                         return IRQ_WAKE_THREAD;
1190                 else if (host->sd_error)
1191                         mmcif_dma_complete(host);
1192         } else {
1193                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1194         }
1195
1196         return IRQ_HANDLED;
1197 }
1198
1199 static void mmcif_timeout_work(struct work_struct *work)
1200 {
1201         struct delayed_work *d = container_of(work, struct delayed_work, work);
1202         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1203         struct mmc_request *mrq = host->mrq;
1204
1205         if (host->dying)
1206                 /* Don't run after mmc_remove_host() */
1207                 return;
1208
1209         /*
1210          * Handle races with cancel_delayed_work(), unless
1211          * cancel_delayed_work_sync() is used
1212          */
1213         switch (host->wait_for) {
1214         case MMCIF_WAIT_FOR_CMD:
1215                 mrq->cmd->error = sh_mmcif_error_manage(host);
1216                 break;
1217         case MMCIF_WAIT_FOR_STOP:
1218                 mrq->stop->error = sh_mmcif_error_manage(host);
1219                 break;
1220         case MMCIF_WAIT_FOR_MREAD:
1221         case MMCIF_WAIT_FOR_MWRITE:
1222         case MMCIF_WAIT_FOR_READ:
1223         case MMCIF_WAIT_FOR_WRITE:
1224         case MMCIF_WAIT_FOR_READ_END:
1225         case MMCIF_WAIT_FOR_WRITE_END:
1226                 host->data->error = sh_mmcif_error_manage(host);
1227                 break;
1228         default:
1229                 BUG();
1230         }
1231
1232         host->state = STATE_IDLE;
1233         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1234         host->data = NULL;
1235         host->mrq = NULL;
1236         mmc_request_done(host->mmc, mrq);
1237 }
1238
1239 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1240 {
1241         int ret = 0, irq[2];
1242         struct mmc_host *mmc;
1243         struct sh_mmcif_host *host;
1244         struct sh_mmcif_plat_data *pd;
1245         struct resource *res;
1246         void __iomem *reg;
1247         char clk_name[8];
1248
1249         irq[0] = platform_get_irq(pdev, 0);
1250         irq[1] = platform_get_irq(pdev, 1);
1251         if (irq[0] < 0 || irq[1] < 0) {
1252                 dev_err(&pdev->dev, "Get irq error\n");
1253                 return -ENXIO;
1254         }
1255         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1256         if (!res) {
1257                 dev_err(&pdev->dev, "platform_get_resource error.\n");
1258                 return -ENXIO;
1259         }
1260         reg = ioremap(res->start, resource_size(res));
1261         if (!reg) {
1262                 dev_err(&pdev->dev, "ioremap error.\n");
1263                 return -ENOMEM;
1264         }
1265         pd = pdev->dev.platform_data;
1266         if (!pd) {
1267                 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1268                 ret = -ENXIO;
1269                 goto clean_up;
1270         }
1271         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1272         if (!mmc) {
1273                 ret = -ENOMEM;
1274                 goto clean_up;
1275         }
1276         host            = mmc_priv(mmc);
1277         host->mmc       = mmc;
1278         host->addr      = reg;
1279         host->timeout   = 1000;
1280
1281         snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1282         host->hclk = clk_get(&pdev->dev, clk_name);
1283         if (IS_ERR(host->hclk)) {
1284                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1285                 ret = PTR_ERR(host->hclk);
1286                 goto clean_up1;
1287         }
1288         clk_enable(host->hclk);
1289         host->clk = clk_get_rate(host->hclk);
1290         host->pd = pdev;
1291
1292         spin_lock_init(&host->lock);
1293
1294         mmc->ops = &sh_mmcif_ops;
1295         mmc->f_max = host->clk;
1296         /* close to 400KHz */
1297         if (mmc->f_max < 51200000)
1298                 mmc->f_min = mmc->f_max / 128;
1299         else if (mmc->f_max < 102400000)
1300                 mmc->f_min = mmc->f_max / 256;
1301         else
1302                 mmc->f_min = mmc->f_max / 512;
1303         if (pd->ocr)
1304                 mmc->ocr_avail = pd->ocr;
1305         mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1306         if (pd->caps)
1307                 mmc->caps |= pd->caps;
1308         mmc->max_segs = 32;
1309         mmc->max_blk_size = 512;
1310         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1311         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1312         mmc->max_seg_size = mmc->max_req_size;
1313
1314         sh_mmcif_sync_reset(host);
1315         platform_set_drvdata(pdev, host);
1316
1317         pm_runtime_enable(&pdev->dev);
1318         host->power = false;
1319
1320         ret = pm_runtime_resume(&pdev->dev);
1321         if (ret < 0)
1322                 goto clean_up2;
1323
1324         mmc_add_host(mmc);
1325
1326         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1327
1328         ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
1329         if (ret) {
1330                 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1331                 goto clean_up3;
1332         }
1333         ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
1334         if (ret) {
1335                 free_irq(irq[0], host);
1336                 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1337                 goto clean_up3;
1338         }
1339
1340         INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1341
1342         mmc_detect_change(host->mmc, 0);
1343
1344         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1345         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1346                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1347         return ret;
1348
1349 clean_up3:
1350         mmc_remove_host(mmc);
1351         pm_runtime_suspend(&pdev->dev);
1352 clean_up2:
1353         pm_runtime_disable(&pdev->dev);
1354         clk_disable(host->hclk);
1355 clean_up1:
1356         mmc_free_host(mmc);
1357 clean_up:
1358         if (reg)
1359                 iounmap(reg);
1360         return ret;
1361 }
1362
1363 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1364 {
1365         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1366         int irq[2];
1367
1368         host->dying = true;
1369         pm_runtime_get_sync(&pdev->dev);
1370
1371         mmc_remove_host(host->mmc);
1372         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1373
1374         /*
1375          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1376          * mmc_remove_host() call above. But swapping order doesn't help either
1377          * (a query on the linux-mmc mailing list didn't bring any replies).
1378          */
1379         cancel_delayed_work_sync(&host->timeout_work);
1380
1381         if (host->addr)
1382                 iounmap(host->addr);
1383
1384         irq[0] = platform_get_irq(pdev, 0);
1385         irq[1] = platform_get_irq(pdev, 1);
1386
1387         free_irq(irq[0], host);
1388         free_irq(irq[1], host);
1389
1390         platform_set_drvdata(pdev, NULL);
1391
1392         clk_disable(host->hclk);
1393         mmc_free_host(host->mmc);
1394         pm_runtime_put_sync(&pdev->dev);
1395         pm_runtime_disable(&pdev->dev);
1396
1397         return 0;
1398 }
1399
1400 #ifdef CONFIG_PM
1401 static int sh_mmcif_suspend(struct device *dev)
1402 {
1403         struct platform_device *pdev = to_platform_device(dev);
1404         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1405         int ret = mmc_suspend_host(host->mmc);
1406
1407         if (!ret) {
1408                 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1409                 clk_disable(host->hclk);
1410         }
1411
1412         return ret;
1413 }
1414
1415 static int sh_mmcif_resume(struct device *dev)
1416 {
1417         struct platform_device *pdev = to_platform_device(dev);
1418         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1419
1420         clk_enable(host->hclk);
1421
1422         return mmc_resume_host(host->mmc);
1423 }
1424 #else
1425 #define sh_mmcif_suspend        NULL
1426 #define sh_mmcif_resume         NULL
1427 #endif  /* CONFIG_PM */
1428
1429 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1430         .suspend = sh_mmcif_suspend,
1431         .resume = sh_mmcif_resume,
1432 };
1433
1434 static struct platform_driver sh_mmcif_driver = {
1435         .probe          = sh_mmcif_probe,
1436         .remove         = sh_mmcif_remove,
1437         .driver         = {
1438                 .name   = DRIVER_NAME,
1439                 .pm     = &sh_mmcif_dev_pm_ops,
1440         },
1441 };
1442
1443 module_platform_driver(sh_mmcif_driver);
1444
1445 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1446 MODULE_LICENSE("GPL");
1447 MODULE_ALIAS("platform:" DRIVER_NAME);
1448 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");