4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
15 * 3. Handle MMC errors better
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/mmc/card.h>
26 #include <linux/mmc/core.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/sdio.h>
30 #include <linux/mmc/sh_mmcif.h>
31 #include <linux/pagemap.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/spinlock.h>
35 #include <linux/module.h>
37 #define DRIVER_NAME "sh_mmcif"
38 #define DRIVER_VERSION "2010-04-28"
41 #define CMD_MASK 0x3f000000
42 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
43 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
44 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
45 #define CMD_SET_RBSY (1 << 21) /* R1b */
46 #define CMD_SET_CCSEN (1 << 20)
47 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
48 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
49 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
50 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
51 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
52 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
53 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
54 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
55 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
56 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
57 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
58 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
59 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
60 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
61 #define CMD_SET_CCSH (1 << 5)
62 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
63 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
64 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
67 #define CMD_CTRL_BREAK (1 << 0)
70 #define BLOCK_SIZE_MASK 0x0000ffff
73 #define INT_CCSDE (1 << 29)
74 #define INT_CMD12DRE (1 << 26)
75 #define INT_CMD12RBE (1 << 25)
76 #define INT_CMD12CRE (1 << 24)
77 #define INT_DTRANE (1 << 23)
78 #define INT_BUFRE (1 << 22)
79 #define INT_BUFWEN (1 << 21)
80 #define INT_BUFREN (1 << 20)
81 #define INT_CCSRCV (1 << 19)
82 #define INT_RBSYE (1 << 17)
83 #define INT_CRSPE (1 << 16)
84 #define INT_CMDVIO (1 << 15)
85 #define INT_BUFVIO (1 << 14)
86 #define INT_WDATERR (1 << 11)
87 #define INT_RDATERR (1 << 10)
88 #define INT_RIDXERR (1 << 9)
89 #define INT_RSPERR (1 << 8)
90 #define INT_CCSTO (1 << 5)
91 #define INT_CRCSTO (1 << 4)
92 #define INT_WDATTO (1 << 3)
93 #define INT_RDATTO (1 << 2)
94 #define INT_RBSYTO (1 << 1)
95 #define INT_RSPTO (1 << 0)
96 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
97 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
98 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
99 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
102 #define MASK_ALL 0x00000000
103 #define MASK_MCCSDE (1 << 29)
104 #define MASK_MCMD12DRE (1 << 26)
105 #define MASK_MCMD12RBE (1 << 25)
106 #define MASK_MCMD12CRE (1 << 24)
107 #define MASK_MDTRANE (1 << 23)
108 #define MASK_MBUFRE (1 << 22)
109 #define MASK_MBUFWEN (1 << 21)
110 #define MASK_MBUFREN (1 << 20)
111 #define MASK_MCCSRCV (1 << 19)
112 #define MASK_MRBSYE (1 << 17)
113 #define MASK_MCRSPE (1 << 16)
114 #define MASK_MCMDVIO (1 << 15)
115 #define MASK_MBUFVIO (1 << 14)
116 #define MASK_MWDATERR (1 << 11)
117 #define MASK_MRDATERR (1 << 10)
118 #define MASK_MRIDXERR (1 << 9)
119 #define MASK_MRSPERR (1 << 8)
120 #define MASK_MCCSTO (1 << 5)
121 #define MASK_MCRCSTO (1 << 4)
122 #define MASK_MWDATTO (1 << 3)
123 #define MASK_MRDATTO (1 << 2)
124 #define MASK_MRBSYTO (1 << 1)
125 #define MASK_MRSPTO (1 << 0)
128 #define STS1_CMDSEQ (1 << 31)
131 #define STS2_CRCSTE (1 << 31)
132 #define STS2_CRC16E (1 << 30)
133 #define STS2_AC12CRCE (1 << 29)
134 #define STS2_RSPCRC7E (1 << 28)
135 #define STS2_CRCSTEBE (1 << 27)
136 #define STS2_RDATEBE (1 << 26)
137 #define STS2_AC12REBE (1 << 25)
138 #define STS2_RSPEBE (1 << 24)
139 #define STS2_AC12IDXE (1 << 23)
140 #define STS2_RSPIDXE (1 << 22)
141 #define STS2_CCSTO (1 << 15)
142 #define STS2_RDATTO (1 << 14)
143 #define STS2_DATBSYTO (1 << 13)
144 #define STS2_CRCSTTO (1 << 12)
145 #define STS2_AC12BSYTO (1 << 11)
146 #define STS2_RSPBSYTO (1 << 10)
147 #define STS2_AC12RSPTO (1 << 9)
148 #define STS2_RSPTO (1 << 8)
149 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
150 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
151 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
152 STS2_DATBSYTO | STS2_CRCSTTO | \
153 STS2_AC12BSYTO | STS2_RSPBSYTO | \
154 STS2_AC12RSPTO | STS2_RSPTO)
156 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
157 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
158 #define CLKDEV_INIT 400000 /* 400 KHz */
166 struct sh_mmcif_host {
167 struct mmc_host *mmc;
168 struct mmc_data *data;
169 struct platform_device *pd;
170 struct sh_dmae_slave dma_slave_tx;
171 struct sh_dmae_slave dma_slave_rx;
178 struct completion intr_wait;
179 enum mmcif_state state;
185 struct dma_chan *chan_rx;
186 struct dma_chan *chan_tx;
187 struct completion dma_complete;
191 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
192 unsigned int reg, u32 val)
194 writel(val | readl(host->addr + reg), host->addr + reg);
197 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
198 unsigned int reg, u32 val)
200 writel(~val & readl(host->addr + reg), host->addr + reg);
203 static void mmcif_dma_complete(void *arg)
205 struct sh_mmcif_host *host = arg;
206 dev_dbg(&host->pd->dev, "Command completed\n");
208 if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
209 dev_name(&host->pd->dev)))
212 if (host->data->flags & MMC_DATA_READ)
213 dma_unmap_sg(host->chan_rx->device->dev,
214 host->data->sg, host->data->sg_len,
217 dma_unmap_sg(host->chan_tx->device->dev,
218 host->data->sg, host->data->sg_len,
221 complete(&host->dma_complete);
224 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
226 struct scatterlist *sg = host->data->sg;
227 struct dma_async_tx_descriptor *desc = NULL;
228 struct dma_chan *chan = host->chan_rx;
229 dma_cookie_t cookie = -EINVAL;
232 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
235 host->dma_active = true;
236 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
237 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
241 desc->callback = mmcif_dma_complete;
242 desc->callback_param = host;
243 cookie = dmaengine_submit(desc);
244 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
245 dma_async_issue_pending(chan);
247 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
248 __func__, host->data->sg_len, ret, cookie);
251 /* DMA failed, fall back to PIO */
254 host->chan_rx = NULL;
255 host->dma_active = false;
256 dma_release_channel(chan);
257 /* Free the Tx channel too */
258 chan = host->chan_tx;
260 host->chan_tx = NULL;
261 dma_release_channel(chan);
263 dev_warn(&host->pd->dev,
264 "DMA failed: %d, falling back to PIO\n", ret);
265 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
268 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
269 desc, cookie, host->data->sg_len);
272 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
274 struct scatterlist *sg = host->data->sg;
275 struct dma_async_tx_descriptor *desc = NULL;
276 struct dma_chan *chan = host->chan_tx;
277 dma_cookie_t cookie = -EINVAL;
280 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
283 host->dma_active = true;
284 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
285 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
289 desc->callback = mmcif_dma_complete;
290 desc->callback_param = host;
291 cookie = dmaengine_submit(desc);
292 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
293 dma_async_issue_pending(chan);
295 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
296 __func__, host->data->sg_len, ret, cookie);
299 /* DMA failed, fall back to PIO */
302 host->chan_tx = NULL;
303 host->dma_active = false;
304 dma_release_channel(chan);
305 /* Free the Rx channel too */
306 chan = host->chan_rx;
308 host->chan_rx = NULL;
309 dma_release_channel(chan);
311 dev_warn(&host->pd->dev,
312 "DMA failed: %d, falling back to PIO\n", ret);
313 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
316 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
320 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
322 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
327 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
328 struct sh_mmcif_plat_data *pdata)
330 struct sh_dmae_slave *tx, *rx;
331 host->dma_active = false;
333 /* We can only either use DMA for both Tx and Rx or not use it at all */
335 dev_warn(&host->pd->dev,
336 "Update your platform to use embedded DMA slave IDs\n");
337 tx = &pdata->dma->chan_priv_tx;
338 rx = &pdata->dma->chan_priv_rx;
340 tx = &host->dma_slave_tx;
341 tx->slave_id = pdata->slave_id_tx;
342 rx = &host->dma_slave_rx;
343 rx->slave_id = pdata->slave_id_rx;
345 if (tx->slave_id > 0 && rx->slave_id > 0) {
349 dma_cap_set(DMA_SLAVE, mask);
351 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx);
352 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
358 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx);
359 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
362 if (!host->chan_rx) {
363 dma_release_channel(host->chan_tx);
364 host->chan_tx = NULL;
368 init_completion(&host->dma_complete);
372 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
374 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
375 /* Descriptors are freed automatically */
377 struct dma_chan *chan = host->chan_tx;
378 host->chan_tx = NULL;
379 dma_release_channel(chan);
382 struct dma_chan *chan = host->chan_rx;
383 host->chan_rx = NULL;
384 dma_release_channel(chan);
387 host->dma_active = false;
390 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
392 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
394 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
395 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
399 if (p->sup_pclk && clk == host->clk)
400 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
402 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
403 ((fls(host->clk / clk) - 1) << 16));
405 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
408 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
412 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
414 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
415 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
416 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
417 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
419 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
422 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
425 int ret, timeout = 10000000;
427 host->sd_error = false;
429 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
430 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
431 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
432 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
434 if (state1 & STS1_CMDSEQ) {
435 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
436 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
440 dev_err(&host->pd->dev,
441 "Forceed end of command sequence timeout err\n");
444 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
449 sh_mmcif_sync_reset(host);
450 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
454 if (state2 & STS2_CRC_ERR) {
455 dev_dbg(&host->pd->dev, ": Happened CRC error\n");
457 } else if (state2 & STS2_TIMEOUT_ERR) {
458 dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
461 dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
467 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
468 struct mmc_request *mrq)
470 struct mmc_data *data = mrq->data;
472 u32 blocksize, i, *p = sg_virt(data->sg);
474 /* buf read enable */
475 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
476 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
478 if (time <= 0 || host->sd_error)
479 return sh_mmcif_error_manage(host);
481 blocksize = (BLOCK_SIZE_MASK &
482 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
483 for (i = 0; i < blocksize / 4; i++)
484 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
486 /* buffer read end */
487 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
488 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
490 if (time <= 0 || host->sd_error)
491 return sh_mmcif_error_manage(host);
496 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
497 struct mmc_request *mrq)
499 struct mmc_data *data = mrq->data;
501 u32 blocksize, i, j, sec, *p;
503 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
505 for (j = 0; j < data->sg_len; j++) {
506 p = sg_virt(data->sg);
507 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
508 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
509 /* buf read enable */
510 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
513 if (time <= 0 || host->sd_error)
514 return sh_mmcif_error_manage(host);
516 for (i = 0; i < blocksize / 4; i++)
517 *p++ = sh_mmcif_readl(host->addr,
520 if (j < data->sg_len - 1)
526 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
527 struct mmc_request *mrq)
529 struct mmc_data *data = mrq->data;
531 u32 blocksize, i, *p = sg_virt(data->sg);
533 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
535 /* buf write enable */
536 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
538 if (time <= 0 || host->sd_error)
539 return sh_mmcif_error_manage(host);
541 blocksize = (BLOCK_SIZE_MASK &
542 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
543 for (i = 0; i < blocksize / 4; i++)
544 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
546 /* buffer write end */
547 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
549 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
551 if (time <= 0 || host->sd_error)
552 return sh_mmcif_error_manage(host);
557 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
558 struct mmc_request *mrq)
560 struct mmc_data *data = mrq->data;
562 u32 i, sec, j, blocksize, *p;
564 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
567 for (j = 0; j < data->sg_len; j++) {
568 p = sg_virt(data->sg);
569 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
570 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
571 /* buf write enable*/
572 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
575 if (time <= 0 || host->sd_error)
576 return sh_mmcif_error_manage(host);
578 for (i = 0; i < blocksize / 4; i++)
579 sh_mmcif_writel(host->addr,
580 MMCIF_CE_DATA, *p++);
582 if (j < data->sg_len - 1)
588 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
589 struct mmc_command *cmd)
591 if (cmd->flags & MMC_RSP_136) {
592 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
593 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
594 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
595 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
597 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
600 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
601 struct mmc_command *cmd)
603 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
606 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
607 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
611 /* Response Type check */
612 switch (mmc_resp_type(cmd)) {
614 tmp |= CMD_SET_RTYP_NO;
619 tmp |= CMD_SET_RTYP_6B;
622 tmp |= CMD_SET_RTYP_17B;
625 dev_err(&host->pd->dev, "Unsupported response type.\n");
631 case MMC_STOP_TRANSMISSION:
632 case MMC_SET_WRITE_PROT:
633 case MMC_CLR_WRITE_PROT:
642 switch (host->bus_width) {
643 case MMC_BUS_WIDTH_1:
644 tmp |= CMD_SET_DATW_1;
646 case MMC_BUS_WIDTH_4:
647 tmp |= CMD_SET_DATW_4;
649 case MMC_BUS_WIDTH_8:
650 tmp |= CMD_SET_DATW_8;
653 dev_err(&host->pd->dev, "Unsupported bus width.\n");
658 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
661 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
662 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
663 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
664 mrq->data->blocks << 16);
666 /* RIDXC[1:0] check bits */
667 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
668 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
669 tmp |= CMD_SET_RIDXC_BITS;
670 /* RCRC7C[1:0] check bits */
671 if (opc == MMC_SEND_OP_COND)
672 tmp |= CMD_SET_CRC7C_BITS;
673 /* RCRC7C[1:0] internal CRC7 */
674 if (opc == MMC_ALL_SEND_CID ||
675 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
676 tmp |= CMD_SET_CRC7C_INTERNAL;
678 return opc = ((opc << 24) | tmp);
681 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
682 struct mmc_request *mrq, u32 opc)
687 case MMC_READ_MULTIPLE_BLOCK:
688 ret = sh_mmcif_multi_read(host, mrq);
690 case MMC_WRITE_MULTIPLE_BLOCK:
691 ret = sh_mmcif_multi_write(host, mrq);
693 case MMC_WRITE_BLOCK:
694 ret = sh_mmcif_single_write(host, mrq);
696 case MMC_READ_SINGLE_BLOCK:
697 case MMC_SEND_EXT_CSD:
698 ret = sh_mmcif_single_read(host, mrq);
701 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
708 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
709 struct mmc_request *mrq, struct mmc_command *cmd)
712 int ret = 0, mask = 0;
713 u32 opc = cmd->opcode;
716 /* respons busy check */
718 case MMC_STOP_TRANSMISSION:
719 case MMC_SET_WRITE_PROT:
720 case MMC_CLR_WRITE_PROT:
729 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
730 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
731 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
732 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
735 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
736 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
739 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
741 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
742 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
744 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
746 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
748 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
751 cmd->error = sh_mmcif_error_manage(host);
754 if (host->sd_error) {
755 switch (cmd->opcode) {
756 case MMC_ALL_SEND_CID:
757 case MMC_SELECT_CARD:
759 cmd->error = -ETIMEDOUT;
762 dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
764 cmd->error = sh_mmcif_error_manage(host);
767 host->sd_error = false;
770 if (!(cmd->flags & MMC_RSP_PRESENT)) {
774 sh_mmcif_get_response(host, cmd);
776 if (!host->dma_active) {
777 ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
780 wait_for_completion_interruptible_timeout(&host->dma_complete,
786 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
787 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
788 host->dma_active = false;
791 mrq->data->bytes_xfered = 0;
793 mrq->data->bytes_xfered =
794 mrq->data->blocks * mrq->data->blksz;
799 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
800 struct mmc_request *mrq, struct mmc_command *cmd)
804 if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
805 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
806 else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
807 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
809 dev_err(&host->pd->dev, "unsupported stop cmd\n");
810 cmd->error = sh_mmcif_error_manage(host);
814 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
816 if (time <= 0 || host->sd_error) {
817 cmd->error = sh_mmcif_error_manage(host);
820 sh_mmcif_get_cmd12response(host, cmd);
824 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
826 struct sh_mmcif_host *host = mmc_priv(mmc);
829 spin_lock_irqsave(&host->lock, flags);
830 if (host->state != STATE_IDLE) {
831 spin_unlock_irqrestore(&host->lock, flags);
832 mrq->cmd->error = -EAGAIN;
833 mmc_request_done(mmc, mrq);
837 host->state = STATE_REQUEST;
838 spin_unlock_irqrestore(&host->lock, flags);
840 switch (mrq->cmd->opcode) {
841 /* MMCIF does not support SD/SDIO command */
842 case SD_IO_SEND_OP_COND:
844 host->state = STATE_IDLE;
845 mrq->cmd->error = -ETIMEDOUT;
846 mmc_request_done(mmc, mrq);
848 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
850 /* send_if_cond cmd (not support) */
851 host->state = STATE_IDLE;
852 mrq->cmd->error = -ETIMEDOUT;
853 mmc_request_done(mmc, mrq);
860 host->data = mrq->data;
862 if (mrq->data->flags & MMC_DATA_READ) {
864 sh_mmcif_start_dma_rx(host);
867 sh_mmcif_start_dma_tx(host);
870 sh_mmcif_start_cmd(host, mrq, mrq->cmd);
873 if (!mrq->cmd->error && mrq->stop)
874 sh_mmcif_stop_cmd(host, mrq, mrq->stop);
875 host->state = STATE_IDLE;
876 mmc_request_done(mmc, mrq);
879 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
881 struct sh_mmcif_host *host = mmc_priv(mmc);
882 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
885 spin_lock_irqsave(&host->lock, flags);
886 if (host->state != STATE_IDLE) {
887 spin_unlock_irqrestore(&host->lock, flags);
891 host->state = STATE_IOS;
892 spin_unlock_irqrestore(&host->lock, flags);
894 if (ios->power_mode == MMC_POWER_UP) {
895 if (!host->card_present) {
896 /* See if we also get DMA */
897 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
898 host->card_present = true;
900 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
902 sh_mmcif_clock_control(host, 0);
903 if (ios->power_mode == MMC_POWER_OFF) {
904 if (host->card_present) {
905 sh_mmcif_release_dma(host);
906 host->card_present = false;
910 pm_runtime_put(&host->pd->dev);
912 if (p->down_pwr && ios->power_mode == MMC_POWER_OFF)
913 p->down_pwr(host->pd);
915 host->state = STATE_IDLE;
922 p->set_pwr(host->pd, ios->power_mode);
923 pm_runtime_get_sync(&host->pd->dev);
925 sh_mmcif_sync_reset(host);
927 sh_mmcif_clock_control(host, ios->clock);
930 host->bus_width = ios->bus_width;
931 host->state = STATE_IDLE;
934 static int sh_mmcif_get_cd(struct mmc_host *mmc)
936 struct sh_mmcif_host *host = mmc_priv(mmc);
937 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
942 return p->get_cd(host->pd);
945 static struct mmc_host_ops sh_mmcif_ops = {
946 .request = sh_mmcif_request,
947 .set_ios = sh_mmcif_set_ios,
948 .get_cd = sh_mmcif_get_cd,
951 static void sh_mmcif_detect(struct mmc_host *mmc)
953 mmc_detect_change(mmc, 0);
956 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
958 struct sh_mmcif_host *host = dev_id;
962 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
964 if (state & INT_ERR_STS) {
965 /* error interrupts - process first */
966 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
967 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
969 } else if (state & INT_RBSYE) {
970 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
971 ~(INT_RBSYE | INT_CRSPE));
972 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
973 } else if (state & INT_CRSPE) {
974 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
975 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
976 } else if (state & INT_BUFREN) {
977 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
978 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
979 } else if (state & INT_BUFWEN) {
980 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
981 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
982 } else if (state & INT_CMD12DRE) {
983 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
984 ~(INT_CMD12DRE | INT_CMD12RBE |
985 INT_CMD12CRE | INT_BUFRE));
986 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
987 } else if (state & INT_BUFRE) {
988 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
989 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
990 } else if (state & INT_DTRANE) {
991 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
992 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
993 } else if (state & INT_CMD12RBE) {
994 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
995 ~(INT_CMD12RBE | INT_CMD12CRE));
996 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
998 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
999 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1000 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1004 host->sd_error = true;
1005 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
1007 if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
1008 complete(&host->intr_wait);
1010 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1015 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1017 int ret = 0, irq[2];
1018 struct mmc_host *mmc;
1019 struct sh_mmcif_host *host;
1020 struct sh_mmcif_plat_data *pd;
1021 struct resource *res;
1025 irq[0] = platform_get_irq(pdev, 0);
1026 irq[1] = platform_get_irq(pdev, 1);
1027 if (irq[0] < 0 || irq[1] < 0) {
1028 dev_err(&pdev->dev, "Get irq error\n");
1031 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1033 dev_err(&pdev->dev, "platform_get_resource error.\n");
1036 reg = ioremap(res->start, resource_size(res));
1038 dev_err(&pdev->dev, "ioremap error.\n");
1041 pd = pdev->dev.platform_data;
1043 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1047 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1052 host = mmc_priv(mmc);
1055 host->timeout = 1000;
1057 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1058 host->hclk = clk_get(&pdev->dev, clk_name);
1059 if (IS_ERR(host->hclk)) {
1060 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1061 ret = PTR_ERR(host->hclk);
1064 clk_enable(host->hclk);
1065 host->clk = clk_get_rate(host->hclk);
1068 init_completion(&host->intr_wait);
1069 spin_lock_init(&host->lock);
1071 mmc->ops = &sh_mmcif_ops;
1072 mmc->f_max = host->clk;
1073 /* close to 400KHz */
1074 if (mmc->f_max < 51200000)
1075 mmc->f_min = mmc->f_max / 128;
1076 else if (mmc->f_max < 102400000)
1077 mmc->f_min = mmc->f_max / 256;
1079 mmc->f_min = mmc->f_max / 512;
1081 mmc->ocr_avail = pd->ocr;
1082 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1084 mmc->caps |= pd->caps;
1086 mmc->max_blk_size = 512;
1087 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1088 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1089 mmc->max_seg_size = mmc->max_req_size;
1091 sh_mmcif_sync_reset(host);
1092 platform_set_drvdata(pdev, host);
1094 pm_runtime_enable(&pdev->dev);
1095 host->power = false;
1097 ret = pm_runtime_resume(&pdev->dev);
1103 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1105 ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
1107 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1110 ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
1112 free_irq(irq[0], host);
1113 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1117 sh_mmcif_detect(host->mmc);
1119 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1120 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1121 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1125 mmc_remove_host(mmc);
1126 pm_runtime_suspend(&pdev->dev);
1128 pm_runtime_disable(&pdev->dev);
1129 clk_disable(host->hclk);
1138 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1140 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1143 pm_runtime_get_sync(&pdev->dev);
1145 mmc_remove_host(host->mmc);
1146 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1149 iounmap(host->addr);
1151 irq[0] = platform_get_irq(pdev, 0);
1152 irq[1] = platform_get_irq(pdev, 1);
1154 free_irq(irq[0], host);
1155 free_irq(irq[1], host);
1157 platform_set_drvdata(pdev, NULL);
1159 clk_disable(host->hclk);
1160 mmc_free_host(host->mmc);
1161 pm_runtime_put_sync(&pdev->dev);
1162 pm_runtime_disable(&pdev->dev);
1168 static int sh_mmcif_suspend(struct device *dev)
1170 struct platform_device *pdev = to_platform_device(dev);
1171 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1172 int ret = mmc_suspend_host(host->mmc);
1175 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1176 clk_disable(host->hclk);
1182 static int sh_mmcif_resume(struct device *dev)
1184 struct platform_device *pdev = to_platform_device(dev);
1185 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1187 clk_enable(host->hclk);
1189 return mmc_resume_host(host->mmc);
1192 #define sh_mmcif_suspend NULL
1193 #define sh_mmcif_resume NULL
1194 #endif /* CONFIG_PM */
1196 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1197 .suspend = sh_mmcif_suspend,
1198 .resume = sh_mmcif_resume,
1201 static struct platform_driver sh_mmcif_driver = {
1202 .probe = sh_mmcif_probe,
1203 .remove = sh_mmcif_remove,
1205 .name = DRIVER_NAME,
1206 .pm = &sh_mmcif_dev_pm_ops,
1210 module_platform_driver(sh_mmcif_driver);
1212 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1213 MODULE_LICENSE("GPL");
1214 MODULE_ALIAS("platform:" DRIVER_NAME);
1215 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");