drivers/mmc/host/sh_mobile_sdhi.c

   1 /*
   2  * SuperH Mobile SDHI
   3  *
   4  * Copyright (C) 2016 Sang Engineering, Wolfram Sang
   5  * Copyright (C) 2015-16 Renesas Electronics Corporation
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Based on "Compaq ASIC3 support":
  13  *
  14  * Copyright 2001 Compaq Computer Corporation.
  15  * Copyright 2004-2005 Phil Blundell
  16  * Copyright 2007-2008 OpenedHand Ltd.
  17  *
  18  * Authors: Phil Blundell <pb@handhelds.org>,
  19  *          Samuel Ortiz <sameo@openedhand.com>
  20  *
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/clk.h>
  25 #include <linux/slab.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/module.h>
  28 #include <linux/of_device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mfd/tmio.h>
  32 #include <linux/sh_dma.h>
  33 #include <linux/delay.h>
  34 #include <linux/pinctrl/consumer.h>
  35 #include <linux/pinctrl/pinctrl-state.h>
  36 #include <linux/regulator/consumer.h>
  37
  38 #include "tmio_mmc.h"
  39
  40 #define EXT_ACC           0xe4
  41
  42 #define SDHI_VER_GEN2_SDR50     0x490c
  43 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  44 #define SDHI_VER_GEN2_SDR104    0xcb0d
  45 #define SDHI_VER_GEN3_SD        0xcc10
  46 #define SDHI_VER_GEN3_SDMMC     0xcd10
  47
  48 #define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data)
  49
  50 struct sh_mobile_sdhi_scc {
  51         unsigned long clk_rate; /* clock rate for SDR104 */
  52         u32 tap;                /* sampling clock position for SDR104 */
  53 };
  54
  55 struct sh_mobile_sdhi_of_data {
  56         unsigned long tmio_flags;
  57         u32           tmio_ocr_mask;
  58         unsigned long capabilities;
  59         unsigned long capabilities2;
  60         enum dma_slave_buswidth dma_buswidth;
  61         dma_addr_t dma_rx_offset;
  62         unsigned bus_shift;
  63         int scc_offset;
  64         struct sh_mobile_sdhi_scc *taps;
  65         int taps_num;
  66 };
  67
  68 static const struct sh_mobile_sdhi_of_data of_default_cfg = {
  69         .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  70 };
  71
  72 static const struct sh_mobile_sdhi_of_data of_rz_compatible = {
  73         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT,
  74         .tmio_ocr_mask  = MMC_VDD_32_33,
  75         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  76 };
  77
  78 static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = {
  79         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
  80                           TMIO_MMC_CLK_ACTUAL,
  81         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  82 };
  83
  84 /* Definitions for sampling clocks */
  85 static struct sh_mobile_sdhi_scc rcar_gen2_scc_taps[] = {
  86         {
  87                 .clk_rate = 156000000,
  88                 .tap = 0x00000703,
  89         },
  90         {
  91                 .clk_rate = 0,
  92                 .tap = 0x00000300,
  93         },
  94 };
  95
  96 static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = {
  97         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
  98                           TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
  99         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
 100         .dma_buswidth   = DMA_SLAVE_BUSWIDTH_4_BYTES,
 101         .dma_rx_offset  = 0x2000,
 102         .scc_offset     = 0x0300,
 103         .taps           = rcar_gen2_scc_taps,
 104         .taps_num       = ARRAY_SIZE(rcar_gen2_scc_taps),
 105 };
 106
 107 /* Definitions for sampling clocks */
 108 static struct sh_mobile_sdhi_scc rcar_gen3_scc_taps[] = {
 109         {
 110                 .clk_rate = 0,
 111                 .tap = 0x00000300,
 112         },
 113 };
 114
 115 static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = {
 116         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
 117                           TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
 118         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
 119         .bus_shift      = 2,
 120         .scc_offset     = 0x1000,
 121         .taps           = rcar_gen3_scc_taps,
 122         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
 123 };
 124
 125 static const struct of_device_id sh_mobile_sdhi_of_match[] = {
 126         { .compatible = "renesas,sdhi-shmobile" },
 127         { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
 128         { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
 129         { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
 130         { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
 131         { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
 132         { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
 133         { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
 134         { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
 135         { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
 136         { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
 137         { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
 138         { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
 139         { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
 140         {},
 141 };
 142 MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
 143
 144 struct sh_mobile_sdhi {
 145         struct clk *clk;
 146         struct clk *clk_cd;
 147         struct tmio_mmc_data mmc_data;
 148         struct tmio_mmc_dma dma_priv;
 149         struct pinctrl *pinctrl;
 150         struct pinctrl_state *pins_default, *pins_uhs;
 151         void __iomem *scc_ctl;
 152 };
 153
 154 static void sh_mobile_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
 155 {
 156         u32 val;
 157
 158         /*
 159          * see also
 160          *      sh_mobile_sdhi_of_data :: dma_buswidth
 161          */
 162         switch (sd_ctrl_read16(host, CTL_VERSION)) {
 163         case SDHI_VER_GEN2_SDR50:
 164                 val = (width == 32) ? 0x0001 : 0x0000;
 165                 break;
 166         case SDHI_VER_GEN2_SDR104:
 167                 val = (width == 32) ? 0x0000 : 0x0001;
 168                 break;
 169         case SDHI_VER_GEN3_SD:
 170         case SDHI_VER_GEN3_SDMMC:
 171                 if (width == 64)
 172                         val = 0x0000;
 173                 else if (width == 32)
 174                         val = 0x0101;
 175                 else
 176                         val = 0x0001;
 177                 break;
 178         default:
 179                 /* nothing to do */
 180                 return;
 181         }
 182
 183         sd_ctrl_write16(host, EXT_ACC, val);
 184 }
 185
 186 static int sh_mobile_sdhi_clk_enable(struct tmio_mmc_host *host)
 187 {
 188         struct mmc_host *mmc = host->mmc;
 189         struct sh_mobile_sdhi *priv = host_to_priv(host);
 190         int ret = clk_prepare_enable(priv->clk);
 191         if (ret < 0)
 192                 return ret;
 193
 194         ret = clk_prepare_enable(priv->clk_cd);
 195         if (ret < 0) {
 196                 clk_disable_unprepare(priv->clk);
 197                 return ret;
 198         }
 199
 200         /*
 201          * The clock driver may not know what maximum frequency
 202          * actually works, so it should be set with the max-frequency
 203          * property which will already have been read to f_max.  If it
 204          * was missing, assume the current frequency is the maximum.
 205          */
 206         if (!mmc->f_max)
 207                 mmc->f_max = clk_get_rate(priv->clk);
 208
 209         /*
 210          * Minimum frequency is the minimum input clock frequency
 211          * divided by our maximum divider.
 212          */
 213         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 214
 215         /* enable 16bit data access on SDBUF as default */
 216         sh_mobile_sdhi_sdbuf_width(host, 16);
 217
 218         return 0;
 219 }
 220
 221 static unsigned int sh_mobile_sdhi_clk_update(struct tmio_mmc_host *host,
 222                                               unsigned int new_clock)
 223 {
 224         struct sh_mobile_sdhi *priv = host_to_priv(host);
 225         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 226         int i, ret;
 227
 228         /* tested only on RCar Gen2+ currently; may work for others */
 229         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 230                 return clk_get_rate(priv->clk);
 231
 232         /*
 233          * We want the bus clock to be as close as possible to, but no
 234          * greater than, new_clock.  As we can divide by 1 << i for
 235          * any i in [0, 9] we want the input clock to be as close as
 236          * possible, but no greater than, new_clock << i.
 237          */
 238         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 239                 freq = clk_round_rate(priv->clk, new_clock << i);
 240                 if (freq > (new_clock << i)) {
 241                         /* Too fast; look for a slightly slower option */
 242                         freq = clk_round_rate(priv->clk,
 243                                               (new_clock << i) / 4 * 3);
 244                         if (freq > (new_clock << i))
 245                                 continue;
 246                 }
 247
 248                 diff = new_clock - (freq >> i);
 249                 if (diff <= diff_min) {
 250                         best_freq = freq;
 251                         diff_min = diff;
 252                 }
 253         }
 254
 255         ret = clk_set_rate(priv->clk, best_freq);
 256
 257         return ret == 0 ? best_freq : clk_get_rate(priv->clk);
 258 }
 259
 260 static void sh_mobile_sdhi_clk_disable(struct tmio_mmc_host *host)
 261 {
 262         struct sh_mobile_sdhi *priv = host_to_priv(host);
 263
 264         clk_disable_unprepare(priv->clk);
 265         clk_disable_unprepare(priv->clk_cd);
 266 }
 267
 268 static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc)
 269 {
 270         struct tmio_mmc_host *host = mmc_priv(mmc);
 271
 272         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_DAT0);
 273 }
 274
 275 static int sh_mobile_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 276                                                       struct mmc_ios *ios)
 277 {
 278         struct tmio_mmc_host *host = mmc_priv(mmc);
 279         struct sh_mobile_sdhi *priv = host_to_priv(host);
 280         struct pinctrl_state *pin_state;
 281         int ret;
 282
 283         switch (ios->signal_voltage) {
 284         case MMC_SIGNAL_VOLTAGE_330:
 285                 pin_state = priv->pins_default;
 286                 break;
 287         case MMC_SIGNAL_VOLTAGE_180:
 288                 pin_state = priv->pins_uhs;
 289                 break;
 290         default:
 291                 return -EINVAL;
 292         }
 293
 294         /*
 295          * If anything is missing, assume signal voltage is fixed at
 296          * 3.3V and succeed/fail accordingly.
 297          */
 298         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 299                 return ios->signal_voltage ==
 300                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 301
 302         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 303         if (ret)
 304                 return ret;
 305
 306         return pinctrl_select_state(priv->pinctrl, pin_state);
 307 }
 308
 309 /* SCC registers */
 310 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 311 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 312 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 313 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 314 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 315 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 316
 317 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
 318 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 319 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 320 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 321
 322 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
 323 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 324 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
 325 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 326 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
 327 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 328
 329 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 330                                 struct sh_mobile_sdhi *priv, int addr)
 331 {
 332         return readl(priv->scc_ctl + (addr << host->bus_shift));
 333 }
 334
 335 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 336                                   struct sh_mobile_sdhi *priv,
 337                                   int addr, u32 val)
 338 {
 339         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 340 }
 341
 342 static unsigned int sh_mobile_sdhi_init_tuning(struct tmio_mmc_host *host)
 343 {
 344         struct sh_mobile_sdhi *priv;
 345
 346         priv = host_to_priv(host);
 347
 348         /* set sampling clock selection range */
 349         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 350                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 351
 352         /* Initialize SCC */
 353         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 354
 355         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 356                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 357                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
 358
 359         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 360                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 361
 362         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 363                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 364                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 365
 366         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 367                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 368
 369         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 370                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 371                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 372
 373         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos);
 374
 375         /* Read TAPNUM */
 376         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 377                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 378                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 379 }
 380
 381 static void sh_mobile_sdhi_prepare_tuning(struct tmio_mmc_host *host,
 382                                          unsigned long tap)
 383 {
 384         struct sh_mobile_sdhi *priv = host_to_priv(host);
 385
 386         /* Set sampling clock position */
 387         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
 388 }
 389
 390 #define SH_MOBILE_SDHI_MAX_TAP 3
 391
 392 static int sh_mobile_sdhi_select_tuning(struct tmio_mmc_host *host)
 393 {
 394         struct sh_mobile_sdhi *priv = host_to_priv(host);
 395         unsigned long tap_cnt;  /* counter of tuning success */
 396         unsigned long tap_set;  /* tap position */
 397         unsigned long tap_start;/* start position of tuning success */
 398         unsigned long tap_end;  /* end position of tuning success */
 399         unsigned long ntap;     /* temporary counter of tuning success */
 400         unsigned long i;
 401
 402         /* Clear SCC_RVSREQ */
 403         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 404
 405         /*
 406          * Find the longest consecutive run of successful probes.  If that
 407          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 408          * center index as the tap.
 409          */
 410         tap_cnt = 0;
 411         ntap = 0;
 412         tap_start = 0;
 413         tap_end = 0;
 414         for (i = 0; i < host->tap_num * 2; i++) {
 415                 if (test_bit(i, host->taps))
 416                         ntap++;
 417                 else {
 418                         if (ntap > tap_cnt) {
 419                                 tap_start = i - ntap;
 420                                 tap_end = i - 1;
 421                                 tap_cnt = ntap;
 422                         }
 423                         ntap = 0;
 424                 }
 425         }
 426
 427         if (ntap > tap_cnt) {
 428                 tap_start = i - ntap;
 429                 tap_end = i - 1;
 430                 tap_cnt = ntap;
 431         }
 432
 433         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 434                 tap_set = (tap_start + tap_end) / 2 % host->tap_num;
 435         else
 436                 return -EIO;
 437
 438         /* Set SCC */
 439         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
 440
 441         /* Enable auto re-tuning */
 442         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 443                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 444                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 445
 446         return 0;
 447 }
 448
 449
 450 static bool sh_mobile_sdhi_check_scc_error(struct tmio_mmc_host *host)
 451 {
 452         struct sh_mobile_sdhi *priv = host_to_priv(host);
 453
 454         /* Check SCC error */
 455         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 456             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
 457             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 458             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 459                 /* Clear SCC error */
 460                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 461                 return true;
 462         }
 463
 464         return false;
 465 }
 466
 467 static void sh_mobile_sdhi_hw_reset(struct tmio_mmc_host *host)
 468 {
 469         struct sh_mobile_sdhi *priv;
 470
 471         priv = host_to_priv(host);
 472
 473         /* Reset SCC */
 474         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 475                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 476
 477         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 478                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 479                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 480
 481         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 482                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 483
 484         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 485                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 486                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 487
 488         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 489                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 490                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 491 }
 492
 493 static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host)
 494 {
 495         int timeout = 1000;
 496
 497         while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 498                               & TMIO_STAT_SCLKDIVEN))
 499                 udelay(1);
 500
 501         if (!timeout) {
 502                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 503                 return -EBUSY;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static int sh_mobile_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 510 {
 511         switch (addr)
 512         {
 513         case CTL_SD_CMD:
 514         case CTL_STOP_INTERNAL_ACTION:
 515         case CTL_XFER_BLK_COUNT:
 516         case CTL_SD_CARD_CLK_CTL:
 517         case CTL_SD_XFER_LEN:
 518         case CTL_SD_MEM_CARD_OPT:
 519         case CTL_TRANSACTION_CTL:
 520         case CTL_DMA_ENABLE:
 521         case EXT_ACC:
 522                 return sh_mobile_sdhi_wait_idle(host);
 523         }
 524
 525         return 0;
 526 }
 527
 528 static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card,
 529                                          unsigned int direction, int blk_size)
 530 {
 531         /*
 532          * In Renesas controllers, when performing a
 533          * multiple block read of one or two blocks,
 534          * depending on the timing with which the
 535          * response register is read, the response
 536          * value may not be read properly.
 537          * Use single block read for this HW bug
 538          */
 539         if ((direction == MMC_DATA_READ) &&
 540             blk_size == 2)
 541                 return 1;
 542
 543         return blk_size;
 544 }
 545
 546 static void sh_mobile_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 547 {
 548         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? 2 : 0);
 549
 550         /* enable 32bit access if DMA mode if possibile */
 551         sh_mobile_sdhi_sdbuf_width(host, enable ? 32 : 16);
 552 }
 553
 554 static int sh_mobile_sdhi_probe(struct platform_device *pdev)
 555 {
 556         const struct sh_mobile_sdhi_of_data *of_data = of_device_get_match_data(&pdev->dev);
 557         struct sh_mobile_sdhi *priv;
 558         struct tmio_mmc_data *mmc_data;
 559         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 560         struct tmio_mmc_host *host;
 561         struct resource *res;
 562         int irq, ret, i;
 563         struct tmio_mmc_dma *dma_priv;
 564
 565         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 566         if (!res)
 567                 return -EINVAL;
 568
 569         priv = devm_kzalloc(&pdev->dev, sizeof(struct sh_mobile_sdhi), GFP_KERNEL);
 570         if (!priv)
 571                 return -ENOMEM;
 572
 573         mmc_data = &priv->mmc_data;
 574         dma_priv = &priv->dma_priv;
 575
 576         priv->clk = devm_clk_get(&pdev->dev, NULL);
 577         if (IS_ERR(priv->clk)) {
 578                 ret = PTR_ERR(priv->clk);
 579                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 580                 goto eprobe;
 581         }
 582
 583         /*
 584          * Some controllers provide a 2nd clock just to run the internal card
 585          * detection logic. Unfortunately, the existing driver architecture does
 586          * not support a separation of clocks for runtime PM usage. When
 587          * native hotplug is used, the tmio driver assumes that the core
 588          * must continue to run for card detect to stay active, so we cannot
 589          * disable it.
 590          * Additionally, it is prohibited to supply a clock to the core but not
 591          * to the card detect circuit. That leaves us with if separate clocks
 592          * are presented, we must treat them both as virtually 1 clock.
 593          */
 594         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 595         if (IS_ERR(priv->clk_cd))
 596                 priv->clk_cd = NULL;
 597
 598         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 599         if (!IS_ERR(priv->pinctrl)) {
 600                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 601                                                 PINCTRL_STATE_DEFAULT);
 602                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 603                                                 "state_uhs");
 604         }
 605
 606         host = tmio_mmc_host_alloc(pdev);
 607         if (!host) {
 608                 ret = -ENOMEM;
 609                 goto eprobe;
 610         }
 611
 612
 613         if (of_data) {
 614                 mmc_data->flags |= of_data->tmio_flags;
 615                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 616                 mmc_data->capabilities |= of_data->capabilities;
 617                 mmc_data->capabilities2 |= of_data->capabilities2;
 618                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 619                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 620                 host->bus_shift = of_data->bus_shift;
 621         }
 622
 623         host->dma               = dma_priv;
 624         host->write16_hook      = sh_mobile_sdhi_write16_hook;
 625         host->clk_enable        = sh_mobile_sdhi_clk_enable;
 626         host->clk_update        = sh_mobile_sdhi_clk_update;
 627         host->clk_disable       = sh_mobile_sdhi_clk_disable;
 628         host->multi_io_quirk    = sh_mobile_sdhi_multi_io_quirk;
 629
 630         /* SDR speeds are only available on Gen2+ */
 631         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 632                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 633                 host->card_busy = sh_mobile_sdhi_card_busy;
 634                 host->start_signal_voltage_switch =
 635                         sh_mobile_sdhi_start_signal_voltage_switch;
 636         }
 637
 638         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 639         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 640                 host->bus_shift = 1;
 641
 642         if (mmd)
 643                 *mmc_data = *mmd;
 644
 645         dma_priv->filter = shdma_chan_filter;
 646         dma_priv->enable = sh_mobile_sdhi_enable_dma;
 647
 648         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 649         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 650
 651         /*
 652          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 653          * bus width mode.
 654          */
 655         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 656
 657         /*
 658          * All SDHI blocks support SDIO IRQ signalling.
 659          */
 660         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 661
 662         /*
 663          * All SDHI have CMD12 controll bit
 664          */
 665         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 666
 667         /* All SDHI have SDIO status bits which must be 1 */
 668         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 669
 670         ret = tmio_mmc_host_probe(host, mmc_data);
 671         if (ret < 0)
 672                 goto efree;
 673
 674         /* Enable tuning iff we have an SCC and a supported mode */
 675         if (of_data && of_data->scc_offset &&
 676             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 677              host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) {
 678                 const struct sh_mobile_sdhi_scc *taps = of_data->taps;
 679                 bool hit = false;
 680
 681                 host->mmc->caps |= MMC_CAP_HW_RESET;
 682
 683                 for (i = 0; i < of_data->taps_num; i++) {
 684                         if (taps[i].clk_rate == 0 ||
 685                             taps[i].clk_rate == host->mmc->f_max) {
 686                                 host->scc_tappos = taps->tap;
 687                                 hit = true;
 688                                 break;
 689                         }
 690                 }
 691
 692                 if (!hit)
 693                         dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
 694
 695                 priv->scc_ctl = host->ctl + of_data->scc_offset;
 696                 host->init_tuning = sh_mobile_sdhi_init_tuning;
 697                 host->prepare_tuning = sh_mobile_sdhi_prepare_tuning;
 698                 host->select_tuning = sh_mobile_sdhi_select_tuning;
 699                 host->check_scc_error = sh_mobile_sdhi_check_scc_error;
 700                 host->hw_reset = sh_mobile_sdhi_hw_reset;
 701         }
 702
 703         i = 0;
 704         while (1) {
 705                 irq = platform_get_irq(pdev, i);
 706                 if (irq < 0)
 707                         break;
 708                 i++;
 709                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 710                                   dev_name(&pdev->dev), host);
 711                 if (ret)
 712                         goto eirq;
 713         }
 714
 715         /* There must be at least one IRQ source */
 716         if (!i) {
 717                 ret = irq;
 718                 goto eirq;
 719         }
 720
 721         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 722                  mmc_hostname(host->mmc), (unsigned long)
 723                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 724                  host->mmc->f_max / 1000000);
 725
 726         return ret;
 727
 728 eirq:
 729         tmio_mmc_host_remove(host);
 730 efree:
 731         tmio_mmc_host_free(host);
 732 eprobe:
 733         return ret;
 734 }
 735
 736 static int sh_mobile_sdhi_remove(struct platform_device *pdev)
 737 {
 738         struct mmc_host *mmc = platform_get_drvdata(pdev);
 739         struct tmio_mmc_host *host = mmc_priv(mmc);
 740
 741         tmio_mmc_host_remove(host);
 742
 743         return 0;
 744 }
 745
 746 static const struct dev_pm_ops tmio_mmc_dev_pm_ops = {
 747         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 748                         pm_runtime_force_resume)
 749         SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
 750                         tmio_mmc_host_runtime_resume,
 751                         NULL)
 752 };
 753
 754 static struct platform_driver sh_mobile_sdhi_driver = {
 755         .driver         = {
 756                 .name   = "sh_mobile_sdhi",
 757                 .pm     = &tmio_mmc_dev_pm_ops,
 758                 .of_match_table = sh_mobile_sdhi_of_match,
 759         },
 760         .probe          = sh_mobile_sdhi_probe,
 761         .remove         = sh_mobile_sdhi_remove,
 762 };
 763
 764 module_platform_driver(sh_mobile_sdhi_driver);
 765
 766 MODULE_DESCRIPTION("SuperH Mobile SDHI driver");
 767 MODULE_AUTHOR("Magnus Damm");
 768 MODULE_LICENSE("GPL v2");
 769 MODULE_ALIAS("platform:sh_mobile_sdhi");