2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 * (C) Copyright 2017 Sootech SA
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_device.h>
27 #include <linux/spinlock.h>
28 #include <linux/scatterlist.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/reset.h>
32 #include <linux/regulator/consumer.h>
34 #include <linux/of_address.h>
35 #include <linux/of_gpio.h>
36 #include <linux/of_platform.h>
38 #include <linux/mmc/host.h>
39 #include <linux/mmc/sd.h>
40 #include <linux/mmc/sdio.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/core.h>
43 #include <linux/mmc/card.h>
44 #include <linux/mmc/slot-gpio.h>
46 /* register offset definitions */
47 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
48 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
49 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
50 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
51 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
52 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
53 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
54 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
55 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
56 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
57 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
58 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
59 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
60 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
61 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
62 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
63 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
64 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
65 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
66 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
67 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
68 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
69 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
70 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
71 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
72 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
73 #define SDXC_REG_CHDA (0x90)
74 #define SDXC_REG_CBDA (0x94)
76 /* New registers introduced in A64 */
77 #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
78 #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
79 #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
80 #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
81 #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
83 #define mmc_readl(host, reg) \
84 readl((host)->reg_base + SDXC_##reg)
85 #define mmc_writel(host, reg, value) \
86 writel((value), (host)->reg_base + SDXC_##reg)
88 /* global control register bits */
89 #define SDXC_SOFT_RESET BIT(0)
90 #define SDXC_FIFO_RESET BIT(1)
91 #define SDXC_DMA_RESET BIT(2)
92 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
93 #define SDXC_DMA_ENABLE_BIT BIT(5)
94 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
95 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
96 #define SDXC_DDR_MODE BIT(10)
97 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
98 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
99 #define SDXC_ACCESS_BY_AHB BIT(31)
100 #define SDXC_ACCESS_BY_DMA (0 << 31)
101 #define SDXC_HARDWARE_RESET \
102 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
104 /* clock control bits */
105 #define SDXC_MASK_DATA0 BIT(31)
106 #define SDXC_CARD_CLOCK_ON BIT(16)
107 #define SDXC_LOW_POWER_ON BIT(17)
110 #define SDXC_WIDTH1 0
111 #define SDXC_WIDTH4 1
112 #define SDXC_WIDTH8 2
114 /* smc command bits */
115 #define SDXC_RESP_EXPIRE BIT(6)
116 #define SDXC_LONG_RESPONSE BIT(7)
117 #define SDXC_CHECK_RESPONSE_CRC BIT(8)
118 #define SDXC_DATA_EXPIRE BIT(9)
119 #define SDXC_WRITE BIT(10)
120 #define SDXC_SEQUENCE_MODE BIT(11)
121 #define SDXC_SEND_AUTO_STOP BIT(12)
122 #define SDXC_WAIT_PRE_OVER BIT(13)
123 #define SDXC_STOP_ABORT_CMD BIT(14)
124 #define SDXC_SEND_INIT_SEQUENCE BIT(15)
125 #define SDXC_UPCLK_ONLY BIT(21)
126 #define SDXC_READ_CEATA_DEV BIT(22)
127 #define SDXC_CCS_EXPIRE BIT(23)
128 #define SDXC_ENABLE_BIT_BOOT BIT(24)
129 #define SDXC_ALT_BOOT_OPTIONS BIT(25)
130 #define SDXC_BOOT_ACK_EXPIRE BIT(26)
131 #define SDXC_BOOT_ABORT BIT(27)
132 #define SDXC_VOLTAGE_SWITCH BIT(28)
133 #define SDXC_USE_HOLD_REGISTER BIT(29)
134 #define SDXC_START BIT(31)
137 #define SDXC_RESP_ERROR BIT(1)
138 #define SDXC_COMMAND_DONE BIT(2)
139 #define SDXC_DATA_OVER BIT(3)
140 #define SDXC_TX_DATA_REQUEST BIT(4)
141 #define SDXC_RX_DATA_REQUEST BIT(5)
142 #define SDXC_RESP_CRC_ERROR BIT(6)
143 #define SDXC_DATA_CRC_ERROR BIT(7)
144 #define SDXC_RESP_TIMEOUT BIT(8)
145 #define SDXC_DATA_TIMEOUT BIT(9)
146 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
147 #define SDXC_FIFO_RUN_ERROR BIT(11)
148 #define SDXC_HARD_WARE_LOCKED BIT(12)
149 #define SDXC_START_BIT_ERROR BIT(13)
150 #define SDXC_AUTO_COMMAND_DONE BIT(14)
151 #define SDXC_END_BIT_ERROR BIT(15)
152 #define SDXC_SDIO_INTERRUPT BIT(16)
153 #define SDXC_CARD_INSERT BIT(30)
154 #define SDXC_CARD_REMOVE BIT(31)
155 #define SDXC_INTERRUPT_ERROR_BIT \
156 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
157 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
158 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
159 #define SDXC_INTERRUPT_DONE_BIT \
160 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
161 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
164 #define SDXC_RXWL_FLAG BIT(0)
165 #define SDXC_TXWL_FLAG BIT(1)
166 #define SDXC_FIFO_EMPTY BIT(2)
167 #define SDXC_FIFO_FULL BIT(3)
168 #define SDXC_CARD_PRESENT BIT(8)
169 #define SDXC_CARD_DATA_BUSY BIT(9)
170 #define SDXC_DATA_FSM_BUSY BIT(10)
171 #define SDXC_DMA_REQUEST BIT(31)
172 #define SDXC_FIFO_SIZE 16
174 /* Function select */
175 #define SDXC_CEATA_ON (0xceaa << 16)
176 #define SDXC_SEND_IRQ_RESPONSE BIT(0)
177 #define SDXC_SDIO_READ_WAIT BIT(1)
178 #define SDXC_ABORT_READ_DATA BIT(2)
179 #define SDXC_SEND_CCSD BIT(8)
180 #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
181 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
183 /* IDMA controller bus mod bit field */
184 #define SDXC_IDMAC_SOFT_RESET BIT(0)
185 #define SDXC_IDMAC_FIX_BURST BIT(1)
186 #define SDXC_IDMAC_IDMA_ON BIT(7)
187 #define SDXC_IDMAC_REFETCH_DES BIT(31)
189 /* IDMA status bit field */
190 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
191 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
192 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
193 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
194 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
195 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
196 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
197 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
198 #define SDXC_IDMAC_IDLE (0 << 13)
199 #define SDXC_IDMAC_SUSPEND (1 << 13)
200 #define SDXC_IDMAC_DESC_READ (2 << 13)
201 #define SDXC_IDMAC_DESC_CHECK (3 << 13)
202 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
203 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
204 #define SDXC_IDMAC_READ (6 << 13)
205 #define SDXC_IDMAC_WRITE (7 << 13)
206 #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
209 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
210 * Bits 0-12: buf1 size
211 * Bits 13-25: buf2 size
212 * Bits 26-31: not used
213 * Since we only ever set buf1 size, we can simply store it directly.
215 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
216 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
217 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
218 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
219 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
220 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
221 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
223 #define SDXC_CLK_400K 0
224 #define SDXC_CLK_25M 1
225 #define SDXC_CLK_50M 2
226 #define SDXC_CLK_50M_DDR 3
227 #define SDXC_CLK_50M_DDR_8BIT 4
229 #define SDXC_2X_TIMING_MODE BIT(31)
231 #define SDXC_CAL_START BIT(15)
232 #define SDXC_CAL_DONE BIT(14)
233 #define SDXC_CAL_DL_SHIFT 8
234 #define SDXC_CAL_DL_SW_EN BIT(7)
235 #define SDXC_CAL_DL_SW_SHIFT 0
236 #define SDXC_CAL_DL_MASK 0x3f
238 #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
240 struct sunxi_mmc_clk_delay {
245 struct sunxi_idma_des {
248 __le32 buf_addr_ptr1;
249 __le32 buf_addr_ptr2;
252 struct sunxi_mmc_cfg {
253 u32 idma_des_size_bits;
254 const struct sunxi_mmc_clk_delay *clk_delays;
256 /* does the IP block support autocalibration? */
259 /* Does DATA0 needs to be masked while the clock is updated */
262 bool needs_new_timings;
265 struct sunxi_mmc_host {
266 struct mmc_host *mmc;
267 struct reset_control *reset;
268 const struct sunxi_mmc_cfg *cfg;
270 /* IO mapping base */
271 void __iomem *reg_base;
273 /* clock management */
276 struct clk *clk_sample;
277 struct clk *clk_output;
290 struct mmc_request *mrq;
291 struct mmc_request *manual_stop_mrq;
298 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
300 unsigned long expire = jiffies + msecs_to_jiffies(250);
303 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
305 rval = mmc_readl(host, REG_GCTRL);
306 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
308 if (rval & SDXC_HARDWARE_RESET) {
309 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
316 static int sunxi_mmc_init_host(struct mmc_host *mmc)
319 struct sunxi_mmc_host *host = mmc_priv(mmc);
321 if (sunxi_mmc_reset_host(host))
325 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
327 * TODO: sun9i has a larger FIFO and supports higher trigger values
329 mmc_writel(host, REG_FTRGL, 0x20070008);
330 /* Maximum timeout value */
331 mmc_writel(host, REG_TMOUT, 0xffffffff);
332 /* Unmask SDIO interrupt if needed */
333 mmc_writel(host, REG_IMASK, host->sdio_imask);
334 /* Clear all pending interrupts */
335 mmc_writel(host, REG_RINTR, 0xffffffff);
336 /* Debug register? undocumented */
337 mmc_writel(host, REG_DBGC, 0xdeb);
338 /* Enable CEATA support */
339 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
340 /* Set DMA descriptor list base address */
341 mmc_writel(host, REG_DLBA, host->sg_dma);
343 rval = mmc_readl(host, REG_GCTRL);
344 rval |= SDXC_INTERRUPT_ENABLE_BIT;
345 /* Undocumented, but found in Allwinner code */
346 rval &= ~SDXC_ACCESS_DONE_DIRECT;
347 mmc_writel(host, REG_GCTRL, rval);
352 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
353 struct mmc_data *data)
355 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
356 dma_addr_t next_desc = host->sg_dma;
357 int i, max_len = (1 << host->cfg->idma_des_size_bits);
359 for (i = 0; i < data->sg_len; i++) {
360 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
361 SDXC_IDMAC_DES0_OWN |
362 SDXC_IDMAC_DES0_DIC);
364 if (data->sg[i].length == max_len)
365 pdes[i].buf_size = 0; /* 0 == max_len */
367 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
369 next_desc += sizeof(struct sunxi_idma_des);
370 pdes[i].buf_addr_ptr1 =
371 cpu_to_le32(sg_dma_address(&data->sg[i]));
372 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
375 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
376 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
378 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
379 pdes[i - 1].buf_addr_ptr2 = 0;
382 * Avoid the io-store starting the idmac hitting io-mem before the
383 * descriptors hit the main-mem.
388 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
390 if (data->flags & MMC_DATA_WRITE)
391 return DMA_TO_DEVICE;
393 return DMA_FROM_DEVICE;
396 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
397 struct mmc_data *data)
400 struct scatterlist *sg;
402 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
403 sunxi_mmc_get_dma_dir(data));
405 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
409 for_each_sg(data->sg, sg, data->sg_len, i) {
410 if (sg->offset & 3 || sg->length & 3) {
411 dev_err(mmc_dev(host->mmc),
412 "unaligned scatterlist: os %x length %d\n",
413 sg->offset, sg->length);
421 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
422 struct mmc_data *data)
426 sunxi_mmc_init_idma_des(host, data);
428 rval = mmc_readl(host, REG_GCTRL);
429 rval |= SDXC_DMA_ENABLE_BIT;
430 mmc_writel(host, REG_GCTRL, rval);
431 rval |= SDXC_DMA_RESET;
432 mmc_writel(host, REG_GCTRL, rval);
434 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
436 if (!(data->flags & MMC_DATA_WRITE))
437 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
439 mmc_writel(host, REG_DMAC,
440 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
443 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
444 struct mmc_request *req)
446 u32 arg, cmd_val, ri;
447 unsigned long expire = jiffies + msecs_to_jiffies(1000);
449 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
450 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
452 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
453 cmd_val |= SD_IO_RW_DIRECT;
454 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
455 ((req->cmd->arg >> 28) & 0x7);
457 cmd_val |= MMC_STOP_TRANSMISSION;
461 mmc_writel(host, REG_CARG, arg);
462 mmc_writel(host, REG_CMDR, cmd_val);
465 ri = mmc_readl(host, REG_RINTR);
466 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
467 time_before(jiffies, expire));
469 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
470 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
472 req->stop->resp[0] = -ETIMEDOUT;
475 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
478 mmc_writel(host, REG_RINTR, 0xffff);
481 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
483 struct mmc_command *cmd = host->mrq->cmd;
484 struct mmc_data *data = host->mrq->data;
486 /* For some cmds timeout is normal with sd/mmc cards */
487 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
488 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
489 cmd->opcode == SD_IO_RW_DIRECT))
492 dev_err(mmc_dev(host->mmc),
493 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
494 host->mmc->index, cmd->opcode,
495 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
496 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
497 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
498 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
499 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
500 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
501 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
502 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
503 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
504 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
508 /* Called in interrupt context! */
509 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
511 struct mmc_request *mrq = host->mrq;
512 struct mmc_data *data = mrq->data;
515 mmc_writel(host, REG_IMASK, host->sdio_imask);
516 mmc_writel(host, REG_IDIE, 0);
518 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
519 sunxi_mmc_dump_errinfo(host);
520 mrq->cmd->error = -ETIMEDOUT;
523 data->error = -ETIMEDOUT;
524 host->manual_stop_mrq = mrq;
528 mrq->stop->error = -ETIMEDOUT;
530 if (mrq->cmd->flags & MMC_RSP_136) {
531 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
532 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
533 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
534 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
536 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
540 data->bytes_xfered = data->blocks * data->blksz;
544 mmc_writel(host, REG_IDST, 0x337);
545 mmc_writel(host, REG_DMAC, 0);
546 rval = mmc_readl(host, REG_GCTRL);
547 rval |= SDXC_DMA_RESET;
548 mmc_writel(host, REG_GCTRL, rval);
549 rval &= ~SDXC_DMA_ENABLE_BIT;
550 mmc_writel(host, REG_GCTRL, rval);
551 rval |= SDXC_FIFO_RESET;
552 mmc_writel(host, REG_GCTRL, rval);
553 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
554 sunxi_mmc_get_dma_dir(data));
557 mmc_writel(host, REG_RINTR, 0xffff);
561 host->wait_dma = false;
563 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
566 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
568 struct sunxi_mmc_host *host = dev_id;
569 struct mmc_request *mrq;
570 u32 msk_int, idma_int;
571 bool finalize = false;
572 bool sdio_int = false;
573 irqreturn_t ret = IRQ_HANDLED;
575 spin_lock(&host->lock);
577 idma_int = mmc_readl(host, REG_IDST);
578 msk_int = mmc_readl(host, REG_MISTA);
580 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
581 host->mrq, msk_int, idma_int);
585 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
586 host->wait_dma = false;
588 host->int_sum |= msk_int;
590 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
591 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
592 !(host->int_sum & SDXC_COMMAND_DONE))
593 mmc_writel(host, REG_IMASK,
594 host->sdio_imask | SDXC_COMMAND_DONE);
595 /* Don't wait for dma on error */
596 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
598 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
603 if (msk_int & SDXC_SDIO_INTERRUPT)
606 mmc_writel(host, REG_RINTR, msk_int);
607 mmc_writel(host, REG_IDST, idma_int);
610 ret = sunxi_mmc_finalize_request(host);
612 spin_unlock(&host->lock);
614 if (finalize && ret == IRQ_HANDLED)
615 mmc_request_done(host->mmc, mrq);
618 mmc_signal_sdio_irq(host->mmc);
623 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
625 struct sunxi_mmc_host *host = dev_id;
626 struct mmc_request *mrq;
627 unsigned long iflags;
629 spin_lock_irqsave(&host->lock, iflags);
630 mrq = host->manual_stop_mrq;
631 spin_unlock_irqrestore(&host->lock, iflags);
634 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
638 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
641 * We will never have more than one outstanding request,
642 * and we do not complete the request until after
643 * we've cleared host->manual_stop_mrq so we do not need to
644 * spin lock this function.
645 * Additionally we have wait states within this function
646 * so having it in a lock is a very bad idea.
648 sunxi_mmc_send_manual_stop(host, mrq);
650 spin_lock_irqsave(&host->lock, iflags);
651 host->manual_stop_mrq = NULL;
652 spin_unlock_irqrestore(&host->lock, iflags);
654 mmc_request_done(host->mmc, mrq);
659 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
661 unsigned long expire = jiffies + msecs_to_jiffies(750);
664 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
665 oclk_en ? "en" : "dis");
667 rval = mmc_readl(host, REG_CLKCR);
668 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
671 rval |= SDXC_CARD_CLOCK_ON;
672 if (host->cfg->mask_data0)
673 rval |= SDXC_MASK_DATA0;
675 mmc_writel(host, REG_CLKCR, rval);
677 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
678 mmc_writel(host, REG_CMDR, rval);
681 rval = mmc_readl(host, REG_CMDR);
682 } while (time_before(jiffies, expire) && (rval & SDXC_START));
684 /* clear irq status bits set by the command */
685 mmc_writel(host, REG_RINTR,
686 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
688 if (rval & SDXC_START) {
689 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
693 if (host->cfg->mask_data0) {
694 rval = mmc_readl(host, REG_CLKCR);
695 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
701 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
703 if (!host->cfg->can_calibrate)
708 * This is not clear how the calibration is supposed to work
709 * yet. The best rate have been obtained by simply setting the
710 * delay to 0, as Allwinner does in its BSP.
712 * The only mode that doesn't have such a delay is HS400, that
713 * is in itself a TODO.
715 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
720 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
721 struct mmc_ios *ios, u32 rate)
725 if (!host->cfg->clk_delays)
728 /* determine delays */
729 if (rate <= 400000) {
730 index = SDXC_CLK_400K;
731 } else if (rate <= 25000000) {
732 index = SDXC_CLK_25M;
733 } else if (rate <= 52000000) {
734 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
735 ios->timing != MMC_TIMING_MMC_DDR52) {
736 index = SDXC_CLK_50M;
737 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
738 index = SDXC_CLK_50M_DDR_8BIT;
740 index = SDXC_CLK_50M_DDR;
743 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
747 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
748 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
753 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
756 struct mmc_host *mmc = host->mmc;
758 u32 rval, clock = ios->clock;
761 ret = sunxi_mmc_oclk_onoff(host, 0);
765 /* Our clock is gated now */
766 mmc->actual_clock = 0;
771 /* 8 bit DDR requires a higher module clock */
772 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
773 ios->bus_width == MMC_BUS_WIDTH_8)
776 rate = clk_round_rate(host->clk_mmc, clock);
778 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
782 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
785 /* setting clock rate */
786 ret = clk_set_rate(host->clk_mmc, rate);
788 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
793 /* clear internal divider */
794 rval = mmc_readl(host, REG_CLKCR);
796 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
797 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
798 ios->bus_width == MMC_BUS_WIDTH_8) {
802 mmc_writel(host, REG_CLKCR, rval);
804 if (host->cfg->needs_new_timings)
805 mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
807 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
811 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
818 * In HS400 we'll also need to calibrate the data strobe
819 * signal. This should only happen on the MMC2 controller (at
823 ret = sunxi_mmc_oclk_onoff(host, 1);
827 /* And we just enabled our clock back */
828 mmc->actual_clock = rate;
833 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
835 struct sunxi_mmc_host *host = mmc_priv(mmc);
838 /* Set the power state */
839 switch (ios->power_mode) {
844 if (!IS_ERR(mmc->supply.vmmc)) {
845 host->ferror = mmc_regulator_set_ocr(mmc,
852 if (!IS_ERR(mmc->supply.vqmmc)) {
853 host->ferror = regulator_enable(mmc->supply.vqmmc);
855 dev_err(mmc_dev(mmc),
856 "failed to enable vqmmc\n");
859 host->vqmmc_enabled = true;
862 host->ferror = sunxi_mmc_init_host(mmc);
866 dev_dbg(mmc_dev(mmc), "power on!\n");
870 dev_dbg(mmc_dev(mmc), "power off!\n");
871 sunxi_mmc_reset_host(host);
872 if (!IS_ERR(mmc->supply.vmmc))
873 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
875 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
876 regulator_disable(mmc->supply.vqmmc);
877 host->vqmmc_enabled = false;
882 switch (ios->bus_width) {
883 case MMC_BUS_WIDTH_1:
884 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
886 case MMC_BUS_WIDTH_4:
887 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
889 case MMC_BUS_WIDTH_8:
890 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
895 rval = mmc_readl(host, REG_GCTRL);
896 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
897 ios->timing == MMC_TIMING_MMC_DDR52)
898 rval |= SDXC_DDR_MODE;
900 rval &= ~SDXC_DDR_MODE;
901 mmc_writel(host, REG_GCTRL, rval);
904 if (ios->power_mode) {
905 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
906 /* Android code had a usleep_range(50000, 55000); here */
910 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
912 /* vqmmc regulator is available */
913 if (!IS_ERR(mmc->supply.vqmmc))
914 return mmc_regulator_set_vqmmc(mmc, ios);
916 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
917 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
923 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
925 struct sunxi_mmc_host *host = mmc_priv(mmc);
929 spin_lock_irqsave(&host->lock, flags);
931 imask = mmc_readl(host, REG_IMASK);
933 host->sdio_imask = SDXC_SDIO_INTERRUPT;
934 imask |= SDXC_SDIO_INTERRUPT;
936 host->sdio_imask = 0;
937 imask &= ~SDXC_SDIO_INTERRUPT;
939 mmc_writel(host, REG_IMASK, imask);
940 spin_unlock_irqrestore(&host->lock, flags);
943 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
945 struct sunxi_mmc_host *host = mmc_priv(mmc);
946 mmc_writel(host, REG_HWRST, 0);
948 mmc_writel(host, REG_HWRST, 1);
952 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
954 struct sunxi_mmc_host *host = mmc_priv(mmc);
955 struct mmc_command *cmd = mrq->cmd;
956 struct mmc_data *data = mrq->data;
957 unsigned long iflags;
958 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
959 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
960 bool wait_dma = host->wait_dma;
963 /* Check for set_ios errors (should never happen) */
965 mrq->cmd->error = host->ferror;
966 mmc_request_done(mmc, mrq);
971 ret = sunxi_mmc_map_dma(host, data);
973 dev_err(mmc_dev(mmc), "map DMA failed\n");
976 mmc_request_done(mmc, mrq);
981 if (cmd->opcode == MMC_GO_IDLE_STATE) {
982 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
983 imask |= SDXC_COMMAND_DONE;
986 if (cmd->flags & MMC_RSP_PRESENT) {
987 cmd_val |= SDXC_RESP_EXPIRE;
988 if (cmd->flags & MMC_RSP_136)
989 cmd_val |= SDXC_LONG_RESPONSE;
990 if (cmd->flags & MMC_RSP_CRC)
991 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
993 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
994 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
996 if (cmd->data->stop) {
997 imask |= SDXC_AUTO_COMMAND_DONE;
998 cmd_val |= SDXC_SEND_AUTO_STOP;
1000 imask |= SDXC_DATA_OVER;
1003 if (cmd->data->flags & MMC_DATA_WRITE)
1004 cmd_val |= SDXC_WRITE;
1008 imask |= SDXC_COMMAND_DONE;
1011 imask |= SDXC_COMMAND_DONE;
1014 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1015 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1016 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1018 spin_lock_irqsave(&host->lock, iflags);
1020 if (host->mrq || host->manual_stop_mrq) {
1021 spin_unlock_irqrestore(&host->lock, iflags);
1024 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1025 sunxi_mmc_get_dma_dir(data));
1027 dev_err(mmc_dev(mmc), "request already pending\n");
1028 mrq->cmd->error = -EBUSY;
1029 mmc_request_done(mmc, mrq);
1034 mmc_writel(host, REG_BLKSZ, data->blksz);
1035 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1036 sunxi_mmc_start_dma(host, data);
1040 host->wait_dma = wait_dma;
1041 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1042 mmc_writel(host, REG_CARG, cmd->arg);
1043 mmc_writel(host, REG_CMDR, cmd_val);
1045 spin_unlock_irqrestore(&host->lock, iflags);
1048 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1050 struct sunxi_mmc_host *host = mmc_priv(mmc);
1052 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1055 static struct mmc_host_ops sunxi_mmc_ops = {
1056 .request = sunxi_mmc_request,
1057 .set_ios = sunxi_mmc_set_ios,
1058 .get_ro = mmc_gpio_get_ro,
1059 .get_cd = mmc_gpio_get_cd,
1060 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1061 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1062 .hw_reset = sunxi_mmc_hw_reset,
1063 .card_busy = sunxi_mmc_card_busy,
1066 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1067 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1068 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1069 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1070 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
1071 /* Value from A83T "new timing mode". Works but might not be right. */
1072 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
1075 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1076 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1077 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1078 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
1079 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1080 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
1083 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1084 .idma_des_size_bits = 13,
1086 .can_calibrate = false,
1089 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1090 .idma_des_size_bits = 16,
1092 .can_calibrate = false,
1095 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1096 .idma_des_size_bits = 16,
1097 .clk_delays = sunxi_mmc_clk_delays,
1098 .can_calibrate = false,
1101 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1102 .idma_des_size_bits = 16,
1103 .clk_delays = sun9i_mmc_clk_delays,
1104 .can_calibrate = false,
1107 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1108 .idma_des_size_bits = 16,
1110 .can_calibrate = true,
1112 .needs_new_timings = true,
1115 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1116 .idma_des_size_bits = 13,
1118 .can_calibrate = true,
1121 static const struct of_device_id sunxi_mmc_of_match[] = {
1122 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1123 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1124 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1125 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1126 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1127 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1130 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1132 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1133 struct platform_device *pdev)
1137 host->cfg = of_device_get_match_data(&pdev->dev);
1141 ret = mmc_regulator_get_supply(host->mmc);
1143 if (ret != -EPROBE_DEFER)
1144 dev_err(&pdev->dev, "Could not get vmmc supply\n");
1148 host->reg_base = devm_ioremap_resource(&pdev->dev,
1149 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1150 if (IS_ERR(host->reg_base))
1151 return PTR_ERR(host->reg_base);
1153 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1154 if (IS_ERR(host->clk_ahb)) {
1155 dev_err(&pdev->dev, "Could not get ahb clock\n");
1156 return PTR_ERR(host->clk_ahb);
1159 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1160 if (IS_ERR(host->clk_mmc)) {
1161 dev_err(&pdev->dev, "Could not get mmc clock\n");
1162 return PTR_ERR(host->clk_mmc);
1165 if (host->cfg->clk_delays) {
1166 host->clk_output = devm_clk_get(&pdev->dev, "output");
1167 if (IS_ERR(host->clk_output)) {
1168 dev_err(&pdev->dev, "Could not get output clock\n");
1169 return PTR_ERR(host->clk_output);
1172 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1173 if (IS_ERR(host->clk_sample)) {
1174 dev_err(&pdev->dev, "Could not get sample clock\n");
1175 return PTR_ERR(host->clk_sample);
1179 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1180 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1181 return PTR_ERR(host->reset);
1183 ret = clk_prepare_enable(host->clk_ahb);
1185 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1189 ret = clk_prepare_enable(host->clk_mmc);
1191 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1192 goto error_disable_clk_ahb;
1195 ret = clk_prepare_enable(host->clk_output);
1197 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1198 goto error_disable_clk_mmc;
1201 ret = clk_prepare_enable(host->clk_sample);
1203 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1204 goto error_disable_clk_output;
1207 if (!IS_ERR(host->reset)) {
1208 ret = reset_control_deassert(host->reset);
1210 dev_err(&pdev->dev, "reset err %d\n", ret);
1211 goto error_disable_clk_sample;
1216 * Sometimes the controller asserts the irq on boot for some reason,
1217 * make sure the controller is in a sane state before enabling irqs.
1219 ret = sunxi_mmc_reset_host(host);
1221 goto error_assert_reset;
1223 host->irq = platform_get_irq(pdev, 0);
1224 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1225 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1228 if (!IS_ERR(host->reset))
1229 reset_control_assert(host->reset);
1230 error_disable_clk_sample:
1231 clk_disable_unprepare(host->clk_sample);
1232 error_disable_clk_output:
1233 clk_disable_unprepare(host->clk_output);
1234 error_disable_clk_mmc:
1235 clk_disable_unprepare(host->clk_mmc);
1236 error_disable_clk_ahb:
1237 clk_disable_unprepare(host->clk_ahb);
1241 static int sunxi_mmc_probe(struct platform_device *pdev)
1243 struct sunxi_mmc_host *host;
1244 struct mmc_host *mmc;
1247 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1249 dev_err(&pdev->dev, "mmc alloc host failed\n");
1253 host = mmc_priv(mmc);
1255 spin_lock_init(&host->lock);
1257 ret = sunxi_mmc_resource_request(host, pdev);
1259 goto error_free_host;
1261 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1262 &host->sg_dma, GFP_KERNEL);
1263 if (!host->sg_cpu) {
1264 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1266 goto error_free_host;
1269 mmc->ops = &sunxi_mmc_ops;
1270 mmc->max_blk_count = 8192;
1271 mmc->max_blk_size = 4096;
1272 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1273 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
1274 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1275 /* 400kHz ~ 52MHz */
1276 mmc->f_min = 400000;
1277 mmc->f_max = 52000000;
1278 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1279 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1281 if (host->cfg->clk_delays)
1282 mmc->caps |= MMC_CAP_1_8V_DDR;
1284 ret = mmc_of_parse(mmc);
1286 goto error_free_dma;
1288 ret = mmc_add_host(mmc);
1290 goto error_free_dma;
1292 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1293 platform_set_drvdata(pdev, mmc);
1297 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1303 static int sunxi_mmc_remove(struct platform_device *pdev)
1305 struct mmc_host *mmc = platform_get_drvdata(pdev);
1306 struct sunxi_mmc_host *host = mmc_priv(mmc);
1308 mmc_remove_host(mmc);
1309 disable_irq(host->irq);
1310 sunxi_mmc_reset_host(host);
1312 if (!IS_ERR(host->reset))
1313 reset_control_assert(host->reset);
1315 clk_disable_unprepare(host->clk_sample);
1316 clk_disable_unprepare(host->clk_output);
1317 clk_disable_unprepare(host->clk_mmc);
1318 clk_disable_unprepare(host->clk_ahb);
1320 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1326 static struct platform_driver sunxi_mmc_driver = {
1328 .name = "sunxi-mmc",
1329 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1331 .probe = sunxi_mmc_probe,
1332 .remove = sunxi_mmc_remove,
1334 module_platform_driver(sunxi_mmc_driver);
1336 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1337 MODULE_LICENSE("GPL v2");
1338 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1339 MODULE_ALIAS("platform:sunxi-mmc");