drivers/mmc/host/sunxi-mmc.c

   1 /*
   2  * Driver for sunxi SD/MMC host controllers
   3  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
   4  * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
   5  * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
   6  * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
   7  * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
   8  * (C) Copyright 2017 Sootech SA
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/io.h>
  19 #include <linux/device.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23
  24 #include <linux/clk.h>
  25 #include <linux/gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/scatterlist.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/reset.h>
  32 #include <linux/regulator/consumer.h>
  33
  34 #include <linux/of_address.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/of_platform.h>
  37
  38 #include <linux/mmc/host.h>
  39 #include <linux/mmc/sd.h>
  40 #include <linux/mmc/sdio.h>
  41 #include <linux/mmc/mmc.h>
  42 #include <linux/mmc/core.h>
  43 #include <linux/mmc/card.h>
  44 #include <linux/mmc/slot-gpio.h>
  45
  46 /* register offset definitions */
  47 #define SDXC_REG_GCTRL  (0x00) /* SMC Global Control Register */
  48 #define SDXC_REG_CLKCR  (0x04) /* SMC Clock Control Register */
  49 #define SDXC_REG_TMOUT  (0x08) /* SMC Time Out Register */
  50 #define SDXC_REG_WIDTH  (0x0C) /* SMC Bus Width Register */
  51 #define SDXC_REG_BLKSZ  (0x10) /* SMC Block Size Register */
  52 #define SDXC_REG_BCNTR  (0x14) /* SMC Byte Count Register */
  53 #define SDXC_REG_CMDR   (0x18) /* SMC Command Register */
  54 #define SDXC_REG_CARG   (0x1C) /* SMC Argument Register */
  55 #define SDXC_REG_RESP0  (0x20) /* SMC Response Register 0 */
  56 #define SDXC_REG_RESP1  (0x24) /* SMC Response Register 1 */
  57 #define SDXC_REG_RESP2  (0x28) /* SMC Response Register 2 */
  58 #define SDXC_REG_RESP3  (0x2C) /* SMC Response Register 3 */
  59 #define SDXC_REG_IMASK  (0x30) /* SMC Interrupt Mask Register */
  60 #define SDXC_REG_MISTA  (0x34) /* SMC Masked Interrupt Status Register */
  61 #define SDXC_REG_RINTR  (0x38) /* SMC Raw Interrupt Status Register */
  62 #define SDXC_REG_STAS   (0x3C) /* SMC Status Register */
  63 #define SDXC_REG_FTRGL  (0x40) /* SMC FIFO Threshold Watermark Registe */
  64 #define SDXC_REG_FUNS   (0x44) /* SMC Function Select Register */
  65 #define SDXC_REG_CBCR   (0x48) /* SMC CIU Byte Count Register */
  66 #define SDXC_REG_BBCR   (0x4C) /* SMC BIU Byte Count Register */
  67 #define SDXC_REG_DBGC   (0x50) /* SMC Debug Enable Register */
  68 #define SDXC_REG_HWRST  (0x78) /* SMC Card Hardware Reset for Register */
  69 #define SDXC_REG_DMAC   (0x80) /* SMC IDMAC Control Register */
  70 #define SDXC_REG_DLBA   (0x84) /* SMC IDMAC Descriptor List Base Addre */
  71 #define SDXC_REG_IDST   (0x88) /* SMC IDMAC Status Register */
  72 #define SDXC_REG_IDIE   (0x8C) /* SMC IDMAC Interrupt Enable Register */
  73 #define SDXC_REG_CHDA   (0x90)
  74 #define SDXC_REG_CBDA   (0x94)
  75
  76 /* New registers introduced in A64 */
  77 #define SDXC_REG_A12A           0x058 /* SMC Auto Command 12 Register */
  78 #define SDXC_REG_SD_NTSR        0x05C /* SMC New Timing Set Register */
  79 #define SDXC_REG_DRV_DL         0x140 /* Drive Delay Control Register */
  80 #define SDXC_REG_SAMP_DL_REG    0x144 /* SMC sample delay control */
  81 #define SDXC_REG_DS_DL_REG      0x148 /* SMC data strobe delay control */
  82
  83 #define mmc_readl(host, reg) \
  84         readl((host)->reg_base + SDXC_##reg)
  85 #define mmc_writel(host, reg, value) \
  86         writel((value), (host)->reg_base + SDXC_##reg)
  87
  88 /* global control register bits */
  89 #define SDXC_SOFT_RESET                 BIT(0)
  90 #define SDXC_FIFO_RESET                 BIT(1)
  91 #define SDXC_DMA_RESET                  BIT(2)
  92 #define SDXC_INTERRUPT_ENABLE_BIT       BIT(4)
  93 #define SDXC_DMA_ENABLE_BIT             BIT(5)
  94 #define SDXC_DEBOUNCE_ENABLE_BIT        BIT(8)
  95 #define SDXC_POSEDGE_LATCH_DATA         BIT(9)
  96 #define SDXC_DDR_MODE                   BIT(10)
  97 #define SDXC_MEMORY_ACCESS_DONE         BIT(29)
  98 #define SDXC_ACCESS_DONE_DIRECT         BIT(30)
  99 #define SDXC_ACCESS_BY_AHB              BIT(31)
 100 #define SDXC_ACCESS_BY_DMA              (0 << 31)
 101 #define SDXC_HARDWARE_RESET \
 102         (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
 103
 104 /* clock control bits */
 105 #define SDXC_MASK_DATA0                 BIT(31)
 106 #define SDXC_CARD_CLOCK_ON              BIT(16)
 107 #define SDXC_LOW_POWER_ON               BIT(17)
 108
 109 /* bus width */
 110 #define SDXC_WIDTH1                     0
 111 #define SDXC_WIDTH4                     1
 112 #define SDXC_WIDTH8                     2
 113
 114 /* smc command bits */
 115 #define SDXC_RESP_EXPIRE                BIT(6)
 116 #define SDXC_LONG_RESPONSE              BIT(7)
 117 #define SDXC_CHECK_RESPONSE_CRC         BIT(8)
 118 #define SDXC_DATA_EXPIRE                BIT(9)
 119 #define SDXC_WRITE                      BIT(10)
 120 #define SDXC_SEQUENCE_MODE              BIT(11)
 121 #define SDXC_SEND_AUTO_STOP             BIT(12)
 122 #define SDXC_WAIT_PRE_OVER              BIT(13)
 123 #define SDXC_STOP_ABORT_CMD             BIT(14)
 124 #define SDXC_SEND_INIT_SEQUENCE         BIT(15)
 125 #define SDXC_UPCLK_ONLY                 BIT(21)
 126 #define SDXC_READ_CEATA_DEV             BIT(22)
 127 #define SDXC_CCS_EXPIRE                 BIT(23)
 128 #define SDXC_ENABLE_BIT_BOOT            BIT(24)
 129 #define SDXC_ALT_BOOT_OPTIONS           BIT(25)
 130 #define SDXC_BOOT_ACK_EXPIRE            BIT(26)
 131 #define SDXC_BOOT_ABORT                 BIT(27)
 132 #define SDXC_VOLTAGE_SWITCH             BIT(28)
 133 #define SDXC_USE_HOLD_REGISTER          BIT(29)
 134 #define SDXC_START                      BIT(31)
 135
 136 /* interrupt bits */
 137 #define SDXC_RESP_ERROR                 BIT(1)
 138 #define SDXC_COMMAND_DONE               BIT(2)
 139 #define SDXC_DATA_OVER                  BIT(3)
 140 #define SDXC_TX_DATA_REQUEST            BIT(4)
 141 #define SDXC_RX_DATA_REQUEST            BIT(5)
 142 #define SDXC_RESP_CRC_ERROR             BIT(6)
 143 #define SDXC_DATA_CRC_ERROR             BIT(7)
 144 #define SDXC_RESP_TIMEOUT               BIT(8)
 145 #define SDXC_DATA_TIMEOUT               BIT(9)
 146 #define SDXC_VOLTAGE_CHANGE_DONE        BIT(10)
 147 #define SDXC_FIFO_RUN_ERROR             BIT(11)
 148 #define SDXC_HARD_WARE_LOCKED           BIT(12)
 149 #define SDXC_START_BIT_ERROR            BIT(13)
 150 #define SDXC_AUTO_COMMAND_DONE          BIT(14)
 151 #define SDXC_END_BIT_ERROR              BIT(15)
 152 #define SDXC_SDIO_INTERRUPT             BIT(16)
 153 #define SDXC_CARD_INSERT                BIT(30)
 154 #define SDXC_CARD_REMOVE                BIT(31)
 155 #define SDXC_INTERRUPT_ERROR_BIT \
 156         (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
 157          SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
 158          SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
 159 #define SDXC_INTERRUPT_DONE_BIT \
 160         (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
 161          SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
 162
 163 /* status */
 164 #define SDXC_RXWL_FLAG                  BIT(0)
 165 #define SDXC_TXWL_FLAG                  BIT(1)
 166 #define SDXC_FIFO_EMPTY                 BIT(2)
 167 #define SDXC_FIFO_FULL                  BIT(3)
 168 #define SDXC_CARD_PRESENT               BIT(8)
 169 #define SDXC_CARD_DATA_BUSY             BIT(9)
 170 #define SDXC_DATA_FSM_BUSY              BIT(10)
 171 #define SDXC_DMA_REQUEST                BIT(31)
 172 #define SDXC_FIFO_SIZE                  16
 173
 174 /* Function select */
 175 #define SDXC_CEATA_ON                   (0xceaa << 16)
 176 #define SDXC_SEND_IRQ_RESPONSE          BIT(0)
 177 #define SDXC_SDIO_READ_WAIT             BIT(1)
 178 #define SDXC_ABORT_READ_DATA            BIT(2)
 179 #define SDXC_SEND_CCSD                  BIT(8)
 180 #define SDXC_SEND_AUTO_STOPCCSD         BIT(9)
 181 #define SDXC_CEATA_DEV_IRQ_ENABLE       BIT(10)
 182
 183 /* IDMA controller bus mod bit field */
 184 #define SDXC_IDMAC_SOFT_RESET           BIT(0)
 185 #define SDXC_IDMAC_FIX_BURST            BIT(1)
 186 #define SDXC_IDMAC_IDMA_ON              BIT(7)
 187 #define SDXC_IDMAC_REFETCH_DES          BIT(31)
 188
 189 /* IDMA status bit field */
 190 #define SDXC_IDMAC_TRANSMIT_INTERRUPT           BIT(0)
 191 #define SDXC_IDMAC_RECEIVE_INTERRUPT            BIT(1)
 192 #define SDXC_IDMAC_FATAL_BUS_ERROR              BIT(2)
 193 #define SDXC_IDMAC_DESTINATION_INVALID          BIT(4)
 194 #define SDXC_IDMAC_CARD_ERROR_SUM               BIT(5)
 195 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM         BIT(8)
 196 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM       BIT(9)
 197 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT         BIT(10)
 198 #define SDXC_IDMAC_IDLE                         (0 << 13)
 199 #define SDXC_IDMAC_SUSPEND                      (1 << 13)
 200 #define SDXC_IDMAC_DESC_READ                    (2 << 13)
 201 #define SDXC_IDMAC_DESC_CHECK                   (3 << 13)
 202 #define SDXC_IDMAC_READ_REQUEST_WAIT            (4 << 13)
 203 #define SDXC_IDMAC_WRITE_REQUEST_WAIT           (5 << 13)
 204 #define SDXC_IDMAC_READ                         (6 << 13)
 205 #define SDXC_IDMAC_WRITE                        (7 << 13)
 206 #define SDXC_IDMAC_DESC_CLOSE                   (8 << 13)
 207
 208 /*
 209 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
 210 *  Bits  0-12: buf1 size
 211 *  Bits 13-25: buf2 size
 212 *  Bits 26-31: not used
 213 * Since we only ever set buf1 size, we can simply store it directly.
 214 */
 215 #define SDXC_IDMAC_DES0_DIC     BIT(1)  /* disable interrupt on completion */
 216 #define SDXC_IDMAC_DES0_LD      BIT(2)  /* last descriptor */
 217 #define SDXC_IDMAC_DES0_FD      BIT(3)  /* first descriptor */
 218 #define SDXC_IDMAC_DES0_CH      BIT(4)  /* chain mode */
 219 #define SDXC_IDMAC_DES0_ER      BIT(5)  /* end of ring */
 220 #define SDXC_IDMAC_DES0_CES     BIT(30) /* card error summary */
 221 #define SDXC_IDMAC_DES0_OWN     BIT(31) /* 1-idma owns it, 0-host owns it */
 222
 223 #define SDXC_CLK_400K           0
 224 #define SDXC_CLK_25M            1
 225 #define SDXC_CLK_50M            2
 226 #define SDXC_CLK_50M_DDR        3
 227 #define SDXC_CLK_50M_DDR_8BIT   4
 228
 229 #define SDXC_2X_TIMING_MODE     BIT(31)
 230
 231 #define SDXC_CAL_START          BIT(15)
 232 #define SDXC_CAL_DONE           BIT(14)
 233 #define SDXC_CAL_DL_SHIFT       8
 234 #define SDXC_CAL_DL_SW_EN       BIT(7)
 235 #define SDXC_CAL_DL_SW_SHIFT    0
 236 #define SDXC_CAL_DL_MASK        0x3f
 237
 238 #define SDXC_CAL_TIMEOUT        3       /* in seconds, 3s is enough*/
 239
 240 struct sunxi_mmc_clk_delay {
 241         u32 output;
 242         u32 sample;
 243 };
 244
 245 struct sunxi_idma_des {
 246         __le32 config;
 247         __le32 buf_size;
 248         __le32 buf_addr_ptr1;
 249         __le32 buf_addr_ptr2;
 250 };
 251
 252 struct sunxi_mmc_cfg {
 253         u32 idma_des_size_bits;
 254         const struct sunxi_mmc_clk_delay *clk_delays;
 255
 256         /* does the IP block support autocalibration? */
 257         bool can_calibrate;
 258
 259         /* Does DATA0 needs to be masked while the clock is updated */
 260         bool mask_data0;
 261
 262         bool needs_new_timings;
 263 };
 264
 265 struct sunxi_mmc_host {
 266         struct mmc_host *mmc;
 267         struct reset_control *reset;
 268         const struct sunxi_mmc_cfg *cfg;
 269
 270         /* IO mapping base */
 271         void __iomem    *reg_base;
 272
 273         /* clock management */
 274         struct clk      *clk_ahb;
 275         struct clk      *clk_mmc;
 276         struct clk      *clk_sample;
 277         struct clk      *clk_output;
 278
 279         /* irq */
 280         spinlock_t      lock;
 281         int             irq;
 282         u32             int_sum;
 283         u32             sdio_imask;
 284
 285         /* dma */
 286         dma_addr_t      sg_dma;
 287         void            *sg_cpu;
 288         bool            wait_dma;
 289
 290         struct mmc_request *mrq;
 291         struct mmc_request *manual_stop_mrq;
 292         int             ferror;
 293
 294         /* vqmmc */
 295         bool            vqmmc_enabled;
 296 };
 297
 298 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
 299 {
 300         unsigned long expire = jiffies + msecs_to_jiffies(250);
 301         u32 rval;
 302
 303         mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
 304         do {
 305                 rval = mmc_readl(host, REG_GCTRL);
 306         } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
 307
 308         if (rval & SDXC_HARDWARE_RESET) {
 309                 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
 310                 return -EIO;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int sunxi_mmc_init_host(struct mmc_host *mmc)
 317 {
 318         u32 rval;
 319         struct sunxi_mmc_host *host = mmc_priv(mmc);
 320
 321         if (sunxi_mmc_reset_host(host))
 322                 return -EIO;
 323
 324         /*
 325          * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
 326          *
 327          * TODO: sun9i has a larger FIFO and supports higher trigger values
 328          */
 329         mmc_writel(host, REG_FTRGL, 0x20070008);
 330         /* Maximum timeout value */
 331         mmc_writel(host, REG_TMOUT, 0xffffffff);
 332         /* Unmask SDIO interrupt if needed */
 333         mmc_writel(host, REG_IMASK, host->sdio_imask);
 334         /* Clear all pending interrupts */
 335         mmc_writel(host, REG_RINTR, 0xffffffff);
 336         /* Debug register? undocumented */
 337         mmc_writel(host, REG_DBGC, 0xdeb);
 338         /* Enable CEATA support */
 339         mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
 340         /* Set DMA descriptor list base address */
 341         mmc_writel(host, REG_DLBA, host->sg_dma);
 342
 343         rval = mmc_readl(host, REG_GCTRL);
 344         rval |= SDXC_INTERRUPT_ENABLE_BIT;
 345         /* Undocumented, but found in Allwinner code */
 346         rval &= ~SDXC_ACCESS_DONE_DIRECT;
 347         mmc_writel(host, REG_GCTRL, rval);
 348
 349         return 0;
 350 }
 351
 352 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 353                                     struct mmc_data *data)
 354 {
 355         struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
 356         dma_addr_t next_desc = host->sg_dma;
 357         int i, max_len = (1 << host->cfg->idma_des_size_bits);
 358
 359         for (i = 0; i < data->sg_len; i++) {
 360                 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
 361                                              SDXC_IDMAC_DES0_OWN |
 362                                              SDXC_IDMAC_DES0_DIC);
 363
 364                 if (data->sg[i].length == max_len)
 365                         pdes[i].buf_size = 0; /* 0 == max_len */
 366                 else
 367                         pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
 368
 369                 next_desc += sizeof(struct sunxi_idma_des);
 370                 pdes[i].buf_addr_ptr1 =
 371                         cpu_to_le32(sg_dma_address(&data->sg[i]));
 372                 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
 373         }
 374
 375         pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
 376         pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
 377                                           SDXC_IDMAC_DES0_ER);
 378         pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
 379         pdes[i - 1].buf_addr_ptr2 = 0;
 380
 381         /*
 382          * Avoid the io-store starting the idmac hitting io-mem before the
 383          * descriptors hit the main-mem.
 384          */
 385         wmb();
 386 }
 387
 388 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
 389                              struct mmc_data *data)
 390 {
 391         u32 i, dma_len;
 392         struct scatterlist *sg;
 393
 394         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 395                              mmc_get_dma_dir(data));
 396         if (dma_len == 0) {
 397                 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
 398                 return -ENOMEM;
 399         }
 400
 401         for_each_sg(data->sg, sg, data->sg_len, i) {
 402                 if (sg->offset & 3 || sg->length & 3) {
 403                         dev_err(mmc_dev(host->mmc),
 404                                 "unaligned scatterlist: os %x length %d\n",
 405                                 sg->offset, sg->length);
 406                         return -EINVAL;
 407                 }
 408         }
 409
 410         return 0;
 411 }
 412
 413 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
 414                                 struct mmc_data *data)
 415 {
 416         u32 rval;
 417
 418         sunxi_mmc_init_idma_des(host, data);
 419
 420         rval = mmc_readl(host, REG_GCTRL);
 421         rval |= SDXC_DMA_ENABLE_BIT;
 422         mmc_writel(host, REG_GCTRL, rval);
 423         rval |= SDXC_DMA_RESET;
 424         mmc_writel(host, REG_GCTRL, rval);
 425
 426         mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
 427
 428         if (!(data->flags & MMC_DATA_WRITE))
 429                 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
 430
 431         mmc_writel(host, REG_DMAC,
 432                    SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
 433 }
 434
 435 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
 436                                        struct mmc_request *req)
 437 {
 438         u32 arg, cmd_val, ri;
 439         unsigned long expire = jiffies + msecs_to_jiffies(1000);
 440
 441         cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
 442                   SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
 443
 444         if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
 445                 cmd_val |= SD_IO_RW_DIRECT;
 446                 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 447                       ((req->cmd->arg >> 28) & 0x7);
 448         } else {
 449                 cmd_val |= MMC_STOP_TRANSMISSION;
 450                 arg = 0;
 451         }
 452
 453         mmc_writel(host, REG_CARG, arg);
 454         mmc_writel(host, REG_CMDR, cmd_val);
 455
 456         do {
 457                 ri = mmc_readl(host, REG_RINTR);
 458         } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
 459                  time_before(jiffies, expire));
 460
 461         if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
 462                 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
 463                 if (req->stop)
 464                         req->stop->resp[0] = -ETIMEDOUT;
 465         } else {
 466                 if (req->stop)
 467                         req->stop->resp[0] = mmc_readl(host, REG_RESP0);
 468         }
 469
 470         mmc_writel(host, REG_RINTR, 0xffff);
 471 }
 472
 473 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
 474 {
 475         struct mmc_command *cmd = host->mrq->cmd;
 476         struct mmc_data *data = host->mrq->data;
 477
 478         /* For some cmds timeout is normal with sd/mmc cards */
 479         if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
 480                 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
 481                                       cmd->opcode == SD_IO_RW_DIRECT))
 482                 return;
 483
 484         dev_dbg(mmc_dev(host->mmc),
 485                 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
 486                 host->mmc->index, cmd->opcode,
 487                 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
 488                 host->int_sum & SDXC_RESP_ERROR     ? " RE"     : "",
 489                 host->int_sum & SDXC_RESP_CRC_ERROR  ? " RCE"    : "",
 490                 host->int_sum & SDXC_DATA_CRC_ERROR  ? " DCE"    : "",
 491                 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO"    : "",
 492                 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO"    : "",
 493                 host->int_sum & SDXC_FIFO_RUN_ERROR  ? " FE"     : "",
 494                 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL"     : "",
 495                 host->int_sum & SDXC_START_BIT_ERROR ? " SBE"    : "",
 496                 host->int_sum & SDXC_END_BIT_ERROR   ? " EBE"    : ""
 497                 );
 498 }
 499
 500 /* Called in interrupt context! */
 501 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
 502 {
 503         struct mmc_request *mrq = host->mrq;
 504         struct mmc_data *data = mrq->data;
 505         u32 rval;
 506
 507         mmc_writel(host, REG_IMASK, host->sdio_imask);
 508         mmc_writel(host, REG_IDIE, 0);
 509
 510         if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
 511                 sunxi_mmc_dump_errinfo(host);
 512                 mrq->cmd->error = -ETIMEDOUT;
 513
 514                 if (data) {
 515                         data->error = -ETIMEDOUT;
 516                         host->manual_stop_mrq = mrq;
 517                 }
 518
 519                 if (mrq->stop)
 520                         mrq->stop->error = -ETIMEDOUT;
 521         } else {
 522                 if (mrq->cmd->flags & MMC_RSP_136) {
 523                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
 524                         mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
 525                         mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
 526                         mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
 527                 } else {
 528                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
 529                 }
 530
 531                 if (data)
 532                         data->bytes_xfered = data->blocks * data->blksz;
 533         }
 534
 535         if (data) {
 536                 mmc_writel(host, REG_IDST, 0x337);
 537                 mmc_writel(host, REG_DMAC, 0);
 538                 rval = mmc_readl(host, REG_GCTRL);
 539                 rval |= SDXC_DMA_RESET;
 540                 mmc_writel(host, REG_GCTRL, rval);
 541                 rval &= ~SDXC_DMA_ENABLE_BIT;
 542                 mmc_writel(host, REG_GCTRL, rval);
 543                 rval |= SDXC_FIFO_RESET;
 544                 mmc_writel(host, REG_GCTRL, rval);
 545                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 546                              mmc_get_dma_dir(data));
 547         }
 548
 549         mmc_writel(host, REG_RINTR, 0xffff);
 550
 551         host->mrq = NULL;
 552         host->int_sum = 0;
 553         host->wait_dma = false;
 554
 555         return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
 556 }
 557
 558 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
 559 {
 560         struct sunxi_mmc_host *host = dev_id;
 561         struct mmc_request *mrq;
 562         u32 msk_int, idma_int;
 563         bool finalize = false;
 564         bool sdio_int = false;
 565         irqreturn_t ret = IRQ_HANDLED;
 566
 567         spin_lock(&host->lock);
 568
 569         idma_int  = mmc_readl(host, REG_IDST);
 570         msk_int   = mmc_readl(host, REG_MISTA);
 571
 572         dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
 573                 host->mrq, msk_int, idma_int);
 574
 575         mrq = host->mrq;
 576         if (mrq) {
 577                 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
 578                         host->wait_dma = false;
 579
 580                 host->int_sum |= msk_int;
 581
 582                 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
 583                 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
 584                                 !(host->int_sum & SDXC_COMMAND_DONE))
 585                         mmc_writel(host, REG_IMASK,
 586                                    host->sdio_imask | SDXC_COMMAND_DONE);
 587                 /* Don't wait for dma on error */
 588                 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
 589                         finalize = true;
 590                 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
 591                                 !host->wait_dma)
 592                         finalize = true;
 593         }
 594
 595         if (msk_int & SDXC_SDIO_INTERRUPT)
 596                 sdio_int = true;
 597
 598         mmc_writel(host, REG_RINTR, msk_int);
 599         mmc_writel(host, REG_IDST, idma_int);
 600
 601         if (finalize)
 602                 ret = sunxi_mmc_finalize_request(host);
 603
 604         spin_unlock(&host->lock);
 605
 606         if (finalize && ret == IRQ_HANDLED)
 607                 mmc_request_done(host->mmc, mrq);
 608
 609         if (sdio_int)
 610                 mmc_signal_sdio_irq(host->mmc);
 611
 612         return ret;
 613 }
 614
 615 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
 616 {
 617         struct sunxi_mmc_host *host = dev_id;
 618         struct mmc_request *mrq;
 619         unsigned long iflags;
 620
 621         spin_lock_irqsave(&host->lock, iflags);
 622         mrq = host->manual_stop_mrq;
 623         spin_unlock_irqrestore(&host->lock, iflags);
 624
 625         if (!mrq) {
 626                 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
 627                 return IRQ_HANDLED;
 628         }
 629
 630         dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
 631
 632         /*
 633          * We will never have more than one outstanding request,
 634          * and we do not complete the request until after
 635          * we've cleared host->manual_stop_mrq so we do not need to
 636          * spin lock this function.
 637          * Additionally we have wait states within this function
 638          * so having it in a lock is a very bad idea.
 639          */
 640         sunxi_mmc_send_manual_stop(host, mrq);
 641
 642         spin_lock_irqsave(&host->lock, iflags);
 643         host->manual_stop_mrq = NULL;
 644         spin_unlock_irqrestore(&host->lock, iflags);
 645
 646         mmc_request_done(host->mmc, mrq);
 647
 648         return IRQ_HANDLED;
 649 }
 650
 651 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 652 {
 653         unsigned long expire = jiffies + msecs_to_jiffies(750);
 654         u32 rval;
 655
 656         dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
 657                 oclk_en ? "en" : "dis");
 658
 659         rval = mmc_readl(host, REG_CLKCR);
 660         rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
 661
 662         if (oclk_en)
 663                 rval |= SDXC_CARD_CLOCK_ON;
 664         if (host->cfg->mask_data0)
 665                 rval |= SDXC_MASK_DATA0;
 666
 667         mmc_writel(host, REG_CLKCR, rval);
 668
 669         rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
 670         mmc_writel(host, REG_CMDR, rval);
 671
 672         do {
 673                 rval = mmc_readl(host, REG_CMDR);
 674         } while (time_before(jiffies, expire) && (rval & SDXC_START));
 675
 676         /* clear irq status bits set by the command */
 677         mmc_writel(host, REG_RINTR,
 678                    mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
 679
 680         if (rval & SDXC_START) {
 681                 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
 682                 return -EIO;
 683         }
 684
 685         if (host->cfg->mask_data0) {
 686                 rval = mmc_readl(host, REG_CLKCR);
 687                 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
 694 {
 695         if (!host->cfg->can_calibrate)
 696                 return 0;
 697
 698         /*
 699          * FIXME:
 700          * This is not clear how the calibration is supposed to work
 701          * yet. The best rate have been obtained by simply setting the
 702          * delay to 0, as Allwinner does in its BSP.
 703          *
 704          * The only mode that doesn't have such a delay is HS400, that
 705          * is in itself a TODO.
 706          */
 707         writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
 708
 709         return 0;
 710 }
 711
 712 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
 713                                    struct mmc_ios *ios, u32 rate)
 714 {
 715         int index;
 716
 717         if (!host->cfg->clk_delays)
 718                 return 0;
 719
 720         /* determine delays */
 721         if (rate <= 400000) {
 722                 index = SDXC_CLK_400K;
 723         } else if (rate <= 25000000) {
 724                 index = SDXC_CLK_25M;
 725         } else if (rate <= 52000000) {
 726                 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
 727                     ios->timing != MMC_TIMING_MMC_DDR52) {
 728                         index = SDXC_CLK_50M;
 729                 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
 730                         index = SDXC_CLK_50M_DDR_8BIT;
 731                 } else {
 732                         index = SDXC_CLK_50M_DDR;
 733                 }
 734         } else {
 735                 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
 736                 return -EINVAL;
 737         }
 738
 739         clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
 740         clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
 741
 742         return 0;
 743 }
 744
 745 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 746                                   struct mmc_ios *ios)
 747 {
 748         struct mmc_host *mmc = host->mmc;
 749         long rate;
 750         u32 rval, clock = ios->clock;
 751         int ret;
 752
 753         ret = sunxi_mmc_oclk_onoff(host, 0);
 754         if (ret)
 755                 return ret;
 756
 757         /* Our clock is gated now */
 758         mmc->actual_clock = 0;
 759
 760         if (!ios->clock)
 761                 return 0;
 762
 763         /* 8 bit DDR requires a higher module clock */
 764         if (ios->timing == MMC_TIMING_MMC_DDR52 &&
 765             ios->bus_width == MMC_BUS_WIDTH_8)
 766                 clock <<= 1;
 767
 768         rate = clk_round_rate(host->clk_mmc, clock);
 769         if (rate < 0) {
 770                 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
 771                         clock, rate);
 772                 return rate;
 773         }
 774         dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
 775                 clock, rate);
 776
 777         /* setting clock rate */
 778         ret = clk_set_rate(host->clk_mmc, rate);
 779         if (ret) {
 780                 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
 781                         rate, ret);
 782                 return ret;
 783         }
 784
 785         /* clear internal divider */
 786         rval = mmc_readl(host, REG_CLKCR);
 787         rval &= ~0xff;
 788         /* set internal divider for 8 bit eMMC DDR, so card clock is right */
 789         if (ios->timing == MMC_TIMING_MMC_DDR52 &&
 790             ios->bus_width == MMC_BUS_WIDTH_8) {
 791                 rval |= 1;
 792                 rate >>= 1;
 793         }
 794         mmc_writel(host, REG_CLKCR, rval);
 795
 796         if (host->cfg->needs_new_timings)
 797                 mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
 798
 799         ret = sunxi_mmc_clk_set_phase(host, ios, rate);
 800         if (ret)
 801                 return ret;
 802
 803         ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
 804         if (ret)
 805                 return ret;
 806
 807         /*
 808          * FIXME:
 809          *
 810          * In HS400 we'll also need to calibrate the data strobe
 811          * signal. This should only happen on the MMC2 controller (at
 812          * least on the A64).
 813          */
 814
 815         ret = sunxi_mmc_oclk_onoff(host, 1);
 816         if (ret)
 817                 return ret;
 818
 819         /* And we just enabled our clock back */
 820         mmc->actual_clock = rate;
 821
 822         return 0;
 823 }
 824
 825 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 826 {
 827         struct sunxi_mmc_host *host = mmc_priv(mmc);
 828         u32 rval;
 829
 830         /* Set the power state */
 831         switch (ios->power_mode) {
 832         case MMC_POWER_ON:
 833                 break;
 834
 835         case MMC_POWER_UP:
 836                 if (!IS_ERR(mmc->supply.vmmc)) {
 837                         host->ferror = mmc_regulator_set_ocr(mmc,
 838                                                              mmc->supply.vmmc,
 839                                                              ios->vdd);
 840                         if (host->ferror)
 841                                 return;
 842                 }
 843
 844                 if (!IS_ERR(mmc->supply.vqmmc)) {
 845                         host->ferror = regulator_enable(mmc->supply.vqmmc);
 846                         if (host->ferror) {
 847                                 dev_err(mmc_dev(mmc),
 848                                         "failed to enable vqmmc\n");
 849                                 return;
 850                         }
 851                         host->vqmmc_enabled = true;
 852                 }
 853
 854                 host->ferror = sunxi_mmc_init_host(mmc);
 855                 if (host->ferror)
 856                         return;
 857
 858                 dev_dbg(mmc_dev(mmc), "power on!\n");
 859                 break;
 860
 861         case MMC_POWER_OFF:
 862                 dev_dbg(mmc_dev(mmc), "power off!\n");
 863                 sunxi_mmc_reset_host(host);
 864                 if (!IS_ERR(mmc->supply.vmmc))
 865                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 866
 867                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
 868                         regulator_disable(mmc->supply.vqmmc);
 869                 host->vqmmc_enabled = false;
 870                 break;
 871         }
 872
 873         /* set bus width */
 874         switch (ios->bus_width) {
 875         case MMC_BUS_WIDTH_1:
 876                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
 877                 break;
 878         case MMC_BUS_WIDTH_4:
 879                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
 880                 break;
 881         case MMC_BUS_WIDTH_8:
 882                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
 883                 break;
 884         }
 885
 886         /* set ddr mode */
 887         rval = mmc_readl(host, REG_GCTRL);
 888         if (ios->timing == MMC_TIMING_UHS_DDR50 ||
 889             ios->timing == MMC_TIMING_MMC_DDR52)
 890                 rval |= SDXC_DDR_MODE;
 891         else
 892                 rval &= ~SDXC_DDR_MODE;
 893         mmc_writel(host, REG_GCTRL, rval);
 894
 895         /* set up clock */
 896         if (ios->power_mode) {
 897                 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
 898                 /* Android code had a usleep_range(50000, 55000); here */
 899         }
 900 }
 901
 902 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
 903 {
 904         /* vqmmc regulator is available */
 905         if (!IS_ERR(mmc->supply.vqmmc))
 906                 return mmc_regulator_set_vqmmc(mmc, ios);
 907
 908         /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
 909         if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 910                 return 0;
 911
 912         return -EINVAL;
 913 }
 914
 915 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 916 {
 917         struct sunxi_mmc_host *host = mmc_priv(mmc);
 918         unsigned long flags;
 919         u32 imask;
 920
 921         spin_lock_irqsave(&host->lock, flags);
 922
 923         imask = mmc_readl(host, REG_IMASK);
 924         if (enable) {
 925                 host->sdio_imask = SDXC_SDIO_INTERRUPT;
 926                 imask |= SDXC_SDIO_INTERRUPT;
 927         } else {
 928                 host->sdio_imask = 0;
 929                 imask &= ~SDXC_SDIO_INTERRUPT;
 930         }
 931         mmc_writel(host, REG_IMASK, imask);
 932         spin_unlock_irqrestore(&host->lock, flags);
 933 }
 934
 935 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
 936 {
 937         struct sunxi_mmc_host *host = mmc_priv(mmc);
 938         mmc_writel(host, REG_HWRST, 0);
 939         udelay(10);
 940         mmc_writel(host, REG_HWRST, 1);
 941         udelay(300);
 942 }
 943
 944 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 945 {
 946         struct sunxi_mmc_host *host = mmc_priv(mmc);
 947         struct mmc_command *cmd = mrq->cmd;
 948         struct mmc_data *data = mrq->data;
 949         unsigned long iflags;
 950         u32 imask = SDXC_INTERRUPT_ERROR_BIT;
 951         u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
 952         bool wait_dma = host->wait_dma;
 953         int ret;
 954
 955         /* Check for set_ios errors (should never happen) */
 956         if (host->ferror) {
 957                 mrq->cmd->error = host->ferror;
 958                 mmc_request_done(mmc, mrq);
 959                 return;
 960         }
 961
 962         if (data) {
 963                 ret = sunxi_mmc_map_dma(host, data);
 964                 if (ret < 0) {
 965                         dev_err(mmc_dev(mmc), "map DMA failed\n");
 966                         cmd->error = ret;
 967                         data->error = ret;
 968                         mmc_request_done(mmc, mrq);
 969                         return;
 970                 }
 971         }
 972
 973         if (cmd->opcode == MMC_GO_IDLE_STATE) {
 974                 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
 975                 imask |= SDXC_COMMAND_DONE;
 976         }
 977
 978         if (cmd->flags & MMC_RSP_PRESENT) {
 979                 cmd_val |= SDXC_RESP_EXPIRE;
 980                 if (cmd->flags & MMC_RSP_136)
 981                         cmd_val |= SDXC_LONG_RESPONSE;
 982                 if (cmd->flags & MMC_RSP_CRC)
 983                         cmd_val |= SDXC_CHECK_RESPONSE_CRC;
 984
 985                 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
 986                         cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
 987
 988                         if (cmd->data->stop) {
 989                                 imask |= SDXC_AUTO_COMMAND_DONE;
 990                                 cmd_val |= SDXC_SEND_AUTO_STOP;
 991                         } else {
 992                                 imask |= SDXC_DATA_OVER;
 993                         }
 994
 995                         if (cmd->data->flags & MMC_DATA_WRITE)
 996                                 cmd_val |= SDXC_WRITE;
 997                         else
 998                                 wait_dma = true;
 999                 } else {
1000                         imask |= SDXC_COMMAND_DONE;
1001                 }
1002         } else {
1003                 imask |= SDXC_COMMAND_DONE;
1004         }
1005
1006         dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1007                 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1008                 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1009
1010         spin_lock_irqsave(&host->lock, iflags);
1011
1012         if (host->mrq || host->manual_stop_mrq) {
1013                 spin_unlock_irqrestore(&host->lock, iflags);
1014
1015                 if (data)
1016                         dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1017                                      mmc_get_dma_dir(data));
1018
1019                 dev_err(mmc_dev(mmc), "request already pending\n");
1020                 mrq->cmd->error = -EBUSY;
1021                 mmc_request_done(mmc, mrq);
1022                 return;
1023         }
1024
1025         if (data) {
1026                 mmc_writel(host, REG_BLKSZ, data->blksz);
1027                 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1028                 sunxi_mmc_start_dma(host, data);
1029         }
1030
1031         host->mrq = mrq;
1032         host->wait_dma = wait_dma;
1033         mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1034         mmc_writel(host, REG_CARG, cmd->arg);
1035         mmc_writel(host, REG_CMDR, cmd_val);
1036
1037         spin_unlock_irqrestore(&host->lock, iflags);
1038 }
1039
1040 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1041 {
1042         struct sunxi_mmc_host *host = mmc_priv(mmc);
1043
1044         return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1045 }
1046
1047 static struct mmc_host_ops sunxi_mmc_ops = {
1048         .request         = sunxi_mmc_request,
1049         .set_ios         = sunxi_mmc_set_ios,
1050         .get_ro          = mmc_gpio_get_ro,
1051         .get_cd          = mmc_gpio_get_cd,
1052         .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1053         .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1054         .hw_reset        = sunxi_mmc_hw_reset,
1055         .card_busy       = sunxi_mmc_card_busy,
1056 };
1057
1058 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1059         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
1060         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
1061         [SDXC_CLK_50M]          = { .output =  90, .sample = 120 },
1062         [SDXC_CLK_50M_DDR]      = { .output =  60, .sample = 120 },
1063         /* Value from A83T "new timing mode". Works but might not be right. */
1064         [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 180 },
1065 };
1066
1067 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1068         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
1069         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
1070         [SDXC_CLK_50M]          = { .output = 150, .sample = 120 },
1071         [SDXC_CLK_50M_DDR]      = { .output =  54, .sample =  36 },
1072         [SDXC_CLK_50M_DDR_8BIT] = { .output =  72, .sample =  72 },
1073 };
1074
1075 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1076         .idma_des_size_bits = 13,
1077         .clk_delays = NULL,
1078         .can_calibrate = false,
1079 };
1080
1081 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1082         .idma_des_size_bits = 16,
1083         .clk_delays = NULL,
1084         .can_calibrate = false,
1085 };
1086
1087 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1088         .idma_des_size_bits = 16,
1089         .clk_delays = sunxi_mmc_clk_delays,
1090         .can_calibrate = false,
1091 };
1092
1093 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1094         .idma_des_size_bits = 16,
1095         .clk_delays = sun9i_mmc_clk_delays,
1096         .can_calibrate = false,
1097 };
1098
1099 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1100         .idma_des_size_bits = 16,
1101         .clk_delays = NULL,
1102         .can_calibrate = true,
1103         .mask_data0 = true,
1104         .needs_new_timings = true,
1105 };
1106
1107 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1108         .idma_des_size_bits = 13,
1109         .clk_delays = NULL,
1110         .can_calibrate = true,
1111 };
1112
1113 static const struct of_device_id sunxi_mmc_of_match[] = {
1114         { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1115         { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1116         { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1117         { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1118         { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1119         { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1120         { /* sentinel */ }
1121 };
1122 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1123
1124 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1125                                       struct platform_device *pdev)
1126 {
1127         int ret;
1128
1129         host->cfg = of_device_get_match_data(&pdev->dev);
1130         if (!host->cfg)
1131                 return -EINVAL;
1132
1133         ret = mmc_regulator_get_supply(host->mmc);
1134         if (ret) {
1135                 if (ret != -EPROBE_DEFER)
1136                         dev_err(&pdev->dev, "Could not get vmmc supply\n");
1137                 return ret;
1138         }
1139
1140         host->reg_base = devm_ioremap_resource(&pdev->dev,
1141                               platform_get_resource(pdev, IORESOURCE_MEM, 0));
1142         if (IS_ERR(host->reg_base))
1143                 return PTR_ERR(host->reg_base);
1144
1145         host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1146         if (IS_ERR(host->clk_ahb)) {
1147                 dev_err(&pdev->dev, "Could not get ahb clock\n");
1148                 return PTR_ERR(host->clk_ahb);
1149         }
1150
1151         host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1152         if (IS_ERR(host->clk_mmc)) {
1153                 dev_err(&pdev->dev, "Could not get mmc clock\n");
1154                 return PTR_ERR(host->clk_mmc);
1155         }
1156
1157         if (host->cfg->clk_delays) {
1158                 host->clk_output = devm_clk_get(&pdev->dev, "output");
1159                 if (IS_ERR(host->clk_output)) {
1160                         dev_err(&pdev->dev, "Could not get output clock\n");
1161                         return PTR_ERR(host->clk_output);
1162                 }
1163
1164                 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1165                 if (IS_ERR(host->clk_sample)) {
1166                         dev_err(&pdev->dev, "Could not get sample clock\n");
1167                         return PTR_ERR(host->clk_sample);
1168                 }
1169         }
1170
1171         host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1172         if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1173                 return PTR_ERR(host->reset);
1174
1175         ret = clk_prepare_enable(host->clk_ahb);
1176         if (ret) {
1177                 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1178                 return ret;
1179         }
1180
1181         ret = clk_prepare_enable(host->clk_mmc);
1182         if (ret) {
1183                 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1184                 goto error_disable_clk_ahb;
1185         }
1186
1187         ret = clk_prepare_enable(host->clk_output);
1188         if (ret) {
1189                 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1190                 goto error_disable_clk_mmc;
1191         }
1192
1193         ret = clk_prepare_enable(host->clk_sample);
1194         if (ret) {
1195                 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1196                 goto error_disable_clk_output;
1197         }
1198
1199         if (!IS_ERR(host->reset)) {
1200                 ret = reset_control_deassert(host->reset);
1201                 if (ret) {
1202                         dev_err(&pdev->dev, "reset err %d\n", ret);
1203                         goto error_disable_clk_sample;
1204                 }
1205         }
1206
1207         /*
1208          * Sometimes the controller asserts the irq on boot for some reason,
1209          * make sure the controller is in a sane state before enabling irqs.
1210          */
1211         ret = sunxi_mmc_reset_host(host);
1212         if (ret)
1213                 goto error_assert_reset;
1214
1215         host->irq = platform_get_irq(pdev, 0);
1216         return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1217                         sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1218
1219 error_assert_reset:
1220         if (!IS_ERR(host->reset))
1221                 reset_control_assert(host->reset);
1222 error_disable_clk_sample:
1223         clk_disable_unprepare(host->clk_sample);
1224 error_disable_clk_output:
1225         clk_disable_unprepare(host->clk_output);
1226 error_disable_clk_mmc:
1227         clk_disable_unprepare(host->clk_mmc);
1228 error_disable_clk_ahb:
1229         clk_disable_unprepare(host->clk_ahb);
1230         return ret;
1231 }
1232
1233 static int sunxi_mmc_probe(struct platform_device *pdev)
1234 {
1235         struct sunxi_mmc_host *host;
1236         struct mmc_host *mmc;
1237         int ret;
1238
1239         mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1240         if (!mmc) {
1241                 dev_err(&pdev->dev, "mmc alloc host failed\n");
1242                 return -ENOMEM;
1243         }
1244
1245         host = mmc_priv(mmc);
1246         host->mmc = mmc;
1247         spin_lock_init(&host->lock);
1248
1249         ret = sunxi_mmc_resource_request(host, pdev);
1250         if (ret)
1251                 goto error_free_host;
1252
1253         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1254                                           &host->sg_dma, GFP_KERNEL);
1255         if (!host->sg_cpu) {
1256                 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1257                 ret = -ENOMEM;
1258                 goto error_free_host;
1259         }
1260
1261         mmc->ops                = &sunxi_mmc_ops;
1262         mmc->max_blk_count      = 8192;
1263         mmc->max_blk_size       = 4096;
1264         mmc->max_segs           = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1265         mmc->max_seg_size       = (1 << host->cfg->idma_des_size_bits);
1266         mmc->max_req_size       = mmc->max_seg_size * mmc->max_segs;
1267         /* 400kHz ~ 52MHz */
1268         mmc->f_min              =   400000;
1269         mmc->f_max              = 52000000;
1270         mmc->caps              |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1271                                   MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1272
1273         if (host->cfg->clk_delays)
1274                 mmc->caps      |= MMC_CAP_1_8V_DDR;
1275
1276         ret = mmc_of_parse(mmc);
1277         if (ret)
1278                 goto error_free_dma;
1279
1280         ret = mmc_add_host(mmc);
1281         if (ret)
1282                 goto error_free_dma;
1283
1284         dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1285         platform_set_drvdata(pdev, mmc);
1286         return 0;
1287
1288 error_free_dma:
1289         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1290 error_free_host:
1291         mmc_free_host(mmc);
1292         return ret;
1293 }
1294
1295 static int sunxi_mmc_remove(struct platform_device *pdev)
1296 {
1297         struct mmc_host *mmc = platform_get_drvdata(pdev);
1298         struct sunxi_mmc_host *host = mmc_priv(mmc);
1299
1300         mmc_remove_host(mmc);
1301         disable_irq(host->irq);
1302         sunxi_mmc_reset_host(host);
1303
1304         if (!IS_ERR(host->reset))
1305                 reset_control_assert(host->reset);
1306
1307         clk_disable_unprepare(host->clk_sample);
1308         clk_disable_unprepare(host->clk_output);
1309         clk_disable_unprepare(host->clk_mmc);
1310         clk_disable_unprepare(host->clk_ahb);
1311
1312         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1313         mmc_free_host(mmc);
1314
1315         return 0;
1316 }
1317
1318 static struct platform_driver sunxi_mmc_driver = {
1319         .driver = {
1320                 .name   = "sunxi-mmc",
1321                 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1322         },
1323         .probe          = sunxi_mmc_probe,
1324         .remove         = sunxi_mmc_remove,
1325 };
1326 module_platform_driver(sunxi_mmc_driver);
1327
1328 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1329 MODULE_LICENSE("GPL v2");
1330 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1331 MODULE_ALIAS("platform:sunxi-mmc");