2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/list.h>
19 #include "mmc_private.h"
21 static struct list_head mmc_devices;
22 static int cur_dev_num = -1;
23 static int mmc_dev_count;
25 __weak int board_mmc_getwp(struct mmc *mmc)
30 int mmc_getwp(struct mmc *mmc)
34 wp = board_mmc_getwp(mmc);
37 if (mmc->cfg->ops->getwp)
38 wp = mmc->cfg->ops->getwp(mmc);
46 __weak int board_mmc_getcd(struct mmc *mmc)
51 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
55 #ifdef CONFIG_MMC_TRACE
59 printf("CMD_SEND:%d\n", cmd->cmdidx);
60 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
61 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
62 switch (cmd->resp_type) {
64 printf("\t\tMMC_RSP_NONE\n");
67 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
71 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
75 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
77 printf("\t\t \t\t 0x%08X \n",
79 printf("\t\t \t\t 0x%08X \n",
81 printf("\t\t \t\t 0x%08X \n",
84 printf("\t\t\t\t\tDUMPING DATA\n");
85 for (i = 0; i < 4; i++) {
87 printf("\t\t\t\t\t%03d - ", i*4);
88 ptr = (u8 *)&cmd->response[i];
90 for (j = 0; j < 4; j++)
91 printf("%02X ", *ptr--);
96 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
100 printf("\t\tERROR MMC rsp not supported\n");
104 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
109 int mmc_send_status(struct mmc *mmc, int timeout)
112 int err, retries = 5;
113 #ifdef CONFIG_MMC_TRACE
117 cmd.cmdidx = MMC_CMD_SEND_STATUS;
118 cmd.resp_type = MMC_RSP_R1;
119 if (!mmc_host_is_spi(mmc))
120 cmd.cmdarg = mmc->rca << 16;
123 err = mmc_send_cmd(mmc, &cmd, NULL);
125 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
126 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
129 else if (cmd.response[0] & MMC_STATUS_MASK) {
130 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
131 printf("Status Error: 0x%08X\n",
136 } else if (--retries < 0)
145 #ifdef CONFIG_MMC_TRACE
146 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
147 printf("CURR STATE:%d\n", status);
150 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
151 printf("Timeout waiting card ready\n");
155 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
161 int mmc_set_blocklen(struct mmc *mmc, int len)
168 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
169 cmd.resp_type = MMC_RSP_R1;
172 return mmc_send_cmd(mmc, &cmd, NULL);
175 struct mmc *find_mmc_device(int dev_num)
178 struct list_head *entry;
180 list_for_each(entry, &mmc_devices) {
181 m = list_entry(entry, struct mmc, link);
183 if (m->block_dev.dev == dev_num)
187 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
188 printf("MMC Device %d not found\n", dev_num);
194 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
198 struct mmc_data data;
201 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
203 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
205 if (mmc->high_capacity)
208 cmd.cmdarg = start * mmc->read_bl_len;
210 cmd.resp_type = MMC_RSP_R1;
213 data.blocks = blkcnt;
214 data.blocksize = mmc->read_bl_len;
215 data.flags = MMC_DATA_READ;
217 if (mmc_send_cmd(mmc, &cmd, &data))
221 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
223 cmd.resp_type = MMC_RSP_R1b;
224 if (mmc_send_cmd(mmc, &cmd, NULL)) {
225 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
226 printf("mmc fail to send stop cmd\n");
235 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
237 lbaint_t cur, blocks_todo = blkcnt;
242 struct mmc *mmc = find_mmc_device(dev_num);
246 if ((start + blkcnt) > mmc->block_dev.lba) {
247 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
248 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
249 start + blkcnt, mmc->block_dev.lba);
254 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
255 debug("%s: Failed to set blocklen\n", __func__);
260 cur = (blocks_todo > mmc->cfg->b_max) ?
261 mmc->cfg->b_max : blocks_todo;
262 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
263 debug("%s: Failed to read blocks\n", __func__);
268 dst += cur * mmc->read_bl_len;
269 } while (blocks_todo > 0);
274 static int mmc_go_idle(struct mmc *mmc)
281 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
283 cmd.resp_type = MMC_RSP_NONE;
285 err = mmc_send_cmd(mmc, &cmd, NULL);
295 static int sd_send_op_cond(struct mmc *mmc)
302 cmd.cmdidx = MMC_CMD_APP_CMD;
303 cmd.resp_type = MMC_RSP_R1;
306 err = mmc_send_cmd(mmc, &cmd, NULL);
311 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
312 cmd.resp_type = MMC_RSP_R3;
315 * Most cards do not answer if some reserved bits
316 * in the ocr are set. However, Some controller
317 * can set bit 7 (reserved for low voltages), but
318 * how to manage low voltages SD card is not yet
321 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
322 (mmc->cfg->voltages & 0xff8000);
324 if (mmc->version == SD_VERSION_2)
325 cmd.cmdarg |= OCR_HCS;
327 err = mmc_send_cmd(mmc, &cmd, NULL);
332 if (cmd.response[0] & OCR_BUSY)
341 if (mmc->version != SD_VERSION_2)
342 mmc->version = SD_VERSION_1_0;
344 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
345 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
346 cmd.resp_type = MMC_RSP_R3;
349 err = mmc_send_cmd(mmc, &cmd, NULL);
355 mmc->ocr = cmd.response[0];
357 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
363 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
368 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
369 cmd.resp_type = MMC_RSP_R3;
371 if (use_arg && !mmc_host_is_spi(mmc))
372 cmd.cmdarg = OCR_HCS |
373 (mmc->cfg->voltages &
374 (mmc->ocr & OCR_VOLTAGE_MASK)) |
375 (mmc->ocr & OCR_ACCESS_MODE);
377 err = mmc_send_cmd(mmc, &cmd, NULL);
380 mmc->ocr = cmd.response[0];
384 static int mmc_send_op_cond(struct mmc *mmc)
388 /* Some cards seem to need this */
391 /* Asking to the card its capabilities */
392 for (i = 0; i < 2; i++) {
393 err = mmc_send_op_cond_iter(mmc, i != 0);
397 /* exit if not busy (flag seems to be inverted) */
398 if (mmc->ocr & OCR_BUSY)
401 mmc->op_cond_pending = 1;
405 static int mmc_complete_op_cond(struct mmc *mmc)
412 mmc->op_cond_pending = 0;
413 if (!(mmc->ocr & OCR_BUSY)) {
414 start = get_timer_masked();
416 err = mmc_send_op_cond_iter(mmc, 1);
419 if (mmc->ocr & OCR_BUSY)
421 if (get_timer(start) > timeout)
427 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
428 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
429 cmd.resp_type = MMC_RSP_R3;
432 err = mmc_send_cmd(mmc, &cmd, NULL);
437 mmc->ocr = cmd.response[0];
440 mmc->version = MMC_VERSION_UNKNOWN;
442 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
449 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
452 struct mmc_data data;
455 /* Get the Card Status Register */
456 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
457 cmd.resp_type = MMC_RSP_R1;
460 data.dest = (char *)ext_csd;
462 data.blocksize = MMC_MAX_BLOCK_LEN;
463 data.flags = MMC_DATA_READ;
465 err = mmc_send_cmd(mmc, &cmd, &data);
471 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
477 cmd.cmdidx = MMC_CMD_SWITCH;
478 cmd.resp_type = MMC_RSP_R1b;
479 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
483 ret = mmc_send_cmd(mmc, &cmd, NULL);
485 /* Waiting for the ready status */
487 ret = mmc_send_status(mmc, timeout);
493 static int mmc_change_freq(struct mmc *mmc)
495 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
501 if (mmc_host_is_spi(mmc))
504 /* Only version 4 supports high-speed */
505 if (mmc->version < MMC_VERSION_4)
508 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
510 err = mmc_send_ext_csd(mmc, ext_csd);
515 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
517 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
520 return err == SWITCH_ERR ? 0 : err;
522 /* Now check to see that it worked */
523 err = mmc_send_ext_csd(mmc, ext_csd);
528 /* No high-speed support */
529 if (!ext_csd[EXT_CSD_HS_TIMING])
532 /* High Speed is set, there are two types: 52MHz and 26MHz */
533 if (cardtype & EXT_CSD_CARD_TYPE_52) {
534 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
535 mmc->card_caps |= MMC_MODE_DDR_52MHz;
536 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
538 mmc->card_caps |= MMC_MODE_HS;
544 static int mmc_set_capacity(struct mmc *mmc, int part_num)
548 mmc->capacity = mmc->capacity_user;
552 mmc->capacity = mmc->capacity_boot;
555 mmc->capacity = mmc->capacity_rpmb;
561 mmc->capacity = mmc->capacity_gp[part_num - 4];
567 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
572 int mmc_select_hwpart(int dev_num, int hwpart)
574 struct mmc *mmc = find_mmc_device(dev_num);
580 if (mmc->part_num == hwpart)
583 if (mmc->part_config == MMCPART_NOAVAILABLE) {
584 printf("Card doesn't support part_switch\n");
588 ret = mmc_switch_part(dev_num, hwpart);
592 mmc->part_num = hwpart;
598 int mmc_switch_part(int dev_num, unsigned int part_num)
600 struct mmc *mmc = find_mmc_device(dev_num);
606 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
607 (mmc->part_config & ~PART_ACCESS_MASK)
608 | (part_num & PART_ACCESS_MASK));
611 * Set the capacity if the switch succeeded or was intended
612 * to return to representing the raw device.
614 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
615 ret = mmc_set_capacity(mmc, part_num);
620 int mmc_hwpart_config(struct mmc *mmc,
621 const struct mmc_hwpart_conf *conf,
622 enum mmc_hwpart_conf_mode mode)
628 u32 max_enh_size_mult;
629 u32 tot_enh_size_mult = 0;
632 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
634 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
637 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
638 printf("eMMC >= 4.4 required for enhanced user data area\n");
642 if (!(mmc->part_support & PART_SUPPORT)) {
643 printf("Card does not support partitioning\n");
647 if (!mmc->hc_wp_grp_size) {
648 printf("Card does not define HC WP group size\n");
652 /* check partition alignment and total enhanced size */
653 if (conf->user.enh_size) {
654 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
655 conf->user.enh_start % mmc->hc_wp_grp_size) {
656 printf("User data enhanced area not HC WP group "
660 part_attrs |= EXT_CSD_ENH_USR;
661 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
662 if (mmc->high_capacity) {
663 enh_start_addr = conf->user.enh_start;
665 enh_start_addr = (conf->user.enh_start << 9);
671 tot_enh_size_mult += enh_size_mult;
673 for (pidx = 0; pidx < 4; pidx++) {
674 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
675 printf("GP%i partition not HC WP group size "
676 "aligned\n", pidx+1);
679 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
680 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
681 part_attrs |= EXT_CSD_ENH_GP(pidx);
682 tot_enh_size_mult += gp_size_mult[pidx];
686 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
687 printf("Card does not support enhanced attribute\n");
691 err = mmc_send_ext_csd(mmc, ext_csd);
696 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
697 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
698 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
699 if (tot_enh_size_mult > max_enh_size_mult) {
700 printf("Total enhanced size exceeds maximum (%u > %u)\n",
701 tot_enh_size_mult, max_enh_size_mult);
705 /* The default value of EXT_CSD_WR_REL_SET is device
706 * dependent, the values can only be changed if the
707 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
708 * changed only once and before partitioning is completed. */
709 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
710 if (conf->user.wr_rel_change) {
711 if (conf->user.wr_rel_set)
712 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
714 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
716 for (pidx = 0; pidx < 4; pidx++) {
717 if (conf->gp_part[pidx].wr_rel_change) {
718 if (conf->gp_part[pidx].wr_rel_set)
719 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
721 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
725 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
726 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
727 puts("Card does not support host controlled partition write "
728 "reliability settings\n");
732 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
733 EXT_CSD_PARTITION_SETTING_COMPLETED) {
734 printf("Card already partitioned\n");
738 if (mode == MMC_HWPART_CONF_CHECK)
741 /* Partitioning requires high-capacity size definitions */
742 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
743 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
744 EXT_CSD_ERASE_GROUP_DEF, 1);
749 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
751 /* update erase group size to be high-capacity */
752 mmc->erase_grp_size =
753 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
757 /* all OK, write the configuration */
758 for (i = 0; i < 4; i++) {
759 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
760 EXT_CSD_ENH_START_ADDR+i,
761 (enh_start_addr >> (i*8)) & 0xFF);
765 for (i = 0; i < 3; i++) {
766 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
767 EXT_CSD_ENH_SIZE_MULT+i,
768 (enh_size_mult >> (i*8)) & 0xFF);
772 for (pidx = 0; pidx < 4; pidx++) {
773 for (i = 0; i < 3; i++) {
774 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
775 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
776 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
781 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
782 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
786 if (mode == MMC_HWPART_CONF_SET)
789 /* The WR_REL_SET is a write-once register but shall be
790 * written before setting PART_SETTING_COMPLETED. As it is
791 * write-once we can only write it when completing the
793 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
794 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
795 EXT_CSD_WR_REL_SET, wr_rel_set);
800 /* Setting PART_SETTING_COMPLETED confirms the partition
801 * configuration but it only becomes effective after power
802 * cycle, so we do not adjust the partition related settings
803 * in the mmc struct. */
805 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
806 EXT_CSD_PARTITION_SETTING,
807 EXT_CSD_PARTITION_SETTING_COMPLETED);
814 int mmc_getcd(struct mmc *mmc)
818 cd = board_mmc_getcd(mmc);
821 if (mmc->cfg->ops->getcd)
822 cd = mmc->cfg->ops->getcd(mmc);
830 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
833 struct mmc_data data;
835 /* Switch the frequency */
836 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
837 cmd.resp_type = MMC_RSP_R1;
838 cmd.cmdarg = (mode << 31) | 0xffffff;
839 cmd.cmdarg &= ~(0xf << (group * 4));
840 cmd.cmdarg |= value << (group * 4);
842 data.dest = (char *)resp;
845 data.flags = MMC_DATA_READ;
847 return mmc_send_cmd(mmc, &cmd, &data);
851 static int sd_change_freq(struct mmc *mmc)
855 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
856 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
857 struct mmc_data data;
862 if (mmc_host_is_spi(mmc))
865 /* Read the SCR to find out if this card supports higher speeds */
866 cmd.cmdidx = MMC_CMD_APP_CMD;
867 cmd.resp_type = MMC_RSP_R1;
868 cmd.cmdarg = mmc->rca << 16;
870 err = mmc_send_cmd(mmc, &cmd, NULL);
875 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
876 cmd.resp_type = MMC_RSP_R1;
882 data.dest = (char *)scr;
885 data.flags = MMC_DATA_READ;
887 err = mmc_send_cmd(mmc, &cmd, &data);
896 mmc->scr[0] = __be32_to_cpu(scr[0]);
897 mmc->scr[1] = __be32_to_cpu(scr[1]);
899 switch ((mmc->scr[0] >> 24) & 0xf) {
901 mmc->version = SD_VERSION_1_0;
904 mmc->version = SD_VERSION_1_10;
907 mmc->version = SD_VERSION_2;
908 if ((mmc->scr[0] >> 15) & 0x1)
909 mmc->version = SD_VERSION_3;
912 mmc->version = SD_VERSION_1_0;
916 if (mmc->scr[0] & SD_DATA_4BIT)
917 mmc->card_caps |= MMC_MODE_4BIT;
919 /* Version 1.0 doesn't support switching */
920 if (mmc->version == SD_VERSION_1_0)
925 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
926 (u8 *)switch_status);
931 /* The high-speed function is busy. Try again */
932 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
936 /* If high-speed isn't supported, we return */
937 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
941 * If the host doesn't support SD_HIGHSPEED, do not switch card to
942 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
943 * This can avoid furthur problem when the card runs in different
944 * mode between the host.
946 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
947 (mmc->cfg->host_caps & MMC_MODE_HS)))
950 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
955 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
956 mmc->card_caps |= MMC_MODE_HS;
961 /* frequency bases */
962 /* divided by 10 to be nice to platforms without floating point */
963 static const int fbase[] = {
970 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
971 * to platforms without floating point.
973 static const int multipliers[] = {
992 static void mmc_set_ios(struct mmc *mmc)
994 if (mmc->cfg->ops->set_ios)
995 mmc->cfg->ops->set_ios(mmc);
998 void mmc_set_clock(struct mmc *mmc, uint clock)
1000 if (clock > mmc->cfg->f_max)
1001 clock = mmc->cfg->f_max;
1003 if (clock < mmc->cfg->f_min)
1004 clock = mmc->cfg->f_min;
1011 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1013 mmc->bus_width = width;
1018 static int mmc_startup(struct mmc *mmc)
1022 u64 cmult, csize, capacity;
1024 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1025 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1027 bool has_parts = false;
1028 bool part_completed;
1030 #ifdef CONFIG_MMC_SPI_CRC_ON
1031 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1032 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1033 cmd.resp_type = MMC_RSP_R1;
1035 err = mmc_send_cmd(mmc, &cmd, NULL);
1042 /* Put the Card in Identify Mode */
1043 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1044 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1045 cmd.resp_type = MMC_RSP_R2;
1048 err = mmc_send_cmd(mmc, &cmd, NULL);
1053 memcpy(mmc->cid, cmd.response, 16);
1056 * For MMC cards, set the Relative Address.
1057 * For SD cards, get the Relatvie Address.
1058 * This also puts the cards into Standby State
1060 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1061 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1062 cmd.cmdarg = mmc->rca << 16;
1063 cmd.resp_type = MMC_RSP_R6;
1065 err = mmc_send_cmd(mmc, &cmd, NULL);
1071 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1074 /* Get the Card-Specific Data */
1075 cmd.cmdidx = MMC_CMD_SEND_CSD;
1076 cmd.resp_type = MMC_RSP_R2;
1077 cmd.cmdarg = mmc->rca << 16;
1079 err = mmc_send_cmd(mmc, &cmd, NULL);
1081 /* Waiting for the ready status */
1082 mmc_send_status(mmc, timeout);
1087 mmc->csd[0] = cmd.response[0];
1088 mmc->csd[1] = cmd.response[1];
1089 mmc->csd[2] = cmd.response[2];
1090 mmc->csd[3] = cmd.response[3];
1092 if (mmc->version == MMC_VERSION_UNKNOWN) {
1093 int version = (cmd.response[0] >> 26) & 0xf;
1097 mmc->version = MMC_VERSION_1_2;
1100 mmc->version = MMC_VERSION_1_4;
1103 mmc->version = MMC_VERSION_2_2;
1106 mmc->version = MMC_VERSION_3;
1109 mmc->version = MMC_VERSION_4;
1112 mmc->version = MMC_VERSION_1_2;
1117 /* divide frequency by 10, since the mults are 10x bigger */
1118 freq = fbase[(cmd.response[0] & 0x7)];
1119 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1121 mmc->tran_speed = freq * mult;
1123 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1124 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1127 mmc->write_bl_len = mmc->read_bl_len;
1129 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1131 if (mmc->high_capacity) {
1132 csize = (mmc->csd[1] & 0x3f) << 16
1133 | (mmc->csd[2] & 0xffff0000) >> 16;
1136 csize = (mmc->csd[1] & 0x3ff) << 2
1137 | (mmc->csd[2] & 0xc0000000) >> 30;
1138 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1141 mmc->capacity_user = (csize + 1) << (cmult + 2);
1142 mmc->capacity_user *= mmc->read_bl_len;
1143 mmc->capacity_boot = 0;
1144 mmc->capacity_rpmb = 0;
1145 for (i = 0; i < 4; i++)
1146 mmc->capacity_gp[i] = 0;
1148 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1149 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1151 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1152 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1154 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1155 cmd.cmdidx = MMC_CMD_SET_DSR;
1156 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1157 cmd.resp_type = MMC_RSP_NONE;
1158 if (mmc_send_cmd(mmc, &cmd, NULL))
1159 printf("MMC: SET_DSR failed\n");
1162 /* Select the card, and put it into Transfer Mode */
1163 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1164 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1165 cmd.resp_type = MMC_RSP_R1;
1166 cmd.cmdarg = mmc->rca << 16;
1167 err = mmc_send_cmd(mmc, &cmd, NULL);
1174 * For SD, its erase group is always one sector
1176 mmc->erase_grp_size = 1;
1177 mmc->part_config = MMCPART_NOAVAILABLE;
1178 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1179 /* check ext_csd version and capacity */
1180 err = mmc_send_ext_csd(mmc, ext_csd);
1183 if (ext_csd[EXT_CSD_REV] >= 2) {
1185 * According to the JEDEC Standard, the value of
1186 * ext_csd's capacity is valid if the value is more
1189 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1190 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1191 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1192 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1193 capacity *= MMC_MAX_BLOCK_LEN;
1194 if ((capacity >> 20) > 2 * 1024)
1195 mmc->capacity_user = capacity;
1198 switch (ext_csd[EXT_CSD_REV]) {
1200 mmc->version = MMC_VERSION_4_1;
1203 mmc->version = MMC_VERSION_4_2;
1206 mmc->version = MMC_VERSION_4_3;
1209 mmc->version = MMC_VERSION_4_41;
1212 mmc->version = MMC_VERSION_4_5;
1215 mmc->version = MMC_VERSION_5_0;
1219 /* The partition data may be non-zero but it is only
1220 * effective if PARTITION_SETTING_COMPLETED is set in
1221 * EXT_CSD, so ignore any data if this bit is not set,
1222 * except for enabling the high-capacity group size
1223 * definition (see below). */
1224 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1225 EXT_CSD_PARTITION_SETTING_COMPLETED);
1227 /* store the partition info of emmc */
1228 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1229 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1230 ext_csd[EXT_CSD_BOOT_MULT])
1231 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1232 if (part_completed &&
1233 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1234 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1236 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1238 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1240 for (i = 0; i < 4; i++) {
1241 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1242 uint mult = (ext_csd[idx + 2] << 16) +
1243 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1246 if (!part_completed)
1248 mmc->capacity_gp[i] = mult;
1249 mmc->capacity_gp[i] *=
1250 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1251 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1252 mmc->capacity_gp[i] <<= 19;
1255 if (part_completed) {
1256 mmc->enh_user_size =
1257 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1258 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1259 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1260 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1261 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1262 mmc->enh_user_size <<= 19;
1263 mmc->enh_user_start =
1264 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1265 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1266 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1267 ext_csd[EXT_CSD_ENH_START_ADDR];
1268 if (mmc->high_capacity)
1269 mmc->enh_user_start <<= 9;
1273 * Host needs to enable ERASE_GRP_DEF bit if device is
1274 * partitioned. This bit will be lost every time after a reset
1275 * or power off. This will affect erase size.
1279 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1280 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1283 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1284 EXT_CSD_ERASE_GROUP_DEF, 1);
1289 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1292 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1293 /* Read out group size from ext_csd */
1294 mmc->erase_grp_size =
1295 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1297 * if high capacity and partition setting completed
1298 * SEC_COUNT is valid even if it is smaller than 2 GiB
1299 * JEDEC Standard JESD84-B45, 6.2.4
1301 if (mmc->high_capacity && part_completed) {
1302 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1303 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1304 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1305 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1306 capacity *= MMC_MAX_BLOCK_LEN;
1307 mmc->capacity_user = capacity;
1310 /* Calculate the group size from the csd value. */
1311 int erase_gsz, erase_gmul;
1312 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1313 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1314 mmc->erase_grp_size = (erase_gsz + 1)
1318 mmc->hc_wp_grp_size = 1024
1319 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1320 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1322 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1325 err = mmc_set_capacity(mmc, mmc->part_num);
1330 err = sd_change_freq(mmc);
1332 err = mmc_change_freq(mmc);
1337 /* Restrict card's capabilities by what the host can do */
1338 mmc->card_caps &= mmc->cfg->host_caps;
1341 if (mmc->card_caps & MMC_MODE_4BIT) {
1342 cmd.cmdidx = MMC_CMD_APP_CMD;
1343 cmd.resp_type = MMC_RSP_R1;
1344 cmd.cmdarg = mmc->rca << 16;
1346 err = mmc_send_cmd(mmc, &cmd, NULL);
1350 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1351 cmd.resp_type = MMC_RSP_R1;
1353 err = mmc_send_cmd(mmc, &cmd, NULL);
1357 mmc_set_bus_width(mmc, 4);
1360 if (mmc->card_caps & MMC_MODE_HS)
1361 mmc->tran_speed = 50000000;
1363 mmc->tran_speed = 25000000;
1364 } else if (mmc->version >= MMC_VERSION_4) {
1365 /* Only version 4 of MMC supports wider bus widths */
1368 /* An array of possible bus widths in order of preference */
1369 static unsigned ext_csd_bits[] = {
1370 EXT_CSD_DDR_BUS_WIDTH_8,
1371 EXT_CSD_DDR_BUS_WIDTH_4,
1372 EXT_CSD_BUS_WIDTH_8,
1373 EXT_CSD_BUS_WIDTH_4,
1374 EXT_CSD_BUS_WIDTH_1,
1377 /* An array to map CSD bus widths to host cap bits */
1378 static unsigned ext_to_hostcaps[] = {
1379 [EXT_CSD_DDR_BUS_WIDTH_4] =
1380 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1381 [EXT_CSD_DDR_BUS_WIDTH_8] =
1382 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1383 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1384 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1387 /* An array to map chosen bus width to an integer */
1388 static unsigned widths[] = {
1392 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1393 unsigned int extw = ext_csd_bits[idx];
1394 unsigned int caps = ext_to_hostcaps[extw];
1397 * If the bus width is still not changed,
1398 * don't try to set the default again.
1399 * Otherwise, recover from switch attempts
1400 * by switching to 1-bit bus width.
1402 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1403 mmc->bus_width == 1) {
1409 * Check to make sure the card and controller support
1410 * these capabilities
1412 if ((mmc->card_caps & caps) != caps)
1415 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1416 EXT_CSD_BUS_WIDTH, extw);
1421 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1422 mmc_set_bus_width(mmc, widths[idx]);
1424 err = mmc_send_ext_csd(mmc, test_csd);
1429 /* Only compare read only fields */
1430 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1431 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1432 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1433 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1434 ext_csd[EXT_CSD_REV]
1435 == test_csd[EXT_CSD_REV] &&
1436 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1437 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1438 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1439 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1448 if (mmc->card_caps & MMC_MODE_HS) {
1449 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1450 mmc->tran_speed = 52000000;
1452 mmc->tran_speed = 26000000;
1456 mmc_set_clock(mmc, mmc->tran_speed);
1458 /* Fix the block length for DDR mode */
1459 if (mmc->ddr_mode) {
1460 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1461 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1464 /* fill in device description */
1465 mmc->block_dev.lun = 0;
1466 mmc->block_dev.type = 0;
1467 mmc->block_dev.blksz = mmc->read_bl_len;
1468 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
1469 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
1470 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1471 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1472 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1473 (mmc->cid[3] >> 16) & 0xffff);
1474 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1475 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1476 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1477 (mmc->cid[2] >> 24) & 0xff);
1478 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1479 (mmc->cid[2] >> 16) & 0xf);
1481 mmc->block_dev.vendor[0] = 0;
1482 mmc->block_dev.product[0] = 0;
1483 mmc->block_dev.revision[0] = 0;
1485 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1486 init_part(&mmc->block_dev);
1492 static int mmc_send_if_cond(struct mmc *mmc)
1497 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1498 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1499 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1500 cmd.resp_type = MMC_RSP_R7;
1502 err = mmc_send_cmd(mmc, &cmd, NULL);
1507 if ((cmd.response[0] & 0xff) != 0xaa)
1508 return UNUSABLE_ERR;
1510 mmc->version = SD_VERSION_2;
1515 /* not used any more */
1516 int __deprecated mmc_register(struct mmc *mmc)
1518 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1519 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1524 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
1528 /* quick validation */
1529 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1530 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1533 mmc = calloc(1, sizeof(*mmc));
1540 /* the following chunk was mmc_register() */
1542 /* Setup dsr related values */
1544 mmc->dsr = 0xffffffff;
1545 /* Setup the universal parts of the block interface just once */
1546 mmc->block_dev.if_type = IF_TYPE_MMC;
1547 mmc->block_dev.dev = cur_dev_num++;
1548 mmc->block_dev.removable = 1;
1549 mmc->block_dev.block_read = mmc_bread;
1550 mmc->block_dev.block_write = mmc_bwrite;
1551 mmc->block_dev.block_erase = mmc_berase;
1553 /* setup initial part type */
1554 mmc->block_dev.part_type = mmc->cfg->part_type;
1556 INIT_LIST_HEAD(&mmc->link);
1558 list_add_tail(&mmc->link, &mmc_devices);
1564 void mmc_destroy(struct mmc *mmc)
1566 /* only freeing memory for now */
1570 #ifdef CONFIG_PARTITIONS
1571 block_dev_desc_t *mmc_get_dev(int dev)
1573 struct mmc *mmc = find_mmc_device(dev);
1574 if (!mmc || mmc_init(mmc))
1577 return &mmc->block_dev;
1581 /* board-specific MMC power initializations. */
1582 __weak void board_mmc_power_init(void)
1586 int mmc_start_init(struct mmc *mmc)
1590 /* we pretend there's no card when init is NULL */
1591 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1593 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1594 printf("MMC: no card present\n");
1602 board_mmc_power_init();
1604 /* made sure it's not NULL earlier */
1605 err = mmc->cfg->ops->init(mmc);
1611 mmc_set_bus_width(mmc, 1);
1612 mmc_set_clock(mmc, 1);
1614 /* Reset the Card */
1615 err = mmc_go_idle(mmc);
1620 /* The internal partition reset to user partition(0) at every CMD0*/
1623 /* Test for SD version 2 */
1624 err = mmc_send_if_cond(mmc);
1626 /* Now try to get the SD card's operating condition */
1627 err = sd_send_op_cond(mmc);
1629 /* If the command timed out, we check for an MMC card */
1630 if (err == TIMEOUT) {
1631 err = mmc_send_op_cond(mmc);
1634 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1635 printf("Card did not respond to voltage select!\n");
1637 return UNUSABLE_ERR;
1642 mmc->init_in_progress = 1;
1647 static int mmc_complete_init(struct mmc *mmc)
1651 mmc->init_in_progress = 0;
1652 if (mmc->op_cond_pending)
1653 err = mmc_complete_op_cond(mmc);
1656 err = mmc_startup(mmc);
1664 int mmc_init(struct mmc *mmc)
1667 unsigned long start;
1672 start = get_timer(0);
1674 if (!mmc->init_in_progress)
1675 err = mmc_start_init(mmc);
1678 err = mmc_complete_init(mmc);
1679 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1683 int mmc_set_dsr(struct mmc *mmc, u16 val)
1689 /* CPU-specific MMC initializations */
1690 __weak int cpu_mmc_init(bd_t *bis)
1695 /* board-specific MMC initializations. */
1696 __weak int board_mmc_init(bd_t *bis)
1701 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1703 void print_mmc_devices(char separator)
1706 struct list_head *entry;
1709 list_for_each(entry, &mmc_devices) {
1710 m = list_entry(entry, struct mmc, link);
1713 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1717 printf("%s: %d", m->cfg->name, m->block_dev.dev);
1719 printf(" (%s)", mmc_type);
1721 if (entry->next != &mmc_devices) {
1722 printf("%c", separator);
1723 if (separator != '\n')
1732 void print_mmc_devices(char separator) { }
1735 int get_mmc_num(void)
1740 int get_mmc_dev_count(void)
1742 return mmc_dev_count;
1745 void mmc_set_preinit(struct mmc *mmc, int preinit)
1747 mmc->preinit = preinit;
1750 static void do_preinit(void)
1753 struct list_head *entry;
1755 list_for_each(entry, &mmc_devices) {
1756 m = list_entry(entry, struct mmc, link);
1758 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1759 mmc_set_preinit(m, 1);
1767 int mmc_initialize(bd_t *bis)
1769 static int initialized = 0;
1770 if (initialized) /* Avoid initializing mmc multiple times */
1774 INIT_LIST_HEAD (&mmc_devices);
1777 #ifndef CONFIG_DM_MMC
1778 if (board_mmc_init(bis) < 0)
1782 #ifndef CONFIG_SPL_BUILD
1783 print_mmc_devices(',');
1790 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1792 * This function changes the size of boot partition and the size of rpmb
1793 * partition present on EMMC devices.
1796 * struct *mmc: pointer for the mmc device strcuture
1797 * bootsize: size of boot partition
1798 * rpmbsize: size of rpmb partition
1800 * Returns 0 on success.
1803 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1804 unsigned long rpmbsize)
1809 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1810 cmd.cmdidx = MMC_CMD_RES_MAN;
1811 cmd.resp_type = MMC_RSP_R1b;
1812 cmd.cmdarg = MMC_CMD62_ARG1;
1814 err = mmc_send_cmd(mmc, &cmd, NULL);
1816 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1820 /* Boot partition changing mode */
1821 cmd.cmdidx = MMC_CMD_RES_MAN;
1822 cmd.resp_type = MMC_RSP_R1b;
1823 cmd.cmdarg = MMC_CMD62_ARG2;
1825 err = mmc_send_cmd(mmc, &cmd, NULL);
1827 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1830 /* boot partition size is multiple of 128KB */
1831 bootsize = (bootsize * 1024) / 128;
1833 /* Arg: boot partition size */
1834 cmd.cmdidx = MMC_CMD_RES_MAN;
1835 cmd.resp_type = MMC_RSP_R1b;
1836 cmd.cmdarg = bootsize;
1838 err = mmc_send_cmd(mmc, &cmd, NULL);
1840 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1843 /* RPMB partition size is multiple of 128KB */
1844 rpmbsize = (rpmbsize * 1024) / 128;
1845 /* Arg: RPMB partition size */
1846 cmd.cmdidx = MMC_CMD_RES_MAN;
1847 cmd.resp_type = MMC_RSP_R1b;
1848 cmd.cmdarg = rpmbsize;
1850 err = mmc_send_cmd(mmc, &cmd, NULL);
1852 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1859 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1860 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1863 * Returns 0 on success.
1865 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1869 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1870 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1871 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1872 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1880 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1881 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1884 * Returns 0 on success.
1886 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1890 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1891 EXT_CSD_BOOT_ACK(ack) |
1892 EXT_CSD_BOOT_PART_NUM(part_num) |
1893 EXT_CSD_PARTITION_ACCESS(access));
1901 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1902 * for enable. Note that this is a write-once field for non-zero values.
1904 * Returns 0 on success.
1906 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1909 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1911 ret = mmc_send_ext_csd(mmc, ext_csd);
1915 if (ext_csd[EXT_CSD_RST_N_FUNCTION] != 0 &&
1916 ext_csd[EXT_CSD_RST_N_FUNCTION] != enable) {
1917 printf("RST_N_FUNCTION is already set to %u; cannot change to %u\n",
1918 ext_csd[EXT_CSD_RST_N_FUNCTION], enable);
1921 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,