2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/errno.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
29 #include <bouncebuf.h>
33 struct mxs_ssp_regs *regs;
35 int (*mmc_is_wp)(int);
37 struct mxs_dma_desc *desc;
40 #define MXSMMC_MAX_TIMEOUT 10000
41 #define MXSMMC_SMALL_TRANSFER 512
43 static int mxsmmc_cd(struct mxsmmc_priv *priv)
45 struct mxs_ssp_regs *ssp_regs = priv->regs;
48 return priv->mmc_cd(priv->id);
50 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
53 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
55 struct mxs_ssp_regs *ssp_regs = priv->regs;
57 int timeout = MXSMMC_MAX_TIMEOUT;
59 uint32_t data_count = data->blocksize * data->blocks;
61 if (data->flags & MMC_DATA_READ) {
62 data_ptr = (uint32_t *)data->dest;
63 while (data_count && --timeout) {
64 reg = readl(&ssp_regs->hw_ssp_status);
65 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
66 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
68 timeout = MXSMMC_MAX_TIMEOUT;
73 data_ptr = (uint32_t *)data->src;
75 while (data_count && --timeout) {
76 reg = readl(&ssp_regs->hw_ssp_status);
77 if (!(reg & SSP_STATUS_FIFO_FULL)) {
78 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
80 timeout = MXSMMC_MAX_TIMEOUT;
86 return timeout ? 0 : COMM_ERR;
89 static int mxsmmc_send_cmd_dma(struct mmc *mmc, struct mxsmmc_priv *priv,
90 struct mmc_data *data)
92 uint32_t data_count = data->blocksize * data->blocks;
94 struct mxs_dma_desc *desc = priv->desc;
97 struct bounce_buffer bbstate;
98 unsigned long xfer_rate = (mmc->clock ?: 400000) * mmc->bus_width;
99 unsigned long dma_timeout = data_count * 8 /
100 DIV_ROUND_UP(xfer_rate, 1000);
102 memset(desc, 0, sizeof(struct mxs_dma_desc));
103 desc->address = (dma_addr_t)desc;
105 if (data->flags & MMC_DATA_READ) {
106 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
108 flags = GEN_BB_WRITE;
110 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
111 addr = (void *)data->src;
115 bounce_buffer_start(&bbstate, addr, data_count, flags);
117 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
119 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
120 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
122 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
123 mxs_dma_desc_append(dmach, priv->desc);
124 /* set DMA timeout adding 250ms for min timeout according to SD spec. */
125 mxs_dma_set_timeout(dmach, dma_timeout + 250);
126 if (mxs_dma_go(dmach)) {
127 bounce_buffer_stop(&bbstate);
131 bounce_buffer_stop(&bbstate);
137 * Sends a command out on the bus. Takes the mmc pointer,
138 * a command pointer, and an optional data pointer.
141 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
143 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
144 struct mxs_ssp_regs *ssp_regs = priv->regs;
148 const uint32_t busy_stat = SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
152 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
155 timeout = MXSMMC_MAX_TIMEOUT;
156 while ((reg = readl(&ssp_regs->hw_ssp_status)) & busy_stat) {
161 if (reg & busy_stat && readl(&ssp_regs->hw_ssp_status) & busy_stat) {
162 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
166 /* See if card is present */
167 if (!mxsmmc_cd(priv)) {
168 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
172 /* Start building CTRL0 contents */
173 ctrl0 = priv->buswidth;
176 if (!(cmd->resp_type & MMC_RSP_CRC))
177 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
178 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
179 ctrl0 |= SSP_CTRL0_GET_RESP;
180 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
181 ctrl0 |= SSP_CTRL0_LONG_RESP;
183 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
184 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
186 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
189 reg = readl(&ssp_regs->hw_ssp_cmd0);
190 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
191 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
192 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
193 reg |= SSP_CMD0_APPEND_8CYC;
194 writel(reg, &ssp_regs->hw_ssp_cmd0);
196 /* Command argument */
197 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
202 if (data->flags & MMC_DATA_READ) {
203 ctrl0 |= SSP_CTRL0_READ;
204 } else if (priv->mmc_is_wp &&
205 priv->mmc_is_wp(mmc->block_dev.dev)) {
206 printf("MMC%d: Can not write a locked card!\n",
211 ctrl0 |= SSP_CTRL0_DATA_XFER;
213 reg = data->blocksize * data->blocks;
214 #if defined(CONFIG_MX23)
215 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
217 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
218 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
219 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
220 ((ffs(data->blocksize) - 1) <<
221 SSP_CMD0_BLOCK_SIZE_OFFSET));
222 #elif defined(CONFIG_MX28)
223 writel(reg, &ssp_regs->hw_ssp_xfer_size);
225 reg = ((data->blocks - 1) <<
226 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
227 ((ffs(data->blocksize) - 1) <<
228 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
229 writel(reg, &ssp_regs->hw_ssp_block_size);
233 /* Kick off the command */
234 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
235 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
237 /* Wait for the command to complete */
238 timeout = MXSMMC_MAX_TIMEOUT;
241 reg = readl(&ssp_regs->hw_ssp_status);
242 if (!(reg & SSP_STATUS_CMD_BUSY))
245 if ((reg & SSP_STATUS_CMD_BUSY) &&
246 (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CMD_BUSY)) {
247 printf("MMC%d: Command %d busy\n",
248 mmc->block_dev.dev, cmd->cmdidx);
252 /* Check command timeout */
253 if (reg & SSP_STATUS_RESP_TIMEOUT) {
254 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
255 mmc->block_dev.dev, cmd->cmdidx, reg);
259 /* Check command errors */
260 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
261 printf("MMC%d: Command %d error (status 0x%08x)!\n",
262 mmc->block_dev.dev, cmd->cmdidx, reg);
266 /* Copy response to response buffer */
267 if (cmd->resp_type & MMC_RSP_136) {
268 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
269 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
270 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
271 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
273 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
275 /* Return if no data to process */
279 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
280 ret = mxsmmc_send_cmd_pio(priv, data);
282 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
283 mmc->block_dev.dev, cmd->cmdidx, reg);
287 ret = mxsmmc_send_cmd_dma(mmc, priv, data);
289 printf("MMC%d: DMA transfer failed\n",
295 /* Check data errors */
296 reg = readl(&ssp_regs->hw_ssp_status);
298 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
299 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
300 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
301 mmc->block_dev.dev, cmd->cmdidx, reg);
308 static void mxsmmc_set_ios(struct mmc *mmc)
310 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
311 struct mxs_ssp_regs *ssp_regs = priv->regs;
313 /* Set the clock speed */
315 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
317 switch (mmc->bus_width) {
319 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
322 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
325 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
329 /* Set the bus width */
330 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
331 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
333 debug("MMC%d: Set %d bits bus width\n",
334 mmc->block_dev.dev, mmc->bus_width);
337 static int mxsmmc_init(struct mmc *mmc)
339 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
340 struct mxs_ssp_regs *ssp_regs = priv->regs;
343 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
345 /* Reconfigure the SSP block for MMC operation */
346 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
347 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
348 SSP_CTRL1_DMA_ENABLE |
350 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
351 SSP_CTRL1_DATA_CRC_IRQ_EN |
352 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
353 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
354 SSP_CTRL1_RESP_ERR_IRQ_EN,
355 &ssp_regs->hw_ssp_ctrl1_set);
357 /* Set initial bit clock 400 KHz */
358 mxs_set_ssp_busclock(priv->id, 400);
360 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
361 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
363 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
368 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
370 struct mmc *mmc = NULL;
371 struct mxsmmc_priv *priv = NULL;
373 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
375 if (!mxs_ssp_bus_id_valid(id))
378 mmc = calloc(sizeof(struct mmc), 1);
382 priv = calloc(sizeof(struct mxsmmc_priv), 1);
388 priv->desc = mxs_dma_desc_alloc();
395 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
399 priv->mmc_is_wp = wp;
402 priv->regs = mxs_ssp_regs_by_bus(id);
404 sprintf(mmc->name, "MXS MMC");
405 mmc->send_cmd = mxsmmc_send_cmd;
406 mmc->set_ios = mxsmmc_set_ios;
407 mmc->init = mxsmmc_init;
412 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
414 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
415 MMC_MODE_HS_52MHz | MMC_MODE_HS;
418 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
419 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
420 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
421 * CLOCK_RATE could be any integer from 0 to 255.
424 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;