2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/errno.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
29 #include <bouncebuf.h>
33 struct mxs_ssp_regs *regs;
35 int (*mmc_is_wp)(int);
37 struct mxs_dma_desc *desc;
40 #define MXSMMC_MAX_TIMEOUT 10000
41 #define MXSMMC_SMALL_TRANSFER 512
43 static int mxsmmc_cd(struct mxsmmc_priv *priv)
45 struct mxs_ssp_regs *ssp_regs = priv->regs;
48 return priv->mmc_cd(priv->id);
50 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
53 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
55 struct mxs_ssp_regs *ssp_regs = priv->regs;
57 int timeout = MXSMMC_MAX_TIMEOUT;
59 uint32_t data_count = data->blocksize * data->blocks;
61 if (data->flags & MMC_DATA_READ) {
62 data_ptr = (uint32_t *)data->dest;
63 while (data_count && --timeout) {
64 reg = readl(&ssp_regs->hw_ssp_status);
65 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
66 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
68 timeout = MXSMMC_MAX_TIMEOUT;
73 data_ptr = (uint32_t *)data->src;
75 while (data_count && --timeout) {
76 reg = readl(&ssp_regs->hw_ssp_status);
77 if (!(reg & SSP_STATUS_FIFO_FULL)) {
78 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
80 timeout = MXSMMC_MAX_TIMEOUT;
86 return timeout ? 0 : COMM_ERR;
89 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
91 uint32_t data_count = data->blocksize * data->blocks;
93 struct mxs_dma_desc *desc = priv->desc;
96 struct bounce_buffer bbstate;
98 memset(desc, 0, sizeof(struct mxs_dma_desc));
99 desc->address = (dma_addr_t)desc;
101 if (data->flags & MMC_DATA_READ) {
102 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
104 flags = GEN_BB_WRITE;
106 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
107 addr = (void *)data->src;
111 bounce_buffer_start(&bbstate, addr, data_count, flags);
113 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
115 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
116 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
118 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
119 mxs_dma_desc_append(dmach, priv->desc);
120 if (mxs_dma_go(dmach)) {
121 bounce_buffer_stop(&bbstate);
125 bounce_buffer_stop(&bbstate);
131 * Sends a command out on the bus. Takes the mmc pointer,
132 * a command pointer, and an optional data pointer.
135 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
137 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
138 struct mxs_ssp_regs *ssp_regs = priv->regs;
142 const uint32_t busy_stat = SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
146 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
149 timeout = MXSMMC_MAX_TIMEOUT;
150 while ((reg = readl(&ssp_regs->hw_ssp_status)) & busy_stat) {
155 if (reg & busy_stat && readl(&ssp_regs->hw_ssp_status) & busy_stat) {
156 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
160 /* See if card is present */
161 if (!mxsmmc_cd(priv)) {
162 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
166 /* Start building CTRL0 contents */
167 ctrl0 = priv->buswidth;
170 if (!(cmd->resp_type & MMC_RSP_CRC))
171 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
172 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
173 ctrl0 |= SSP_CTRL0_GET_RESP;
174 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
175 ctrl0 |= SSP_CTRL0_LONG_RESP;
177 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
178 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
180 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
183 reg = readl(&ssp_regs->hw_ssp_cmd0);
184 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
185 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
186 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
187 reg |= SSP_CMD0_APPEND_8CYC;
188 writel(reg, &ssp_regs->hw_ssp_cmd0);
190 /* Command argument */
191 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
196 if (data->flags & MMC_DATA_READ) {
197 ctrl0 |= SSP_CTRL0_READ;
198 } else if (priv->mmc_is_wp &&
199 priv->mmc_is_wp(mmc->block_dev.dev)) {
200 printf("MMC%d: Can not write a locked card!\n",
205 ctrl0 |= SSP_CTRL0_DATA_XFER;
207 reg = data->blocksize * data->blocks;
208 #if defined(CONFIG_MX23)
209 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
211 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
212 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
213 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
214 ((ffs(data->blocksize) - 1) <<
215 SSP_CMD0_BLOCK_SIZE_OFFSET));
216 #elif defined(CONFIG_MX28)
217 writel(reg, &ssp_regs->hw_ssp_xfer_size);
219 reg = ((data->blocks - 1) <<
220 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
221 ((ffs(data->blocksize) - 1) <<
222 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
223 writel(reg, &ssp_regs->hw_ssp_block_size);
227 /* Kick off the command */
228 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
229 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
231 /* Wait for the command to complete */
232 timeout = MXSMMC_MAX_TIMEOUT;
235 reg = readl(&ssp_regs->hw_ssp_status);
236 if (!(reg & SSP_STATUS_CMD_BUSY))
239 if ((reg & SSP_STATUS_CMD_BUSY) &&
240 (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CMD_BUSY)) {
241 printf("MMC%d: Command %d busy\n",
242 mmc->block_dev.dev, cmd->cmdidx);
246 /* Check command timeout */
247 if (reg & SSP_STATUS_RESP_TIMEOUT) {
248 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
249 mmc->block_dev.dev, cmd->cmdidx, reg);
253 /* Check command errors */
254 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
255 printf("MMC%d: Command %d error (status 0x%08x)!\n",
256 mmc->block_dev.dev, cmd->cmdidx, reg);
260 /* Copy response to response buffer */
261 if (cmd->resp_type & MMC_RSP_136) {
262 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
263 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
264 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
265 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
267 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
269 /* Return if no data to process */
273 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
274 ret = mxsmmc_send_cmd_pio(priv, data);
276 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
277 mmc->block_dev.dev, cmd->cmdidx, reg);
281 ret = mxsmmc_send_cmd_dma(priv, data);
283 printf("MMC%d: DMA transfer failed\n",
289 /* Check data errors */
290 reg = readl(&ssp_regs->hw_ssp_status);
292 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
293 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
294 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
295 mmc->block_dev.dev, cmd->cmdidx, reg);
302 static void mxsmmc_set_ios(struct mmc *mmc)
304 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
305 struct mxs_ssp_regs *ssp_regs = priv->regs;
307 /* Set the clock speed */
309 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
311 switch (mmc->bus_width) {
313 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
316 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
319 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
323 /* Set the bus width */
324 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
325 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
327 debug("MMC%d: Set %d bits bus width\n",
328 mmc->block_dev.dev, mmc->bus_width);
331 static int mxsmmc_init(struct mmc *mmc)
333 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
334 struct mxs_ssp_regs *ssp_regs = priv->regs;
337 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
339 /* Reconfigure the SSP block for MMC operation */
340 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
341 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
342 SSP_CTRL1_DMA_ENABLE |
344 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
345 SSP_CTRL1_DATA_CRC_IRQ_EN |
346 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
347 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
348 SSP_CTRL1_RESP_ERR_IRQ_EN,
349 &ssp_regs->hw_ssp_ctrl1_set);
351 /* Set initial bit clock 400 KHz */
352 mxs_set_ssp_busclock(priv->id, 400);
354 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
355 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
357 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
362 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
364 struct mmc *mmc = NULL;
365 struct mxsmmc_priv *priv = NULL;
367 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
369 if (!mxs_ssp_bus_id_valid(id))
372 mmc = calloc(sizeof(struct mmc), 1);
376 priv = calloc(sizeof(struct mxsmmc_priv), 1);
382 priv->desc = mxs_dma_desc_alloc();
389 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
393 priv->mmc_is_wp = wp;
396 priv->regs = mxs_ssp_regs_by_bus(id);
398 sprintf(mmc->name, "MXS MMC");
399 mmc->send_cmd = mxsmmc_send_cmd;
400 mmc->set_ios = mxsmmc_set_ios;
401 mmc->init = mxsmmc_init;
406 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
408 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
409 MMC_MODE_HS_52MHz | MMC_MODE_HS;
412 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
413 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
414 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
415 * CLOCK_RATE could be any integer from 0 to 255.
418 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;