2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/errno.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/sys_proto.h>
44 #include <asm/imx-common/dma.h>
45 #include <bouncebuf.h>
49 struct mxs_ssp_regs *regs;
51 int (*mmc_is_wp)(int);
53 struct mxs_dma_desc *desc;
56 #define MXSMMC_MAX_TIMEOUT 10000
57 #define MXSMMC_SMALL_TRANSFER 512
59 static int mxsmmc_cd(struct mxsmmc_priv *priv)
61 struct mxs_ssp_regs *ssp_regs = priv->regs;
64 return priv->mmc_cd(priv->id);
66 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
69 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
71 struct mxs_ssp_regs *ssp_regs = priv->regs;
73 int timeout = MXSMMC_MAX_TIMEOUT;
75 uint32_t data_count = data->blocksize * data->blocks;
77 if (data->flags & MMC_DATA_READ) {
78 data_ptr = (uint32_t *)data->dest;
79 while (data_count && --timeout) {
80 reg = readl(&ssp_regs->hw_ssp_status);
81 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
82 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
84 timeout = MXSMMC_MAX_TIMEOUT;
89 data_ptr = (uint32_t *)data->src;
91 while (data_count && --timeout) {
92 reg = readl(&ssp_regs->hw_ssp_status);
93 if (!(reg & SSP_STATUS_FIFO_FULL)) {
94 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
96 timeout = MXSMMC_MAX_TIMEOUT;
102 return timeout ? 0 : COMM_ERR;
105 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
107 uint32_t data_count = data->blocksize * data->blocks;
109 struct mxs_dma_desc *desc = priv->desc;
112 struct bounce_buffer bbstate;
114 memset(desc, 0, sizeof(struct mxs_dma_desc));
115 desc->address = (dma_addr_t)desc;
117 if (data->flags & MMC_DATA_READ) {
118 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
120 flags = GEN_BB_WRITE;
122 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
123 addr = (void *)data->src;
127 bounce_buffer_start(&bbstate, addr, data_count, flags);
129 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
131 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
132 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
134 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
135 mxs_dma_desc_append(dmach, priv->desc);
136 if (mxs_dma_go(dmach)) {
137 bounce_buffer_stop(&bbstate);
141 bounce_buffer_stop(&bbstate);
147 * Sends a command out on the bus. Takes the mmc pointer,
148 * a command pointer, and an optional data pointer.
151 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
153 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
154 struct mxs_ssp_regs *ssp_regs = priv->regs;
160 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
163 timeout = MXSMMC_MAX_TIMEOUT;
166 reg = readl(&ssp_regs->hw_ssp_status);
168 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
169 SSP_STATUS_CMD_BUSY))) {
175 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
179 /* See if card is present */
180 if (!mxsmmc_cd(priv)) {
181 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
185 /* Start building CTRL0 contents */
186 ctrl0 = priv->buswidth;
189 if (!(cmd->resp_type & MMC_RSP_CRC))
190 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
191 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
192 ctrl0 |= SSP_CTRL0_GET_RESP;
193 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
194 ctrl0 |= SSP_CTRL0_LONG_RESP;
196 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
197 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
199 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
202 reg = readl(&ssp_regs->hw_ssp_cmd0);
203 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
204 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
205 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
206 reg |= SSP_CMD0_APPEND_8CYC;
207 writel(reg, &ssp_regs->hw_ssp_cmd0);
209 /* Command argument */
210 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
215 if (data->flags & MMC_DATA_READ) {
216 ctrl0 |= SSP_CTRL0_READ;
217 } else if (priv->mmc_is_wp &&
218 priv->mmc_is_wp(mmc->block_dev.dev)) {
219 printf("MMC%d: Can not write a locked card!\n",
224 ctrl0 |= SSP_CTRL0_DATA_XFER;
226 reg = data->blocksize * data->blocks;
227 #if defined(CONFIG_MX23)
228 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
230 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
231 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
232 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
233 ((ffs(data->blocksize) - 1) <<
234 SSP_CMD0_BLOCK_SIZE_OFFSET));
235 #elif defined(CONFIG_MX28)
236 writel(reg, &ssp_regs->hw_ssp_xfer_size);
238 reg = ((data->blocks - 1) <<
239 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
240 ((ffs(data->blocksize) - 1) <<
241 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
242 writel(reg, &ssp_regs->hw_ssp_block_size);
246 /* Kick off the command */
247 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
248 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
250 /* Wait for the command to complete */
251 timeout = MXSMMC_MAX_TIMEOUT;
254 reg = readl(&ssp_regs->hw_ssp_status);
255 if (!(reg & SSP_STATUS_CMD_BUSY))
260 printf("MMC%d: Command %d busy\n",
261 mmc->block_dev.dev, cmd->cmdidx);
265 /* Check command timeout */
266 if (reg & SSP_STATUS_RESP_TIMEOUT) {
267 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
268 mmc->block_dev.dev, cmd->cmdidx, reg);
272 /* Check command errors */
273 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
274 printf("MMC%d: Command %d error (status 0x%08x)!\n",
275 mmc->block_dev.dev, cmd->cmdidx, reg);
279 /* Copy response to response buffer */
280 if (cmd->resp_type & MMC_RSP_136) {
281 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
282 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
283 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
284 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
286 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
288 /* Return if no data to process */
292 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
293 ret = mxsmmc_send_cmd_pio(priv, data);
295 printf("MMC%d: Data timeout with command %d "
296 "(status 0x%08x)!\n",
297 mmc->block_dev.dev, cmd->cmdidx, reg);
301 ret = mxsmmc_send_cmd_dma(priv, data);
303 printf("MMC%d: DMA transfer failed\n",
309 /* Check data errors */
310 reg = readl(&ssp_regs->hw_ssp_status);
312 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
313 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
314 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
315 mmc->block_dev.dev, cmd->cmdidx, reg);
322 static void mxsmmc_set_ios(struct mmc *mmc)
324 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
325 struct mxs_ssp_regs *ssp_regs = priv->regs;
327 /* Set the clock speed */
329 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
331 switch (mmc->bus_width) {
333 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
336 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
339 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
343 /* Set the bus width */
344 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
345 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
347 debug("MMC%d: Set %d bits bus width\n",
348 mmc->block_dev.dev, mmc->bus_width);
351 static int mxsmmc_init(struct mmc *mmc)
353 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
354 struct mxs_ssp_regs *ssp_regs = priv->regs;
357 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
359 /* Reconfigure the SSP block for MMC operation */
360 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
361 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
362 SSP_CTRL1_DMA_ENABLE |
364 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
365 SSP_CTRL1_DATA_CRC_IRQ_EN |
366 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
367 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
368 SSP_CTRL1_RESP_ERR_IRQ_EN,
369 &ssp_regs->hw_ssp_ctrl1_set);
371 /* Set initial bit clock 400 KHz */
372 mxs_set_ssp_busclock(priv->id, 400);
374 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
375 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
377 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
382 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
384 struct mmc *mmc = NULL;
385 struct mxsmmc_priv *priv = NULL;
387 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
389 if (!mxs_ssp_bus_id_valid(id))
392 mmc = malloc(sizeof(struct mmc));
396 priv = malloc(sizeof(struct mxsmmc_priv));
402 priv->desc = mxs_dma_desc_alloc();
409 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
413 priv->mmc_is_wp = wp;
416 priv->regs = mxs_ssp_regs_by_bus(id);
418 sprintf(mmc->name, "MXS MMC");
419 mmc->send_cmd = mxsmmc_send_cmd;
420 mmc->set_ios = mxsmmc_set_ios;
421 mmc->init = mxsmmc_init;
426 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
428 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
429 MMC_MODE_HS_52MHz | MMC_MODE_HS;
432 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
433 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
434 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
435 * CLOCK_RATE could be any integer from 0 to 255.
438 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;