3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/mmc_host_def.h>
38 #include <asm/arch/sys_proto.h>
40 /* simplify defines to OMAP_HSMMC_USE_GPIO */
41 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
42 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
43 #define OMAP_HSMMC_USE_GPIO
45 #undef OMAP_HSMMC_USE_GPIO
48 /* common definitions for all OMAPs */
49 #define SYSCTL_SRC (1 << 25)
50 #define SYSCTL_SRD (1 << 26)
52 struct omap_hsmmc_data {
53 struct hsmmc *base_addr;
54 struct mmc_config cfg;
55 #ifdef OMAP_HSMMC_USE_GPIO
61 /* If we fail after 1 second wait, something is really bad */
62 #define MAX_RETRY_MS 1000
64 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
65 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
68 #ifdef OMAP_HSMMC_USE_GPIO
69 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
73 #ifndef CONFIG_DM_GPIO
74 if (!gpio_is_valid(gpio))
77 ret = gpio_request(gpio, label);
81 ret = gpio_direction_input(gpio);
89 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
90 static void omap4_vmmc_pbias_config(struct mmc *mmc)
94 value = readl((*ctrl)->control_pbiaslite);
95 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
96 writel(value, (*ctrl)->control_pbiaslite);
98 twl6030_power_mmc_init();
99 value = readl((*ctrl)->control_pbiaslite);
100 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
101 writel(value, (*ctrl)->control_pbiaslite);
105 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
106 static void omap5_pbias_config(struct mmc *mmc)
110 value = readl((*ctrl)->control_pbias);
111 value &= ~SDCARD_PWRDNZ;
112 writel(value, (*ctrl)->control_pbias);
113 udelay(10); /* wait 10 us */
114 value &= ~SDCARD_BIAS_PWRDNZ;
115 writel(value, (*ctrl)->control_pbias);
117 palmas_mmc1_poweron_ldo();
119 value = readl((*ctrl)->control_pbias);
120 value |= SDCARD_BIAS_PWRDNZ;
121 writel(value, (*ctrl)->control_pbias);
122 udelay(150); /* wait 150 us */
123 value |= SDCARD_PWRDNZ;
124 writel(value, (*ctrl)->control_pbias);
125 udelay(150); /* wait 150 us */
129 static void mmc_board_init(struct mmc *mmc)
131 #if defined(CONFIG_OMAP34XX)
132 t2_t *t2_base = (t2_t *)T2_BASE;
133 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
136 pbias_lite = readl(&t2_base->pbias_lite);
137 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
138 #ifdef CONFIG_TARGET_OMAP3_CAIRO
139 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
140 pbias_lite &= ~PBIASLITEVMODE0;
142 writel(pbias_lite, &t2_base->pbias_lite);
144 writel(pbias_lite | PBIASLITEPWRDNZ1 |
145 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
146 &t2_base->pbias_lite);
148 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
151 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
154 /* Change from default of 52MHz to 26MHz if necessary */
155 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
156 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
157 &t2_base->ctl_prog_io1);
159 writel(readl(&prcm_base->fclken1_core) |
160 EN_MMC1 | EN_MMC2 | EN_MMC3,
161 &prcm_base->fclken1_core);
163 writel(readl(&prcm_base->iclken1_core) |
164 EN_MMC1 | EN_MMC2 | EN_MMC3,
165 &prcm_base->iclken1_core);
168 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
169 /* PBIAS config needed for MMC1 only */
170 if (mmc->block_dev.dev == 0)
171 omap4_vmmc_pbias_config(mmc);
173 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
174 if (mmc->block_dev.dev == 0)
175 omap5_pbias_config(mmc);
179 void mmc_init_stream(struct hsmmc *mmc_base)
183 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
185 writel(MMC_CMD0, &mmc_base->cmd);
186 start = get_timer(0);
187 while (!(readl(&mmc_base->stat) & CC_MASK)) {
188 if (get_timer(start) > MAX_RETRY_MS)
191 if (!(readl(&mmc_base->stat) & CC_MASK)) {
192 printf("%s: timeout waiting for cc!\n", __func__);
196 writel(CC_MASK, &mmc_base->stat);
197 writel(MMC_CMD0, &mmc_base->cmd);
199 start = get_timer(0);
200 while (!(readl(&mmc_base->stat) & CC_MASK)) {
201 if (get_timer(start) > MAX_RETRY_MS)
204 if (!(readl(&mmc_base->stat) & CC_MASK)) {
205 printf("%s: timeout waiting for cc2!\n", __func__);
208 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
212 static int omap_hsmmc_init_setup(struct mmc *mmc)
214 struct omap_hsmmc_data *priv_data = mmc->priv;
215 struct hsmmc *mmc_base = priv_data->base_addr;
216 unsigned int reg_val;
222 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
223 &mmc_base->sysconfig);
224 start = get_timer(0);
225 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
226 if (get_timer(start) > MAX_RETRY_MS)
229 if ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
230 printf("%s: timeout %08x waiting for softreset done!\n", __func__,
231 readl(&mmc_base->sysstatus));
234 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
235 start = get_timer(0);
236 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
237 if (get_timer(start) > MAX_RETRY_MS)
240 if ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
241 printf("%s: timeout waiting for softresetall!\n", __func__);
244 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
245 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
248 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
250 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
251 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
252 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
255 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
256 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
257 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
258 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
259 start = get_timer(0);
260 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
261 if (get_timer(start) > MAX_RETRY_MS)
264 if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
265 printf("%s: timeout waiting for ics!\n", __func__);
268 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
270 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
272 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
273 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
276 mmc_init_stream(mmc_base);
282 * MMC controller internal finite state machine reset
284 * Used to reset command or data internal state machines, using respectively
285 * SRC or SRD bit of SYSCTL register
287 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
291 mmc_reg_out(&mmc_base->sysctl, bit, bit);
294 * CMD(DAT) lines reset procedures are slightly different
295 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
296 * According to OMAP3 TRM:
297 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
299 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
300 * procedure steps must be as follows:
301 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
302 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
303 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
304 * 3. Wait until the SRC (SRD) bit returns to 0x0
305 * (reset procedure is completed).
307 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
308 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
309 if (!(readl(&mmc_base->sysctl) & bit)) {
310 start = get_timer(0);
311 while (!(readl(&mmc_base->sysctl) & bit)) {
312 if (get_timer(0) - start > MAX_RETRY_MS)
317 start = get_timer(0);
318 while ((readl(&mmc_base->sysctl) & bit) != 0) {
319 if (get_timer(0) - start > MAX_RETRY_MS)
322 if ((readl(&mmc_base->sysctl) & bit) != 0) {
323 printf("%s: timedout waiting for sysctl %x to clear\n", __func__, bit);
328 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
329 struct mmc_data *data)
331 struct omap_hsmmc_data *priv_data = mmc->priv;
332 struct hsmmc *mmc_base = priv_data->base_addr;
333 unsigned int flags, mmc_stat;
336 start = get_timer(0);
337 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
338 if (get_timer(start) > MAX_RETRY_MS)
341 if ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
342 printf("%s: timeout waiting on cmd inhibit to clear\n", __func__);
345 writel(0xFFFFFFFF, &mmc_base->stat);
346 start = get_timer(0);
347 while (readl(&mmc_base->stat)) {
348 if (get_timer(start) > MAX_RETRY_MS)
351 if (readl(&mmc_base->stat)) {
352 printf("%s: timeout waiting for stat!\n", __func__);
357 * CMDIDX[13:8] : Command index
358 * DATAPRNT[5] : Data Present Select
359 * ENCMDIDX[4] : Command Index Check Enable
360 * ENCMDCRC[3] : Command CRC Check Enable
365 * 11 = Length 48 Check busy after response
367 /* Delay added before checking the status of frq change
368 * retry not supported by mmc.c(core file)
370 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
371 udelay(50000); /* wait 50 ms */
373 if (!(cmd->resp_type & MMC_RSP_PRESENT))
375 else if (cmd->resp_type & MMC_RSP_136)
376 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
377 else if (cmd->resp_type & MMC_RSP_BUSY)
378 flags = RSP_TYPE_LGHT48B;
380 flags = RSP_TYPE_LGHT48;
382 /* enable default flags */
383 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
384 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
386 if (cmd->resp_type & MMC_RSP_CRC)
388 if (cmd->resp_type & MMC_RSP_OPCODE)
392 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
393 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
394 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
395 data->blocksize = 512;
396 writel(data->blocksize | (data->blocks << 16),
399 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
401 if (data->flags & MMC_DATA_READ)
402 flags |= (DP_DATA | DDIR_READ);
404 flags |= (DP_DATA | DDIR_WRITE);
407 writel(cmd->cmdarg, &mmc_base->arg);
408 udelay(20); /* To fix "No status update" error on eMMC */
409 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
411 start = get_timer(0);
412 while (!(mmc_stat = readl(&mmc_base->stat))) {
413 if (get_timer(start) > MAX_RETRY_MS)
417 printf("%s : timeout: No status update\n", __func__);
421 if ((mmc_stat & IE_CTO) != 0) {
422 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
424 } else if ((mmc_stat & ERRI_MASK) != 0)
427 if (mmc_stat & CC_MASK) {
428 writel(CC_MASK, &mmc_base->stat);
429 if (cmd->resp_type & MMC_RSP_PRESENT) {
430 if (cmd->resp_type & MMC_RSP_136) {
431 /* response type 2 */
432 cmd->response[3] = readl(&mmc_base->rsp10);
433 cmd->response[2] = readl(&mmc_base->rsp32);
434 cmd->response[1] = readl(&mmc_base->rsp54);
435 cmd->response[0] = readl(&mmc_base->rsp76);
437 /* response types 1, 1b, 3, 4, 5, 6 */
438 cmd->response[0] = readl(&mmc_base->rsp10);
442 if (data && (data->flags & MMC_DATA_READ)) {
443 mmc_read_data(mmc_base, data->dest,
444 data->blocksize * data->blocks);
445 } else if (data && (data->flags & MMC_DATA_WRITE)) {
446 mmc_write_data(mmc_base, data->src,
447 data->blocksize * data->blocks);
452 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
454 unsigned int *output_buf = (unsigned int *)buf;
455 unsigned int mmc_stat;
461 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
465 ulong start = get_timer(0);
467 while (!(mmc_stat = readl(&mmc_base->stat))) {
468 if (get_timer(start) > MAX_RETRY_MS)
472 printf("%s: timeout waiting for status!\n", __func__);
476 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
477 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
479 if ((mmc_stat & ERRI_MASK) != 0)
482 if (mmc_stat & BRR_MASK) {
485 writel(readl(&mmc_base->stat) | BRR_MASK,
487 for (k = 0; k < count; k++) {
488 *output_buf = readl(&mmc_base->data);
494 if (mmc_stat & BWR_MASK)
495 writel(readl(&mmc_base->stat) | BWR_MASK,
498 if (mmc_stat & TC_MASK) {
499 writel(readl(&mmc_base->stat) | TC_MASK,
507 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
510 unsigned int *input_buf = (unsigned int *)buf;
511 unsigned int mmc_stat;
517 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
521 ulong start = get_timer(0);
523 while (!(mmc_stat = readl(&mmc_base->stat))) {
524 if (get_timer(start) > MAX_RETRY_MS)
528 printf("%s: timeout waiting for status!\n", __func__);
532 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
533 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
535 if ((mmc_stat & ERRI_MASK) != 0)
538 if (mmc_stat & BWR_MASK) {
541 writel(readl(&mmc_base->stat) | BWR_MASK,
543 for (k = 0; k < count; k++) {
544 writel(*input_buf, &mmc_base->data);
550 if (mmc_stat & BRR_MASK)
551 writel(readl(&mmc_base->stat) | BRR_MASK,
554 if (mmc_stat & TC_MASK) {
555 writel(readl(&mmc_base->stat) | TC_MASK,
563 static void omap_hsmmc_set_ios(struct mmc *mmc)
565 struct omap_hsmmc_data *priv_data = mmc->priv;
566 struct hsmmc *mmc_base = priv_data->base_addr;
567 unsigned int dsor = 0;
570 /* configue bus width */
571 switch (mmc->bus_width) {
573 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
578 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
580 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
586 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
588 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
593 /* configure clock with 96Mhz system clock.
595 if (mmc->clock != 0) {
596 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
597 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
601 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
602 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
604 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
605 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
607 start = get_timer(0);
608 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
609 if (get_timer(start) > MAX_RETRY_MS)
612 if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
613 printf("%s: timeout waiting for ics!\n", __func__);
616 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
619 #ifdef OMAP_HSMMC_USE_GPIO
620 static int omap_hsmmc_getcd(struct mmc *mmc)
622 struct omap_hsmmc_data *priv_data = mmc->priv;
625 /* if no CD return as 1 */
626 cd_gpio = priv_data->cd_gpio;
630 /* NOTE: assumes card detect signal is active-low */
631 return !gpio_get_value(cd_gpio);
634 static int omap_hsmmc_getwp(struct mmc *mmc)
636 struct omap_hsmmc_data *priv_data = mmc->priv;
639 /* if no WP return as 0 */
640 wp_gpio = priv_data->wp_gpio;
644 /* NOTE: assumes write protect signal is active-high */
645 return gpio_get_value(wp_gpio);
649 static const struct mmc_ops omap_hsmmc_ops = {
650 .send_cmd = omap_hsmmc_send_cmd,
651 .set_ios = omap_hsmmc_set_ios,
652 .init = omap_hsmmc_init_setup,
653 #ifdef OMAP_HSMMC_USE_GPIO
654 .getcd = omap_hsmmc_getcd,
655 .getwp = omap_hsmmc_getwp,
659 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
664 struct omap_hsmmc_data *priv_data;
665 struct mmc_config *cfg;
668 priv_data = calloc(sizeof(*priv_data), 1);
669 if (priv_data == NULL)
672 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
676 priv_data->base_addr = (void *)OMAP_HSMMC1_BASE;
678 #ifdef OMAP_HSMMC2_BASE
680 priv_data->base_addr = (void *)OMAP_HSMMC2_BASE;
681 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
682 defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
683 defined(CONFIG_AM43XX)) && defined(CONFIG_HSMMC2_8BIT)
684 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
685 host_caps_val |= MMC_MODE_8BIT;
689 #ifdef OMAP_HSMMC3_BASE
691 priv_data->base_addr = (void *)OMAP_HSMMC3_BASE;
692 #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
693 /* Enable 8-bit interface for eMMC on DRA7XX */
694 host_caps_val |= MMC_MODE_8BIT;
699 printf("Invalid MMC device index: %d\n", dev_index);
703 #ifdef OMAP_HSMMC_USE_GPIO
704 /* on error gpio values are set to -1, which is what we want */
705 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
706 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
709 cfg = &priv_data->cfg;
711 cfg->name = "OMAP SD/MMC";
712 cfg->ops = &omap_hsmmc_ops;
714 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
715 cfg->host_caps = host_caps_val & ~host_caps_mask;
722 if (cfg->host_caps & MMC_MODE_HS) {
723 if (cfg->host_caps & MMC_MODE_HS_52MHz)
724 cfg->f_max = 52000000;
726 cfg->f_max = 26000000;
728 cfg->f_max = 20000000;
731 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
733 #if defined(CONFIG_OMAP34XX)
735 * Silicon revs 2.1 and older do not support multiblock transfers.
737 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
740 mmc = mmc_create(cfg, priv_data);