3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/mmc_host_def.h>
34 #include <asm/arch/sys_proto.h>
36 /* If we fail after 1 second wait, something is really bad */
37 #define MAX_RETRY_MS 1000
39 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
40 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
42 static struct mmc hsmmc_dev[2];
44 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
45 static void omap4_vmmc_pbias_config(struct mmc *mmc)
48 struct omap4_sys_ctrl_regs *const ctrl =
49 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
52 value = readl(&ctrl->control_pbiaslite);
53 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
54 writel(value, &ctrl->control_pbiaslite);
56 twl6030_power_mmc_init();
57 value = readl(&ctrl->control_pbiaslite);
58 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
59 writel(value, &ctrl->control_pbiaslite);
63 unsigned char mmc_board_init(struct mmc *mmc)
65 #if defined(CONFIG_TWL4030_POWER)
66 twl4030_power_mmc_init();
69 #if defined(CONFIG_OMAP34XX)
70 t2_t *t2_base = (t2_t *)T2_BASE;
71 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
73 writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
74 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
75 &t2_base->pbias_lite);
77 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
80 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
83 /* Change from default of 52MHz to 26MHz if necessary */
84 if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
85 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
86 &t2_base->ctl_prog_io1);
88 writel(readl(&prcm_base->fclken1_core) |
89 EN_MMC1 | EN_MMC2 | EN_MMC3,
90 &prcm_base->fclken1_core);
92 writel(readl(&prcm_base->iclken1_core) |
93 EN_MMC1 | EN_MMC2 | EN_MMC3,
94 &prcm_base->iclken1_core);
97 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
98 /* PBIAS config needed for MMC1 only */
99 if (mmc->block_dev.dev == 0)
100 omap4_vmmc_pbias_config(mmc);
106 void mmc_init_stream(struct hsmmc *mmc_base)
110 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
112 writel(MMC_CMD0, &mmc_base->cmd);
113 start = get_timer(0);
114 while (!(readl(&mmc_base->stat) & CC_MASK)) {
115 if (get_timer(0) - start > MAX_RETRY_MS) {
116 printf("%s: timedout waiting for cc!\n", __func__);
120 writel(CC_MASK, &mmc_base->stat)
122 writel(MMC_CMD0, &mmc_base->cmd)
124 start = get_timer(0);
125 while (!(readl(&mmc_base->stat) & CC_MASK)) {
126 if (get_timer(0) - start > MAX_RETRY_MS) {
127 printf("%s: timedout waiting for cc2!\n", __func__);
131 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
135 static int mmc_init_setup(struct mmc *mmc)
137 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
138 unsigned int reg_val;
144 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
145 &mmc_base->sysconfig);
146 start = get_timer(0);
147 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
148 if (get_timer(0) - start > MAX_RETRY_MS) {
149 printf("%s: timedout waiting for cc2!\n", __func__);
153 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
154 start = get_timer(0);
155 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
156 if (get_timer(0) - start > MAX_RETRY_MS) {
157 printf("%s: timedout waiting for softresetall!\n",
162 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
163 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
166 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
168 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
169 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
170 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
173 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
174 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
175 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
176 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
177 start = get_timer(0);
178 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
179 if (get_timer(0) - start > MAX_RETRY_MS) {
180 printf("%s: timedout waiting for ics!\n", __func__);
184 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
186 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
188 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
189 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
192 mmc_init_stream(mmc_base);
198 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
199 struct mmc_data *data)
201 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
202 unsigned int flags, mmc_stat;
205 start = get_timer(0);
206 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
207 if (get_timer(0) - start > MAX_RETRY_MS) {
208 printf("%s: timedout waiting on cmd inhibit to clear\n",
213 writel(0xFFFFFFFF, &mmc_base->stat);
214 start = get_timer(0);
215 while (readl(&mmc_base->stat)) {
216 if (get_timer(0) - start > MAX_RETRY_MS) {
217 printf("%s: timedout waiting for stat!\n", __func__);
223 * CMDIDX[13:8] : Command index
224 * DATAPRNT[5] : Data Present Select
225 * ENCMDIDX[4] : Command Index Check Enable
226 * ENCMDCRC[3] : Command CRC Check Enable
231 * 11 = Length 48 Check busy after response
233 /* Delay added before checking the status of frq change
234 * retry not supported by mmc.c(core file)
236 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
237 udelay(50000); /* wait 50 ms */
239 if (!(cmd->resp_type & MMC_RSP_PRESENT))
241 else if (cmd->resp_type & MMC_RSP_136)
242 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
243 else if (cmd->resp_type & MMC_RSP_BUSY)
244 flags = RSP_TYPE_LGHT48B;
246 flags = RSP_TYPE_LGHT48;
248 /* enable default flags */
249 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
250 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
252 if (cmd->resp_type & MMC_RSP_CRC)
254 if (cmd->resp_type & MMC_RSP_OPCODE)
258 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
259 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
260 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
261 data->blocksize = 512;
262 writel(data->blocksize | (data->blocks << 16),
265 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
267 if (data->flags & MMC_DATA_READ)
268 flags |= (DP_DATA | DDIR_READ);
270 flags |= (DP_DATA | DDIR_WRITE);
273 writel(cmd->cmdarg, &mmc_base->arg);
274 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
276 start = get_timer(0);
278 mmc_stat = readl(&mmc_base->stat);
279 if (get_timer(0) - start > MAX_RETRY_MS) {
280 printf("%s : timeout: No status update\n", __func__);
285 if ((mmc_stat & IE_CTO) != 0)
287 else if ((mmc_stat & ERRI_MASK) != 0)
290 if (mmc_stat & CC_MASK) {
291 writel(CC_MASK, &mmc_base->stat);
292 if (cmd->resp_type & MMC_RSP_PRESENT) {
293 if (cmd->resp_type & MMC_RSP_136) {
294 /* response type 2 */
295 cmd->response[3] = readl(&mmc_base->rsp10);
296 cmd->response[2] = readl(&mmc_base->rsp32);
297 cmd->response[1] = readl(&mmc_base->rsp54);
298 cmd->response[0] = readl(&mmc_base->rsp76);
300 /* response types 1, 1b, 3, 4, 5, 6 */
301 cmd->response[0] = readl(&mmc_base->rsp10);
305 if (data && (data->flags & MMC_DATA_READ)) {
306 mmc_read_data(mmc_base, data->dest,
307 data->blocksize * data->blocks);
308 } else if (data && (data->flags & MMC_DATA_WRITE)) {
309 mmc_write_data(mmc_base, data->src,
310 data->blocksize * data->blocks);
315 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
317 unsigned int *output_buf = (unsigned int *)buf;
318 unsigned int mmc_stat;
324 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
328 ulong start = get_timer(0);
330 mmc_stat = readl(&mmc_base->stat);
331 if (get_timer(0) - start > MAX_RETRY_MS) {
332 printf("%s: timedout waiting for status!\n",
336 } while (mmc_stat == 0);
338 if ((mmc_stat & ERRI_MASK) != 0)
341 if (mmc_stat & BRR_MASK) {
344 writel(readl(&mmc_base->stat) | BRR_MASK,
346 for (k = 0; k < count; k++) {
347 *output_buf = readl(&mmc_base->data);
353 if (mmc_stat & BWR_MASK)
354 writel(readl(&mmc_base->stat) | BWR_MASK,
357 if (mmc_stat & TC_MASK) {
358 writel(readl(&mmc_base->stat) | TC_MASK,
366 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
369 unsigned int *input_buf = (unsigned int *)buf;
370 unsigned int mmc_stat;
376 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
380 ulong start = get_timer(0);
382 mmc_stat = readl(&mmc_base->stat);
383 if (get_timer(0) - start > MAX_RETRY_MS) {
384 printf("%s: timedout waiting for status!\n",
388 } while (mmc_stat == 0);
390 if ((mmc_stat & ERRI_MASK) != 0)
393 if (mmc_stat & BWR_MASK) {
396 writel(readl(&mmc_base->stat) | BWR_MASK,
398 for (k = 0; k < count; k++) {
399 writel(*input_buf, &mmc_base->data);
405 if (mmc_stat & BRR_MASK)
406 writel(readl(&mmc_base->stat) | BRR_MASK,
409 if (mmc_stat & TC_MASK) {
410 writel(readl(&mmc_base->stat) | TC_MASK,
418 static void mmc_set_ios(struct mmc *mmc)
420 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
421 unsigned int dsor = 0;
424 /* configue bus width */
425 switch (mmc->bus_width) {
427 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
432 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
434 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
440 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
442 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
447 /* configure clock with 96Mhz system clock.
449 if (mmc->clock != 0) {
450 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
451 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
455 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
456 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
458 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
459 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
461 start = get_timer(0);
462 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
463 if (get_timer(0) - start > MAX_RETRY_MS) {
464 printf("%s: timedout waiting for ics!\n", __func__);
468 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
471 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
475 mmc = &hsmmc_dev[dev_index];
477 sprintf(mmc->name, "OMAP SD/MMC");
478 mmc->send_cmd = mmc_send_cmd;
479 mmc->set_ios = mmc_set_ios;
480 mmc->init = mmc_init_setup;
485 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
487 #ifdef OMAP_HSMMC2_BASE
489 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
492 #ifdef OMAP_HSMMC3_BASE
494 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
498 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
501 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
502 mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
503 MMC_MODE_HC) & ~host_caps_mask;
510 if (mmc->host_caps & MMC_MODE_HS) {
511 if (mmc->host_caps & MMC_MODE_HS_52MHz)
512 mmc->f_max = 52000000;
514 mmc->f_max = 26000000;
516 mmc->f_max = 20000000;
521 #if defined(CONFIG_OMAP34XX)
523 * Silicon revs 2.1 and older do not support multiblock transfers.
525 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))