2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18 static void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
20 static void *aligned_buffer;
23 static void sdhci_reset(struct sdhci_host *host, u8 mask)
25 unsigned long timeout;
29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
32 printf("%s: Reset 0x%x never completed.\n",
41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
44 if (cmd->resp_type & MMC_RSP_136) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i = 0; i < 4; i++) {
47 cmd->response[i] = sdhci_readl(host,
48 SDHCI_RESPONSE + (3-i)*4) << 8;
50 cmd->response[i] |= sdhci_readb(host,
51 SDHCI_RESPONSE + (3-i)*4-1);
54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
62 for (i = 0; i < data->blocksize; i += 4) {
63 offs = data->dest + i;
64 if (data->flags == MMC_DATA_READ)
65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
72 unsigned int start_addr)
74 unsigned int stat, rdy, mask, timeout, block = 0;
75 #ifdef CONFIG_MMC_SDMA
77 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
78 ctrl &= ~SDHCI_CTRL_DMA_MASK;
79 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
83 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
84 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
86 stat = sdhci_readl(host, SDHCI_INT_STATUS);
87 if (stat & SDHCI_INT_ERROR) {
88 printf("%s: Error detected in status(0x%X)!\n",
93 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
95 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
96 sdhci_transfer_pio(host, data);
97 data->dest += data->blocksize;
98 if (++block >= data->blocks)
101 #ifdef CONFIG_MMC_SDMA
102 if (stat & SDHCI_INT_DMA_END) {
103 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
104 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
105 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
106 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
112 printf("%s: Transfer data timeout\n", __func__);
115 } while (!(stat & SDHCI_INT_DATA_END));
120 * No command will be sent by driver if card is busy, so driver must wait
121 * for card ready state.
122 * Every time when card is busy after timeout then (last) timeout value will be
123 * increased twice but only if it doesn't exceed global defined maximum.
124 * Each function call will use last timeout value.
126 #define SDHCI_CMD_MAX_TIMEOUT 3200
127 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
128 #define SDHCI_READ_STATUS_TIMEOUT 1000
130 #ifdef CONFIG_DM_MMC_OPS
131 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
132 struct mmc_data *data)
134 struct mmc *mmc = mmc_get_mmc_dev(dev);
137 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
138 struct mmc_data *data)
141 struct sdhci_host *host = mmc->priv;
144 int trans_bytes = 0, is_aligned = 1;
145 u32 mask, flags, mode;
146 unsigned int time = 0, start_addr = 0;
147 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
148 unsigned long start = get_timer(0);
150 /* Timeout unit - ms */
151 unsigned int cmd_timeout;
153 cmd_timeout = cmd->cmdidx == MMC_CMD_SEND_STATUS ? 10 : 200;
155 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
156 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
158 /* We shouldn't wait for data inihibit for stop commands, even
159 though they might use busy signaling */
160 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
161 mask &= ~SDHCI_DATA_INHIBIT;
163 while ((stat = sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) {
164 if (time++ >= cmd_timeout) {
165 debug("%s: MMC: %d busy\n", __func__, mmc_dev);
166 if (stat & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT))
174 mask = SDHCI_INT_RESPONSE;
175 if (!(cmd->resp_type & MMC_RSP_PRESENT))
176 flags = SDHCI_CMD_RESP_NONE;
177 else if (cmd->resp_type & MMC_RSP_136)
178 flags = SDHCI_CMD_RESP_LONG;
179 else if (cmd->resp_type & MMC_RSP_BUSY) {
180 flags = SDHCI_CMD_RESP_SHORT_BUSY;
182 mask |= SDHCI_INT_DATA_END;
184 flags = SDHCI_CMD_RESP_SHORT;
186 if (cmd->resp_type & MMC_RSP_CRC)
187 flags |= SDHCI_CMD_CRC;
188 if (cmd->resp_type & MMC_RSP_OPCODE)
189 flags |= SDHCI_CMD_INDEX;
191 flags |= SDHCI_CMD_DATA;
193 /* Set Transfer mode regarding to data flag */
195 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
196 mode = SDHCI_TRNS_BLK_CNT_EN;
197 trans_bytes = data->blocks * data->blocksize;
198 if (data->blocks > 1)
199 mode |= SDHCI_TRNS_MULTI;
201 if (data->flags == MMC_DATA_READ)
202 mode |= SDHCI_TRNS_READ;
204 #ifdef CONFIG_MMC_SDMA
205 if (data->flags == MMC_DATA_READ)
206 start_addr = (unsigned long)data->dest;
208 start_addr = (unsigned long)data->src;
209 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
210 (start_addr & 0x7) != 0x0) {
212 start_addr = (unsigned long)aligned_buffer;
213 if (data->flags != MMC_DATA_READ)
214 memcpy(aligned_buffer, data->src, trans_bytes);
217 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
219 * Always use this bounce-buffer when
220 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
223 start_addr = (unsigned long)aligned_buffer;
224 if (data->flags != MMC_DATA_READ)
225 memcpy(aligned_buffer, data->src, trans_bytes);
227 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
228 mode |= SDHCI_TRNS_DMA;
230 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
233 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
234 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
235 } else if (cmd->resp_type & MMC_RSP_BUSY) {
236 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
239 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
240 #ifdef CONFIG_MMC_SDMA
241 flush_cache(start_addr, trans_bytes);
243 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
244 start = get_timer(0);
246 stat = sdhci_readl(host, SDHCI_INT_STATUS);
247 if (stat & SDHCI_INT_ERROR)
250 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
251 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
254 printf("%s: Timeout for status update!\n",
259 } while ((stat & mask) != mask);
261 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
262 sdhci_cmd_done(host, cmd);
263 sdhci_writel(host, mask, SDHCI_INT_STATUS);
269 ret = sdhci_transfer_data(host, data, start_addr);
271 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
274 stat = sdhci_readl(host, SDHCI_INT_STATUS);
275 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
277 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
278 !is_aligned && (data->flags == MMC_DATA_READ))
279 memcpy(data->dest, aligned_buffer, trans_bytes);
283 sdhci_reset(host, SDHCI_RESET_CMD);
284 sdhci_reset(host, SDHCI_RESET_DATA);
285 if (stat & SDHCI_INT_TIMEOUT)
291 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
293 struct sdhci_host *host = mmc->priv;
294 unsigned int div, timeout, reg;
299 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
300 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
302 printf("%s: Timeout waiting for cmd & data inhibit\n",
311 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
312 reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
313 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
318 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
320 * Check if the Host Controller supports Programmable Clock
324 for (div = 1; div <= 1024; div++) {
325 if ((mmc->cfg->f_max * host->clk_mul / div)
331 * Set Programmable Clock Mode in the Clock
334 clk = SDHCI_PROG_CLOCK_MODE;
337 /* Version 3.00 divisors must be a multiple of 2. */
338 if (mmc->cfg->f_max <= clock) {
342 div < SDHCI_MAX_DIV_SPEC_300;
344 if ((mmc->cfg->f_max / div) <= clock)
351 /* Version 2.00 divisors must be a power of 2. */
352 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
353 if ((mmc->cfg->f_max / div) <= clock)
360 host->set_clock(host->index, div);
362 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
363 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
364 << SDHCI_DIVIDER_HI_SHIFT;
365 clk |= SDHCI_CLOCK_INT_EN;
366 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
370 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
371 & SDHCI_CLOCK_INT_STABLE)) {
373 printf("%s: Internal clock never stabilised.\n",
381 clk |= SDHCI_CLOCK_CARD_EN;
382 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
386 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
390 if (power != (unsigned short)-1) {
391 switch (1 << power) {
392 case MMC_VDD_165_195:
393 pwr = SDHCI_POWER_180;
397 pwr = SDHCI_POWER_300;
401 pwr = SDHCI_POWER_330;
407 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
411 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
412 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
414 pwr |= SDHCI_POWER_ON;
416 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
419 #ifdef CONFIG_DM_MMC_OPS
420 static int sdhci_set_ios(struct udevice *dev)
422 struct mmc *mmc = mmc_get_mmc_dev(dev);
424 static void sdhci_set_ios(struct mmc *mmc)
428 struct sdhci_host *host = mmc->priv;
430 if (host->set_control_reg)
431 host->set_control_reg(host);
433 if (mmc->clock != host->clock)
434 sdhci_set_clock(mmc, mmc->clock);
437 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
438 if (mmc->bus_width == 8) {
439 ctrl &= ~SDHCI_CTRL_4BITBUS;
440 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
441 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
442 ctrl |= SDHCI_CTRL_8BITBUS;
444 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
445 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
446 ctrl &= ~SDHCI_CTRL_8BITBUS;
447 if (mmc->bus_width == 4)
448 ctrl |= SDHCI_CTRL_4BITBUS;
450 ctrl &= ~SDHCI_CTRL_4BITBUS;
453 if (mmc->clock > 26000000)
454 ctrl |= SDHCI_CTRL_HISPD;
456 ctrl &= ~SDHCI_CTRL_HISPD;
458 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
459 ctrl &= ~SDHCI_CTRL_HISPD;
461 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
462 #ifdef CONFIG_DM_MMC_OPS
467 static int sdhci_init(struct mmc *mmc)
469 struct sdhci_host *host = mmc->priv;
471 sdhci_reset(host, SDHCI_RESET_ALL);
473 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
474 aligned_buffer = memalign(8, 512*1024);
475 if (!aligned_buffer) {
476 printf("%s: Aligned buffer alloc failed!!!\n",
482 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
484 if (host->quirks & SDHCI_QUIRK_NO_CD) {
485 #if defined(CONFIG_PIC32_SDHCI)
486 /* PIC32 SDHCI CD errata:
487 * - set CD_TEST and clear CD_TEST_INS bit
489 sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
493 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
496 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
497 while ((!(status & SDHCI_CARD_PRESENT)) ||
498 (!(status & SDHCI_CARD_STATE_STABLE)) ||
499 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
500 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
504 /* Enable only interrupts served by the SD controller */
505 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
507 /* Mask all sdhci interrupt sources */
508 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
513 #ifdef CONFIG_DM_MMC_OPS
514 int sdhci_probe(struct udevice *dev)
516 struct mmc *mmc = mmc_get_mmc_dev(dev);
518 return sdhci_init(mmc);
521 const struct dm_mmc_ops sdhci_ops = {
522 .send_cmd = sdhci_send_command,
523 .set_ios = sdhci_set_ios,
526 static const struct mmc_ops sdhci_ops = {
527 .send_cmd = sdhci_send_command,
528 .set_ios = sdhci_set_ios,
533 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
534 u32 max_clk, u32 min_clk)
538 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
540 #ifdef CONFIG_MMC_SDMA
541 if (!(caps & SDHCI_CAN_DO_SDMA)) {
542 printf("%s: Your controller doesn't support SDMA!!\n",
547 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
549 cfg->name = host->name;
550 #ifndef CONFIG_DM_MMC_OPS
551 cfg->ops = &sdhci_ops;
554 cfg->f_max = max_clk;
556 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
557 cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
558 SDHCI_CLOCK_BASE_SHIFT;
560 cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
561 SDHCI_CLOCK_BASE_SHIFT;
562 cfg->f_max *= 1000000;
564 if (cfg->f_max == 0) {
565 printf("%s: Hardware doesn't specify base clock frequency\n",
570 cfg->f_min = min_clk;
572 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
573 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
575 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
578 if (caps & SDHCI_CAN_VDD_330)
579 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
580 if (caps & SDHCI_CAN_VDD_300)
581 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
582 if (caps & SDHCI_CAN_VDD_180)
583 cfg->voltages |= MMC_VDD_165_195;
585 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
586 cfg->voltages |= host->voltages;
588 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
589 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
590 if (caps & SDHCI_CAN_DO_8BIT)
591 cfg->host_caps |= MMC_MODE_8BIT;
595 cfg->host_caps |= host->host_caps;
598 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
601 * In case of Host Controller v3.00, find out whether clock
602 * multiplier is supported.
604 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
605 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
606 SDHCI_CLOCK_MUL_SHIFT;
612 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
614 return mmc_bind(dev, mmc, cfg);
617 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
621 ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
625 host->mmc = mmc_create(&host->cfg, host);
626 if (host->mmc == NULL) {
627 printf("%s: mmc create fail!\n", __func__);