drivers/mmc/tegra2_mmc.c

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Portions Copyright 2011 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <common.h>
  23 #include <mmc.h>
  24 #include <asm/gpio.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/clk_rst.h>
  27 #include <asm/arch/clock.h>
  28 #include "tegra2_mmc.h"
  29
  30 /* support 4 mmc hosts */
  31 struct mmc mmc_dev[4];
  32 struct mmc_host mmc_host[4];
  33
  34
  35 /**
  36  * Get the host address and peripheral ID for a device. Devices are numbered
  37  * from 0 to 3.
  38  *
  39  * @param host          Structure to fill in (base, reg, mmc_id)
  40  * @param dev_index     Device index (0-3)
  41  */
  42 static void tegra2_get_setup(struct mmc_host *host, int dev_index)
  43 {
  44         debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
  45
  46         switch (dev_index) {
  47         case 1:
  48                 host->base = TEGRA2_SDMMC3_BASE;
  49                 host->mmc_id = PERIPH_ID_SDMMC3;
  50                 break;
  51         case 2:
  52                 host->base = TEGRA2_SDMMC2_BASE;
  53                 host->mmc_id = PERIPH_ID_SDMMC2;
  54                 break;
  55         case 3:
  56                 host->base = TEGRA2_SDMMC1_BASE;
  57                 host->mmc_id = PERIPH_ID_SDMMC1;
  58                 break;
  59         case 0:
  60         default:
  61                 host->base = TEGRA2_SDMMC4_BASE;
  62                 host->mmc_id = PERIPH_ID_SDMMC4;
  63                 break;
  64         }
  65
  66         host->reg = (struct tegra2_mmc *)host->base;
  67 }
  68
  69 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
  70 {
  71         unsigned char ctrl;
  72
  73         debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
  74         (u32)data->dest, data->blocks, data->blocksize);
  75
  76         writel((u32)data->dest, &host->reg->sysad);
  77         /*
  78          * DMASEL[4:3]
  79          * 00 = Selects SDMA
  80          * 01 = Reserved
  81          * 10 = Selects 32-bit Address ADMA2
  82          * 11 = Selects 64-bit Address ADMA2
  83          */
  84         ctrl = readb(&host->reg->hostctl);
  85         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  86         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  87         writeb(ctrl, &host->reg->hostctl);
  88
  89         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  90         writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
  91         writew(data->blocks, &host->reg->blkcnt);
  92 }
  93
  94 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
  95 {
  96         unsigned short mode;
  97         debug(" mmc_set_transfer_mode called\n");
  98         /*
  99          * TRNMOD
 100          * MUL1SIN0[5]  : Multi/Single Block Select
 101          * RD1WT0[4]    : Data Transfer Direction Select
 102          *      1 = read
 103          *      0 = write
 104          * ENACMD12[2]  : Auto CMD12 Enable
 105          * ENBLKCNT[1]  : Block Count Enable
 106          * ENDMA[0]     : DMA Enable
 107          */
 108         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 109                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 110
 111         if (data->blocks > 1)
 112                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 113
 114         if (data->flags & MMC_DATA_READ)
 115                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 116
 117         writew(mode, &host->reg->trnmod);
 118 }
 119
 120 static int mmc_wait_inhibit(struct mmc_host *host,
 121                             struct mmc_cmd *cmd,
 122                             struct mmc_data *data,
 123                             unsigned int timeout)
 124 {
 125         /*
 126          * PRNSTS
 127          * CMDINHDAT[1] : Command Inhibit (DAT)
 128          * CMDINHCMD[0] : Command Inhibit (CMD)
 129          */
 130         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 131
 132         /*
 133          * We shouldn't wait for data inhibit for stop commands, even
 134          * though they might use busy signaling
 135          */
 136         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 137                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 138
 139         while (readl(&host->reg->prnsts) & mask) {
 140                 if (timeout == 0) {
 141                         printf("%s: timeout error\n", __func__);
 142                         return -1;
 143                 }
 144                 timeout--;
 145                 udelay(1000);
 146         }
 147
 148         return 0;
 149 }
 150
 151 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 152                         struct mmc_data *data)
 153 {
 154         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 155         int flags, i;
 156         int result;
 157         unsigned int mask;
 158         unsigned int retry = 0x100000;
 159         debug(" mmc_send_cmd called\n");
 160
 161         result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
 162
 163         if (result < 0)
 164                 return result;
 165
 166         if (data)
 167                 mmc_prepare_data(host, data);
 168
 169         debug("cmd->arg: %08x\n", cmd->cmdarg);
 170         writel(cmd->cmdarg, &host->reg->argument);
 171
 172         if (data)
 173                 mmc_set_transfer_mode(host, data);
 174
 175         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 176                 return -1;
 177
 178         /*
 179          * CMDREG
 180          * CMDIDX[13:8] : Command index
 181          * DATAPRNT[5]  : Data Present Select
 182          * ENCMDIDX[4]  : Command Index Check Enable
 183          * ENCMDCRC[3]  : Command CRC Check Enable
 184          * RSPTYP[1:0]
 185          *      00 = No Response
 186          *      01 = Length 136
 187          *      10 = Length 48
 188          *      11 = Length 48 Check busy after response
 189          */
 190         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 191                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 192         else if (cmd->resp_type & MMC_RSP_136)
 193                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 194         else if (cmd->resp_type & MMC_RSP_BUSY)
 195                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 196         else
 197                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 198
 199         if (cmd->resp_type & MMC_RSP_CRC)
 200                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 201         if (cmd->resp_type & MMC_RSP_OPCODE)
 202                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 203         if (data)
 204                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 205
 206         debug("cmd: %d\n", cmd->cmdidx);
 207
 208         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
 209
 210         for (i = 0; i < retry; i++) {
 211                 mask = readl(&host->reg->norintsts);
 212                 /* Command Complete */
 213                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 214                         if (!data)
 215                                 writel(mask, &host->reg->norintsts);
 216                         break;
 217                 }
 218         }
 219
 220         if (i == retry) {
 221                 printf("%s: waiting for status update\n", __func__);
 222                 return TIMEOUT;
 223         }
 224
 225         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 226                 /* Timeout Error */
 227                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 228                 return TIMEOUT;
 229         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 230                 /* Error Interrupt */
 231                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 232                 return -1;
 233         }
 234
 235         if (cmd->resp_type & MMC_RSP_PRESENT) {
 236                 if (cmd->resp_type & MMC_RSP_136) {
 237                         /* CRC is stripped so we need to do some shifting. */
 238                         for (i = 0; i < 4; i++) {
 239                                 unsigned int offset =
 240                                         (unsigned int)(&host->reg->rspreg3 - i);
 241                                 cmd->response[i] = readl(offset) << 8;
 242
 243                                 if (i != 3) {
 244                                         cmd->response[i] |=
 245                                                 readb(offset - 1);
 246                                 }
 247                                 debug("cmd->resp[%d]: %08x\n",
 248                                                 i, cmd->response[i]);
 249                         }
 250                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 251                         for (i = 0; i < retry; i++) {
 252                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 253                                 if (readl(&host->reg->prnsts)
 254                                         & (1 << 20))    /* DAT[0] */
 255                                         break;
 256                         }
 257
 258                         if (i == retry) {
 259                                 printf("%s: card is still busy\n", __func__);
 260                                 return TIMEOUT;
 261                         }
 262
 263                         cmd->response[0] = readl(&host->reg->rspreg0);
 264                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 265                 } else {
 266                         cmd->response[0] = readl(&host->reg->rspreg0);
 267                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 268                 }
 269         }
 270
 271         if (data) {
 272                 unsigned long   start = get_timer(0);
 273
 274                 while (1) {
 275                         mask = readl(&host->reg->norintsts);
 276
 277                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 278                                 /* Error Interrupt */
 279                                 writel(mask, &host->reg->norintsts);
 280                                 printf("%s: error during transfer: 0x%08x\n",
 281                                                 __func__, mask);
 282                                 return -1;
 283                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 284                                 /*
 285                                  * DMA Interrupt, restart the transfer where
 286                                  * it was interrupted.
 287                                  */
 288                                 unsigned int address = readl(&host->reg->sysad);
 289
 290                                 debug("DMA end\n");
 291                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 292                                        &host->reg->norintsts);
 293                                 writel(address, &host->reg->sysad);
 294                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 295                                 /* Transfer Complete */
 296                                 debug("r/w is done\n");
 297                                 break;
 298                         } else if (get_timer(start) > 2000UL) {
 299                                 writel(mask, &host->reg->norintsts);
 300                                 printf("%s: MMC Timeout\n"
 301                                        "    Interrupt status        0x%08x\n"
 302                                        "    Interrupt status enable 0x%08x\n"
 303                                        "    Interrupt signal enable 0x%08x\n"
 304                                        "    Present status          0x%08x\n",
 305                                        __func__, mask,
 306                                        readl(&host->reg->norintstsen),
 307                                        readl(&host->reg->norintsigen),
 308                                        readl(&host->reg->prnsts));
 309                                 return -1;
 310                         }
 311                 }
 312                 writel(mask, &host->reg->norintsts);
 313         }
 314
 315         udelay(1000);
 316         return 0;
 317 }
 318
 319 static void mmc_change_clock(struct mmc_host *host, uint clock)
 320 {
 321         int div;
 322         unsigned short clk;
 323         unsigned long timeout;
 324
 325         debug(" mmc_change_clock called\n");
 326
 327         /*
 328          * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
 329          * PLLP_OUT0
 330          */
 331         if (clock == 0)
 332                 goto out;
 333         clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 334                                     &div);
 335         debug("div = %d\n", div);
 336
 337         writew(0, &host->reg->clkcon);
 338
 339         /*
 340          * CLKCON
 341          * SELFREQ[15:8]        : base clock divided by value
 342          * ENSDCLK[2]           : SD Clock Enable
 343          * STBLINTCLK[1]        : Internal Clock Stable
 344          * ENINTCLK[0]          : Internal Clock Enable
 345          */
 346         div >>= 1;
 347         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 348                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 349         writew(clk, &host->reg->clkcon);
 350
 351         /* Wait max 10 ms */
 352         timeout = 10;
 353         while (!(readw(&host->reg->clkcon) &
 354                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 355                 if (timeout == 0) {
 356                         printf("%s: timeout error\n", __func__);
 357                         return;
 358                 }
 359                 timeout--;
 360                 udelay(1000);
 361         }
 362
 363         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 364         writew(clk, &host->reg->clkcon);
 365
 366         debug("mmc_change_clock: clkcon = %08X\n", clk);
 367
 368 out:
 369         host->clock = clock;
 370 }
 371
 372 static void mmc_set_ios(struct mmc *mmc)
 373 {
 374         struct mmc_host *host = mmc->priv;
 375         unsigned char ctrl;
 376         debug(" mmc_set_ios called\n");
 377
 378         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 379
 380         /* Change clock first */
 381         mmc_change_clock(host, mmc->clock);
 382
 383         ctrl = readb(&host->reg->hostctl);
 384
 385         /*
 386          * WIDE8[5]
 387          * 0 = Depend on WIDE4
 388          * 1 = 8-bit mode
 389          * WIDE4[1]
 390          * 1 = 4-bit mode
 391          * 0 = 1-bit mode
 392          */
 393         if (mmc->bus_width == 8)
 394                 ctrl |= (1 << 5);
 395         else if (mmc->bus_width == 4)
 396                 ctrl |= (1 << 1);
 397         else
 398                 ctrl &= ~(1 << 1);
 399
 400         writeb(ctrl, &host->reg->hostctl);
 401         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 402 }
 403
 404 static void mmc_reset(struct mmc_host *host)
 405 {
 406         unsigned int timeout;
 407         debug(" mmc_reset called\n");
 408
 409         /*
 410          * RSTALL[0] : Software reset for all
 411          * 1 = reset
 412          * 0 = work
 413          */
 414         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
 415
 416         host->clock = 0;
 417
 418         /* Wait max 100 ms */
 419         timeout = 100;
 420
 421         /* hw clears the bit when it's done */
 422         while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 423                 if (timeout == 0) {
 424                         printf("%s: timeout error\n", __func__);
 425                         return;
 426                 }
 427                 timeout--;
 428                 udelay(1000);
 429         }
 430 }
 431
 432 static int mmc_core_init(struct mmc *mmc)
 433 {
 434         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 435         unsigned int mask;
 436         debug(" mmc_core_init called\n");
 437
 438         mmc_reset(host);
 439
 440         host->version = readw(&host->reg->hcver);
 441         debug("host version = %x\n", host->version);
 442
 443         /* mask all */
 444         writel(0xffffffff, &host->reg->norintstsen);
 445         writel(0xffffffff, &host->reg->norintsigen);
 446
 447         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
 448         /*
 449          * NORMAL Interrupt Status Enable Register init
 450          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 451          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 452          * [3] ENSTADMAINT   : DMA boundary interrupt
 453          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 454          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 455         */
 456         mask = readl(&host->reg->norintstsen);
 457         mask &= ~(0xffff);
 458         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 459                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 460                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 461                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 462                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 463         writel(mask, &host->reg->norintstsen);
 464
 465         /*
 466          * NORMAL Interrupt Signal Enable Register init
 467          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 468          */
 469         mask = readl(&host->reg->norintsigen);
 470         mask &= ~(0xffff);
 471         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 472         writel(mask, &host->reg->norintsigen);
 473
 474         return 0;
 475 }
 476
 477 int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 478 {
 479         struct mmc_host *host;
 480         char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
 481         struct mmc *mmc;
 482
 483         debug(" tegra2_mmc_init: index %d, bus width %d "
 484                 "pwr_gpio %d cd_gpio %d\n",
 485                 dev_index, bus_width, pwr_gpio, cd_gpio);
 486
 487         host = &mmc_host[dev_index];
 488
 489         host->clock = 0;
 490         host->pwr_gpio = pwr_gpio;
 491         host->cd_gpio = cd_gpio;
 492         tegra2_get_setup(host, dev_index);
 493
 494         clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 495
 496         if (host->pwr_gpio >= 0) {
 497                 sprintf(gpusage, "SD/MMC%d PWR", dev_index);
 498                 gpio_request(host->pwr_gpio, gpusage);
 499                 gpio_direction_output(host->pwr_gpio, 1);
 500         }
 501
 502         if (host->cd_gpio >= 0) {
 503                 sprintf(gpusage, "SD/MMC%d CD", dev_index);
 504                 gpio_request(host->cd_gpio, gpusage);
 505                 gpio_direction_input(host->cd_gpio);
 506         }
 507
 508         mmc = &mmc_dev[dev_index];
 509
 510         sprintf(mmc->name, "Tegra2 SD/MMC");
 511         mmc->priv = host;
 512         mmc->send_cmd = mmc_send_cmd;
 513         mmc->set_ios = mmc_set_ios;
 514         mmc->init = mmc_core_init;
 515
 516         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 517         if (bus_width == 8)
 518                 mmc->host_caps = MMC_MODE_8BIT;
 519         else
 520                 mmc->host_caps = MMC_MODE_4BIT;
 521         mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 522
 523         /*
 524          * min freq is for card identification, and is the highest
 525          *  low-speed SDIO card frequency (actually 400KHz)
 526          * max freq is highest HS eMMC clock as per the SD/MMC spec
 527          *  (actually 52MHz)
 528          * Both of these are the closest equivalents w/216MHz source
 529          *  clock and Tegra2 SDMMC divisors.
 530          */
 531         mmc->f_min = 375000;
 532         mmc->f_max = 48000000;
 533
 534         mmc_register(mmc);
 535
 536         return 0;
 537 }
 538
 539 /* this is a weak define that we are overriding */
 540 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 541 {
 542         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 543
 544         debug("board_mmc_getcd called\n");
 545
 546         *cd = 1; /* Assume card is inserted, or eMMC */
 547
 548         if (IS_SD(mmc)) {
 549                 if (host->cd_gpio >= 0) {
 550                         if (gpio_get_value(host->cd_gpio))
 551                                 *cd = 0;
 552                 }
 553         }
 554
 555         return 0;
 556 }