1 menu "RAM/ROM/Flash chip drivers"
4 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
8 The Common Flash Interface specification was developed by Intel,
9 AMD and other flash manufactures that provides a universal method
10 for probing the capabilities of flash devices. If you wish to
11 support any device that is CFI-compliant, you need to enable this
12 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
13 for more information on CFI.
16 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
19 This option enables JEDEC-style probing of flash chips which are not
20 compatible with the Common Flash Interface, but will use the common
21 CFI-targetted flash drivers for any chips which are identified which
22 are in fact compatible in all but the probe method. This actually
23 covers most AMD/Fujitsu-compatible chips and also non-CFI
31 config MTD_CFI_ADV_OPTIONS
32 bool "Flash chip driver advanced configuration options"
34 If you need to specify a specific endianness for access to flash
35 chips, or if you wish to reduce the size of the kernel by including
36 support for only specific arrangements of flash chips, say 'Y'. This
37 option does not directly affect the code, but will enable other
38 configuration options which allow you to do so.
42 if MTD_CFI_ADV_OPTIONS
45 prompt "Flash cmd/query data swapping"
46 default MTD_CFI_NOSWAP
51 This option defines the way in which the CPU attempts to arrange
52 data bits when writing the 'magic' commands to the chips. Saying
53 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
54 enabled, means that the CPU will not do any swapping; the chips
55 are expected to be wired to the CPU in 'host-endian' form.
56 Specific arrangements are possible with the BIG_ENDIAN_BYTE and
57 LITTLE_ENDIAN_BYTE, if the bytes are reversed.
59 If you have a LART, on which the data (and address) lines were
60 connected in a fashion which ensured that the nets were as short
61 as possible, resulting in a bit-shuffling which seems utterly
62 random to the untrained eye, you need the LART_ENDIAN_BYTE option.
64 Yes, there really exists something sicker than PDP-endian :)
66 config MTD_CFI_BE_BYTE_SWAP
67 bool "BIG_ENDIAN_BYTE"
69 config MTD_CFI_LE_BYTE_SWAP
70 bool "LITTLE_ENDIAN_BYTE"
74 config MTD_CFI_GEOMETRY
75 bool "Specific CFI Flash geometry selection"
77 This option does not affect the code directly, but will enable
78 some other configuration options which would allow you to reduce
79 the size of the kernel by including support for only certain
80 arrangements of CFI chips. If unsure, say 'N' and all options
81 which are supported by the current code will be enabled.
85 config MTD_MAP_BANK_WIDTH_1
86 bool "Support 8-bit buswidth"
89 If you wish to support CFI devices on a physical bus which is
92 config MTD_MAP_BANK_WIDTH_2
93 bool "Support 16-bit buswidth"
96 If you wish to support CFI devices on a physical bus which is
97 16 bits wide, say 'Y'.
99 config MTD_MAP_BANK_WIDTH_4
100 bool "Support 32-bit buswidth"
103 If you wish to support CFI devices on a physical bus which is
104 32 bits wide, say 'Y'.
106 config MTD_MAP_BANK_WIDTH_8
107 bool "Support 64-bit buswidth"
109 If you wish to support CFI devices on a physical bus which is
110 64 bits wide, say 'Y'.
112 config MTD_MAP_BANK_WIDTH_16
113 bool "Support 128-bit buswidth"
115 If you wish to support CFI devices on a physical bus which is
116 128 bits wide, say 'Y'.
118 config MTD_MAP_BANK_WIDTH_32
119 bool "Support 256-bit buswidth"
121 If you wish to support CFI devices on a physical bus which is
122 256 bits wide, say 'Y'.
125 bool "Support 1-chip flash interleave"
128 If your flash chips are not interleaved - i.e. you only have one
129 flash chip addressed by each bus cycle, then say 'Y'.
132 bool "Support 2-chip flash interleave"
135 If your flash chips are interleaved in pairs - i.e. you have two
136 flash chips addressed by each bus cycle, then say 'Y'.
139 bool "Support 4-chip flash interleave"
141 If your flash chips are interleaved in fours - i.e. you have four
142 flash chips addressed by each bus cycle, then say 'Y'.
145 bool "Support 8-chip flash interleave"
147 If your flash chips are interleaved in eights - i.e. you have eight
148 flash chips addressed by each bus cycle, then say 'Y'.
150 endif # MTD_CFI_GEOMETRY
153 bool "Protection Registers aka one-time programmable (OTP) bits"
156 This enables support for reading, writing and locking so called
157 "Protection Registers" present on some flash chips.
158 A subset of them are pre-programmed at the factory with a
159 unique set of values. The rest is user-programmable.
161 The user-programmable Protection Registers contain one-time
162 programmable (OTP) bits; when programmed, register bits cannot be
163 erased. Each Protection Register can be accessed multiple times to
164 program individual bits, as long as the register remains unlocked.
166 Each Protection Register has an associated Lock Register bit. When a
167 Lock Register bit is programmed, the associated Protection Register
168 can only be read; it can no longer be programmed. Additionally,
169 because the Lock Register bits themselves are OTP, when programmed,
170 Lock Register bits cannot be erased. Therefore, when a Protection
171 Register is locked, it cannot be unlocked.
173 This feature should therefore be used with extreme care. Any mistake
174 in the programming of OTP bits will waste them.
176 endif # MTD_CFI_ADV_OPTIONS
178 config MTD_CFI_INTELEXT
179 tristate "Support for Intel/Sharp flash chips"
182 The Common Flash Interface defines a number of different command
183 sets which a CFI-compliant chip may claim to implement. This code
184 provides support for one of those command sets, used on Intel
185 StrataFlash and other parts.
187 config MTD_CFI_AMDSTD
188 tristate "Support for AMD/Fujitsu/Spansion flash chips"
191 The Common Flash Interface defines a number of different command
192 sets which a CFI-compliant chip may claim to implement. This code
193 provides support for one of those command sets, used on chips
194 including the AMD Am29LV320.
197 tristate "Support for ST (Advanced Architecture) flash chips"
200 The Common Flash Interface defines a number of different command
201 sets which a CFI-compliant chip may claim to implement. This code
202 provides support for one of those command sets.
204 endif # MTD_GEN_PROBE
210 tristate "Support for RAM chips in bus mapping"
212 This option enables basic support for RAM chips accessed through
213 a bus mapping driver.
216 tristate "Support for ROM chips in bus mapping"
218 This option enables basic support for ROM chips accessed through
219 a bus mapping driver.
222 tristate "Support for absent chips in bus mapping"
224 This option enables support for a dummy probing driver used to
225 allocated placeholder MTD devices on systems that have socketed
226 or removable media. Use of this driver as a fallback chip probe
227 preserves the expected registration order of MTD device nodes on
228 the system regardless of media presence. Device nodes created
229 with this driver will return -ENODEV upon access.
232 bool "XIP aware MTD support"
233 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
234 default y if XIP_KERNEL
236 This allows MTD support to work with flash memory which is also
237 used for XIP purposes. If you're not sure what this is all about