2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
29 #include <asm/byteorder.h>
31 #include <linux/errno.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/reboot.h>
36 #include <linux/mtd/map.h>
37 #include <linux/mtd/mtd.h>
38 #include <linux/mtd/cfi.h>
39 #include <linux/mtd/xip.h>
41 #define AMD_BOOTLOC_BUG
42 #define FORCE_WORD_WRITE 0
44 #define MAX_WORD_RETRIES 3
46 #define SST49LF004B 0x0060
47 #define SST49LF040B 0x0050
48 #define SST49LF008A 0x005a
49 #define AT49BV6416 0x00d6
51 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
52 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
53 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
55 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
56 static void cfi_amdstd_sync (struct mtd_info *);
57 static int cfi_amdstd_suspend (struct mtd_info *);
58 static void cfi_amdstd_resume (struct mtd_info *);
59 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
60 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
62 static void cfi_amdstd_destroy(struct mtd_info *);
64 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
65 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
67 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
68 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
71 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
72 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
74 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
75 .probe = NULL, /* Not usable directly */
76 .destroy = cfi_amdstd_destroy,
77 .name = "cfi_cmdset_0002",
82 /* #define DEBUG_CFI_FEATURES */
85 #ifdef DEBUG_CFI_FEATURES
86 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
88 const char* erase_suspend[3] = {
89 "Not supported", "Read only", "Read/write"
91 const char* top_bottom[6] = {
92 "No WP", "8x8KiB sectors at top & bottom, no WP",
93 "Bottom boot", "Top boot",
94 "Uniform, Bottom WP", "Uniform, Top WP"
97 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
98 printk(" Address sensitive unlock: %s\n",
99 (extp->SiliconRevision & 1) ? "Not required" : "Required");
101 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
102 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
104 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
106 if (extp->BlkProt == 0)
107 printk(" Block protection: Not supported\n");
109 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
112 printk(" Temporary block unprotect: %s\n",
113 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
114 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
115 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
116 printk(" Burst mode: %s\n",
117 extp->BurstMode ? "Supported" : "Not supported");
118 if (extp->PageMode == 0)
119 printk(" Page mode: Not supported\n");
121 printk(" Page mode: %d word page\n", extp->PageMode << 2);
123 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
124 extp->VppMin >> 4, extp->VppMin & 0xf);
125 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
126 extp->VppMax >> 4, extp->VppMax & 0xf);
128 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
129 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
131 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
135 #ifdef AMD_BOOTLOC_BUG
136 /* Wheee. Bring me the head of someone at AMD. */
137 static void fixup_amd_bootblock(struct mtd_info *mtd)
139 struct map_info *map = mtd->priv;
140 struct cfi_private *cfi = map->fldrv_priv;
141 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
142 __u8 major = extp->MajorVersion;
143 __u8 minor = extp->MinorVersion;
145 if (((major << 8) | minor) < 0x3131) {
146 /* CFI version 1.0 => don't trust bootloc */
148 DEBUG(MTD_DEBUG_LEVEL1,
149 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
150 map->name, cfi->mfr, cfi->id);
152 /* AFAICS all 29LV400 with a bottom boot block have a device ID
153 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
154 * These were badly detected as they have the 0x80 bit set
155 * so treat them as a special case.
157 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
159 /* Macronix added CFI to their 2nd generation
160 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
161 * Fujitsu, Spansion, EON, ESI and older Macronix)
164 * Therefore also check the manufacturer.
165 * This reduces the risk of false detection due to
166 * the 8-bit device ID.
168 (cfi->mfr == CFI_MFR_MACRONIX)) {
169 DEBUG(MTD_DEBUG_LEVEL1,
170 "%s: Macronix MX29LV400C with bottom boot block"
171 " detected\n", map->name);
172 extp->TopBottom = 2; /* bottom boot */
174 if (cfi->id & 0x80) {
175 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
176 extp->TopBottom = 3; /* top boot */
178 extp->TopBottom = 2; /* bottom boot */
181 DEBUG(MTD_DEBUG_LEVEL1,
182 "%s: AMD CFI PRI V%c.%c has no boot block field;"
183 " deduced %s from Device ID\n", map->name, major, minor,
184 extp->TopBottom == 2 ? "bottom" : "top");
189 static void fixup_use_write_buffers(struct mtd_info *mtd)
191 struct map_info *map = mtd->priv;
192 struct cfi_private *cfi = map->fldrv_priv;
193 if (cfi->cfiq->BufWriteTimeoutTyp) {
194 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
195 mtd->write = cfi_amdstd_write_buffers;
199 /* Atmel chips don't use the same PRI format as AMD chips */
200 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
202 struct map_info *map = mtd->priv;
203 struct cfi_private *cfi = map->fldrv_priv;
204 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
205 struct cfi_pri_atmel atmel_pri;
207 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
208 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
210 if (atmel_pri.Features & 0x02)
211 extp->EraseSuspend = 2;
213 /* Some chips got it backwards... */
214 if (cfi->id == AT49BV6416) {
215 if (atmel_pri.BottomBoot)
220 if (atmel_pri.BottomBoot)
226 /* burst write mode not supported */
227 cfi->cfiq->BufWriteTimeoutTyp = 0;
228 cfi->cfiq->BufWriteTimeoutMax = 0;
231 static void fixup_use_secsi(struct mtd_info *mtd)
233 /* Setup for chips with a secsi area */
234 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
235 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
238 static void fixup_use_erase_chip(struct mtd_info *mtd)
240 struct map_info *map = mtd->priv;
241 struct cfi_private *cfi = map->fldrv_priv;
242 if ((cfi->cfiq->NumEraseRegions == 1) &&
243 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
244 mtd->erase = cfi_amdstd_erase_chip;
250 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
253 static void fixup_use_atmel_lock(struct mtd_info *mtd)
255 mtd->lock = cfi_atmel_lock;
256 mtd->unlock = cfi_atmel_unlock;
257 mtd->flags |= MTD_POWERUP_LOCK;
260 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
262 struct map_info *map = mtd->priv;
263 struct cfi_private *cfi = map->fldrv_priv;
266 * These flashes report two seperate eraseblock regions based on the
267 * sector_erase-size and block_erase-size, although they both operate on the
268 * same memory. This is not allowed according to CFI, so we just pick the
271 cfi->cfiq->NumEraseRegions = 1;
274 static void fixup_sst39vf(struct mtd_info *mtd)
276 struct map_info *map = mtd->priv;
277 struct cfi_private *cfi = map->fldrv_priv;
279 fixup_old_sst_eraseregion(mtd);
281 cfi->addr_unlock1 = 0x5555;
282 cfi->addr_unlock2 = 0x2AAA;
285 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
287 struct map_info *map = mtd->priv;
288 struct cfi_private *cfi = map->fldrv_priv;
290 fixup_old_sst_eraseregion(mtd);
292 cfi->addr_unlock1 = 0x555;
293 cfi->addr_unlock2 = 0x2AA;
295 cfi->sector_erase_cmd = CMD(0x50);
298 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
300 struct map_info *map = mtd->priv;
301 struct cfi_private *cfi = map->fldrv_priv;
303 fixup_sst39vf_rev_b(mtd);
306 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
307 * it should report a size of 8KBytes (0x0020*256).
309 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
310 pr_warning("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", mtd->name);
313 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
315 struct map_info *map = mtd->priv;
316 struct cfi_private *cfi = map->fldrv_priv;
318 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
319 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
320 pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name);
324 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
326 struct map_info *map = mtd->priv;
327 struct cfi_private *cfi = map->fldrv_priv;
329 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
330 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
331 pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name);
335 /* Used to fix CFI-Tables of chips without Extended Query Tables */
336 static struct cfi_fixup cfi_nopri_fixup_table[] = {
337 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
338 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
339 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
340 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
341 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
342 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
343 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
344 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
348 static struct cfi_fixup cfi_fixup_table[] = {
349 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
350 #ifdef AMD_BOOTLOC_BUG
351 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
352 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
354 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
355 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
356 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
357 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
358 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
359 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
360 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
361 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
362 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
363 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
364 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
365 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
366 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
367 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
368 #if !FORCE_WORD_WRITE
369 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
373 static struct cfi_fixup jedec_fixup_table[] = {
374 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
375 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
376 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
380 static struct cfi_fixup fixup_table[] = {
381 /* The CFI vendor ids and the JEDEC vendor IDs appear
382 * to be common. It is like the devices id's are as
383 * well. This table is to pick all cases where
384 * we know that is the case.
386 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
387 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
392 static void cfi_fixup_major_minor(struct cfi_private *cfi,
393 struct cfi_pri_amdstd *extp)
395 if (cfi->mfr == CFI_MFR_SAMSUNG) {
396 if (extp->MajorVersion == '0' && extp->MinorVersion == '0') {
398 * Samsung K8P2815UQB and K8D6x16UxM chips
399 * report major=0 / minor=0.
401 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
402 " Extended Query version to 1.%c\n",
404 extp->MajorVersion = '1';
409 * SST 38VF640x chips report major=0xFF / minor=0xFF.
411 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
412 extp->MajorVersion = '1';
413 extp->MinorVersion = '0';
417 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
419 struct cfi_private *cfi = map->fldrv_priv;
420 struct mtd_info *mtd;
423 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
425 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
429 mtd->type = MTD_NORFLASH;
431 /* Fill in the default mtd operations */
432 mtd->erase = cfi_amdstd_erase_varsize;
433 mtd->write = cfi_amdstd_write_words;
434 mtd->read = cfi_amdstd_read;
435 mtd->sync = cfi_amdstd_sync;
436 mtd->suspend = cfi_amdstd_suspend;
437 mtd->resume = cfi_amdstd_resume;
438 mtd->flags = MTD_CAP_NORFLASH;
439 mtd->name = map->name;
442 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
444 if (cfi->cfi_mode==CFI_MODE_CFI){
445 unsigned char bootloc;
446 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
447 struct cfi_pri_amdstd *extp;
449 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
452 * It's a real CFI chip, not one for which the probe
453 * routine faked a CFI structure.
455 cfi_fixup_major_minor(cfi, extp);
458 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4
459 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
460 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
461 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
463 if (extp->MajorVersion != '1' ||
464 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '4'))) {
465 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
466 "version %c.%c (%#02x/%#02x).\n",
467 extp->MajorVersion, extp->MinorVersion,
468 extp->MajorVersion, extp->MinorVersion);
474 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
475 extp->MajorVersion, extp->MinorVersion);
477 /* Install our own private info structure */
478 cfi->cmdset_priv = extp;
480 /* Apply cfi device specific fixups */
481 cfi_fixup(mtd, cfi_fixup_table);
483 #ifdef DEBUG_CFI_FEATURES
484 /* Tell the user about it in lots of lovely detail */
485 cfi_tell_features(extp);
488 bootloc = extp->TopBottom;
489 if ((bootloc < 2) || (bootloc > 5)) {
490 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
491 "bank location (%d). Assuming bottom.\n",
496 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
497 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
499 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
500 int j = (cfi->cfiq->NumEraseRegions-1)-i;
503 swap = cfi->cfiq->EraseRegionInfo[i];
504 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
505 cfi->cfiq->EraseRegionInfo[j] = swap;
508 /* Set the default CFI lock/unlock addresses */
509 cfi->addr_unlock1 = 0x555;
510 cfi->addr_unlock2 = 0x2aa;
512 cfi_fixup(mtd, cfi_nopri_fixup_table);
514 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
520 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
521 /* Apply jedec specific fixups */
522 cfi_fixup(mtd, jedec_fixup_table);
524 /* Apply generic fixups */
525 cfi_fixup(mtd, fixup_table);
527 for (i=0; i< cfi->numchips; i++) {
528 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
529 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
530 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
531 cfi->chips[i].ref_point_counter = 0;
532 init_waitqueue_head(&(cfi->chips[i].wq));
535 map->fldrv = &cfi_amdstd_chipdrv;
537 return cfi_amdstd_setup(mtd);
539 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
540 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
541 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
542 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
543 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
545 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
547 struct map_info *map = mtd->priv;
548 struct cfi_private *cfi = map->fldrv_priv;
549 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
550 unsigned long offset = 0;
553 printk(KERN_NOTICE "number of %s chips: %d\n",
554 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
555 /* Select the correct geometry setup */
556 mtd->size = devsize * cfi->numchips;
558 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
559 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
560 * mtd->numeraseregions, GFP_KERNEL);
561 if (!mtd->eraseregions) {
562 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
566 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
567 unsigned long ernum, ersize;
568 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
569 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
571 if (mtd->erasesize < ersize) {
572 mtd->erasesize = ersize;
574 for (j=0; j<cfi->numchips; j++) {
575 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
576 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
577 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
579 offset += (ersize * ernum);
581 if (offset != devsize) {
583 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
587 __module_get(THIS_MODULE);
588 register_reboot_notifier(&mtd->reboot_notifier);
592 kfree(mtd->eraseregions);
594 kfree(cfi->cmdset_priv);
600 * Return true if the chip is ready.
602 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
603 * non-suspended sector) and is indicated by no toggle bits toggling.
605 * Note that anything more complicated than checking if no bits are toggling
606 * (including checking DQ5 for an error status) is tricky to get working
607 * correctly and is therefore not done (particulary with interleaved chips
608 * as each chip must be checked independantly of the others).
610 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
614 d = map_read(map, addr);
615 t = map_read(map, addr);
617 return map_word_equal(map, d, t);
621 * Return true if the chip is ready and has the correct value.
623 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
624 * non-suspended sector) and it is indicated by no bits toggling.
626 * Error are indicated by toggling bits or bits held with the wrong value,
627 * or with bits toggling.
629 * Note that anything more complicated than checking if no bits are toggling
630 * (including checking DQ5 for an error status) is tricky to get working
631 * correctly and is therefore not done (particulary with interleaved chips
632 * as each chip must be checked independantly of the others).
635 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
639 oldd = map_read(map, addr);
640 curd = map_read(map, addr);
642 return map_word_equal(map, oldd, curd) &&
643 map_word_equal(map, curd, expected);
646 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
648 DECLARE_WAITQUEUE(wait, current);
649 struct cfi_private *cfi = map->fldrv_priv;
651 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
654 timeo = jiffies + HZ;
656 switch (chip->state) {
660 if (chip_ready(map, adr))
663 if (time_after(jiffies, timeo)) {
664 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
667 mutex_unlock(&chip->mutex);
669 mutex_lock(&chip->mutex);
670 /* Someone else might have been playing with it. */
680 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
681 !(mode == FL_READY || mode == FL_POINT ||
682 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
685 /* We could check to see if we're trying to access the sector
686 * that is currently being erased. However, no user will try
687 * anything like that so we just wait for the timeout. */
690 /* It's harmless to issue the Erase-Suspend and Erase-Resume
691 * commands when the erase algorithm isn't in progress. */
692 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
693 chip->oldstate = FL_ERASING;
694 chip->state = FL_ERASE_SUSPENDING;
695 chip->erase_suspended = 1;
697 if (chip_ready(map, adr))
700 if (time_after(jiffies, timeo)) {
701 /* Should have suspended the erase by now.
702 * Send an Erase-Resume command as either
703 * there was an error (so leave the erase
704 * routine to recover from it) or we trying to
705 * use the erase-in-progress sector. */
706 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
707 chip->state = FL_ERASING;
708 chip->oldstate = FL_READY;
709 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
713 mutex_unlock(&chip->mutex);
715 mutex_lock(&chip->mutex);
716 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
717 So we can just loop here. */
719 chip->state = FL_READY;
722 case FL_XIP_WHILE_ERASING:
723 if (mode != FL_READY && mode != FL_POINT &&
724 (!cfip || !(cfip->EraseSuspend&2)))
726 chip->oldstate = chip->state;
727 chip->state = FL_READY;
731 /* The machine is rebooting */
735 /* Only if there's no operation suspended... */
736 if (mode == FL_READY && chip->oldstate == FL_READY)
741 set_current_state(TASK_UNINTERRUPTIBLE);
742 add_wait_queue(&chip->wq, &wait);
743 mutex_unlock(&chip->mutex);
745 remove_wait_queue(&chip->wq, &wait);
746 mutex_lock(&chip->mutex);
752 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
754 struct cfi_private *cfi = map->fldrv_priv;
756 switch(chip->oldstate) {
758 chip->state = chip->oldstate;
759 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
760 chip->oldstate = FL_READY;
761 chip->state = FL_ERASING;
764 case FL_XIP_WHILE_ERASING:
765 chip->state = chip->oldstate;
766 chip->oldstate = FL_READY;
771 /* We should really make set_vpp() count, rather than doing this */
775 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
780 #ifdef CONFIG_MTD_XIP
783 * No interrupt what so ever can be serviced while the flash isn't in array
784 * mode. This is ensured by the xip_disable() and xip_enable() functions
785 * enclosing any code path where the flash is known not to be in array mode.
786 * And within a XIP disabled code path, only functions marked with __xipram
787 * may be called and nothing else (it's a good thing to inspect generated
788 * assembly to make sure inline functions were actually inlined and that gcc
789 * didn't emit calls to its own support functions). Also configuring MTD CFI
790 * support to a single buswidth and a single interleave is also recommended.
793 static void xip_disable(struct map_info *map, struct flchip *chip,
796 /* TODO: chips with no XIP use should ignore and return */
797 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
801 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
804 struct cfi_private *cfi = map->fldrv_priv;
806 if (chip->state != FL_POINT && chip->state != FL_READY) {
807 map_write(map, CMD(0xf0), adr);
808 chip->state = FL_READY;
810 (void) map_read(map, adr);
816 * When a delay is required for the flash operation to complete, the
817 * xip_udelay() function is polling for both the given timeout and pending
818 * (but still masked) hardware interrupts. Whenever there is an interrupt
819 * pending then the flash erase operation is suspended, array mode restored
820 * and interrupts unmasked. Task scheduling might also happen at that
821 * point. The CPU eventually returns from the interrupt or the call to
822 * schedule() and the suspended flash operation is resumed for the remaining
823 * of the delay period.
825 * Warning: this function _will_ fool interrupt latency tracing tools.
828 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
829 unsigned long adr, int usec)
831 struct cfi_private *cfi = map->fldrv_priv;
832 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
833 map_word status, OK = CMD(0x80);
834 unsigned long suspended, start = xip_currtime();
839 if (xip_irqpending() && extp &&
840 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
841 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
843 * Let's suspend the erase operation when supported.
844 * Note that we currently don't try to suspend
845 * interleaved chips if there is already another
846 * operation suspended (imagine what happens
847 * when one chip was already done with the current
848 * operation while another chip suspended it, then
849 * we resume the whole thing at once). Yes, it
852 map_write(map, CMD(0xb0), adr);
853 usec -= xip_elapsed_since(start);
854 suspended = xip_currtime();
856 if (xip_elapsed_since(suspended) > 100000) {
858 * The chip doesn't want to suspend
859 * after waiting for 100 msecs.
860 * This is a critical error but there
861 * is not much we can do here.
865 status = map_read(map, adr);
866 } while (!map_word_andequal(map, status, OK, OK));
868 /* Suspend succeeded */
869 oldstate = chip->state;
870 if (!map_word_bitsset(map, status, CMD(0x40)))
872 chip->state = FL_XIP_WHILE_ERASING;
873 chip->erase_suspended = 1;
874 map_write(map, CMD(0xf0), adr);
875 (void) map_read(map, adr);
878 mutex_unlock(&chip->mutex);
883 * We're back. However someone else might have
884 * decided to go write to the chip if we are in
885 * a suspended erase state. If so let's wait
888 mutex_lock(&chip->mutex);
889 while (chip->state != FL_XIP_WHILE_ERASING) {
890 DECLARE_WAITQUEUE(wait, current);
891 set_current_state(TASK_UNINTERRUPTIBLE);
892 add_wait_queue(&chip->wq, &wait);
893 mutex_unlock(&chip->mutex);
895 remove_wait_queue(&chip->wq, &wait);
896 mutex_lock(&chip->mutex);
898 /* Disallow XIP again */
901 /* Resume the write or erase operation */
902 map_write(map, cfi->sector_erase_cmd, adr);
903 chip->state = oldstate;
904 start = xip_currtime();
905 } else if (usec >= 1000000/HZ) {
907 * Try to save on CPU power when waiting delay
908 * is at least a system timer tick period.
909 * No need to be extremely accurate here.
913 status = map_read(map, adr);
914 } while (!map_word_andequal(map, status, OK, OK)
915 && xip_elapsed_since(start) < usec);
918 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
921 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
922 * the flash is actively programming or erasing since we have to poll for
923 * the operation to complete anyway. We can't do that in a generic way with
924 * a XIP setup so do it before the actual flash operation in this case
925 * and stub it out from INVALIDATE_CACHE_UDELAY.
927 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
928 INVALIDATE_CACHED_RANGE(map, from, size)
930 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
931 UDELAY(map, chip, adr, usec)
936 * Activating this XIP support changes the way the code works a bit. For
937 * example the code to suspend the current process when concurrent access
938 * happens is never executed because xip_udelay() will always return with the
939 * same chip state as it was entered with. This is why there is no care for
940 * the presence of add_wait_queue() or schedule() calls from within a couple
941 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
942 * The queueing and scheduling are always happening within xip_udelay().
944 * Similarly, get_chip() and put_chip() just happen to always be executed
945 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
946 * is in array mode, therefore never executing many cases therein and not
947 * causing any problem with XIP.
952 #define xip_disable(map, chip, adr)
953 #define xip_enable(map, chip, adr)
954 #define XIP_INVAL_CACHED_RANGE(x...)
956 #define UDELAY(map, chip, adr, usec) \
958 mutex_unlock(&chip->mutex); \
960 mutex_lock(&chip->mutex); \
963 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
965 mutex_unlock(&chip->mutex); \
966 INVALIDATE_CACHED_RANGE(map, adr, len); \
968 mutex_lock(&chip->mutex); \
973 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
975 unsigned long cmd_addr;
976 struct cfi_private *cfi = map->fldrv_priv;
981 /* Ensure cmd read/writes are aligned. */
982 cmd_addr = adr & ~(map_bankwidth(map)-1);
984 mutex_lock(&chip->mutex);
985 ret = get_chip(map, chip, cmd_addr, FL_READY);
987 mutex_unlock(&chip->mutex);
991 if (chip->state != FL_POINT && chip->state != FL_READY) {
992 map_write(map, CMD(0xf0), cmd_addr);
993 chip->state = FL_READY;
996 map_copy_from(map, buf, adr, len);
998 put_chip(map, chip, cmd_addr);
1000 mutex_unlock(&chip->mutex);
1005 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1007 struct map_info *map = mtd->priv;
1008 struct cfi_private *cfi = map->fldrv_priv;
1013 /* ofs: offset within the first chip that the first read should start */
1015 chipnum = (from >> cfi->chipshift);
1016 ofs = from - (chipnum << cfi->chipshift);
1022 unsigned long thislen;
1024 if (chipnum >= cfi->numchips)
1027 if ((len + ofs -1) >> cfi->chipshift)
1028 thislen = (1<<cfi->chipshift) - ofs;
1032 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1047 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1049 DECLARE_WAITQUEUE(wait, current);
1050 unsigned long timeo = jiffies + HZ;
1051 struct cfi_private *cfi = map->fldrv_priv;
1054 mutex_lock(&chip->mutex);
1056 if (chip->state != FL_READY){
1057 set_current_state(TASK_UNINTERRUPTIBLE);
1058 add_wait_queue(&chip->wq, &wait);
1060 mutex_unlock(&chip->mutex);
1063 remove_wait_queue(&chip->wq, &wait);
1064 timeo = jiffies + HZ;
1071 chip->state = FL_READY;
1073 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1074 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1075 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1077 map_copy_from(map, buf, adr, len);
1079 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1080 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1081 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1082 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1085 mutex_unlock(&chip->mutex);
1090 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1092 struct map_info *map = mtd->priv;
1093 struct cfi_private *cfi = map->fldrv_priv;
1099 /* ofs: offset within the first chip that the first read should start */
1101 /* 8 secsi bytes per chip */
1109 unsigned long thislen;
1111 if (chipnum >= cfi->numchips)
1114 if ((len + ofs -1) >> 3)
1115 thislen = (1<<3) - ofs;
1119 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1134 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
1136 struct cfi_private *cfi = map->fldrv_priv;
1137 unsigned long timeo = jiffies + HZ;
1139 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1140 * have a max write time of a few hundreds usec). However, we should
1141 * use the maximum timeout value given by the chip at probe time
1142 * instead. Unfortunately, struct flchip does have a field for
1143 * maximum timeout, only for typical which can be far too short
1144 * depending of the conditions. The ' + 1' is to avoid having a
1145 * timeout of 0 jiffies if HZ is smaller than 1000.
1147 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1154 mutex_lock(&chip->mutex);
1155 ret = get_chip(map, chip, adr, FL_WRITING);
1157 mutex_unlock(&chip->mutex);
1161 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1162 __func__, adr, datum.x[0] );
1165 * Check for a NOP for the case when the datum to write is already
1166 * present - it saves time and works around buggy chips that corrupt
1167 * data at other locations when 0xff is written to a location that
1168 * already contains 0xff.
1170 oldd = map_read(map, adr);
1171 if (map_word_equal(map, oldd, datum)) {
1172 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1177 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1179 xip_disable(map, chip, adr);
1181 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1182 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1183 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1184 map_write(map, datum, adr);
1185 chip->state = FL_WRITING;
1187 INVALIDATE_CACHE_UDELAY(map, chip,
1188 adr, map_bankwidth(map),
1189 chip->word_write_time);
1191 /* See comment above for timeout value. */
1192 timeo = jiffies + uWriteTimeout;
1194 if (chip->state != FL_WRITING) {
1195 /* Someone's suspended the write. Sleep */
1196 DECLARE_WAITQUEUE(wait, current);
1198 set_current_state(TASK_UNINTERRUPTIBLE);
1199 add_wait_queue(&chip->wq, &wait);
1200 mutex_unlock(&chip->mutex);
1202 remove_wait_queue(&chip->wq, &wait);
1203 timeo = jiffies + (HZ / 2); /* FIXME */
1204 mutex_lock(&chip->mutex);
1208 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1209 xip_enable(map, chip, adr);
1210 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1211 xip_disable(map, chip, adr);
1215 if (chip_ready(map, adr))
1218 /* Latency issues. Drop the lock, wait a while and retry */
1219 UDELAY(map, chip, adr, 1);
1221 /* Did we succeed? */
1222 if (!chip_good(map, adr, datum)) {
1223 /* reset on all failures. */
1224 map_write( map, CMD(0xF0), chip->start );
1225 /* FIXME - should have reset delay before continuing */
1227 if (++retry_cnt <= MAX_WORD_RETRIES)
1232 xip_enable(map, chip, adr);
1234 chip->state = FL_READY;
1235 put_chip(map, chip, adr);
1236 mutex_unlock(&chip->mutex);
1242 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1243 size_t *retlen, const u_char *buf)
1245 struct map_info *map = mtd->priv;
1246 struct cfi_private *cfi = map->fldrv_priv;
1249 unsigned long ofs, chipstart;
1250 DECLARE_WAITQUEUE(wait, current);
1256 chipnum = to >> cfi->chipshift;
1257 ofs = to - (chipnum << cfi->chipshift);
1258 chipstart = cfi->chips[chipnum].start;
1260 /* If it's not bus-aligned, do the first byte write */
1261 if (ofs & (map_bankwidth(map)-1)) {
1262 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1263 int i = ofs - bus_ofs;
1268 mutex_lock(&cfi->chips[chipnum].mutex);
1270 if (cfi->chips[chipnum].state != FL_READY) {
1271 set_current_state(TASK_UNINTERRUPTIBLE);
1272 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1274 mutex_unlock(&cfi->chips[chipnum].mutex);
1277 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1281 /* Load 'tmp_buf' with old contents of flash */
1282 tmp_buf = map_read(map, bus_ofs+chipstart);
1284 mutex_unlock(&cfi->chips[chipnum].mutex);
1286 /* Number of bytes to copy from buffer */
1287 n = min_t(int, len, map_bankwidth(map)-i);
1289 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1291 ret = do_write_oneword(map, &cfi->chips[chipnum],
1301 if (ofs >> cfi->chipshift) {
1304 if (chipnum == cfi->numchips)
1309 /* We are now aligned, write as much as possible */
1310 while(len >= map_bankwidth(map)) {
1313 datum = map_word_load(map, buf);
1315 ret = do_write_oneword(map, &cfi->chips[chipnum],
1320 ofs += map_bankwidth(map);
1321 buf += map_bankwidth(map);
1322 (*retlen) += map_bankwidth(map);
1323 len -= map_bankwidth(map);
1325 if (ofs >> cfi->chipshift) {
1328 if (chipnum == cfi->numchips)
1330 chipstart = cfi->chips[chipnum].start;
1334 /* Write the trailing bytes if any */
1335 if (len & (map_bankwidth(map)-1)) {
1339 mutex_lock(&cfi->chips[chipnum].mutex);
1341 if (cfi->chips[chipnum].state != FL_READY) {
1342 set_current_state(TASK_UNINTERRUPTIBLE);
1343 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1345 mutex_unlock(&cfi->chips[chipnum].mutex);
1348 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1352 tmp_buf = map_read(map, ofs + chipstart);
1354 mutex_unlock(&cfi->chips[chipnum].mutex);
1356 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1358 ret = do_write_oneword(map, &cfi->chips[chipnum],
1371 * FIXME: interleaved mode not tested, and probably not supported!
1373 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1374 unsigned long adr, const u_char *buf,
1377 struct cfi_private *cfi = map->fldrv_priv;
1378 unsigned long timeo = jiffies + HZ;
1379 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1380 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1382 unsigned long cmd_adr;
1389 mutex_lock(&chip->mutex);
1390 ret = get_chip(map, chip, adr, FL_WRITING);
1392 mutex_unlock(&chip->mutex);
1396 datum = map_word_load(map, buf);
1398 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1399 __func__, adr, datum.x[0] );
1401 XIP_INVAL_CACHED_RANGE(map, adr, len);
1403 xip_disable(map, chip, cmd_adr);
1405 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1406 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1408 /* Write Buffer Load */
1409 map_write(map, CMD(0x25), cmd_adr);
1411 chip->state = FL_WRITING_TO_BUFFER;
1413 /* Write length of data to come */
1414 words = len / map_bankwidth(map);
1415 map_write(map, CMD(words - 1), cmd_adr);
1418 while(z < words * map_bankwidth(map)) {
1419 datum = map_word_load(map, buf);
1420 map_write(map, datum, adr + z);
1422 z += map_bankwidth(map);
1423 buf += map_bankwidth(map);
1425 z -= map_bankwidth(map);
1429 /* Write Buffer Program Confirm: GO GO GO */
1430 map_write(map, CMD(0x29), cmd_adr);
1431 chip->state = FL_WRITING;
1433 INVALIDATE_CACHE_UDELAY(map, chip,
1434 adr, map_bankwidth(map),
1435 chip->word_write_time);
1437 timeo = jiffies + uWriteTimeout;
1440 if (chip->state != FL_WRITING) {
1441 /* Someone's suspended the write. Sleep */
1442 DECLARE_WAITQUEUE(wait, current);
1444 set_current_state(TASK_UNINTERRUPTIBLE);
1445 add_wait_queue(&chip->wq, &wait);
1446 mutex_unlock(&chip->mutex);
1448 remove_wait_queue(&chip->wq, &wait);
1449 timeo = jiffies + (HZ / 2); /* FIXME */
1450 mutex_lock(&chip->mutex);
1454 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1457 if (chip_ready(map, adr)) {
1458 xip_enable(map, chip, adr);
1462 /* Latency issues. Drop the lock, wait a while and retry */
1463 UDELAY(map, chip, adr, 1);
1466 /* reset on all failures. */
1467 map_write( map, CMD(0xF0), chip->start );
1468 xip_enable(map, chip, adr);
1469 /* FIXME - should have reset delay before continuing */
1471 printk(KERN_WARNING "MTD %s(): software timeout\n",
1476 chip->state = FL_READY;
1477 put_chip(map, chip, adr);
1478 mutex_unlock(&chip->mutex);
1484 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1485 size_t *retlen, const u_char *buf)
1487 struct map_info *map = mtd->priv;
1488 struct cfi_private *cfi = map->fldrv_priv;
1489 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1498 chipnum = to >> cfi->chipshift;
1499 ofs = to - (chipnum << cfi->chipshift);
1501 /* If it's not bus-aligned, do the first word write */
1502 if (ofs & (map_bankwidth(map)-1)) {
1503 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1504 if (local_len > len)
1506 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1507 local_len, retlen, buf);
1514 if (ofs >> cfi->chipshift) {
1517 if (chipnum == cfi->numchips)
1522 /* Write buffer is worth it only if more than one word to write... */
1523 while (len >= map_bankwidth(map) * 2) {
1524 /* We must not cross write block boundaries */
1525 int size = wbufsize - (ofs & (wbufsize-1));
1529 if (size % map_bankwidth(map))
1530 size -= size % map_bankwidth(map);
1532 ret = do_write_buffer(map, &cfi->chips[chipnum],
1542 if (ofs >> cfi->chipshift) {
1545 if (chipnum == cfi->numchips)
1551 size_t retlen_dregs = 0;
1553 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1554 len, &retlen_dregs, buf);
1556 *retlen += retlen_dregs;
1565 * Handle devices with one erase region, that only implement
1566 * the chip erase command.
1568 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1570 struct cfi_private *cfi = map->fldrv_priv;
1571 unsigned long timeo = jiffies + HZ;
1572 unsigned long int adr;
1573 DECLARE_WAITQUEUE(wait, current);
1576 adr = cfi->addr_unlock1;
1578 mutex_lock(&chip->mutex);
1579 ret = get_chip(map, chip, adr, FL_WRITING);
1581 mutex_unlock(&chip->mutex);
1585 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1586 __func__, chip->start );
1588 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1590 xip_disable(map, chip, adr);
1592 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1593 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1594 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1595 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1596 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1597 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1599 chip->state = FL_ERASING;
1600 chip->erase_suspended = 0;
1601 chip->in_progress_block_addr = adr;
1603 INVALIDATE_CACHE_UDELAY(map, chip,
1605 chip->erase_time*500);
1607 timeo = jiffies + (HZ*20);
1610 if (chip->state != FL_ERASING) {
1611 /* Someone's suspended the erase. Sleep */
1612 set_current_state(TASK_UNINTERRUPTIBLE);
1613 add_wait_queue(&chip->wq, &wait);
1614 mutex_unlock(&chip->mutex);
1616 remove_wait_queue(&chip->wq, &wait);
1617 mutex_lock(&chip->mutex);
1620 if (chip->erase_suspended) {
1621 /* This erase was suspended and resumed.
1622 Adjust the timeout */
1623 timeo = jiffies + (HZ*20); /* FIXME */
1624 chip->erase_suspended = 0;
1627 if (chip_ready(map, adr))
1630 if (time_after(jiffies, timeo)) {
1631 printk(KERN_WARNING "MTD %s(): software timeout\n",
1636 /* Latency issues. Drop the lock, wait a while and retry */
1637 UDELAY(map, chip, adr, 1000000/HZ);
1639 /* Did we succeed? */
1640 if (!chip_good(map, adr, map_word_ff(map))) {
1641 /* reset on all failures. */
1642 map_write( map, CMD(0xF0), chip->start );
1643 /* FIXME - should have reset delay before continuing */
1648 chip->state = FL_READY;
1649 xip_enable(map, chip, adr);
1650 put_chip(map, chip, adr);
1651 mutex_unlock(&chip->mutex);
1657 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1659 struct cfi_private *cfi = map->fldrv_priv;
1660 unsigned long timeo = jiffies + HZ;
1661 DECLARE_WAITQUEUE(wait, current);
1666 mutex_lock(&chip->mutex);
1667 ret = get_chip(map, chip, adr, FL_ERASING);
1669 mutex_unlock(&chip->mutex);
1673 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1676 XIP_INVAL_CACHED_RANGE(map, adr, len);
1678 xip_disable(map, chip, adr);
1680 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1681 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1682 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1683 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1684 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1685 map_write(map, cfi->sector_erase_cmd, adr);
1687 chip->state = FL_ERASING;
1688 chip->erase_suspended = 0;
1689 chip->in_progress_block_addr = adr;
1691 INVALIDATE_CACHE_UDELAY(map, chip,
1693 chip->erase_time*500);
1695 timeo = jiffies + (HZ*20);
1698 if (chip->state != FL_ERASING) {
1699 /* Someone's suspended the erase. Sleep */
1700 set_current_state(TASK_UNINTERRUPTIBLE);
1701 add_wait_queue(&chip->wq, &wait);
1702 mutex_unlock(&chip->mutex);
1704 remove_wait_queue(&chip->wq, &wait);
1705 mutex_lock(&chip->mutex);
1708 if (chip->erase_suspended) {
1709 /* This erase was suspended and resumed.
1710 Adjust the timeout */
1711 timeo = jiffies + (HZ*20); /* FIXME */
1712 chip->erase_suspended = 0;
1715 if (chip_ready(map, adr)) {
1716 xip_enable(map, chip, adr);
1720 if (time_after(jiffies, timeo)) {
1721 xip_enable(map, chip, adr);
1722 printk(KERN_WARNING "MTD %s(): software timeout\n",
1727 /* Latency issues. Drop the lock, wait a while and retry */
1728 UDELAY(map, chip, adr, 1000000/HZ);
1730 /* Did we succeed? */
1731 if (!chip_good(map, adr, map_word_ff(map))) {
1732 /* reset on all failures. */
1733 map_write( map, CMD(0xF0), chip->start );
1734 /* FIXME - should have reset delay before continuing */
1739 chip->state = FL_READY;
1740 put_chip(map, chip, adr);
1741 mutex_unlock(&chip->mutex);
1746 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1748 unsigned long ofs, len;
1754 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1758 instr->state = MTD_ERASE_DONE;
1759 mtd_erase_callback(instr);
1765 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1767 struct map_info *map = mtd->priv;
1768 struct cfi_private *cfi = map->fldrv_priv;
1771 if (instr->addr != 0)
1774 if (instr->len != mtd->size)
1777 ret = do_erase_chip(map, &cfi->chips[0]);
1781 instr->state = MTD_ERASE_DONE;
1782 mtd_erase_callback(instr);
1787 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1788 unsigned long adr, int len, void *thunk)
1790 struct cfi_private *cfi = map->fldrv_priv;
1793 mutex_lock(&chip->mutex);
1794 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1797 chip->state = FL_LOCKING;
1799 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1800 __func__, adr, len);
1802 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1803 cfi->device_type, NULL);
1804 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1805 cfi->device_type, NULL);
1806 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1807 cfi->device_type, NULL);
1808 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1809 cfi->device_type, NULL);
1810 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1811 cfi->device_type, NULL);
1812 map_write(map, CMD(0x40), chip->start + adr);
1814 chip->state = FL_READY;
1815 put_chip(map, chip, adr + chip->start);
1819 mutex_unlock(&chip->mutex);
1823 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1824 unsigned long adr, int len, void *thunk)
1826 struct cfi_private *cfi = map->fldrv_priv;
1829 mutex_lock(&chip->mutex);
1830 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1833 chip->state = FL_UNLOCKING;
1835 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1836 __func__, adr, len);
1838 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1839 cfi->device_type, NULL);
1840 map_write(map, CMD(0x70), adr);
1842 chip->state = FL_READY;
1843 put_chip(map, chip, adr + chip->start);
1847 mutex_unlock(&chip->mutex);
1851 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1853 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1856 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1858 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1862 static void cfi_amdstd_sync (struct mtd_info *mtd)
1864 struct map_info *map = mtd->priv;
1865 struct cfi_private *cfi = map->fldrv_priv;
1867 struct flchip *chip;
1869 DECLARE_WAITQUEUE(wait, current);
1871 for (i=0; !ret && i<cfi->numchips; i++) {
1872 chip = &cfi->chips[i];
1875 mutex_lock(&chip->mutex);
1877 switch(chip->state) {
1881 case FL_JEDEC_QUERY:
1882 chip->oldstate = chip->state;
1883 chip->state = FL_SYNCING;
1884 /* No need to wake_up() on this state change -
1885 * as the whole point is that nobody can do anything
1886 * with the chip now anyway.
1889 mutex_unlock(&chip->mutex);
1893 /* Not an idle state */
1894 set_current_state(TASK_UNINTERRUPTIBLE);
1895 add_wait_queue(&chip->wq, &wait);
1897 mutex_unlock(&chip->mutex);
1901 remove_wait_queue(&chip->wq, &wait);
1907 /* Unlock the chips again */
1909 for (i--; i >=0; i--) {
1910 chip = &cfi->chips[i];
1912 mutex_lock(&chip->mutex);
1914 if (chip->state == FL_SYNCING) {
1915 chip->state = chip->oldstate;
1918 mutex_unlock(&chip->mutex);
1923 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1925 struct map_info *map = mtd->priv;
1926 struct cfi_private *cfi = map->fldrv_priv;
1928 struct flchip *chip;
1931 for (i=0; !ret && i<cfi->numchips; i++) {
1932 chip = &cfi->chips[i];
1934 mutex_lock(&chip->mutex);
1936 switch(chip->state) {
1940 case FL_JEDEC_QUERY:
1941 chip->oldstate = chip->state;
1942 chip->state = FL_PM_SUSPENDED;
1943 /* No need to wake_up() on this state change -
1944 * as the whole point is that nobody can do anything
1945 * with the chip now anyway.
1947 case FL_PM_SUSPENDED:
1954 mutex_unlock(&chip->mutex);
1957 /* Unlock the chips again */
1960 for (i--; i >=0; i--) {
1961 chip = &cfi->chips[i];
1963 mutex_lock(&chip->mutex);
1965 if (chip->state == FL_PM_SUSPENDED) {
1966 chip->state = chip->oldstate;
1969 mutex_unlock(&chip->mutex);
1977 static void cfi_amdstd_resume(struct mtd_info *mtd)
1979 struct map_info *map = mtd->priv;
1980 struct cfi_private *cfi = map->fldrv_priv;
1982 struct flchip *chip;
1984 for (i=0; i<cfi->numchips; i++) {
1986 chip = &cfi->chips[i];
1988 mutex_lock(&chip->mutex);
1990 if (chip->state == FL_PM_SUSPENDED) {
1991 chip->state = FL_READY;
1992 map_write(map, CMD(0xF0), chip->start);
1996 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1998 mutex_unlock(&chip->mutex);
2004 * Ensure that the flash device is put back into read array mode before
2005 * unloading the driver or rebooting. On some systems, rebooting while
2006 * the flash is in query/program/erase mode will prevent the CPU from
2007 * fetching the bootloader code, requiring a hard reset or power cycle.
2009 static int cfi_amdstd_reset(struct mtd_info *mtd)
2011 struct map_info *map = mtd->priv;
2012 struct cfi_private *cfi = map->fldrv_priv;
2014 struct flchip *chip;
2016 for (i = 0; i < cfi->numchips; i++) {
2018 chip = &cfi->chips[i];
2020 mutex_lock(&chip->mutex);
2022 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2024 map_write(map, CMD(0xF0), chip->start);
2025 chip->state = FL_SHUTDOWN;
2026 put_chip(map, chip, chip->start);
2029 mutex_unlock(&chip->mutex);
2036 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2039 struct mtd_info *mtd;
2041 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2042 cfi_amdstd_reset(mtd);
2047 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2049 struct map_info *map = mtd->priv;
2050 struct cfi_private *cfi = map->fldrv_priv;
2052 cfi_amdstd_reset(mtd);
2053 unregister_reboot_notifier(&mtd->reboot_notifier);
2054 kfree(cfi->cmdset_priv);
2057 kfree(mtd->eraseregions);
2060 MODULE_LICENSE("GPL");
2061 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2062 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2063 MODULE_ALIAS("cfi_cmdset_0006");
2064 MODULE_ALIAS("cfi_cmdset_0701");