2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
4 * Author: Mike Lavender, mike@steroidmicros.com
6 * Copyright (c) 2005, Intec Automation Inc.
8 * Some parts are based on lart.c by Abraham Van Der Merwe
10 * Cleaned up and generalized based on mtd_dataflash.c
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/math64.h>
24 #include <linux/sched.h>
25 #include <linux/mod_devicetable.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/partitions.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/flash.h>
34 #define OPCODE_WREN 0x06 /* Write enable */
35 #define OPCODE_RDSR 0x05 /* Read status register */
36 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
37 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
38 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
39 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
40 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
41 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
42 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
43 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
44 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
46 /* Used for SST flashes only. */
47 #define OPCODE_BP 0x02 /* Byte program */
48 #define OPCODE_WRDI 0x04 /* Write disable */
49 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
51 /* Status Register bits. */
52 #define SR_WIP 1 /* Write in progress */
53 #define SR_WEL 2 /* Write enable latch */
54 /* meaning of other SR_* bits may differ between vendors */
55 #define SR_BP0 4 /* Block protect 0 */
56 #define SR_BP1 8 /* Block protect 1 */
57 #define SR_BP2 0x10 /* Block protect 2 */
58 #define SR_SRWD 0x80 /* SR write protect */
60 /* Define max times to check status register before we give up. */
61 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
62 #define MAX_CMD_SIZE 4
64 #ifdef CONFIG_M25PXX_USE_FAST_READ
65 #define OPCODE_READ OPCODE_FAST_READ
66 #define FAST_READ_DUMMY_BYTE 1
68 #define OPCODE_READ OPCODE_NORM_READ
69 #define FAST_READ_DUMMY_BYTE 0
72 /****************************************************************************/
75 struct spi_device *spi;
78 unsigned partitioned:1;
85 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
87 return container_of(mtd, struct m25p, mtd);
90 /****************************************************************************/
93 * Internal helper functions
97 * Read the status register, returning its value in the location
98 * Return the status register value.
99 * Returns negative if error occurred.
101 static int read_sr(struct m25p *flash)
104 u8 code = OPCODE_RDSR;
107 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
110 dev_err(&flash->spi->dev, "error %d reading SR\n",
119 * Write status register 1 byte
120 * Returns negative if error occurred.
122 static int write_sr(struct m25p *flash, u8 val)
124 flash->command[0] = OPCODE_WRSR;
125 flash->command[1] = val;
127 return spi_write(flash->spi, flash->command, 2);
131 * Set write enable latch with Write Enable command.
132 * Returns negative if error occurred.
134 static inline int write_enable(struct m25p *flash)
136 u8 code = OPCODE_WREN;
138 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
142 * Send write disble instruction to the chip.
144 static inline int write_disable(struct m25p *flash)
146 u8 code = OPCODE_WRDI;
148 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
152 * Service routine to read status register until ready, or timeout occurs.
153 * Returns non-zero if error.
155 static int wait_till_ready(struct m25p *flash)
157 unsigned long deadline;
160 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
163 if ((sr = read_sr(flash)) < 0)
165 else if (!(sr & SR_WIP))
170 } while (!time_after_eq(jiffies, deadline));
176 * Erase the whole flash memory
178 * Returns 0 if successful, non-zero otherwise.
180 static int erase_chip(struct m25p *flash)
182 DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %lldKiB\n",
183 dev_name(&flash->spi->dev), __func__,
184 (long long)(flash->mtd.size >> 10));
186 /* Wait until finished previous write command. */
187 if (wait_till_ready(flash))
190 /* Send write enable, then erase commands. */
193 /* Set up command buffer. */
194 flash->command[0] = OPCODE_CHIP_ERASE;
196 spi_write(flash->spi, flash->command, 1);
201 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
203 /* opcode is in cmd[0] */
204 cmd[1] = addr >> (flash->addr_width * 8 - 8);
205 cmd[2] = addr >> (flash->addr_width * 8 - 16);
206 cmd[3] = addr >> (flash->addr_width * 8 - 24);
209 static int m25p_cmdsz(struct m25p *flash)
211 return 1 + flash->addr_width;
215 * Erase one sector of flash memory at offset ``offset'' which is any
216 * address within the sector which should be erased.
218 * Returns 0 if successful, non-zero otherwise.
220 static int erase_sector(struct m25p *flash, u32 offset)
222 DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n",
223 dev_name(&flash->spi->dev), __func__,
224 flash->mtd.erasesize / 1024, offset);
226 /* Wait until finished previous write command. */
227 if (wait_till_ready(flash))
230 /* Send write enable, then erase commands. */
233 /* Set up command buffer. */
234 flash->command[0] = flash->erase_opcode;
235 m25p_addr2cmd(flash, offset, flash->command);
237 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
242 /****************************************************************************/
249 * Erase an address range on the flash chip. The address range may extend
250 * one or more erase sectors. Return an error is there is a problem erasing.
252 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
254 struct m25p *flash = mtd_to_m25p(mtd);
258 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%llx, len %lld\n",
259 dev_name(&flash->spi->dev), __func__, "at",
260 (long long)instr->addr, (long long)instr->len);
263 if (instr->addr + instr->len > flash->mtd.size)
265 div_u64_rem(instr->len, mtd->erasesize, &rem);
272 mutex_lock(&flash->lock);
274 /* whole-chip erase? */
275 if (len == flash->mtd.size) {
276 if (erase_chip(flash)) {
277 instr->state = MTD_ERASE_FAILED;
278 mutex_unlock(&flash->lock);
282 /* REVISIT in some cases we could speed up erasing large regions
283 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
284 * to use "small sector erase", but that's not always optimal.
287 /* "sector"-at-a-time erase */
290 if (erase_sector(flash, addr)) {
291 instr->state = MTD_ERASE_FAILED;
292 mutex_unlock(&flash->lock);
296 addr += mtd->erasesize;
297 len -= mtd->erasesize;
301 mutex_unlock(&flash->lock);
303 instr->state = MTD_ERASE_DONE;
304 mtd_erase_callback(instr);
310 * Read an address range from the flash chip. The address range
311 * may be any size provided it is within the physical boundaries.
313 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
314 size_t *retlen, u_char *buf)
316 struct m25p *flash = mtd_to_m25p(mtd);
317 struct spi_transfer t[2];
318 struct spi_message m;
320 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
321 dev_name(&flash->spi->dev), __func__, "from",
328 if (from + len > flash->mtd.size)
331 spi_message_init(&m);
332 memset(t, 0, (sizeof t));
335 * OPCODE_FAST_READ (if available) is faster.
336 * Should add 1 byte DUMMY_BYTE.
338 t[0].tx_buf = flash->command;
339 t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
340 spi_message_add_tail(&t[0], &m);
344 spi_message_add_tail(&t[1], &m);
346 /* Byte count starts at zero. */
350 mutex_lock(&flash->lock);
352 /* Wait till previous write/erase is done. */
353 if (wait_till_ready(flash)) {
354 /* REVISIT status return?? */
355 mutex_unlock(&flash->lock);
359 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
360 * clocks; and at this writing, every chip this driver handles
361 * supports that opcode.
364 /* Set up the write data buffer. */
365 flash->command[0] = OPCODE_READ;
366 m25p_addr2cmd(flash, from, flash->command);
368 spi_sync(flash->spi, &m);
370 *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
372 mutex_unlock(&flash->lock);
378 * Write an address range to the flash chip. Data must be written in
379 * FLASH_PAGESIZE chunks. The address range may be any size provided
380 * it is within the physical boundaries.
382 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
383 size_t *retlen, const u_char *buf)
385 struct m25p *flash = mtd_to_m25p(mtd);
386 u32 page_offset, page_size;
387 struct spi_transfer t[2];
388 struct spi_message m;
390 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
391 dev_name(&flash->spi->dev), __func__, "to",
401 if (to + len > flash->mtd.size)
404 spi_message_init(&m);
405 memset(t, 0, (sizeof t));
407 t[0].tx_buf = flash->command;
408 t[0].len = m25p_cmdsz(flash);
409 spi_message_add_tail(&t[0], &m);
412 spi_message_add_tail(&t[1], &m);
414 mutex_lock(&flash->lock);
416 /* Wait until finished previous write command. */
417 if (wait_till_ready(flash)) {
418 mutex_unlock(&flash->lock);
424 /* Set up the opcode in the write buffer. */
425 flash->command[0] = OPCODE_PP;
426 m25p_addr2cmd(flash, to, flash->command);
428 page_offset = to & (flash->page_size - 1);
430 /* do all the bytes fit onto one page? */
431 if (page_offset + len <= flash->page_size) {
434 spi_sync(flash->spi, &m);
436 *retlen = m.actual_length - m25p_cmdsz(flash);
440 /* the size of data remaining on the first page */
441 page_size = flash->page_size - page_offset;
443 t[1].len = page_size;
444 spi_sync(flash->spi, &m);
446 *retlen = m.actual_length - m25p_cmdsz(flash);
448 /* write everything in flash->page_size chunks */
449 for (i = page_size; i < len; i += page_size) {
451 if (page_size > flash->page_size)
452 page_size = flash->page_size;
454 /* write the next page to flash */
455 m25p_addr2cmd(flash, to + i, flash->command);
457 t[1].tx_buf = buf + i;
458 t[1].len = page_size;
460 wait_till_ready(flash);
464 spi_sync(flash->spi, &m);
467 *retlen += m.actual_length - m25p_cmdsz(flash);
471 mutex_unlock(&flash->lock);
476 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
477 size_t *retlen, const u_char *buf)
479 struct m25p *flash = mtd_to_m25p(mtd);
480 struct spi_transfer t[2];
481 struct spi_message m;
492 if (to + len > flash->mtd.size)
495 spi_message_init(&m);
496 memset(t, 0, (sizeof t));
498 t[0].tx_buf = flash->command;
499 t[0].len = m25p_cmdsz(flash);
500 spi_message_add_tail(&t[0], &m);
503 spi_message_add_tail(&t[1], &m);
505 mutex_lock(&flash->lock);
507 /* Wait until finished previous write command. */
508 ret = wait_till_ready(flash);
515 /* Start write from odd address. */
517 flash->command[0] = OPCODE_BP;
518 m25p_addr2cmd(flash, to, flash->command);
520 /* write one byte. */
522 spi_sync(flash->spi, &m);
523 ret = wait_till_ready(flash);
526 *retlen += m.actual_length - m25p_cmdsz(flash);
530 flash->command[0] = OPCODE_AAI_WP;
531 m25p_addr2cmd(flash, to, flash->command);
533 /* Write out most of the data here. */
534 cmd_sz = m25p_cmdsz(flash);
535 for (; actual < len - 1; actual += 2) {
537 /* write two bytes. */
539 t[1].tx_buf = buf + actual;
541 spi_sync(flash->spi, &m);
542 ret = wait_till_ready(flash);
545 *retlen += m.actual_length - cmd_sz;
549 write_disable(flash);
550 ret = wait_till_ready(flash);
554 /* Write out trailing byte if it exists. */
557 flash->command[0] = OPCODE_BP;
558 m25p_addr2cmd(flash, to, flash->command);
559 t[0].len = m25p_cmdsz(flash);
561 t[1].tx_buf = buf + actual;
563 spi_sync(flash->spi, &m);
564 ret = wait_till_ready(flash);
567 *retlen += m.actual_length - m25p_cmdsz(flash);
568 write_disable(flash);
572 mutex_unlock(&flash->lock);
576 /****************************************************************************/
579 * SPI device driver setup and teardown
583 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
584 * a high byte of zero plus three data bytes: the manufacturer id,
585 * then a two byte device id.
590 /* The size listed here is what works with OPCODE_SE, which isn't
591 * necessarily called a "sector" by the vendor.
593 unsigned sector_size;
600 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
601 #define M25P_NO_ERASE 0x02 /* No erase command needed */
604 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
605 ((kernel_ulong_t)&(struct flash_info) { \
606 .jedec_id = (_jedec_id), \
607 .ext_id = (_ext_id), \
608 .sector_size = (_sector_size), \
609 .n_sectors = (_n_sectors), \
615 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
616 ((kernel_ulong_t)&(struct flash_info) { \
617 .sector_size = (_sector_size), \
618 .n_sectors = (_n_sectors), \
619 .page_size = (_page_size), \
620 .addr_width = (_addr_width), \
621 .flags = M25P_NO_ERASE, \
624 /* NOTE: double check command sets and memory organization when you add
625 * more flash chips. This current list focusses on newer chips, which
626 * have been converging on command sets which including JEDEC ID.
628 static const struct spi_device_id m25p_ids[] = {
629 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
630 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
631 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
633 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
634 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
636 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
637 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
638 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
639 { "at26df321", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
642 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
643 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
644 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
645 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
646 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
648 /* Spansion -- single (large) sector size only, at least
649 * for the chips listed here (without boot sectors).
651 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
652 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
653 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
654 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
655 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
656 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
657 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
658 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
659 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
661 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
662 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
663 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
664 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
665 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
666 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
667 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
668 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
669 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
671 /* ST Microelectronics -- newer production may have feature updates */
672 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
673 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
674 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
675 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
676 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
677 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
678 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
679 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
680 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
682 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
683 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
684 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
686 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
687 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
689 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
690 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
691 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
692 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
693 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
694 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
695 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
696 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
698 /* Catalyst / On Semiconductor -- non-JEDEC */
699 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
700 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
701 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
702 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
703 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
706 MODULE_DEVICE_TABLE(spi, m25p_ids);
708 static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi)
711 u8 code = OPCODE_RDID;
715 struct flash_info *info;
717 /* JEDEC also defines an optional "extended device information"
718 * string for after vendor-specific data, after the three bytes
719 * we use here. Supporting some chips might require using it.
721 tmp = spi_write_then_read(spi, &code, 1, id, 5);
723 DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n",
724 dev_name(&spi->dev), tmp);
734 * Some chips (like Numonyx M25P80) have JEDEC and non-JEDEC variants,
735 * which depend on technology process. Officially RDID command doesn't
736 * exist for non-JEDEC chips, but for compatibility they return ID 0.
741 ext_jedec = id[3] << 8 | id[4];
743 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
744 info = (void *)m25p_ids[tmp].driver_data;
745 if (info->jedec_id == jedec) {
746 if (info->ext_id != 0 && info->ext_id != ext_jedec)
748 return &m25p_ids[tmp];
756 * board specific setup should have ensured the SPI clock used here
757 * matches what the READ command supports, at least until this driver
758 * understands FAST_READ (for clocks over 25 MHz).
760 static int __devinit m25p_probe(struct spi_device *spi)
762 const struct spi_device_id *id = spi_get_device_id(spi);
763 struct flash_platform_data *data;
765 struct flash_info *info;
768 /* Platform data helps sort out which chip type we have, as
769 * well as how this board partitions it. If we don't have
770 * a chip ID, try the JEDEC id commands; they'll work for most
771 * newer chips, even if we don't recognize the particular chip.
773 data = spi->dev.platform_data;
774 if (data && data->type) {
775 const struct spi_device_id *plat_id;
777 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
778 plat_id = &m25p_ids[i];
779 if (strcmp(data->type, plat_id->name))
787 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
790 info = (void *)id->driver_data;
792 if (info->jedec_id) {
793 const struct spi_device_id *jid;
795 jid = jedec_probe(spi);
797 dev_info(&spi->dev, "non-JEDEC variant of %s\n",
799 } else if (jid != id) {
801 * JEDEC knows better, so overwrite platform ID. We
802 * can't trust partitions any longer, but we'll let
803 * mtd apply them anyway, since some partitions may be
804 * marked read-only, and we don't want to lose that
805 * information, even if it's not 100% accurate.
807 dev_warn(&spi->dev, "found %s, expected %s\n",
808 jid->name, id->name);
810 info = (void *)jid->driver_data;
814 flash = kzalloc(sizeof *flash, GFP_KERNEL);
817 flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
818 if (!flash->command) {
824 mutex_init(&flash->lock);
825 dev_set_drvdata(&spi->dev, flash);
828 * Atmel and SST serial flash tend to power
829 * up with the software protection bits set
832 if (info->jedec_id >> 16 == 0x1f ||
833 info->jedec_id >> 16 == 0xbf) {
838 if (data && data->name)
839 flash->mtd.name = data->name;
841 flash->mtd.name = dev_name(&spi->dev);
843 flash->mtd.type = MTD_NORFLASH;
844 flash->mtd.writesize = 1;
845 flash->mtd.flags = MTD_CAP_NORFLASH;
846 flash->mtd.size = info->sector_size * info->n_sectors;
847 flash->mtd.erase = m25p80_erase;
848 flash->mtd.read = m25p80_read;
850 /* sst flash chips use AAI word program */
851 if (info->jedec_id >> 16 == 0xbf)
852 flash->mtd.write = sst_write;
854 flash->mtd.write = m25p80_write;
856 /* prefer "small sector" erase if possible */
857 if (info->flags & SECT_4K) {
858 flash->erase_opcode = OPCODE_BE_4K;
859 flash->mtd.erasesize = 4096;
861 flash->erase_opcode = OPCODE_SE;
862 flash->mtd.erasesize = info->sector_size;
865 if (info->flags & M25P_NO_ERASE)
866 flash->mtd.flags |= MTD_NO_ERASE;
868 flash->mtd.dev.parent = &spi->dev;
869 flash->page_size = info->page_size;
870 flash->addr_width = info->addr_width;
872 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
873 (long long)flash->mtd.size >> 10);
875 DEBUG(MTD_DEBUG_LEVEL2,
876 "mtd .name = %s, .size = 0x%llx (%lldMiB) "
877 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
879 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
880 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
881 flash->mtd.numeraseregions);
883 if (flash->mtd.numeraseregions)
884 for (i = 0; i < flash->mtd.numeraseregions; i++)
885 DEBUG(MTD_DEBUG_LEVEL2,
886 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
887 ".erasesize = 0x%.8x (%uKiB), "
888 ".numblocks = %d }\n",
889 i, (long long)flash->mtd.eraseregions[i].offset,
890 flash->mtd.eraseregions[i].erasesize,
891 flash->mtd.eraseregions[i].erasesize / 1024,
892 flash->mtd.eraseregions[i].numblocks);
895 /* partitions should match sector boundaries; and it may be good to
896 * use readonly partitions for writeprotected sectors (BP2..BP0).
898 if (mtd_has_partitions()) {
899 struct mtd_partition *parts = NULL;
902 if (mtd_has_cmdlinepart()) {
903 static const char *part_probes[]
904 = { "cmdlinepart", NULL, };
906 nr_parts = parse_mtd_partitions(&flash->mtd,
907 part_probes, &parts, 0);
910 if (nr_parts <= 0 && data && data->parts) {
912 nr_parts = data->nr_parts;
916 for (i = 0; i < nr_parts; i++) {
917 DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = "
918 "{.name = %s, .offset = 0x%llx, "
919 ".size = 0x%llx (%lldKiB) }\n",
921 (long long)parts[i].offset,
922 (long long)parts[i].size,
923 (long long)(parts[i].size >> 10));
925 flash->partitioned = 1;
926 return add_mtd_partitions(&flash->mtd, parts, nr_parts);
928 } else if (data && data->nr_parts)
929 dev_warn(&spi->dev, "ignoring %d default partitions on %s\n",
930 data->nr_parts, data->name);
932 return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0;
936 static int __devexit m25p_remove(struct spi_device *spi)
938 struct m25p *flash = dev_get_drvdata(&spi->dev);
941 /* Clean up MTD stuff. */
942 if (mtd_has_partitions() && flash->partitioned)
943 status = del_mtd_partitions(&flash->mtd);
945 status = del_mtd_device(&flash->mtd);
947 kfree(flash->command);
954 static struct spi_driver m25p80_driver = {
957 .bus = &spi_bus_type,
958 .owner = THIS_MODULE,
960 .id_table = m25p_ids,
962 .remove = __devexit_p(m25p_remove),
964 /* REVISIT: many of these chips have deep power-down modes, which
965 * should clearly be entered on suspend() to minimize power use.
966 * And also when they're otherwise idle...
971 static int __init m25p80_init(void)
973 return spi_register_driver(&m25p80_driver);
977 static void __exit m25p80_exit(void)
979 spi_unregister_driver(&m25p80_driver);
983 module_init(m25p80_init);
984 module_exit(m25p80_exit);
986 MODULE_LICENSE("GPL");
987 MODULE_AUTHOR("Mike Lavender");
988 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");