2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
4 * Author: Mike Lavender, mike@steroidmicros.com
6 * Copyright (c) 2005, Intec Automation Inc.
8 * Some parts are based on lart.c by Abraham Van Der Merwe
10 * Cleaned up and generalized based on mtd_dataflash.c
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
47 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
48 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
49 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
50 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
52 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
53 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
54 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
55 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
56 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
58 /* Used for SST flashes only. */
59 #define OPCODE_BP 0x02 /* Byte program */
60 #define OPCODE_WRDI 0x04 /* Write disable */
61 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
63 /* Used for Macronix and Winbond flashes. */
64 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
65 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
67 /* Used for Spansion flashes only. */
68 #define OPCODE_BRWR 0x17 /* Bank register write */
70 /* Status Register bits. */
71 #define SR_WIP 1 /* Write in progress */
72 #define SR_WEL 2 /* Write enable latch */
73 /* meaning of other SR_* bits may differ between vendors */
74 #define SR_BP0 4 /* Block protect 0 */
75 #define SR_BP1 8 /* Block protect 1 */
76 #define SR_BP2 0x10 /* Block protect 2 */
77 #define SR_SRWD 0x80 /* SR write protect */
79 /* Define max times to check status register before we give up. */
80 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
81 #define MAX_CMD_SIZE 5
83 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
85 /****************************************************************************/
88 struct spi_device *spi;
100 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
102 return container_of(mtd, struct m25p, mtd);
105 /****************************************************************************/
108 * Internal helper functions
112 * Read the status register, returning its value in the location
113 * Return the status register value.
114 * Returns negative if error occurred.
116 static int read_sr(struct m25p *flash)
119 u8 code = OPCODE_RDSR;
122 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
125 dev_err(&flash->spi->dev, "error %d reading SR\n",
134 * Write status register 1 byte
135 * Returns negative if error occurred.
137 static int write_sr(struct m25p *flash, u8 val)
139 flash->command[0] = OPCODE_WRSR;
140 flash->command[1] = val;
142 return spi_write(flash->spi, flash->command, 2);
146 * Set write enable latch with Write Enable command.
147 * Returns negative if error occurred.
149 static inline int write_enable(struct m25p *flash)
151 u8 code = OPCODE_WREN;
153 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
157 * Send write disble instruction to the chip.
159 static inline int write_disable(struct m25p *flash)
161 u8 code = OPCODE_WRDI;
163 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
167 * Enable/disable 4-byte addressing mode.
169 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
171 switch (JEDEC_MFR(jedec_id)) {
172 case CFI_MFR_MACRONIX:
173 case CFI_MFR_ST: /* Micron, actually */
174 case 0xEF /* winbond */:
175 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
176 return spi_write(flash->spi, flash->command, 1);
179 flash->command[0] = OPCODE_BRWR;
180 flash->command[1] = enable << 7;
181 return spi_write(flash->spi, flash->command, 2);
186 * Service routine to read status register until ready, or timeout occurs.
187 * Returns non-zero if error.
189 static int wait_till_ready(struct m25p *flash)
191 unsigned long deadline;
194 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
197 if ((sr = read_sr(flash)) < 0)
199 else if (!(sr & SR_WIP))
204 } while (!time_after_eq(jiffies, deadline));
210 * Erase the whole flash memory
212 * Returns 0 if successful, non-zero otherwise.
214 static int erase_chip(struct m25p *flash)
216 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
217 (long long)(flash->mtd.size >> 10));
219 /* Wait until finished previous write command. */
220 if (wait_till_ready(flash))
223 /* Send write enable, then erase commands. */
226 /* Set up command buffer. */
227 flash->command[0] = OPCODE_CHIP_ERASE;
229 spi_write(flash->spi, flash->command, 1);
234 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
236 /* opcode is in cmd[0] */
237 cmd[1] = addr >> (flash->addr_width * 8 - 8);
238 cmd[2] = addr >> (flash->addr_width * 8 - 16);
239 cmd[3] = addr >> (flash->addr_width * 8 - 24);
240 cmd[4] = addr >> (flash->addr_width * 8 - 32);
243 static int m25p_cmdsz(struct m25p *flash)
245 return 1 + flash->addr_width;
249 * Erase one sector of flash memory at offset ``offset'' which is any
250 * address within the sector which should be erased.
252 * Returns 0 if successful, non-zero otherwise.
254 static int erase_sector(struct m25p *flash, u32 offset)
256 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
257 __func__, flash->mtd.erasesize / 1024, offset);
259 /* Wait until finished previous write command. */
260 if (wait_till_ready(flash))
263 /* Send write enable, then erase commands. */
266 /* Set up command buffer. */
267 flash->command[0] = flash->erase_opcode;
268 m25p_addr2cmd(flash, offset, flash->command);
270 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
275 /****************************************************************************/
282 * Erase an address range on the flash chip. The address range may extend
283 * one or more erase sectors. Return an error is there is a problem erasing.
285 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
287 struct m25p *flash = mtd_to_m25p(mtd);
291 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
292 __func__, (long long)instr->addr,
293 (long long)instr->len);
295 div_u64_rem(instr->len, mtd->erasesize, &rem);
302 mutex_lock(&flash->lock);
304 /* whole-chip erase? */
305 if (len == flash->mtd.size) {
306 if (erase_chip(flash)) {
307 instr->state = MTD_ERASE_FAILED;
308 mutex_unlock(&flash->lock);
312 /* REVISIT in some cases we could speed up erasing large regions
313 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
314 * to use "small sector erase", but that's not always optimal.
317 /* "sector"-at-a-time erase */
320 if (erase_sector(flash, addr)) {
321 instr->state = MTD_ERASE_FAILED;
322 mutex_unlock(&flash->lock);
326 addr += mtd->erasesize;
327 len -= mtd->erasesize;
331 mutex_unlock(&flash->lock);
333 instr->state = MTD_ERASE_DONE;
334 mtd_erase_callback(instr);
340 * Read an address range from the flash chip. The address range
341 * may be any size provided it is within the physical boundaries.
343 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
344 size_t *retlen, u_char *buf)
346 struct m25p *flash = mtd_to_m25p(mtd);
347 struct spi_transfer t[2];
348 struct spi_message m;
351 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
352 __func__, (u32)from, len);
354 spi_message_init(&m);
355 memset(t, 0, (sizeof t));
358 * OPCODE_FAST_READ (if available) is faster.
359 * Should add 1 byte DUMMY_BYTE.
361 t[0].tx_buf = flash->command;
362 t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
363 spi_message_add_tail(&t[0], &m);
367 spi_message_add_tail(&t[1], &m);
369 mutex_lock(&flash->lock);
371 /* Wait till previous write/erase is done. */
372 if (wait_till_ready(flash)) {
373 /* REVISIT status return?? */
374 mutex_unlock(&flash->lock);
378 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
379 * clocks; and at this writing, every chip this driver handles
380 * supports that opcode.
383 /* Set up the write data buffer. */
384 opcode = flash->read_opcode;
385 flash->command[0] = opcode;
386 m25p_addr2cmd(flash, from, flash->command);
388 spi_sync(flash->spi, &m);
390 *retlen = m.actual_length - m25p_cmdsz(flash) -
391 (flash->fast_read ? 1 : 0);
393 mutex_unlock(&flash->lock);
399 * Write an address range to the flash chip. Data must be written in
400 * FLASH_PAGESIZE chunks. The address range may be any size provided
401 * it is within the physical boundaries.
403 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
404 size_t *retlen, const u_char *buf)
406 struct m25p *flash = mtd_to_m25p(mtd);
407 u32 page_offset, page_size;
408 struct spi_transfer t[2];
409 struct spi_message m;
411 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
412 __func__, (u32)to, len);
414 spi_message_init(&m);
415 memset(t, 0, (sizeof t));
417 t[0].tx_buf = flash->command;
418 t[0].len = m25p_cmdsz(flash);
419 spi_message_add_tail(&t[0], &m);
422 spi_message_add_tail(&t[1], &m);
424 mutex_lock(&flash->lock);
426 /* Wait until finished previous write command. */
427 if (wait_till_ready(flash)) {
428 mutex_unlock(&flash->lock);
434 /* Set up the opcode in the write buffer. */
435 flash->command[0] = flash->program_opcode;
436 m25p_addr2cmd(flash, to, flash->command);
438 page_offset = to & (flash->page_size - 1);
440 /* do all the bytes fit onto one page? */
441 if (page_offset + len <= flash->page_size) {
444 spi_sync(flash->spi, &m);
446 *retlen = m.actual_length - m25p_cmdsz(flash);
450 /* the size of data remaining on the first page */
451 page_size = flash->page_size - page_offset;
453 t[1].len = page_size;
454 spi_sync(flash->spi, &m);
456 *retlen = m.actual_length - m25p_cmdsz(flash);
458 /* write everything in flash->page_size chunks */
459 for (i = page_size; i < len; i += page_size) {
461 if (page_size > flash->page_size)
462 page_size = flash->page_size;
464 /* write the next page to flash */
465 m25p_addr2cmd(flash, to + i, flash->command);
467 t[1].tx_buf = buf + i;
468 t[1].len = page_size;
470 wait_till_ready(flash);
474 spi_sync(flash->spi, &m);
476 *retlen += m.actual_length - m25p_cmdsz(flash);
480 mutex_unlock(&flash->lock);
485 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
486 size_t *retlen, const u_char *buf)
488 struct m25p *flash = mtd_to_m25p(mtd);
489 struct spi_transfer t[2];
490 struct spi_message m;
494 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
495 __func__, (u32)to, len);
497 spi_message_init(&m);
498 memset(t, 0, (sizeof t));
500 t[0].tx_buf = flash->command;
501 t[0].len = m25p_cmdsz(flash);
502 spi_message_add_tail(&t[0], &m);
505 spi_message_add_tail(&t[1], &m);
507 mutex_lock(&flash->lock);
509 /* Wait until finished previous write command. */
510 ret = wait_till_ready(flash);
517 /* Start write from odd address. */
519 flash->command[0] = OPCODE_BP;
520 m25p_addr2cmd(flash, to, flash->command);
522 /* write one byte. */
524 spi_sync(flash->spi, &m);
525 ret = wait_till_ready(flash);
528 *retlen += m.actual_length - m25p_cmdsz(flash);
532 flash->command[0] = OPCODE_AAI_WP;
533 m25p_addr2cmd(flash, to, flash->command);
535 /* Write out most of the data here. */
536 cmd_sz = m25p_cmdsz(flash);
537 for (; actual < len - 1; actual += 2) {
539 /* write two bytes. */
541 t[1].tx_buf = buf + actual;
543 spi_sync(flash->spi, &m);
544 ret = wait_till_ready(flash);
547 *retlen += m.actual_length - cmd_sz;
551 write_disable(flash);
552 ret = wait_till_ready(flash);
556 /* Write out trailing byte if it exists. */
559 flash->command[0] = OPCODE_BP;
560 m25p_addr2cmd(flash, to, flash->command);
561 t[0].len = m25p_cmdsz(flash);
563 t[1].tx_buf = buf + actual;
565 spi_sync(flash->spi, &m);
566 ret = wait_till_ready(flash);
569 *retlen += m.actual_length - m25p_cmdsz(flash);
570 write_disable(flash);
574 mutex_unlock(&flash->lock);
578 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
580 struct m25p *flash = mtd_to_m25p(mtd);
581 uint32_t offset = ofs;
582 uint8_t status_old, status_new;
585 mutex_lock(&flash->lock);
586 /* Wait until finished previous command */
587 if (wait_till_ready(flash)) {
592 status_old = read_sr(flash);
594 if (offset < flash->mtd.size-(flash->mtd.size/2))
595 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
596 else if (offset < flash->mtd.size-(flash->mtd.size/4))
597 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
598 else if (offset < flash->mtd.size-(flash->mtd.size/8))
599 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
600 else if (offset < flash->mtd.size-(flash->mtd.size/16))
601 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
602 else if (offset < flash->mtd.size-(flash->mtd.size/32))
603 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
604 else if (offset < flash->mtd.size-(flash->mtd.size/64))
605 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
607 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
609 /* Only modify protection if it will not unlock other areas */
610 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
611 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
613 if (write_sr(flash, status_new) < 0) {
619 err: mutex_unlock(&flash->lock);
623 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
625 struct m25p *flash = mtd_to_m25p(mtd);
626 uint32_t offset = ofs;
627 uint8_t status_old, status_new;
630 mutex_lock(&flash->lock);
631 /* Wait until finished previous command */
632 if (wait_till_ready(flash)) {
637 status_old = read_sr(flash);
639 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
640 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
641 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
642 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
643 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
644 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
645 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
646 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
647 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
648 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
649 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
650 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
652 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
654 /* Only modify protection if it will not lock other areas */
655 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
656 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
658 if (write_sr(flash, status_new) < 0) {
664 err: mutex_unlock(&flash->lock);
668 /****************************************************************************/
671 * SPI device driver setup and teardown
675 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
676 * a high byte of zero plus three data bytes: the manufacturer id,
677 * then a two byte device id.
682 /* The size listed here is what works with OPCODE_SE, which isn't
683 * necessarily called a "sector" by the vendor.
685 unsigned sector_size;
692 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
693 #define M25P_NO_ERASE 0x02 /* No erase command needed */
694 #define SST_WRITE 0x04 /* use SST byte programming */
695 #define M25P_NO_FR 0x08 /* Can't do fastread */
696 #define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
699 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
700 ((kernel_ulong_t)&(struct flash_info) { \
701 .jedec_id = (_jedec_id), \
702 .ext_id = (_ext_id), \
703 .sector_size = (_sector_size), \
704 .n_sectors = (_n_sectors), \
709 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
710 ((kernel_ulong_t)&(struct flash_info) { \
711 .sector_size = (_sector_size), \
712 .n_sectors = (_n_sectors), \
713 .page_size = (_page_size), \
714 .addr_width = (_addr_width), \
718 /* NOTE: double check command sets and memory organization when you add
719 * more flash chips. This current list focusses on newer chips, which
720 * have been converging on command sets which including JEDEC ID.
722 static const struct spi_device_id m25p_ids[] = {
723 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
724 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
725 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
727 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
728 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
729 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
731 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
732 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
733 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
734 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
736 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
739 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
740 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
741 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
742 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
743 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
744 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
747 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
748 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
751 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
752 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
754 /* Intel/Numonyx -- xxxs33b */
755 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
756 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
757 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
760 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
761 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
762 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
763 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
764 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
765 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
766 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
767 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
768 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
769 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
770 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
773 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
774 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
775 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
776 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
779 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
780 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
781 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
783 /* Spansion -- single (large) sector size only, at least
784 * for the chips listed here (without boot sectors).
786 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
787 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
788 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
789 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
790 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
791 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
792 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
793 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
794 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
795 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
796 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
797 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
798 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
799 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
800 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
801 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
802 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
804 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
805 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
806 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
807 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
808 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
809 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
810 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
811 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
812 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
813 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
815 /* ST Microelectronics -- newer production may have feature updates */
816 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
817 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
818 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
819 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
820 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
821 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
822 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
823 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
824 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
825 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
827 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
828 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
829 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
830 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
831 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
832 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
833 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
834 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
835 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
837 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
838 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
839 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
841 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
842 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
843 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
845 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
846 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
847 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
848 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
850 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
851 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
852 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
853 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
854 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
855 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
856 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
857 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
858 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
859 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
860 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
861 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
862 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
863 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
864 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
865 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
867 /* Catalyst / On Semiconductor -- non-JEDEC */
868 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) },
869 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) },
870 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
871 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
872 { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) },
875 MODULE_DEVICE_TABLE(spi, m25p_ids);
877 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
880 u8 code = OPCODE_RDID;
884 struct flash_info *info;
886 /* JEDEC also defines an optional "extended device information"
887 * string for after vendor-specific data, after the three bytes
888 * we use here. Supporting some chips might require using it.
890 tmp = spi_write_then_read(spi, &code, 1, id, 5);
892 pr_debug("%s: error %d reading JEDEC ID\n",
893 dev_name(&spi->dev), tmp);
902 ext_jedec = id[3] << 8 | id[4];
904 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
905 info = (void *)m25p_ids[tmp].driver_data;
906 if (info->jedec_id == jedec) {
907 if (info->ext_id != 0 && info->ext_id != ext_jedec)
909 return &m25p_ids[tmp];
912 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
913 return ERR_PTR(-ENODEV);
918 * board specific setup should have ensured the SPI clock used here
919 * matches what the READ command supports, at least until this driver
920 * understands FAST_READ (for clocks over 25 MHz).
922 static int m25p_probe(struct spi_device *spi)
924 const struct spi_device_id *id = spi_get_device_id(spi);
925 struct flash_platform_data *data;
927 struct flash_info *info;
929 struct mtd_part_parser_data ppdata;
930 struct device_node __maybe_unused *np = spi->dev.of_node;
932 #ifdef CONFIG_MTD_OF_PARTS
933 if (!of_device_is_available(np))
937 /* Platform data helps sort out which chip type we have, as
938 * well as how this board partitions it. If we don't have
939 * a chip ID, try the JEDEC id commands; they'll work for most
940 * newer chips, even if we don't recognize the particular chip.
942 data = dev_get_platdata(&spi->dev);
943 if (data && data->type) {
944 const struct spi_device_id *plat_id;
946 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
947 plat_id = &m25p_ids[i];
948 if (strcmp(data->type, plat_id->name))
953 if (i < ARRAY_SIZE(m25p_ids) - 1)
956 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
959 info = (void *)id->driver_data;
961 if (info->jedec_id) {
962 const struct spi_device_id *jid;
964 jid = jedec_probe(spi);
967 } else if (jid != id) {
969 * JEDEC knows better, so overwrite platform ID. We
970 * can't trust partitions any longer, but we'll let
971 * mtd apply them anyway, since some partitions may be
972 * marked read-only, and we don't want to lose that
973 * information, even if it's not 100% accurate.
975 dev_warn(&spi->dev, "found %s, expected %s\n",
976 jid->name, id->name);
978 info = (void *)jid->driver_data;
982 flash = kzalloc(sizeof *flash, GFP_KERNEL);
985 flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0),
987 if (!flash->command) {
993 mutex_init(&flash->lock);
994 spi_set_drvdata(spi, flash);
997 * Atmel, SST and Intel/Numonyx serial flash tend to power
998 * up with the software protection bits set
1001 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
1002 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
1003 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
1004 write_enable(flash);
1008 if (data && data->name)
1009 flash->mtd.name = data->name;
1011 flash->mtd.name = dev_name(&spi->dev);
1013 flash->mtd.type = MTD_NORFLASH;
1014 flash->mtd.writesize = 1;
1015 flash->mtd.flags = MTD_CAP_NORFLASH;
1016 flash->mtd.size = info->sector_size * info->n_sectors;
1017 flash->mtd._erase = m25p80_erase;
1018 flash->mtd._read = m25p80_read;
1020 /* flash protection support for STmicro chips */
1021 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1022 flash->mtd._lock = m25p80_lock;
1023 flash->mtd._unlock = m25p80_unlock;
1026 /* sst flash chips use AAI word program */
1027 if (info->flags & SST_WRITE)
1028 flash->mtd._write = sst_write;
1030 flash->mtd._write = m25p80_write;
1032 /* prefer "small sector" erase if possible */
1033 if (info->flags & SECT_4K) {
1034 flash->erase_opcode = OPCODE_BE_4K;
1035 flash->mtd.erasesize = 4096;
1036 } else if (info->flags & SECT_4K_PMC) {
1037 flash->erase_opcode = OPCODE_BE_4K_PMC;
1038 flash->mtd.erasesize = 4096;
1040 flash->erase_opcode = OPCODE_SE;
1041 flash->mtd.erasesize = info->sector_size;
1044 if (info->flags & M25P_NO_ERASE)
1045 flash->mtd.flags |= MTD_NO_ERASE;
1047 ppdata.of_node = spi->dev.of_node;
1048 flash->mtd.dev.parent = &spi->dev;
1049 flash->page_size = info->page_size;
1050 flash->mtd.writebufsize = flash->page_size;
1052 flash->fast_read = false;
1053 if (np && of_property_read_bool(np, "m25p,fast-read"))
1054 flash->fast_read = true;
1056 #ifdef CONFIG_M25PXX_USE_FAST_READ
1057 flash->fast_read = true;
1059 if (info->flags & M25P_NO_FR)
1060 flash->fast_read = false;
1062 /* Default commands */
1063 if (flash->fast_read)
1064 flash->read_opcode = OPCODE_FAST_READ;
1066 flash->read_opcode = OPCODE_NORM_READ;
1068 flash->program_opcode = OPCODE_PP;
1070 if (info->addr_width)
1071 flash->addr_width = info->addr_width;
1072 else if (flash->mtd.size > 0x1000000) {
1073 /* enable 4-byte addressing if the device exceeds 16MiB */
1074 flash->addr_width = 4;
1075 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1076 /* Dedicated 4-byte command set */
1077 flash->read_opcode = flash->fast_read ?
1078 OPCODE_FAST_READ_4B :
1079 OPCODE_NORM_READ_4B;
1080 flash->program_opcode = OPCODE_PP_4B;
1081 /* No small sector erase for 4-byte command set */
1082 flash->erase_opcode = OPCODE_SE_4B;
1083 flash->mtd.erasesize = info->sector_size;
1085 set_4byte(flash, info->jedec_id, 1);
1087 flash->addr_width = 3;
1090 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1091 (long long)flash->mtd.size >> 10);
1093 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1094 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1096 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1097 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1098 flash->mtd.numeraseregions);
1100 if (flash->mtd.numeraseregions)
1101 for (i = 0; i < flash->mtd.numeraseregions; i++)
1102 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1103 ".erasesize = 0x%.8x (%uKiB), "
1104 ".numblocks = %d }\n",
1105 i, (long long)flash->mtd.eraseregions[i].offset,
1106 flash->mtd.eraseregions[i].erasesize,
1107 flash->mtd.eraseregions[i].erasesize / 1024,
1108 flash->mtd.eraseregions[i].numblocks);
1111 /* partitions should match sector boundaries; and it may be good to
1112 * use readonly partitions for writeprotected sectors (BP2..BP0).
1114 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1115 data ? data->parts : NULL,
1116 data ? data->nr_parts : 0);
1120 static int m25p_remove(struct spi_device *spi)
1122 struct m25p *flash = spi_get_drvdata(spi);
1125 /* Clean up MTD stuff. */
1126 status = mtd_device_unregister(&flash->mtd);
1128 kfree(flash->command);
1135 static struct spi_driver m25p80_driver = {
1138 .owner = THIS_MODULE,
1140 .id_table = m25p_ids,
1141 .probe = m25p_probe,
1142 .remove = m25p_remove,
1144 /* REVISIT: many of these chips have deep power-down modes, which
1145 * should clearly be entered on suspend() to minimize power use.
1146 * And also when they're otherwise idle...
1150 module_spi_driver(m25p80_driver);
1152 MODULE_LICENSE("GPL");
1153 MODULE_AUTHOR("Mike Lavender");
1154 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");