2 * Copyright © 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License version 2 as
23 * published by the Free Software Foundation.
27 #include <linux/dma-mapping.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/platform_device.h>
33 #include <linux/of_device.h>
34 #include <linux/of_gpio.h>
35 #include <linux/of_mtd.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/partitions.h>
40 #include <linux/dmaengine.h>
41 #include <linux/gpio.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/pinctrl/consumer.h>
48 static int use_dma = 1;
49 module_param(use_dma, int, 0);
51 static int on_flash_bbt = 0;
52 module_param(on_flash_bbt, int, 0);
54 /* Register access macros */
55 #define ecc_readl(add, reg) \
56 __raw_readl(add + ATMEL_ECC_##reg)
57 #define ecc_writel(add, reg, value) \
58 __raw_writel((value), add + ATMEL_ECC_##reg)
60 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
62 /* oob layout for large page size
63 * bad block info is on bytes 0 and 1
64 * the bytes have to be consecutives to avoid
65 * several NAND_CMD_RNDOUT during read
67 static struct nand_ecclayout atmel_oobinfo_large = {
69 .eccpos = {60, 61, 62, 63},
75 /* oob layout for small page size
76 * bad block info is on bytes 4 and 5
77 * the bytes have to be consecutives to avoid
78 * several NAND_CMD_RNDOUT during read
80 static struct nand_ecclayout atmel_oobinfo_small = {
82 .eccpos = {0, 1, 2, 3},
88 struct atmel_nand_host {
89 struct nand_chip nand_chip;
91 void __iomem *io_base;
93 struct atmel_nand_data board;
97 struct completion comp;
98 struct dma_chan *dma_chan;
102 u16 pmecc_sector_size;
103 u32 pmecc_lookup_table_offset;
105 int pmecc_bytes_per_sector;
106 int pmecc_sector_number;
107 int pmecc_degree; /* Degree of remainders */
108 int pmecc_cw_len; /* Length of codeword */
110 void __iomem *pmerrloc_base;
111 void __iomem *pmecc_rom_base;
113 /* lookup table for alpha_to and index_of */
114 void __iomem *pmecc_alpha_to;
115 void __iomem *pmecc_index_of;
117 /* data for pmecc computation */
118 int16_t *pmecc_partial_syn;
120 int16_t *pmecc_smu; /* Sigma table */
121 int16_t *pmecc_lmu; /* polynomal order */
127 static struct nand_ecclayout atmel_pmecc_oobinfo;
129 static int cpu_has_dma(void)
131 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
137 static void atmel_nand_enable(struct atmel_nand_host *host)
139 if (gpio_is_valid(host->board.enable_pin))
140 gpio_set_value(host->board.enable_pin, 0);
146 static void atmel_nand_disable(struct atmel_nand_host *host)
148 if (gpio_is_valid(host->board.enable_pin))
149 gpio_set_value(host->board.enable_pin, 1);
153 * Hardware specific access to control-lines
155 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
157 struct nand_chip *nand_chip = mtd->priv;
158 struct atmel_nand_host *host = nand_chip->priv;
160 if (ctrl & NAND_CTRL_CHANGE) {
162 atmel_nand_enable(host);
164 atmel_nand_disable(host);
166 if (cmd == NAND_CMD_NONE)
170 writeb(cmd, host->io_base + (1 << host->board.cle));
172 writeb(cmd, host->io_base + (1 << host->board.ale));
176 * Read the Device Ready pin.
178 static int atmel_nand_device_ready(struct mtd_info *mtd)
180 struct nand_chip *nand_chip = mtd->priv;
181 struct atmel_nand_host *host = nand_chip->priv;
183 return gpio_get_value(host->board.rdy_pin) ^
184 !!host->board.rdy_pin_active_low;
188 * Minimal-overhead PIO for data access.
190 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
192 struct nand_chip *nand_chip = mtd->priv;
194 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
197 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
199 struct nand_chip *nand_chip = mtd->priv;
201 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
204 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
206 struct nand_chip *nand_chip = mtd->priv;
208 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
211 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
213 struct nand_chip *nand_chip = mtd->priv;
215 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
218 static void dma_complete_func(void *completion)
220 complete(completion);
223 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
226 struct dma_device *dma_dev;
227 enum dma_ctrl_flags flags;
228 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
229 struct dma_async_tx_descriptor *tx = NULL;
231 struct nand_chip *chip = mtd->priv;
232 struct atmel_nand_host *host = chip->priv;
235 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
237 if (buf >= high_memory)
240 dma_dev = host->dma_chan->device;
242 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
243 DMA_COMPL_SKIP_DEST_UNMAP;
245 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
246 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
247 dev_err(host->dev, "Failed to dma_map_single\n");
252 dma_src_addr = host->io_phys;
253 dma_dst_addr = phys_addr;
255 dma_src_addr = phys_addr;
256 dma_dst_addr = host->io_phys;
259 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
260 dma_src_addr, len, flags);
262 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
266 init_completion(&host->comp);
267 tx->callback = dma_complete_func;
268 tx->callback_param = &host->comp;
270 cookie = tx->tx_submit(tx);
271 if (dma_submit_error(cookie)) {
272 dev_err(host->dev, "Failed to do DMA tx_submit\n");
276 dma_async_issue_pending(host->dma_chan);
277 wait_for_completion(&host->comp);
282 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
285 dev_warn(host->dev, "Fall back to CPU I/O\n");
289 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
291 struct nand_chip *chip = mtd->priv;
292 struct atmel_nand_host *host = chip->priv;
294 if (use_dma && len > mtd->oobsize)
295 /* only use DMA for bigger than oob size: better performances */
296 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
299 if (host->board.bus_width_16)
300 atmel_read_buf16(mtd, buf, len);
302 atmel_read_buf8(mtd, buf, len);
305 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
307 struct nand_chip *chip = mtd->priv;
308 struct atmel_nand_host *host = chip->priv;
310 if (use_dma && len > mtd->oobsize)
311 /* only use DMA for bigger than oob size: better performances */
312 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
315 if (host->board.bus_width_16)
316 atmel_write_buf16(mtd, buf, len);
318 atmel_write_buf8(mtd, buf, len);
322 * Return number of ecc bytes per sector according to sector size and
323 * correction capability
325 * Following table shows what at91 PMECC supported:
326 * Correction Capability Sector_512_bytes Sector_1024_bytes
327 * ===================== ================ =================
328 * 2-bits 4-bytes 4-bytes
329 * 4-bits 7-bytes 7-bytes
330 * 8-bits 13-bytes 14-bytes
331 * 12-bits 20-bytes 21-bytes
332 * 24-bits 39-bytes 42-bytes
334 static int __devinit pmecc_get_ecc_bytes(int cap, int sector_size)
336 int m = 12 + sector_size / 512;
337 return (m * cap + 7) / 8;
340 static void __devinit pmecc_config_ecc_layout(struct nand_ecclayout *layout,
341 int oobsize, int ecc_len)
345 layout->eccbytes = ecc_len;
347 /* ECC will occupy the last ecc_len bytes continuously */
348 for (i = 0; i < ecc_len; i++)
349 layout->eccpos[i] = oobsize - ecc_len + i;
351 layout->oobfree[0].offset = 2;
352 layout->oobfree[0].length =
353 oobsize - ecc_len - layout->oobfree[0].offset;
356 static void __devinit __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
360 table_size = host->pmecc_sector_size == 512 ?
361 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
363 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
364 table_size * sizeof(int16_t);
367 static void pmecc_data_free(struct atmel_nand_host *host)
369 kfree(host->pmecc_partial_syn);
370 kfree(host->pmecc_si);
371 kfree(host->pmecc_lmu);
372 kfree(host->pmecc_smu);
373 kfree(host->pmecc_mu);
374 kfree(host->pmecc_dmu);
375 kfree(host->pmecc_delta);
378 static int __devinit pmecc_data_alloc(struct atmel_nand_host *host)
380 const int cap = host->pmecc_corr_cap;
382 host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
384 host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
385 host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
386 host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
388 host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
389 host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
390 host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
392 if (host->pmecc_partial_syn &&
402 pmecc_data_free(host);
406 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
408 struct nand_chip *nand_chip = mtd->priv;
409 struct atmel_nand_host *host = nand_chip->priv;
413 /* Fill odd syndromes */
414 for (i = 0; i < host->pmecc_corr_cap; i++) {
415 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
419 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
423 static void pmecc_substitute(struct mtd_info *mtd)
425 struct nand_chip *nand_chip = mtd->priv;
426 struct atmel_nand_host *host = nand_chip->priv;
427 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
428 int16_t __iomem *index_of = host->pmecc_index_of;
429 int16_t *partial_syn = host->pmecc_partial_syn;
430 const int cap = host->pmecc_corr_cap;
434 /* si[] is a table that holds the current syndrome value,
435 * an element of that table belongs to the field
439 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
441 /* Computation 2t syndromes based on S(x) */
443 for (i = 1; i < 2 * cap; i += 2) {
444 for (j = 0; j < host->pmecc_degree; j++) {
445 if (partial_syn[i] & ((unsigned short)0x1 << j))
446 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
449 /* Even syndrome = (Odd syndrome) ** 2 */
450 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
456 tmp = readw_relaxed(index_of + si[j]);
457 tmp = (tmp * 2) % host->pmecc_cw_len;
458 si[i] = readw_relaxed(alpha_to + tmp);
465 static void pmecc_get_sigma(struct mtd_info *mtd)
467 struct nand_chip *nand_chip = mtd->priv;
468 struct atmel_nand_host *host = nand_chip->priv;
470 int16_t *lmu = host->pmecc_lmu;
471 int16_t *si = host->pmecc_si;
472 int *mu = host->pmecc_mu;
473 int *dmu = host->pmecc_dmu; /* Discrepancy */
474 int *delta = host->pmecc_delta; /* Delta order */
475 int cw_len = host->pmecc_cw_len;
476 const int16_t cap = host->pmecc_corr_cap;
477 const int num = 2 * cap + 1;
478 int16_t __iomem *index_of = host->pmecc_index_of;
479 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
481 uint32_t dmu_0_count, tmp;
482 int16_t *smu = host->pmecc_smu;
484 /* index of largest delta */
496 memset(smu, 0, sizeof(int16_t) * num);
499 /* discrepancy set to 1 */
501 /* polynom order set to 0 */
503 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
509 /* Sigma(x) set to 1 */
510 memset(&smu[num], 0, sizeof(int16_t) * num);
513 /* discrepancy set to S1 */
516 /* polynom order set to 0 */
519 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
521 /* Init the Sigma(x) last row */
522 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
524 for (i = 1; i <= cap; i++) {
526 /* Begin Computing Sigma (Mu+1) and L(mu) */
527 /* check if discrepancy is set to 0 */
531 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
532 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
537 if (dmu_0_count == tmp) {
538 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
539 smu[(cap + 1) * num + j] =
542 lmu[cap + 1] = lmu[i];
547 for (j = 0; j <= lmu[i] >> 1; j++)
548 smu[(i + 1) * num + j] = smu[i * num + j];
550 /* copy previous polynom order to the next */
555 /* find largest delta with dmu != 0 */
556 for (j = 0; j < i; j++) {
557 if ((dmu[j]) && (delta[j] > largest)) {
563 /* compute difference */
564 diff = (mu[i] - mu[ro]);
566 /* Compute degree of the new smu polynomial */
567 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
570 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
572 /* Init smu[i+1] with 0 */
573 for (k = 0; k < num; k++)
574 smu[(i + 1) * num + k] = 0;
576 /* Compute smu[i+1] */
577 for (k = 0; k <= lmu[ro] >> 1; k++) {
580 if (!(smu[ro * num + k] && dmu[i]))
582 a = readw_relaxed(index_of + dmu[i]);
583 b = readw_relaxed(index_of + dmu[ro]);
584 c = readw_relaxed(index_of + smu[ro * num + k]);
585 tmp = a + (cw_len - b) + c;
586 a = readw_relaxed(alpha_to + tmp % cw_len);
587 smu[(i + 1) * num + (k + diff)] = a;
590 for (k = 0; k <= lmu[i] >> 1; k++)
591 smu[(i + 1) * num + k] ^= smu[i * num + k];
594 /* End Computing Sigma (Mu+1) and L(mu) */
595 /* In either case compute delta */
596 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
598 /* Do not compute discrepancy for the last iteration */
602 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
605 dmu[i + 1] = si[tmp + 3];
606 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
608 a = readw_relaxed(index_of +
609 smu[(i + 1) * num + k]);
610 b = si[2 * (i - 1) + 3 - k];
611 c = readw_relaxed(index_of + b);
614 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
623 static int pmecc_err_location(struct mtd_info *mtd)
625 struct nand_chip *nand_chip = mtd->priv;
626 struct atmel_nand_host *host = nand_chip->priv;
627 unsigned long end_time;
628 const int cap = host->pmecc_corr_cap;
629 const int num = 2 * cap + 1;
630 int sector_size = host->pmecc_sector_size;
631 int err_nbr = 0; /* number of error */
632 int roots_nbr; /* number of roots */
635 int16_t *smu = host->pmecc_smu;
637 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
639 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
640 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
641 smu[(cap + 1) * num + i]);
645 val = (err_nbr - 1) << 16;
646 if (sector_size == 1024)
649 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
650 pmerrloc_writel(host->pmerrloc_base, ELEN,
651 sector_size * 8 + host->pmecc_degree * cap);
653 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
654 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
655 & PMERRLOC_CALC_DONE)) {
656 if (unlikely(time_after(jiffies, end_time))) {
657 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
663 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
664 & PMERRLOC_ERR_NUM_MASK) >> 8;
665 /* Number of roots == degree of smu hence <= cap */
666 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
669 /* Number of roots does not match the degree of smu
670 * unable to correct error */
674 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
675 int sector_num, int extra_bytes, int err_nbr)
677 struct nand_chip *nand_chip = mtd->priv;
678 struct atmel_nand_host *host = nand_chip->priv;
680 int byte_pos, bit_pos, sector_size, pos;
684 sector_size = host->pmecc_sector_size;
687 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
691 if (byte_pos >= (sector_size + extra_bytes))
692 BUG(); /* should never happen */
694 if (byte_pos < sector_size) {
695 err_byte = *(buf + byte_pos);
696 *(buf + byte_pos) ^= (1 << bit_pos);
698 pos = sector_num * host->pmecc_sector_size + byte_pos;
699 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
700 pos, bit_pos, err_byte, *(buf + byte_pos));
702 /* Bit flip in OOB area */
703 tmp = sector_num * host->pmecc_bytes_per_sector
704 + (byte_pos - sector_size);
706 ecc[tmp] ^= (1 << bit_pos);
708 pos = tmp + nand_chip->ecc.layout->eccpos[0];
709 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
710 pos, bit_pos, err_byte, ecc[tmp]);
720 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
723 struct nand_chip *nand_chip = mtd->priv;
724 struct atmel_nand_host *host = nand_chip->priv;
725 int i, err_nbr, eccbytes;
728 eccbytes = nand_chip->ecc.bytes;
729 for (i = 0; i < eccbytes; i++)
732 /* Erased page, return OK */
736 for (i = 0; i < host->pmecc_sector_number; i++) {
738 if (pmecc_stat & 0x1) {
739 buf_pos = buf + i * host->pmecc_sector_size;
741 pmecc_gen_syndrome(mtd, i);
742 pmecc_substitute(mtd);
743 pmecc_get_sigma(mtd);
745 err_nbr = pmecc_err_location(mtd);
747 dev_err(host->dev, "PMECC: Too many errors\n");
748 mtd->ecc_stats.failed++;
751 pmecc_correct_data(mtd, buf_pos, ecc, i,
752 host->pmecc_bytes_per_sector, err_nbr);
753 mtd->ecc_stats.corrected += err_nbr;
762 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
763 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
765 struct atmel_nand_host *host = chip->priv;
766 int eccsize = chip->ecc.size;
767 uint8_t *oob = chip->oob_poi;
768 uint32_t *eccpos = chip->ecc.layout->eccpos;
770 unsigned long end_time;
772 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
773 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
774 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
775 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
777 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
778 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
780 chip->read_buf(mtd, buf, eccsize);
781 chip->read_buf(mtd, oob, mtd->oobsize);
783 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
784 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
785 if (unlikely(time_after(jiffies, end_time))) {
786 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
792 stat = pmecc_readl_relaxed(host->ecc, ISR);
794 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
800 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
801 struct nand_chip *chip, const uint8_t *buf, int oob_required)
803 struct atmel_nand_host *host = chip->priv;
804 uint32_t *eccpos = chip->ecc.layout->eccpos;
806 unsigned long end_time;
808 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
809 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
811 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
812 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
814 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
815 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
817 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
819 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
820 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
821 if (unlikely(time_after(jiffies, end_time))) {
822 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
828 for (i = 0; i < host->pmecc_sector_number; i++) {
829 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
832 pos = i * host->pmecc_bytes_per_sector + j;
833 chip->oob_poi[eccpos[pos]] =
834 pmecc_readb_ecc_relaxed(host->ecc, i, j);
837 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
842 static void atmel_pmecc_core_init(struct mtd_info *mtd)
844 struct nand_chip *nand_chip = mtd->priv;
845 struct atmel_nand_host *host = nand_chip->priv;
847 struct nand_ecclayout *ecc_layout;
849 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
850 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
852 switch (host->pmecc_corr_cap) {
854 val = PMECC_CFG_BCH_ERR2;
857 val = PMECC_CFG_BCH_ERR4;
860 val = PMECC_CFG_BCH_ERR8;
863 val = PMECC_CFG_BCH_ERR12;
866 val = PMECC_CFG_BCH_ERR24;
870 if (host->pmecc_sector_size == 512)
871 val |= PMECC_CFG_SECTOR512;
872 else if (host->pmecc_sector_size == 1024)
873 val |= PMECC_CFG_SECTOR1024;
875 switch (host->pmecc_sector_number) {
877 val |= PMECC_CFG_PAGE_1SECTOR;
880 val |= PMECC_CFG_PAGE_2SECTORS;
883 val |= PMECC_CFG_PAGE_4SECTORS;
886 val |= PMECC_CFG_PAGE_8SECTORS;
890 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
891 | PMECC_CFG_AUTO_DISABLE);
892 pmecc_writel(host->ecc, CFG, val);
894 ecc_layout = nand_chip->ecc.layout;
895 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
896 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
897 pmecc_writel(host->ecc, EADDR,
898 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
899 /* See datasheet about PMECC Clock Control Register */
900 pmecc_writel(host->ecc, CLK, 2);
901 pmecc_writel(host->ecc, IDR, 0xff);
902 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
905 static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
906 struct atmel_nand_host *host)
908 struct mtd_info *mtd = &host->mtd;
909 struct nand_chip *nand_chip = &host->nand_chip;
910 struct resource *regs, *regs_pmerr, *regs_rom;
911 int cap, sector_size, err_no;
913 cap = host->pmecc_corr_cap;
914 sector_size = host->pmecc_sector_size;
915 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
918 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
921 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
922 nand_chip->ecc.mode = NAND_ECC_SOFT;
926 host->ecc = ioremap(regs->start, resource_size(regs));
927 if (host->ecc == NULL) {
928 dev_err(host->dev, "ioremap failed\n");
930 goto err_pmecc_ioremap;
933 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
934 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
935 if (regs_pmerr && regs_rom) {
936 host->pmerrloc_base = ioremap(regs_pmerr->start,
937 resource_size(regs_pmerr));
938 host->pmecc_rom_base = ioremap(regs_rom->start,
939 resource_size(regs_rom));
942 if (!host->pmerrloc_base || !host->pmecc_rom_base) {
944 "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
946 goto err_pmloc_ioremap;
949 /* ECC is calculated for the whole page (1 step) */
950 nand_chip->ecc.size = mtd->writesize;
952 /* set ECC page size and oob layout */
953 switch (mtd->writesize) {
955 host->pmecc_degree = PMECC_GF_DIMENSION_13;
956 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
957 host->pmecc_sector_number = mtd->writesize / sector_size;
958 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
960 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
961 host->pmecc_index_of = host->pmecc_rom_base +
962 host->pmecc_lookup_table_offset;
964 nand_chip->ecc.steps = 1;
965 nand_chip->ecc.strength = cap;
966 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
967 host->pmecc_sector_number;
968 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
969 dev_err(host->dev, "No room for ECC bytes\n");
971 goto err_no_ecc_room;
973 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
975 nand_chip->ecc.bytes);
976 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
983 "Unsupported page size for PMECC, use Software ECC\n");
985 /* page size not handled by HW ECC */
986 /* switching back to soft ECC */
987 nand_chip->ecc.mode = NAND_ECC_SOFT;
991 /* Allocate data for PMECC computation */
992 err_no = pmecc_data_alloc(host);
995 "Cannot allocate memory for PMECC computation!\n");
996 goto err_pmecc_data_alloc;
999 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1000 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1002 atmel_pmecc_core_init(mtd);
1006 err_pmecc_data_alloc:
1010 if (host->pmerrloc_base)
1011 iounmap(host->pmerrloc_base);
1012 if (host->pmecc_rom_base)
1013 iounmap(host->pmecc_rom_base);
1021 * function called after a write
1023 * mtd: MTD block structure
1024 * dat: raw data (unused)
1025 * ecc_code: buffer for ECC
1027 static int atmel_nand_calculate(struct mtd_info *mtd,
1028 const u_char *dat, unsigned char *ecc_code)
1030 struct nand_chip *nand_chip = mtd->priv;
1031 struct atmel_nand_host *host = nand_chip->priv;
1032 unsigned int ecc_value;
1034 /* get the first 2 ECC bytes */
1035 ecc_value = ecc_readl(host->ecc, PR);
1037 ecc_code[0] = ecc_value & 0xFF;
1038 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1040 /* get the last 2 ECC bytes */
1041 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1043 ecc_code[2] = ecc_value & 0xFF;
1044 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1050 * HW ECC read page function
1052 * mtd: mtd info structure
1053 * chip: nand chip info structure
1054 * buf: buffer to store read data
1055 * oob_required: caller expects OOB data read to chip->oob_poi
1057 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1058 uint8_t *buf, int oob_required, int page)
1060 int eccsize = chip->ecc.size;
1061 int eccbytes = chip->ecc.bytes;
1062 uint32_t *eccpos = chip->ecc.layout->eccpos;
1064 uint8_t *oob = chip->oob_poi;
1067 unsigned int max_bitflips = 0;
1070 * Errata: ALE is incorrectly wired up to the ECC controller
1071 * on the AP7000, so it will include the address cycles in the
1074 * Workaround: Reset the parity registers before reading the
1077 if (cpu_is_at32ap7000()) {
1078 struct atmel_nand_host *host = chip->priv;
1079 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1083 chip->read_buf(mtd, p, eccsize);
1085 /* move to ECC position if needed */
1086 if (eccpos[0] != 0) {
1087 /* This only works on large pages
1088 * because the ECC controller waits for
1089 * NAND_CMD_RNDOUTSTART after the
1091 * anyway, for small pages, the eccpos[0] == 0
1093 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1094 mtd->writesize + eccpos[0], -1);
1097 /* the ECC controller needs to read the ECC just after the data */
1098 ecc_pos = oob + eccpos[0];
1099 chip->read_buf(mtd, ecc_pos, eccbytes);
1101 /* check if there's an error */
1102 stat = chip->ecc.correct(mtd, p, oob, NULL);
1105 mtd->ecc_stats.failed++;
1107 mtd->ecc_stats.corrected += stat;
1108 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1111 /* get back to oob start (end of page) */
1112 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1115 chip->read_buf(mtd, oob, mtd->oobsize);
1117 return max_bitflips;
1123 * function called after a read
1125 * mtd: MTD block structure
1126 * dat: raw data read from the chip
1127 * read_ecc: ECC from the chip (unused)
1130 * Detect and correct a 1 bit error for a page
1132 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1133 u_char *read_ecc, u_char *isnull)
1135 struct nand_chip *nand_chip = mtd->priv;
1136 struct atmel_nand_host *host = nand_chip->priv;
1137 unsigned int ecc_status;
1138 unsigned int ecc_word, ecc_bit;
1140 /* get the status from the Status Register */
1141 ecc_status = ecc_readl(host->ecc, SR);
1143 /* if there's no error */
1144 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1147 /* get error bit offset (4 bits) */
1148 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1149 /* get word address (12 bits) */
1150 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1153 /* if there are multiple errors */
1154 if (ecc_status & ATMEL_ECC_MULERR) {
1155 /* check if it is a freshly erased block
1156 * (filled with 0xff) */
1157 if ((ecc_bit == ATMEL_ECC_BITADDR)
1158 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1159 /* the block has just been erased, return OK */
1162 /* it doesn't seems to be a freshly
1164 * We can't correct so many errors */
1165 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1166 " Unable to correct.\n");
1170 /* if there's a single bit error : we can correct it */
1171 if (ecc_status & ATMEL_ECC_ECCERR) {
1172 /* there's nothing much to do here.
1173 * the bit error is on the ECC itself.
1175 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1176 " Nothing to correct\n");
1180 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1181 " (word offset in the page :"
1182 " 0x%x bit offset : 0x%x)\n",
1184 /* correct the error */
1185 if (nand_chip->options & NAND_BUSWIDTH_16) {
1187 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1190 dat[ecc_word] ^= (1 << ecc_bit);
1192 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1197 * Enable HW ECC : unused on most chips
1199 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1201 if (cpu_is_at32ap7000()) {
1202 struct nand_chip *nand_chip = mtd->priv;
1203 struct atmel_nand_host *host = nand_chip->priv;
1204 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1208 #if defined(CONFIG_OF)
1209 static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
1210 struct device_node *np)
1212 u32 val, table_offset;
1215 struct atmel_nand_data *board = &host->board;
1216 enum of_gpio_flags flags;
1218 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1220 dev_err(host->dev, "invalid addr-offset %u\n", val);
1226 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1228 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1234 ecc_mode = of_get_nand_ecc_mode(np);
1236 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1238 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1240 if (of_get_nand_bus_width(np) == 16)
1241 board->bus_width_16 = 1;
1243 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1244 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1246 board->enable_pin = of_get_gpio(np, 1);
1247 board->det_pin = of_get_gpio(np, 2);
1249 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1251 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1252 return 0; /* Not using PMECC */
1254 /* use PMECC, get correction capability, sector size and lookup
1257 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) != 0) {
1258 dev_err(host->dev, "Cannot decide PMECC Capability\n");
1260 } else if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1263 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1267 host->pmecc_corr_cap = (u8)val;
1269 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) != 0) {
1270 dev_err(host->dev, "Cannot decide PMECC Sector Size\n");
1272 } else if ((val != 512) && (val != 1024)) {
1274 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1278 host->pmecc_sector_size = (u16)val;
1280 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1282 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1285 table_offset = host->pmecc_sector_size == 512 ? offset[0] : offset[1];
1287 if (!table_offset) {
1288 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1291 host->pmecc_lookup_table_offset = table_offset;
1296 static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
1297 struct device_node *np)
1303 static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1304 struct atmel_nand_host *host)
1306 struct mtd_info *mtd = &host->mtd;
1307 struct nand_chip *nand_chip = &host->nand_chip;
1308 struct resource *regs;
1310 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1313 "Can't get I/O resource regs, use software ECC\n");
1314 nand_chip->ecc.mode = NAND_ECC_SOFT;
1318 host->ecc = ioremap(regs->start, resource_size(regs));
1319 if (host->ecc == NULL) {
1320 dev_err(host->dev, "ioremap failed\n");
1324 /* ECC is calculated for the whole page (1 step) */
1325 nand_chip->ecc.size = mtd->writesize;
1327 /* set ECC page size and oob layout */
1328 switch (mtd->writesize) {
1330 nand_chip->ecc.layout = &atmel_oobinfo_small;
1331 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1334 nand_chip->ecc.layout = &atmel_oobinfo_large;
1335 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1338 nand_chip->ecc.layout = &atmel_oobinfo_large;
1339 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1342 nand_chip->ecc.layout = &atmel_oobinfo_large;
1343 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1346 /* page size not handled by HW ECC */
1347 /* switching back to soft ECC */
1348 nand_chip->ecc.mode = NAND_ECC_SOFT;
1352 /* set up for HW ECC */
1353 nand_chip->ecc.calculate = atmel_nand_calculate;
1354 nand_chip->ecc.correct = atmel_nand_correct;
1355 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1356 nand_chip->ecc.read_page = atmel_nand_read_page;
1357 nand_chip->ecc.bytes = 4;
1358 nand_chip->ecc.strength = 1;
1364 * Probe for the NAND device.
1366 static int __init atmel_nand_probe(struct platform_device *pdev)
1368 struct atmel_nand_host *host;
1369 struct mtd_info *mtd;
1370 struct nand_chip *nand_chip;
1371 struct resource *mem;
1372 struct mtd_part_parser_data ppdata = {};
1374 struct pinctrl *pinctrl;
1376 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1378 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
1382 /* Allocate memory for the device structure (and zero it) */
1383 host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
1385 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
1389 host->io_phys = (dma_addr_t)mem->start;
1391 host->io_base = ioremap(mem->start, resource_size(mem));
1392 if (host->io_base == NULL) {
1393 printk(KERN_ERR "atmel_nand: ioremap failed\n");
1395 goto err_nand_ioremap;
1399 nand_chip = &host->nand_chip;
1400 host->dev = &pdev->dev;
1401 if (pdev->dev.of_node) {
1402 res = atmel_of_init_port(host, pdev->dev.of_node);
1404 goto err_ecc_ioremap;
1406 memcpy(&host->board, pdev->dev.platform_data,
1407 sizeof(struct atmel_nand_data));
1410 nand_chip->priv = host; /* link the private data structures */
1411 mtd->priv = nand_chip;
1412 mtd->owner = THIS_MODULE;
1414 /* Set address of NAND IO lines */
1415 nand_chip->IO_ADDR_R = host->io_base;
1416 nand_chip->IO_ADDR_W = host->io_base;
1417 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1419 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1420 if (IS_ERR(pinctrl)) {
1421 dev_err(host->dev, "Failed to request pinctrl\n");
1422 res = PTR_ERR(pinctrl);
1423 goto err_ecc_ioremap;
1426 if (gpio_is_valid(host->board.rdy_pin)) {
1427 res = gpio_request(host->board.rdy_pin, "nand_rdy");
1430 "can't request rdy gpio %d\n",
1431 host->board.rdy_pin);
1432 goto err_ecc_ioremap;
1435 res = gpio_direction_input(host->board.rdy_pin);
1438 "can't request input direction rdy gpio %d\n",
1439 host->board.rdy_pin);
1440 goto err_ecc_ioremap;
1443 nand_chip->dev_ready = atmel_nand_device_ready;
1446 if (gpio_is_valid(host->board.enable_pin)) {
1447 res = gpio_request(host->board.enable_pin, "nand_enable");
1450 "can't request enable gpio %d\n",
1451 host->board.enable_pin);
1452 goto err_ecc_ioremap;
1455 res = gpio_direction_output(host->board.enable_pin, 1);
1458 "can't request output direction enable gpio %d\n",
1459 host->board.enable_pin);
1460 goto err_ecc_ioremap;
1464 nand_chip->ecc.mode = host->board.ecc_mode;
1465 nand_chip->chip_delay = 20; /* 20us command delay time */
1467 if (host->board.bus_width_16) /* 16-bit bus width */
1468 nand_chip->options |= NAND_BUSWIDTH_16;
1470 nand_chip->read_buf = atmel_read_buf;
1471 nand_chip->write_buf = atmel_write_buf;
1473 platform_set_drvdata(pdev, host);
1474 atmel_nand_enable(host);
1476 if (gpio_is_valid(host->board.det_pin)) {
1477 res = gpio_request(host->board.det_pin, "nand_det");
1480 "can't request det gpio %d\n",
1481 host->board.det_pin);
1485 res = gpio_direction_input(host->board.det_pin);
1488 "can't request input direction det gpio %d\n",
1489 host->board.det_pin);
1493 if (gpio_get_value(host->board.det_pin)) {
1494 printk(KERN_INFO "No SmartMedia card inserted.\n");
1500 if (host->board.on_flash_bbt || on_flash_bbt) {
1501 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
1502 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
1509 dma_cap_mask_t mask;
1512 dma_cap_set(DMA_MEMCPY, mask);
1513 host->dma_chan = dma_request_channel(mask, NULL, NULL);
1514 if (!host->dma_chan) {
1515 dev_err(host->dev, "Failed to request DMA channel\n");
1520 dev_info(host->dev, "Using %s for DMA transfers.\n",
1521 dma_chan_name(host->dma_chan));
1523 dev_info(host->dev, "No DMA support for NAND access.\n");
1525 /* first scan to find the device and get the page size */
1526 if (nand_scan_ident(mtd, 1, NULL)) {
1528 goto err_scan_ident;
1531 if (nand_chip->ecc.mode == NAND_ECC_HW) {
1532 if (host->has_pmecc)
1533 res = atmel_pmecc_nand_init_params(pdev, host);
1535 res = atmel_hw_nand_init_params(pdev, host);
1541 /* second phase scan */
1542 if (nand_scan_tail(mtd)) {
1547 mtd->name = "atmel_nand";
1548 ppdata.of_node = pdev->dev.of_node;
1549 res = mtd_device_parse_register(mtd, NULL, &ppdata,
1550 host->board.parts, host->board.num_parts);
1555 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1556 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1557 pmecc_data_free(host);
1561 if (host->pmerrloc_base)
1562 iounmap(host->pmerrloc_base);
1563 if (host->pmecc_rom_base)
1564 iounmap(host->pmecc_rom_base);
1568 atmel_nand_disable(host);
1569 platform_set_drvdata(pdev, NULL);
1571 dma_release_channel(host->dma_chan);
1573 iounmap(host->io_base);
1580 * Remove a NAND device.
1582 static int __exit atmel_nand_remove(struct platform_device *pdev)
1584 struct atmel_nand_host *host = platform_get_drvdata(pdev);
1585 struct mtd_info *mtd = &host->mtd;
1589 atmel_nand_disable(host);
1591 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1592 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1593 pmerrloc_writel(host->pmerrloc_base, ELDIS,
1595 pmecc_data_free(host);
1598 if (gpio_is_valid(host->board.det_pin))
1599 gpio_free(host->board.det_pin);
1601 if (gpio_is_valid(host->board.enable_pin))
1602 gpio_free(host->board.enable_pin);
1604 if (gpio_is_valid(host->board.rdy_pin))
1605 gpio_free(host->board.rdy_pin);
1609 if (host->pmecc_rom_base)
1610 iounmap(host->pmecc_rom_base);
1611 if (host->pmerrloc_base)
1612 iounmap(host->pmerrloc_base);
1615 dma_release_channel(host->dma_chan);
1617 iounmap(host->io_base);
1623 #if defined(CONFIG_OF)
1624 static const struct of_device_id atmel_nand_dt_ids[] = {
1625 { .compatible = "atmel,at91rm9200-nand" },
1629 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
1632 static struct platform_driver atmel_nand_driver = {
1633 .remove = __exit_p(atmel_nand_remove),
1635 .name = "atmel_nand",
1636 .owner = THIS_MODULE,
1637 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
1641 static int __init atmel_nand_init(void)
1643 return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
1647 static void __exit atmel_nand_exit(void)
1649 platform_driver_unregister(&atmel_nand_driver);
1653 module_init(atmel_nand_init);
1654 module_exit(atmel_nand_exit);
1656 MODULE_LICENSE("GPL");
1657 MODULE_AUTHOR("Rick Bronson");
1658 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
1659 MODULE_ALIAS("platform:atmel_nand");