2 * Copyright © 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #include <linux/dma-mapping.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/of_mtd.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/partitions.h>
43 #include <linux/delay.h>
44 #include <linux/dmaengine.h>
45 #include <linux/gpio.h>
46 #include <linux/interrupt.h>
48 #include <linux/platform_data/atmel.h>
50 static int use_dma = 1;
51 module_param(use_dma, int, 0);
53 static int on_flash_bbt = 0;
54 module_param(on_flash_bbt, int, 0);
56 /* Register access macros */
57 #define ecc_readl(add, reg) \
58 __raw_readl(add + ATMEL_ECC_##reg)
59 #define ecc_writel(add, reg, value) \
60 __raw_writel((value), add + ATMEL_ECC_##reg)
62 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
63 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
65 /* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
70 static struct nand_ecclayout atmel_oobinfo_large = {
72 .eccpos = {60, 61, 62, 63},
78 /* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
83 static struct nand_ecclayout atmel_oobinfo_small = {
85 .eccpos = {0, 1, 2, 3},
92 void __iomem *base_cmd_regs;
93 void __iomem *hsmc_regs;
94 void __iomem *sram_bank0;
95 dma_addr_t sram_bank0_phys;
100 struct completion comp_nfc;
102 /* Point to the sram bank which include readed data via NFC */
103 void __iomem *data_in_sram;
104 bool will_write_sram;
106 static struct atmel_nfc nand_nfc;
108 struct atmel_nand_host {
109 struct nand_chip nand_chip;
111 void __iomem *io_base;
113 struct atmel_nand_data board;
117 struct completion comp;
118 struct dma_chan *dma_chan;
120 struct atmel_nfc *nfc;
124 u16 pmecc_sector_size;
125 u32 pmecc_lookup_table_offset;
126 u32 pmecc_lookup_table_offset_512;
127 u32 pmecc_lookup_table_offset_1024;
129 int pmecc_bytes_per_sector;
130 int pmecc_sector_number;
131 int pmecc_degree; /* Degree of remainders */
132 int pmecc_cw_len; /* Length of codeword */
134 void __iomem *pmerrloc_base;
135 void __iomem *pmecc_rom_base;
137 /* lookup table for alpha_to and index_of */
138 void __iomem *pmecc_alpha_to;
139 void __iomem *pmecc_index_of;
141 /* data for pmecc computation */
142 int16_t *pmecc_partial_syn;
144 int16_t *pmecc_smu; /* Sigma table */
145 int16_t *pmecc_lmu; /* polynomal order */
151 static struct nand_ecclayout atmel_pmecc_oobinfo;
156 static void atmel_nand_enable(struct atmel_nand_host *host)
158 if (gpio_is_valid(host->board.enable_pin))
159 gpio_set_value(host->board.enable_pin, 0);
165 static void atmel_nand_disable(struct atmel_nand_host *host)
167 if (gpio_is_valid(host->board.enable_pin))
168 gpio_set_value(host->board.enable_pin, 1);
172 * Hardware specific access to control-lines
174 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
176 struct nand_chip *nand_chip = mtd->priv;
177 struct atmel_nand_host *host = nand_chip->priv;
179 if (ctrl & NAND_CTRL_CHANGE) {
181 atmel_nand_enable(host);
183 atmel_nand_disable(host);
185 if (cmd == NAND_CMD_NONE)
189 writeb(cmd, host->io_base + (1 << host->board.cle));
191 writeb(cmd, host->io_base + (1 << host->board.ale));
195 * Read the Device Ready pin.
197 static int atmel_nand_device_ready(struct mtd_info *mtd)
199 struct nand_chip *nand_chip = mtd->priv;
200 struct atmel_nand_host *host = nand_chip->priv;
202 return gpio_get_value(host->board.rdy_pin) ^
203 !!host->board.rdy_pin_active_low;
206 /* Set up for hardware ready pin and enable pin. */
207 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
209 struct nand_chip *chip = mtd->priv;
210 struct atmel_nand_host *host = chip->priv;
213 if (gpio_is_valid(host->board.rdy_pin)) {
214 res = devm_gpio_request(host->dev,
215 host->board.rdy_pin, "nand_rdy");
218 "can't request rdy gpio %d\n",
219 host->board.rdy_pin);
223 res = gpio_direction_input(host->board.rdy_pin);
226 "can't request input direction rdy gpio %d\n",
227 host->board.rdy_pin);
231 chip->dev_ready = atmel_nand_device_ready;
234 if (gpio_is_valid(host->board.enable_pin)) {
235 res = devm_gpio_request(host->dev,
236 host->board.enable_pin, "nand_enable");
239 "can't request enable gpio %d\n",
240 host->board.enable_pin);
244 res = gpio_direction_output(host->board.enable_pin, 1);
247 "can't request output direction enable gpio %d\n",
248 host->board.enable_pin);
256 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
260 const __iomem u32 *s = src;
262 for (i = 0; i < (size >> 2); i++)
263 *t++ = readl_relaxed(s++);
266 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
269 u32 __iomem *t = trg;
272 for (i = 0; i < (size >> 2); i++)
273 writel_relaxed(*s++, t++);
277 * Minimal-overhead PIO for data access.
279 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
281 struct nand_chip *nand_chip = mtd->priv;
282 struct atmel_nand_host *host = nand_chip->priv;
284 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
285 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
286 host->nfc->data_in_sram += len;
288 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
292 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
294 struct nand_chip *nand_chip = mtd->priv;
295 struct atmel_nand_host *host = nand_chip->priv;
297 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
298 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
299 host->nfc->data_in_sram += len;
301 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
305 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
307 struct nand_chip *nand_chip = mtd->priv;
309 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
312 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
314 struct nand_chip *nand_chip = mtd->priv;
316 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
319 static void dma_complete_func(void *completion)
321 complete(completion);
324 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
326 /* NFC only has two banks. Must be 0 or 1 */
331 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
332 if (host->mtd.writesize > 2048)
334 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
336 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
342 static uint nfc_get_sram_off(struct atmel_nand_host *host)
344 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
345 return NFC_SRAM_BANK1_OFFSET;
350 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
352 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
353 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
355 return host->nfc->sram_bank0_phys;
358 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
361 struct dma_device *dma_dev;
362 enum dma_ctrl_flags flags;
363 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
364 struct dma_async_tx_descriptor *tx = NULL;
366 struct nand_chip *chip = mtd->priv;
367 struct atmel_nand_host *host = chip->priv;
370 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
371 struct atmel_nfc *nfc = host->nfc;
373 if (buf >= high_memory)
376 dma_dev = host->dma_chan->device;
378 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
379 DMA_COMPL_SKIP_DEST_UNMAP;
381 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
382 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
383 dev_err(host->dev, "Failed to dma_map_single\n");
388 if (nfc && nfc->data_in_sram)
389 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
390 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
392 dma_src_addr = host->io_phys;
394 dma_dst_addr = phys_addr;
396 dma_src_addr = phys_addr;
398 if (nfc && nfc->write_by_sram)
399 dma_dst_addr = nfc_sram_phys(host);
401 dma_dst_addr = host->io_phys;
404 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
405 dma_src_addr, len, flags);
407 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
411 init_completion(&host->comp);
412 tx->callback = dma_complete_func;
413 tx->callback_param = &host->comp;
415 cookie = tx->tx_submit(tx);
416 if (dma_submit_error(cookie)) {
417 dev_err(host->dev, "Failed to do DMA tx_submit\n");
421 dma_async_issue_pending(host->dma_chan);
422 wait_for_completion(&host->comp);
424 if (is_read && nfc && nfc->data_in_sram)
425 /* After read data from SRAM, need to increase the position */
426 nfc->data_in_sram += len;
431 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
434 dev_warn(host->dev, "Fall back to CPU I/O\n");
438 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
440 struct nand_chip *chip = mtd->priv;
441 struct atmel_nand_host *host = chip->priv;
443 if (use_dma && len > mtd->oobsize)
444 /* only use DMA for bigger than oob size: better performances */
445 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
448 if (host->board.bus_width_16)
449 atmel_read_buf16(mtd, buf, len);
451 atmel_read_buf8(mtd, buf, len);
454 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
456 struct nand_chip *chip = mtd->priv;
457 struct atmel_nand_host *host = chip->priv;
459 if (use_dma && len > mtd->oobsize)
460 /* only use DMA for bigger than oob size: better performances */
461 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
464 if (host->board.bus_width_16)
465 atmel_write_buf16(mtd, buf, len);
467 atmel_write_buf8(mtd, buf, len);
471 * Return number of ecc bytes per sector according to sector size and
472 * correction capability
474 * Following table shows what at91 PMECC supported:
475 * Correction Capability Sector_512_bytes Sector_1024_bytes
476 * ===================== ================ =================
477 * 2-bits 4-bytes 4-bytes
478 * 4-bits 7-bytes 7-bytes
479 * 8-bits 13-bytes 14-bytes
480 * 12-bits 20-bytes 21-bytes
481 * 24-bits 39-bytes 42-bytes
483 static int pmecc_get_ecc_bytes(int cap, int sector_size)
485 int m = 12 + sector_size / 512;
486 return (m * cap + 7) / 8;
489 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
490 int oobsize, int ecc_len)
494 layout->eccbytes = ecc_len;
496 /* ECC will occupy the last ecc_len bytes continuously */
497 for (i = 0; i < ecc_len; i++)
498 layout->eccpos[i] = oobsize - ecc_len + i;
500 layout->oobfree[0].offset = 2;
501 layout->oobfree[0].length =
502 oobsize - ecc_len - layout->oobfree[0].offset;
505 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
509 table_size = host->pmecc_sector_size == 512 ?
510 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
512 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
513 table_size * sizeof(int16_t);
516 static int pmecc_data_alloc(struct atmel_nand_host *host)
518 const int cap = host->pmecc_corr_cap;
521 size = (2 * cap + 1) * sizeof(int16_t);
522 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
523 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
524 host->pmecc_lmu = devm_kzalloc(host->dev,
525 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
526 host->pmecc_smu = devm_kzalloc(host->dev,
527 (cap + 2) * size, GFP_KERNEL);
529 size = (cap + 1) * sizeof(int);
530 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
531 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
532 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
534 if (!host->pmecc_partial_syn ||
546 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
548 struct nand_chip *nand_chip = mtd->priv;
549 struct atmel_nand_host *host = nand_chip->priv;
553 /* Fill odd syndromes */
554 for (i = 0; i < host->pmecc_corr_cap; i++) {
555 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
559 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
563 static void pmecc_substitute(struct mtd_info *mtd)
565 struct nand_chip *nand_chip = mtd->priv;
566 struct atmel_nand_host *host = nand_chip->priv;
567 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
568 int16_t __iomem *index_of = host->pmecc_index_of;
569 int16_t *partial_syn = host->pmecc_partial_syn;
570 const int cap = host->pmecc_corr_cap;
574 /* si[] is a table that holds the current syndrome value,
575 * an element of that table belongs to the field
579 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
581 /* Computation 2t syndromes based on S(x) */
583 for (i = 1; i < 2 * cap; i += 2) {
584 for (j = 0; j < host->pmecc_degree; j++) {
585 if (partial_syn[i] & ((unsigned short)0x1 << j))
586 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
589 /* Even syndrome = (Odd syndrome) ** 2 */
590 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
596 tmp = readw_relaxed(index_of + si[j]);
597 tmp = (tmp * 2) % host->pmecc_cw_len;
598 si[i] = readw_relaxed(alpha_to + tmp);
605 static void pmecc_get_sigma(struct mtd_info *mtd)
607 struct nand_chip *nand_chip = mtd->priv;
608 struct atmel_nand_host *host = nand_chip->priv;
610 int16_t *lmu = host->pmecc_lmu;
611 int16_t *si = host->pmecc_si;
612 int *mu = host->pmecc_mu;
613 int *dmu = host->pmecc_dmu; /* Discrepancy */
614 int *delta = host->pmecc_delta; /* Delta order */
615 int cw_len = host->pmecc_cw_len;
616 const int16_t cap = host->pmecc_corr_cap;
617 const int num = 2 * cap + 1;
618 int16_t __iomem *index_of = host->pmecc_index_of;
619 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
621 uint32_t dmu_0_count, tmp;
622 int16_t *smu = host->pmecc_smu;
624 /* index of largest delta */
636 memset(smu, 0, sizeof(int16_t) * num);
639 /* discrepancy set to 1 */
641 /* polynom order set to 0 */
643 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
649 /* Sigma(x) set to 1 */
650 memset(&smu[num], 0, sizeof(int16_t) * num);
653 /* discrepancy set to S1 */
656 /* polynom order set to 0 */
659 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
661 /* Init the Sigma(x) last row */
662 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
664 for (i = 1; i <= cap; i++) {
666 /* Begin Computing Sigma (Mu+1) and L(mu) */
667 /* check if discrepancy is set to 0 */
671 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
672 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
677 if (dmu_0_count == tmp) {
678 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
679 smu[(cap + 1) * num + j] =
682 lmu[cap + 1] = lmu[i];
687 for (j = 0; j <= lmu[i] >> 1; j++)
688 smu[(i + 1) * num + j] = smu[i * num + j];
690 /* copy previous polynom order to the next */
695 /* find largest delta with dmu != 0 */
696 for (j = 0; j < i; j++) {
697 if ((dmu[j]) && (delta[j] > largest)) {
703 /* compute difference */
704 diff = (mu[i] - mu[ro]);
706 /* Compute degree of the new smu polynomial */
707 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
710 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
712 /* Init smu[i+1] with 0 */
713 for (k = 0; k < num; k++)
714 smu[(i + 1) * num + k] = 0;
716 /* Compute smu[i+1] */
717 for (k = 0; k <= lmu[ro] >> 1; k++) {
720 if (!(smu[ro * num + k] && dmu[i]))
722 a = readw_relaxed(index_of + dmu[i]);
723 b = readw_relaxed(index_of + dmu[ro]);
724 c = readw_relaxed(index_of + smu[ro * num + k]);
725 tmp = a + (cw_len - b) + c;
726 a = readw_relaxed(alpha_to + tmp % cw_len);
727 smu[(i + 1) * num + (k + diff)] = a;
730 for (k = 0; k <= lmu[i] >> 1; k++)
731 smu[(i + 1) * num + k] ^= smu[i * num + k];
734 /* End Computing Sigma (Mu+1) and L(mu) */
735 /* In either case compute delta */
736 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
738 /* Do not compute discrepancy for the last iteration */
742 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
745 dmu[i + 1] = si[tmp + 3];
746 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
748 a = readw_relaxed(index_of +
749 smu[(i + 1) * num + k]);
750 b = si[2 * (i - 1) + 3 - k];
751 c = readw_relaxed(index_of + b);
754 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
763 static int pmecc_err_location(struct mtd_info *mtd)
765 struct nand_chip *nand_chip = mtd->priv;
766 struct atmel_nand_host *host = nand_chip->priv;
767 unsigned long end_time;
768 const int cap = host->pmecc_corr_cap;
769 const int num = 2 * cap + 1;
770 int sector_size = host->pmecc_sector_size;
771 int err_nbr = 0; /* number of error */
772 int roots_nbr; /* number of roots */
775 int16_t *smu = host->pmecc_smu;
777 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
779 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
780 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
781 smu[(cap + 1) * num + i]);
785 val = (err_nbr - 1) << 16;
786 if (sector_size == 1024)
789 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
790 pmerrloc_writel(host->pmerrloc_base, ELEN,
791 sector_size * 8 + host->pmecc_degree * cap);
793 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
794 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
795 & PMERRLOC_CALC_DONE)) {
796 if (unlikely(time_after(jiffies, end_time))) {
797 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
803 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
804 & PMERRLOC_ERR_NUM_MASK) >> 8;
805 /* Number of roots == degree of smu hence <= cap */
806 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
809 /* Number of roots does not match the degree of smu
810 * unable to correct error */
814 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
815 int sector_num, int extra_bytes, int err_nbr)
817 struct nand_chip *nand_chip = mtd->priv;
818 struct atmel_nand_host *host = nand_chip->priv;
820 int byte_pos, bit_pos, sector_size, pos;
824 sector_size = host->pmecc_sector_size;
827 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
831 if (byte_pos >= (sector_size + extra_bytes))
832 BUG(); /* should never happen */
834 if (byte_pos < sector_size) {
835 err_byte = *(buf + byte_pos);
836 *(buf + byte_pos) ^= (1 << bit_pos);
838 pos = sector_num * host->pmecc_sector_size + byte_pos;
839 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
840 pos, bit_pos, err_byte, *(buf + byte_pos));
842 /* Bit flip in OOB area */
843 tmp = sector_num * host->pmecc_bytes_per_sector
844 + (byte_pos - sector_size);
846 ecc[tmp] ^= (1 << bit_pos);
848 pos = tmp + nand_chip->ecc.layout->eccpos[0];
849 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
850 pos, bit_pos, err_byte, ecc[tmp]);
860 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
863 struct nand_chip *nand_chip = mtd->priv;
864 struct atmel_nand_host *host = nand_chip->priv;
865 int i, err_nbr, eccbytes;
869 eccbytes = nand_chip->ecc.bytes;
870 for (i = 0; i < eccbytes; i++)
873 /* Erased page, return OK */
877 for (i = 0; i < host->pmecc_sector_number; i++) {
879 if (pmecc_stat & 0x1) {
880 buf_pos = buf + i * host->pmecc_sector_size;
882 pmecc_gen_syndrome(mtd, i);
883 pmecc_substitute(mtd);
884 pmecc_get_sigma(mtd);
886 err_nbr = pmecc_err_location(mtd);
888 dev_err(host->dev, "PMECC: Too many errors\n");
889 mtd->ecc_stats.failed++;
892 pmecc_correct_data(mtd, buf_pos, ecc, i,
893 host->pmecc_bytes_per_sector, err_nbr);
894 mtd->ecc_stats.corrected += err_nbr;
895 total_err += err_nbr;
904 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
908 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
909 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
913 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
914 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
915 val = pmecc_readl_relaxed(host->ecc, CFG);
917 if (ecc_op == NAND_ECC_READ)
918 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
919 | PMECC_CFG_AUTO_ENABLE);
921 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
922 & ~PMECC_CFG_AUTO_ENABLE);
924 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
925 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
928 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
929 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
931 struct atmel_nand_host *host = chip->priv;
932 int eccsize = chip->ecc.size;
933 uint8_t *oob = chip->oob_poi;
934 uint32_t *eccpos = chip->ecc.layout->eccpos;
936 unsigned long end_time;
939 if (!host->nfc || !host->nfc->use_nfc_sram)
940 pmecc_enable(host, NAND_ECC_READ);
942 chip->read_buf(mtd, buf, eccsize);
943 chip->read_buf(mtd, oob, mtd->oobsize);
945 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
946 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
947 if (unlikely(time_after(jiffies, end_time))) {
948 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
954 stat = pmecc_readl_relaxed(host->ecc, ISR);
956 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
958 /* uncorrectable errors */
965 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
966 struct nand_chip *chip, const uint8_t *buf, int oob_required)
968 struct atmel_nand_host *host = chip->priv;
969 uint32_t *eccpos = chip->ecc.layout->eccpos;
971 unsigned long end_time;
973 if (!host->nfc || !host->nfc->write_by_sram) {
974 pmecc_enable(host, NAND_ECC_WRITE);
975 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
978 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
979 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
980 if (unlikely(time_after(jiffies, end_time))) {
981 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
987 for (i = 0; i < host->pmecc_sector_number; i++) {
988 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
991 pos = i * host->pmecc_bytes_per_sector + j;
992 chip->oob_poi[eccpos[pos]] =
993 pmecc_readb_ecc_relaxed(host->ecc, i, j);
996 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1001 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1003 struct nand_chip *nand_chip = mtd->priv;
1004 struct atmel_nand_host *host = nand_chip->priv;
1006 struct nand_ecclayout *ecc_layout;
1008 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1009 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1011 switch (host->pmecc_corr_cap) {
1013 val = PMECC_CFG_BCH_ERR2;
1016 val = PMECC_CFG_BCH_ERR4;
1019 val = PMECC_CFG_BCH_ERR8;
1022 val = PMECC_CFG_BCH_ERR12;
1025 val = PMECC_CFG_BCH_ERR24;
1029 if (host->pmecc_sector_size == 512)
1030 val |= PMECC_CFG_SECTOR512;
1031 else if (host->pmecc_sector_size == 1024)
1032 val |= PMECC_CFG_SECTOR1024;
1034 switch (host->pmecc_sector_number) {
1036 val |= PMECC_CFG_PAGE_1SECTOR;
1039 val |= PMECC_CFG_PAGE_2SECTORS;
1042 val |= PMECC_CFG_PAGE_4SECTORS;
1045 val |= PMECC_CFG_PAGE_8SECTORS;
1049 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1050 | PMECC_CFG_AUTO_DISABLE);
1051 pmecc_writel(host->ecc, CFG, val);
1053 ecc_layout = nand_chip->ecc.layout;
1054 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1055 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1056 pmecc_writel(host->ecc, EADDR,
1057 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1058 /* See datasheet about PMECC Clock Control Register */
1059 pmecc_writel(host->ecc, CLK, 2);
1060 pmecc_writel(host->ecc, IDR, 0xff);
1061 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1065 * Get minimum ecc requirements from NAND.
1066 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1067 * will set them according to minimum ecc requirement. Otherwise, use the
1068 * value in DTS file.
1069 * return 0 if success. otherwise return error code.
1071 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1072 int *cap, int *sector_size)
1074 /* Get minimum ECC requirements */
1075 if (host->nand_chip.ecc_strength_ds) {
1076 *cap = host->nand_chip.ecc_strength_ds;
1077 *sector_size = host->nand_chip.ecc_step_ds;
1078 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1079 *cap, *sector_size);
1083 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1086 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1087 if (host->pmecc_corr_cap == 0) {
1088 /* use the most fitable ecc bits (the near bigger one ) */
1090 host->pmecc_corr_cap = 2;
1092 host->pmecc_corr_cap = 4;
1094 host->pmecc_corr_cap = 8;
1095 else if (*cap <= 12)
1096 host->pmecc_corr_cap = 12;
1097 else if (*cap <= 24)
1098 host->pmecc_corr_cap = 24;
1102 if (host->pmecc_sector_size == 0) {
1103 /* use the most fitable sector size (the near smaller one ) */
1104 if (*sector_size >= 1024)
1105 host->pmecc_sector_size = 1024;
1106 else if (*sector_size >= 512)
1107 host->pmecc_sector_size = 512;
1114 static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
1115 struct atmel_nand_host *host)
1117 struct mtd_info *mtd = &host->mtd;
1118 struct nand_chip *nand_chip = &host->nand_chip;
1119 struct resource *regs, *regs_pmerr, *regs_rom;
1120 int cap, sector_size, err_no;
1122 err_no = pmecc_choose_ecc(host, &cap, §or_size);
1124 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1128 if (cap > host->pmecc_corr_cap ||
1129 sector_size != host->pmecc_sector_size)
1130 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1132 cap = host->pmecc_corr_cap;
1133 sector_size = host->pmecc_sector_size;
1134 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1135 host->pmecc_lookup_table_offset_512 :
1136 host->pmecc_lookup_table_offset_1024;
1138 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1141 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1144 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1145 nand_chip->ecc.mode = NAND_ECC_SOFT;
1149 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1150 if (IS_ERR(host->ecc)) {
1151 dev_err(host->dev, "ioremap failed\n");
1152 err_no = PTR_ERR(host->ecc);
1156 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1157 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1158 if (IS_ERR(host->pmerrloc_base)) {
1160 "Can not get I/O resource for PMECC ERRLOC controller!\n");
1161 err_no = PTR_ERR(host->pmerrloc_base);
1165 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1166 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1167 if (IS_ERR(host->pmecc_rom_base)) {
1168 dev_err(host->dev, "Can not get I/O resource for ROM!\n");
1169 err_no = PTR_ERR(host->pmecc_rom_base);
1173 /* ECC is calculated for the whole page (1 step) */
1174 nand_chip->ecc.size = mtd->writesize;
1176 /* set ECC page size and oob layout */
1177 switch (mtd->writesize) {
1179 host->pmecc_degree = (sector_size == 512) ?
1180 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1181 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1182 host->pmecc_sector_number = mtd->writesize / sector_size;
1183 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1185 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1186 host->pmecc_index_of = host->pmecc_rom_base +
1187 host->pmecc_lookup_table_offset;
1189 nand_chip->ecc.steps = 1;
1190 nand_chip->ecc.strength = cap;
1191 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
1192 host->pmecc_sector_number;
1193 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
1194 dev_err(host->dev, "No room for ECC bytes\n");
1198 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1200 nand_chip->ecc.bytes);
1201 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1208 "Unsupported page size for PMECC, use Software ECC\n");
1210 /* page size not handled by HW ECC */
1211 /* switching back to soft ECC */
1212 nand_chip->ecc.mode = NAND_ECC_SOFT;
1216 /* Allocate data for PMECC computation */
1217 err_no = pmecc_data_alloc(host);
1220 "Cannot allocate memory for PMECC computation!\n");
1224 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1225 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1227 atmel_pmecc_core_init(mtd);
1238 * function called after a write
1240 * mtd: MTD block structure
1241 * dat: raw data (unused)
1242 * ecc_code: buffer for ECC
1244 static int atmel_nand_calculate(struct mtd_info *mtd,
1245 const u_char *dat, unsigned char *ecc_code)
1247 struct nand_chip *nand_chip = mtd->priv;
1248 struct atmel_nand_host *host = nand_chip->priv;
1249 unsigned int ecc_value;
1251 /* get the first 2 ECC bytes */
1252 ecc_value = ecc_readl(host->ecc, PR);
1254 ecc_code[0] = ecc_value & 0xFF;
1255 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1257 /* get the last 2 ECC bytes */
1258 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1260 ecc_code[2] = ecc_value & 0xFF;
1261 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1267 * HW ECC read page function
1269 * mtd: mtd info structure
1270 * chip: nand chip info structure
1271 * buf: buffer to store read data
1272 * oob_required: caller expects OOB data read to chip->oob_poi
1274 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1275 uint8_t *buf, int oob_required, int page)
1277 int eccsize = chip->ecc.size;
1278 int eccbytes = chip->ecc.bytes;
1279 uint32_t *eccpos = chip->ecc.layout->eccpos;
1281 uint8_t *oob = chip->oob_poi;
1284 unsigned int max_bitflips = 0;
1287 * Errata: ALE is incorrectly wired up to the ECC controller
1288 * on the AP7000, so it will include the address cycles in the
1291 * Workaround: Reset the parity registers before reading the
1294 struct atmel_nand_host *host = chip->priv;
1295 if (host->board.need_reset_workaround)
1296 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1299 chip->read_buf(mtd, p, eccsize);
1301 /* move to ECC position if needed */
1302 if (eccpos[0] != 0) {
1303 /* This only works on large pages
1304 * because the ECC controller waits for
1305 * NAND_CMD_RNDOUTSTART after the
1307 * anyway, for small pages, the eccpos[0] == 0
1309 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1310 mtd->writesize + eccpos[0], -1);
1313 /* the ECC controller needs to read the ECC just after the data */
1314 ecc_pos = oob + eccpos[0];
1315 chip->read_buf(mtd, ecc_pos, eccbytes);
1317 /* check if there's an error */
1318 stat = chip->ecc.correct(mtd, p, oob, NULL);
1321 mtd->ecc_stats.failed++;
1323 mtd->ecc_stats.corrected += stat;
1324 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1327 /* get back to oob start (end of page) */
1328 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1331 chip->read_buf(mtd, oob, mtd->oobsize);
1333 return max_bitflips;
1339 * function called after a read
1341 * mtd: MTD block structure
1342 * dat: raw data read from the chip
1343 * read_ecc: ECC from the chip (unused)
1346 * Detect and correct a 1 bit error for a page
1348 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1349 u_char *read_ecc, u_char *isnull)
1351 struct nand_chip *nand_chip = mtd->priv;
1352 struct atmel_nand_host *host = nand_chip->priv;
1353 unsigned int ecc_status;
1354 unsigned int ecc_word, ecc_bit;
1356 /* get the status from the Status Register */
1357 ecc_status = ecc_readl(host->ecc, SR);
1359 /* if there's no error */
1360 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1363 /* get error bit offset (4 bits) */
1364 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1365 /* get word address (12 bits) */
1366 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1369 /* if there are multiple errors */
1370 if (ecc_status & ATMEL_ECC_MULERR) {
1371 /* check if it is a freshly erased block
1372 * (filled with 0xff) */
1373 if ((ecc_bit == ATMEL_ECC_BITADDR)
1374 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1375 /* the block has just been erased, return OK */
1378 /* it doesn't seems to be a freshly
1380 * We can't correct so many errors */
1381 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1382 " Unable to correct.\n");
1386 /* if there's a single bit error : we can correct it */
1387 if (ecc_status & ATMEL_ECC_ECCERR) {
1388 /* there's nothing much to do here.
1389 * the bit error is on the ECC itself.
1391 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1392 " Nothing to correct\n");
1396 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1397 " (word offset in the page :"
1398 " 0x%x bit offset : 0x%x)\n",
1400 /* correct the error */
1401 if (nand_chip->options & NAND_BUSWIDTH_16) {
1403 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1406 dat[ecc_word] ^= (1 << ecc_bit);
1408 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1413 * Enable HW ECC : unused on most chips
1415 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1417 struct nand_chip *nand_chip = mtd->priv;
1418 struct atmel_nand_host *host = nand_chip->priv;
1420 if (host->board.need_reset_workaround)
1421 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1424 static int atmel_of_init_port(struct atmel_nand_host *host,
1425 struct device_node *np)
1430 struct atmel_nand_data *board = &host->board;
1431 enum of_gpio_flags flags = 0;
1433 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1435 dev_err(host->dev, "invalid addr-offset %u\n", val);
1441 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1443 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1449 ecc_mode = of_get_nand_ecc_mode(np);
1451 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1453 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1455 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1457 if (of_get_nand_bus_width(np) == 16)
1458 board->bus_width_16 = 1;
1460 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1461 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1463 board->enable_pin = of_get_gpio(np, 1);
1464 board->det_pin = of_get_gpio(np, 2);
1466 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1468 /* load the nfc driver if there is */
1469 of_platform_populate(np, NULL, NULL, host->dev);
1471 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1472 return 0; /* Not using PMECC */
1474 /* use PMECC, get correction capability, sector size and lookup
1476 * If correction bits and sector size are not specified, then find
1477 * them from NAND ONFI parameters.
1479 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1480 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1483 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1487 host->pmecc_corr_cap = (u8)val;
1490 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1491 if ((val != 512) && (val != 1024)) {
1493 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1497 host->pmecc_sector_size = (u16)val;
1500 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1502 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1505 if (!offset[0] && !offset[1]) {
1506 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1509 host->pmecc_lookup_table_offset_512 = offset[0];
1510 host->pmecc_lookup_table_offset_1024 = offset[1];
1515 static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1516 struct atmel_nand_host *host)
1518 struct mtd_info *mtd = &host->mtd;
1519 struct nand_chip *nand_chip = &host->nand_chip;
1520 struct resource *regs;
1522 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1525 "Can't get I/O resource regs, use software ECC\n");
1526 nand_chip->ecc.mode = NAND_ECC_SOFT;
1530 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1531 if (IS_ERR(host->ecc)) {
1532 dev_err(host->dev, "ioremap failed\n");
1533 return PTR_ERR(host->ecc);
1536 /* ECC is calculated for the whole page (1 step) */
1537 nand_chip->ecc.size = mtd->writesize;
1539 /* set ECC page size and oob layout */
1540 switch (mtd->writesize) {
1542 nand_chip->ecc.layout = &atmel_oobinfo_small;
1543 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1546 nand_chip->ecc.layout = &atmel_oobinfo_large;
1547 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1550 nand_chip->ecc.layout = &atmel_oobinfo_large;
1551 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1554 nand_chip->ecc.layout = &atmel_oobinfo_large;
1555 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1558 /* page size not handled by HW ECC */
1559 /* switching back to soft ECC */
1560 nand_chip->ecc.mode = NAND_ECC_SOFT;
1564 /* set up for HW ECC */
1565 nand_chip->ecc.calculate = atmel_nand_calculate;
1566 nand_chip->ecc.correct = atmel_nand_correct;
1567 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1568 nand_chip->ecc.read_page = atmel_nand_read_page;
1569 nand_chip->ecc.bytes = 4;
1570 nand_chip->ecc.strength = 1;
1575 /* SMC interrupt service routine */
1576 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1578 struct atmel_nand_host *host = dev_id;
1579 u32 status, mask, pending;
1580 irqreturn_t ret = IRQ_HANDLED;
1582 status = nfc_readl(host->nfc->hsmc_regs, SR);
1583 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1584 pending = status & mask;
1586 if (pending & NFC_SR_XFR_DONE) {
1587 complete(&host->nfc->comp_nfc);
1588 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1589 } else if (pending & NFC_SR_RB_EDGE) {
1590 complete(&host->nfc->comp_nfc);
1591 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1592 } else if (pending & NFC_SR_CMD_DONE) {
1593 complete(&host->nfc->comp_nfc);
1594 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1602 /* NFC(Nand Flash Controller) related functions */
1603 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1605 unsigned long timeout;
1606 init_completion(&host->nfc->comp_nfc);
1608 /* Enable interrupt that need to wait for */
1609 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1611 timeout = wait_for_completion_timeout(&host->nfc->comp_nfc,
1612 msecs_to_jiffies(NFC_TIME_OUT_MS));
1616 /* Time out to wait for the interrupt */
1617 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1621 static int nfc_send_command(struct atmel_nand_host *host,
1622 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1624 unsigned long timeout;
1626 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1629 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1630 while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1631 & NFCADDR_CMD_NFCBUSY) {
1632 if (time_after(jiffies, timeout)) {
1634 "Time out to wait CMD_NFCBUSY ready!\n");
1638 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1639 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1640 return nfc_wait_interrupt(host, NFC_SR_CMD_DONE);
1643 static int nfc_device_ready(struct mtd_info *mtd)
1645 struct nand_chip *nand_chip = mtd->priv;
1646 struct atmel_nand_host *host = nand_chip->priv;
1647 if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE))
1652 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1654 struct nand_chip *nand_chip = mtd->priv;
1655 struct atmel_nand_host *host = nand_chip->priv;
1658 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1660 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1663 static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
1664 unsigned int *addr1234, unsigned int *cycle0)
1666 struct nand_chip *chip = mtd->priv;
1669 unsigned char addr_bytes[8];
1670 int index = 0, bit_shift;
1672 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1678 if (chip->options & NAND_BUSWIDTH_16)
1680 addr_bytes[acycle++] = column & 0xff;
1681 if (mtd->writesize > 512)
1682 addr_bytes[acycle++] = (column >> 8) & 0xff;
1685 if (page_addr != -1) {
1686 addr_bytes[acycle++] = page_addr & 0xff;
1687 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1688 if (chip->chipsize > (128 << 20))
1689 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1693 *cycle0 = addr_bytes[index++];
1695 for (bit_shift = 0; index < acycle; bit_shift += 8)
1696 *addr1234 += addr_bytes[index++] << bit_shift;
1698 /* return acycle in cmd register */
1699 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1702 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1703 int column, int page_addr)
1705 struct nand_chip *chip = mtd->priv;
1706 struct atmel_nand_host *host = chip->priv;
1707 unsigned long timeout;
1708 unsigned int nfc_addr_cmd = 0;
1710 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1712 /* Set default settings: no cmd2, no addr cycle. read from nand */
1713 unsigned int cmd2 = 0;
1714 unsigned int vcmd2 = 0;
1715 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1716 int csid = NFCADDR_CMD_CSID_3;
1717 int dataen = NFCADDR_CMD_DATADIS;
1718 int nfcwr = NFCADDR_CMD_NFCRD;
1719 unsigned int addr1234 = 0;
1720 unsigned int cycle0 = 0;
1721 bool do_addr = true;
1722 host->nfc->data_in_sram = NULL;
1724 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1725 __func__, command, column, page_addr);
1728 case NAND_CMD_RESET:
1729 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1730 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1731 udelay(chip->chip_delay);
1733 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1734 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1735 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1736 if (time_after(jiffies, timeout)) {
1738 "Time out to wait status ready!\n");
1743 case NAND_CMD_STATUS:
1746 case NAND_CMD_PARAM:
1747 case NAND_CMD_READID:
1749 acycle = NFCADDR_CMD_ACYCLE_1;
1753 case NAND_CMD_RNDOUT:
1754 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1755 vcmd2 = NFCADDR_CMD_VCMD2;
1757 case NAND_CMD_READ0:
1758 case NAND_CMD_READOOB:
1759 if (command == NAND_CMD_READOOB) {
1760 column += mtd->writesize;
1761 command = NAND_CMD_READ0; /* only READ0 is valid */
1762 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1764 if (host->nfc->use_nfc_sram) {
1765 /* Enable Data transfer to sram */
1766 dataen = NFCADDR_CMD_DATAEN;
1768 /* Need enable PMECC now, since NFC will transfer
1769 * data in bus after sending nfc read command.
1771 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1772 pmecc_enable(host, NAND_ECC_READ);
1775 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1776 vcmd2 = NFCADDR_CMD_VCMD2;
1778 /* For prgramming command, the cmd need set to write enable */
1779 case NAND_CMD_PAGEPROG:
1780 case NAND_CMD_SEQIN:
1781 case NAND_CMD_RNDIN:
1782 nfcwr = NFCADDR_CMD_NFCWR;
1783 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1784 dataen = NFCADDR_CMD_DATAEN;
1791 acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
1794 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1795 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1797 if (dataen == NFCADDR_CMD_DATAEN)
1798 if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE))
1799 dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n");
1802 * Program and erase have their own busy handlers status, sequential
1803 * in, and deplete1 need no delay.
1806 case NAND_CMD_CACHEDPROG:
1807 case NAND_CMD_PAGEPROG:
1808 case NAND_CMD_ERASE1:
1809 case NAND_CMD_ERASE2:
1810 case NAND_CMD_RNDIN:
1811 case NAND_CMD_STATUS:
1812 case NAND_CMD_RNDOUT:
1813 case NAND_CMD_SEQIN:
1814 case NAND_CMD_READID:
1817 case NAND_CMD_READ0:
1818 if (dataen == NFCADDR_CMD_DATAEN) {
1819 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1820 nfc_get_sram_off(host);
1825 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1829 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1830 uint32_t offset, int data_len, const uint8_t *buf,
1831 int oob_required, int page, int cached, int raw)
1835 struct atmel_nand_host *host = chip->priv;
1836 void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1838 /* Subpage write is not supported */
1839 if (offset || (data_len < mtd->writesize))
1842 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1843 len = mtd->writesize;
1845 if (unlikely(raw)) {
1846 len += mtd->oobsize;
1847 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1849 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1851 /* Copy page data to sram that will write to nand via NFC */
1853 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1854 /* Fall back to use cpu copy */
1855 memcpy32_toio(sram, buf, len);
1857 memcpy32_toio(sram, buf, len);
1860 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1862 * When use NFC sram, need set up PMECC before send
1863 * NAND_CMD_SEQIN command. Since when the nand command
1864 * is sent, nfc will do transfer from sram and nand.
1866 pmecc_enable(host, NAND_ECC_WRITE);
1868 host->nfc->will_write_sram = true;
1869 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1870 host->nfc->will_write_sram = false;
1873 /* Need to write ecc into oob */
1874 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1879 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1880 status = chip->waitfunc(mtd, chip);
1882 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1883 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1885 if (status & NAND_STATUS_FAIL)
1891 static int nfc_sram_init(struct mtd_info *mtd)
1893 struct nand_chip *chip = mtd->priv;
1894 struct atmel_nand_host *host = chip->priv;
1897 /* Initialize the NFC CFG register */
1898 unsigned int cfg_nfc = 0;
1900 /* set page size and oob layout */
1901 switch (mtd->writesize) {
1903 cfg_nfc = NFC_CFG_PAGESIZE_512;
1906 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1909 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1912 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1915 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1918 dev_err(host->dev, "Unsupported page size for NFC.\n");
1923 /* oob bytes size = (NFCSPARESIZE + 1) * 4
1924 * Max support spare size is 512 bytes. */
1925 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1926 & NFC_CFG_NFC_SPARESIZE);
1927 /* default set a max timeout */
1928 cfg_nfc |= NFC_CFG_RSPARE |
1929 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1931 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
1933 host->nfc->will_write_sram = false;
1934 nfc_set_sram_bank(host, 0);
1936 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
1937 if (host->nfc->write_by_sram) {
1938 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
1939 chip->ecc.mode == NAND_ECC_NONE)
1940 chip->write_page = nfc_sram_write_page;
1942 host->nfc->write_by_sram = false;
1945 dev_info(host->dev, "Using NFC Sram read %s\n",
1946 host->nfc->write_by_sram ? "and write" : "");
1950 static struct platform_driver atmel_nand_nfc_driver;
1952 * Probe for the NAND device.
1954 static int __init atmel_nand_probe(struct platform_device *pdev)
1956 struct atmel_nand_host *host;
1957 struct mtd_info *mtd;
1958 struct nand_chip *nand_chip;
1959 struct resource *mem;
1960 struct mtd_part_parser_data ppdata = {};
1963 /* Allocate memory for the device structure (and zero it) */
1964 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1966 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
1970 res = platform_driver_register(&atmel_nand_nfc_driver);
1972 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
1974 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1975 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
1976 if (IS_ERR(host->io_base)) {
1977 dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n");
1978 res = PTR_ERR(host->io_base);
1979 goto err_nand_ioremap;
1981 host->io_phys = (dma_addr_t)mem->start;
1984 nand_chip = &host->nand_chip;
1985 host->dev = &pdev->dev;
1986 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
1987 /* Only when CONFIG_OF is enabled of_node can be parsed */
1988 res = atmel_of_init_port(host, pdev->dev.of_node);
1990 goto err_nand_ioremap;
1992 memcpy(&host->board, dev_get_platdata(&pdev->dev),
1993 sizeof(struct atmel_nand_data));
1996 nand_chip->priv = host; /* link the private data structures */
1997 mtd->priv = nand_chip;
1998 mtd->owner = THIS_MODULE;
2000 /* Set address of NAND IO lines */
2001 nand_chip->IO_ADDR_R = host->io_base;
2002 nand_chip->IO_ADDR_W = host->io_base;
2004 if (nand_nfc.is_initialized) {
2005 /* NFC driver is probed and initialized */
2006 host->nfc = &nand_nfc;
2008 nand_chip->select_chip = nfc_select_chip;
2009 nand_chip->dev_ready = nfc_device_ready;
2010 nand_chip->cmdfunc = nfc_nand_command;
2012 /* Initialize the interrupt for NFC */
2013 irq = platform_get_irq(pdev, 0);
2015 dev_err(host->dev, "Cannot get HSMC irq!\n");
2017 goto err_nand_ioremap;
2020 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2023 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2025 goto err_nand_ioremap;
2028 res = atmel_nand_set_enable_ready_pins(mtd);
2030 goto err_nand_ioremap;
2032 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2035 nand_chip->ecc.mode = host->board.ecc_mode;
2036 nand_chip->chip_delay = 20; /* 20us command delay time */
2038 if (host->board.bus_width_16) /* 16-bit bus width */
2039 nand_chip->options |= NAND_BUSWIDTH_16;
2041 nand_chip->read_buf = atmel_read_buf;
2042 nand_chip->write_buf = atmel_write_buf;
2044 platform_set_drvdata(pdev, host);
2045 atmel_nand_enable(host);
2047 if (gpio_is_valid(host->board.det_pin)) {
2048 res = devm_gpio_request(&pdev->dev,
2049 host->board.det_pin, "nand_det");
2052 "can't request det gpio %d\n",
2053 host->board.det_pin);
2057 res = gpio_direction_input(host->board.det_pin);
2060 "can't request input direction det gpio %d\n",
2061 host->board.det_pin);
2065 if (gpio_get_value(host->board.det_pin)) {
2066 printk(KERN_INFO "No SmartMedia card inserted.\n");
2072 if (host->board.on_flash_bbt || on_flash_bbt) {
2073 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
2074 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2077 if (!host->board.has_dma)
2081 dma_cap_mask_t mask;
2084 dma_cap_set(DMA_MEMCPY, mask);
2085 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2086 if (!host->dma_chan) {
2087 dev_err(host->dev, "Failed to request DMA channel\n");
2092 dev_info(host->dev, "Using %s for DMA transfers.\n",
2093 dma_chan_name(host->dma_chan));
2095 dev_info(host->dev, "No DMA support for NAND access.\n");
2097 /* first scan to find the device and get the page size */
2098 if (nand_scan_ident(mtd, 1, NULL)) {
2100 goto err_scan_ident;
2103 if (nand_chip->ecc.mode == NAND_ECC_HW) {
2104 if (host->has_pmecc)
2105 res = atmel_pmecc_nand_init_params(pdev, host);
2107 res = atmel_hw_nand_init_params(pdev, host);
2113 /* initialize the nfc configuration register */
2114 if (host->nfc && host->nfc->use_nfc_sram) {
2115 res = nfc_sram_init(mtd);
2117 host->nfc->use_nfc_sram = false;
2118 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2122 /* second phase scan */
2123 if (nand_scan_tail(mtd)) {
2128 mtd->name = "atmel_nand";
2129 ppdata.of_node = pdev->dev.of_node;
2130 res = mtd_device_parse_register(mtd, NULL, &ppdata,
2131 host->board.parts, host->board.num_parts);
2136 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2137 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2141 atmel_nand_disable(host);
2143 dma_release_channel(host->dma_chan);
2145 platform_driver_unregister(&atmel_nand_nfc_driver);
2150 * Remove a NAND device.
2152 static int __exit atmel_nand_remove(struct platform_device *pdev)
2154 struct atmel_nand_host *host = platform_get_drvdata(pdev);
2155 struct mtd_info *mtd = &host->mtd;
2159 atmel_nand_disable(host);
2161 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2162 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2163 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2168 dma_release_channel(host->dma_chan);
2170 platform_driver_unregister(&atmel_nand_nfc_driver);
2175 static const struct of_device_id atmel_nand_dt_ids[] = {
2176 { .compatible = "atmel,at91rm9200-nand" },
2180 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2182 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2184 struct atmel_nfc *nfc = &nand_nfc;
2185 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2187 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2188 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2189 if (IS_ERR(nfc->base_cmd_regs))
2190 return PTR_ERR(nfc->base_cmd_regs);
2192 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2193 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2194 if (IS_ERR(nfc->hsmc_regs))
2195 return PTR_ERR(nfc->hsmc_regs);
2197 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2199 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
2200 if (IS_ERR(nfc->sram_bank0)) {
2201 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2202 PTR_ERR(nfc->sram_bank0));
2204 nfc->use_nfc_sram = true;
2205 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2207 if (pdev->dev.of_node)
2208 nfc->write_by_sram = of_property_read_bool(
2210 "atmel,write-by-sram");
2214 nfc->is_initialized = true;
2215 dev_info(&pdev->dev, "NFC is probed.\n");
2219 static const struct of_device_id atmel_nand_nfc_match[] = {
2220 { .compatible = "atmel,sama5d3-nfc" },
2223 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2225 static struct platform_driver atmel_nand_nfc_driver = {
2227 .name = "atmel_nand_nfc",
2228 .owner = THIS_MODULE,
2229 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2231 .probe = atmel_nand_nfc_probe,
2234 static struct platform_driver atmel_nand_driver = {
2235 .remove = __exit_p(atmel_nand_remove),
2237 .name = "atmel_nand",
2238 .owner = THIS_MODULE,
2239 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2243 module_platform_driver_probe(atmel_nand_driver, atmel_nand_probe);
2245 MODULE_LICENSE("GPL");
2246 MODULE_AUTHOR("Rick Bronson");
2247 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2248 MODULE_ALIAS("platform:atmel_nand");