2 * Copyright (C) 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/mtd/partitions.h>
33 #include <linux/gpio.h>
36 #include <mach/board.h>
39 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
45 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
51 static int on_flash_bbt = 0;
52 module_param(on_flash_bbt, int, 0);
54 /* Register access macros */
55 #define ecc_readl(add, reg) \
56 __raw_readl(add + ATMEL_ECC_##reg)
57 #define ecc_writel(add, reg, value) \
58 __raw_writel((value), add + ATMEL_ECC_##reg)
60 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
62 /* oob layout for large page size
63 * bad block info is on bytes 0 and 1
64 * the bytes have to be consecutives to avoid
65 * several NAND_CMD_RNDOUT during read
67 static struct nand_ecclayout atmel_oobinfo_large = {
69 .eccpos = {60, 61, 62, 63},
75 /* oob layout for small page size
76 * bad block info is on bytes 4 and 5
77 * the bytes have to be consecutives to avoid
78 * several NAND_CMD_RNDOUT during read
80 static struct nand_ecclayout atmel_oobinfo_small = {
82 .eccpos = {0, 1, 2, 3},
88 struct atmel_nand_host {
89 struct nand_chip nand_chip;
91 void __iomem *io_base;
92 struct atmel_nand_data *board;
100 static void atmel_nand_enable(struct atmel_nand_host *host)
102 if (host->board->enable_pin)
103 gpio_set_value(host->board->enable_pin, 0);
109 static void atmel_nand_disable(struct atmel_nand_host *host)
111 if (host->board->enable_pin)
112 gpio_set_value(host->board->enable_pin, 1);
116 * Hardware specific access to control-lines
118 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
120 struct nand_chip *nand_chip = mtd->priv;
121 struct atmel_nand_host *host = nand_chip->priv;
123 if (ctrl & NAND_CTRL_CHANGE) {
125 atmel_nand_enable(host);
127 atmel_nand_disable(host);
129 if (cmd == NAND_CMD_NONE)
133 writeb(cmd, host->io_base + (1 << host->board->cle));
135 writeb(cmd, host->io_base + (1 << host->board->ale));
139 * Read the Device Ready pin.
141 static int atmel_nand_device_ready(struct mtd_info *mtd)
143 struct nand_chip *nand_chip = mtd->priv;
144 struct atmel_nand_host *host = nand_chip->priv;
146 return gpio_get_value(host->board->rdy_pin) ^
147 !!host->board->rdy_pin_active_low;
151 * Minimal-overhead PIO for data access.
153 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
155 struct nand_chip *nand_chip = mtd->priv;
157 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
160 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
162 struct nand_chip *nand_chip = mtd->priv;
164 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
167 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
169 struct nand_chip *nand_chip = mtd->priv;
171 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
174 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
176 struct nand_chip *nand_chip = mtd->priv;
178 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
184 * function called after a write
186 * mtd: MTD block structure
187 * dat: raw data (unused)
188 * ecc_code: buffer for ECC
190 static int atmel_nand_calculate(struct mtd_info *mtd,
191 const u_char *dat, unsigned char *ecc_code)
193 struct nand_chip *nand_chip = mtd->priv;
194 struct atmel_nand_host *host = nand_chip->priv;
195 unsigned int ecc_value;
197 /* get the first 2 ECC bytes */
198 ecc_value = ecc_readl(host->ecc, PR);
200 ecc_code[0] = ecc_value & 0xFF;
201 ecc_code[1] = (ecc_value >> 8) & 0xFF;
203 /* get the last 2 ECC bytes */
204 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
206 ecc_code[2] = ecc_value & 0xFF;
207 ecc_code[3] = (ecc_value >> 8) & 0xFF;
213 * HW ECC read page function
215 * mtd: mtd info structure
216 * chip: nand chip info structure
217 * buf: buffer to store read data
219 static int atmel_nand_read_page(struct mtd_info *mtd,
220 struct nand_chip *chip, uint8_t *buf, int page)
222 int eccsize = chip->ecc.size;
223 int eccbytes = chip->ecc.bytes;
224 uint32_t *eccpos = chip->ecc.layout->eccpos;
226 uint8_t *oob = chip->oob_poi;
231 * Errata: ALE is incorrectly wired up to the ECC controller
232 * on the AP7000, so it will include the address cycles in the
235 * Workaround: Reset the parity registers before reading the
238 if (cpu_is_at32ap7000()) {
239 struct atmel_nand_host *host = chip->priv;
240 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
244 chip->read_buf(mtd, p, eccsize);
246 /* move to ECC position if needed */
247 if (eccpos[0] != 0) {
248 /* This only works on large pages
249 * because the ECC controller waits for
250 * NAND_CMD_RNDOUTSTART after the
252 * anyway, for small pages, the eccpos[0] == 0
254 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
255 mtd->writesize + eccpos[0], -1);
258 /* the ECC controller needs to read the ECC just after the data */
259 ecc_pos = oob + eccpos[0];
260 chip->read_buf(mtd, ecc_pos, eccbytes);
262 /* check if there's an error */
263 stat = chip->ecc.correct(mtd, p, oob, NULL);
266 mtd->ecc_stats.failed++;
268 mtd->ecc_stats.corrected += stat;
270 /* get back to oob start (end of page) */
271 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
274 chip->read_buf(mtd, oob, mtd->oobsize);
282 * function called after a read
284 * mtd: MTD block structure
285 * dat: raw data read from the chip
286 * read_ecc: ECC from the chip (unused)
289 * Detect and correct a 1 bit error for a page
291 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
292 u_char *read_ecc, u_char *isnull)
294 struct nand_chip *nand_chip = mtd->priv;
295 struct atmel_nand_host *host = nand_chip->priv;
296 unsigned int ecc_status;
297 unsigned int ecc_word, ecc_bit;
299 /* get the status from the Status Register */
300 ecc_status = ecc_readl(host->ecc, SR);
302 /* if there's no error */
303 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
306 /* get error bit offset (4 bits) */
307 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
308 /* get word address (12 bits) */
309 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
312 /* if there are multiple errors */
313 if (ecc_status & ATMEL_ECC_MULERR) {
314 /* check if it is a freshly erased block
315 * (filled with 0xff) */
316 if ((ecc_bit == ATMEL_ECC_BITADDR)
317 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
318 /* the block has just been erased, return OK */
321 /* it doesn't seems to be a freshly
323 * We can't correct so many errors */
324 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
325 " Unable to correct.\n");
329 /* if there's a single bit error : we can correct it */
330 if (ecc_status & ATMEL_ECC_ECCERR) {
331 /* there's nothing much to do here.
332 * the bit error is on the ECC itself.
334 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
335 " Nothing to correct\n");
339 dev_dbg(host->dev, "atmel_nand : one bit error on data."
340 " (word offset in the page :"
341 " 0x%x bit offset : 0x%x)\n",
343 /* correct the error */
344 if (nand_chip->options & NAND_BUSWIDTH_16) {
346 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
349 dat[ecc_word] ^= (1 << ecc_bit);
351 dev_dbg(host->dev, "atmel_nand : error corrected\n");
356 * Enable HW ECC : unused on most chips
358 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
360 if (cpu_is_at32ap7000()) {
361 struct nand_chip *nand_chip = mtd->priv;
362 struct atmel_nand_host *host = nand_chip->priv;
363 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
367 #ifdef CONFIG_MTD_CMDLINE_PARTS
368 static const char *part_probes[] = { "cmdlinepart", NULL };
372 * Probe for the NAND device.
374 static int __init atmel_nand_probe(struct platform_device *pdev)
376 struct atmel_nand_host *host;
377 struct mtd_info *mtd;
378 struct nand_chip *nand_chip;
379 struct resource *regs;
380 struct resource *mem;
383 #ifdef CONFIG_MTD_PARTITIONS
384 struct mtd_partition *partitions = NULL;
385 int num_partitions = 0;
388 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
390 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
394 /* Allocate memory for the device structure (and zero it) */
395 host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
397 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
401 host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
402 if (host->io_base == NULL) {
403 printk(KERN_ERR "atmel_nand: ioremap failed\n");
405 goto err_nand_ioremap;
409 nand_chip = &host->nand_chip;
410 host->board = pdev->dev.platform_data;
411 host->dev = &pdev->dev;
413 nand_chip->priv = host; /* link the private data structures */
414 mtd->priv = nand_chip;
415 mtd->owner = THIS_MODULE;
417 /* Set address of NAND IO lines */
418 nand_chip->IO_ADDR_R = host->io_base;
419 nand_chip->IO_ADDR_W = host->io_base;
420 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
422 if (host->board->rdy_pin)
423 nand_chip->dev_ready = atmel_nand_device_ready;
425 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
426 if (!regs && hard_ecc) {
427 printk(KERN_ERR "atmel_nand: can't get I/O resource "
428 "regs\nFalling back on software ECC\n");
431 nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
433 nand_chip->ecc.mode = NAND_ECC_NONE;
434 if (hard_ecc && regs) {
435 host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
436 if (host->ecc == NULL) {
437 printk(KERN_ERR "atmel_nand: ioremap failed\n");
439 goto err_ecc_ioremap;
441 nand_chip->ecc.mode = NAND_ECC_HW;
442 nand_chip->ecc.calculate = atmel_nand_calculate;
443 nand_chip->ecc.correct = atmel_nand_correct;
444 nand_chip->ecc.hwctl = atmel_nand_hwctl;
445 nand_chip->ecc.read_page = atmel_nand_read_page;
446 nand_chip->ecc.bytes = 4;
449 nand_chip->chip_delay = 20; /* 20us command delay time */
451 if (host->board->bus_width_16) { /* 16-bit bus width */
452 nand_chip->options |= NAND_BUSWIDTH_16;
453 nand_chip->read_buf = atmel_read_buf16;
454 nand_chip->write_buf = atmel_write_buf16;
456 nand_chip->read_buf = atmel_read_buf;
457 nand_chip->write_buf = atmel_write_buf;
460 platform_set_drvdata(pdev, host);
461 atmel_nand_enable(host);
463 if (host->board->det_pin) {
464 if (gpio_get_value(host->board->det_pin)) {
465 printk(KERN_INFO "No SmartMedia card inserted.\n");
472 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
473 nand_chip->options |= NAND_USE_FLASH_BBT;
476 /* first scan to find the device and get the page size */
477 if (nand_scan_ident(mtd, 1, NULL)) {
482 if (nand_chip->ecc.mode == NAND_ECC_HW) {
483 /* ECC is calculated for the whole page (1 step) */
484 nand_chip->ecc.size = mtd->writesize;
486 /* set ECC page size and oob layout */
487 switch (mtd->writesize) {
489 nand_chip->ecc.layout = &atmel_oobinfo_small;
490 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
493 nand_chip->ecc.layout = &atmel_oobinfo_large;
494 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
497 nand_chip->ecc.layout = &atmel_oobinfo_large;
498 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
501 nand_chip->ecc.layout = &atmel_oobinfo_large;
502 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
505 /* page size not handled by HW ECC */
506 /* switching back to soft ECC */
507 nand_chip->ecc.mode = NAND_ECC_SOFT;
508 nand_chip->ecc.calculate = NULL;
509 nand_chip->ecc.correct = NULL;
510 nand_chip->ecc.hwctl = NULL;
511 nand_chip->ecc.read_page = NULL;
512 nand_chip->ecc.postpad = 0;
513 nand_chip->ecc.prepad = 0;
514 nand_chip->ecc.bytes = 0;
519 /* second phase scan */
520 if (nand_scan_tail(mtd)) {
525 #ifdef CONFIG_MTD_PARTITIONS
526 #ifdef CONFIG_MTD_CMDLINE_PARTS
527 mtd->name = "atmel_nand";
528 num_partitions = parse_mtd_partitions(mtd, part_probes,
531 if (num_partitions <= 0 && host->board->partition_info)
532 partitions = host->board->partition_info(mtd->size,
535 if ((!partitions) || (num_partitions == 0)) {
536 printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n");
538 goto err_no_partitions;
541 res = add_mtd_partitions(mtd, partitions, num_partitions);
543 res = add_mtd_device(mtd);
549 #ifdef CONFIG_MTD_PARTITIONS
556 atmel_nand_disable(host);
557 platform_set_drvdata(pdev, NULL);
561 iounmap(host->io_base);
568 * Remove a NAND device.
570 static int __exit atmel_nand_remove(struct platform_device *pdev)
572 struct atmel_nand_host *host = platform_get_drvdata(pdev);
573 struct mtd_info *mtd = &host->mtd;
577 atmel_nand_disable(host);
581 iounmap(host->io_base);
587 static struct platform_driver atmel_nand_driver = {
588 .remove = __exit_p(atmel_nand_remove),
590 .name = "atmel_nand",
591 .owner = THIS_MODULE,
595 static int __init atmel_nand_init(void)
597 return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
601 static void __exit atmel_nand_exit(void)
603 platform_driver_unregister(&atmel_nand_driver);
607 module_init(atmel_nand_init);
608 module_exit(atmel_nand_exit);
610 MODULE_LICENSE("GPL");
611 MODULE_AUTHOR("Rick Bronson");
612 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
613 MODULE_ALIAS("platform:atmel_nand");