2 * drivers/mtd/nand/au1550nd.c
4 * Copyright (C) 2004 Embedded Edge, LLC
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/slab.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/platform_device.h>
21 #include <asm/mach-au1x00/au1000.h>
22 #include <asm/mach-au1x00/au1550nd.h>
27 struct nand_chip chip;
31 void (*write_byte)(struct mtd_info *, u_char);
35 * au_read_byte - read one byte from the chip
36 * @mtd: MTD device structure
38 * read function for 8bit buswidth
40 static u_char au_read_byte(struct mtd_info *mtd)
42 struct nand_chip *this = mtd->priv;
43 u_char ret = readb(this->IO_ADDR_R);
49 * au_write_byte - write one byte to the chip
50 * @mtd: MTD device structure
51 * @byte: pointer to data byte to write
53 * write function for 8it buswidth
55 static void au_write_byte(struct mtd_info *mtd, u_char byte)
57 struct nand_chip *this = mtd->priv;
58 writeb(byte, this->IO_ADDR_W);
63 * au_read_byte16 - read one byte endianness aware from the chip
64 * @mtd: MTD device structure
66 * read function for 16bit buswidth with endianness conversion
68 static u_char au_read_byte16(struct mtd_info *mtd)
70 struct nand_chip *this = mtd->priv;
71 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
77 * au_write_byte16 - write one byte endianness aware to the chip
78 * @mtd: MTD device structure
79 * @byte: pointer to data byte to write
81 * write function for 16bit buswidth with endianness conversion
83 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
85 struct nand_chip *this = mtd->priv;
86 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
91 * au_read_word - read one word from the chip
92 * @mtd: MTD device structure
94 * read function for 16bit buswidth without endianness conversion
96 static u16 au_read_word(struct mtd_info *mtd)
98 struct nand_chip *this = mtd->priv;
99 u16 ret = readw(this->IO_ADDR_R);
105 * au_write_buf - write buffer to chip
106 * @mtd: MTD device structure
108 * @len: number of bytes to write
110 * write function for 8bit buswidth
112 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
115 struct nand_chip *this = mtd->priv;
117 for (i = 0; i < len; i++) {
118 writeb(buf[i], this->IO_ADDR_W);
124 * au_read_buf - read chip data into buffer
125 * @mtd: MTD device structure
126 * @buf: buffer to store date
127 * @len: number of bytes to read
129 * read function for 8bit buswidth
131 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
134 struct nand_chip *this = mtd->priv;
136 for (i = 0; i < len; i++) {
137 buf[i] = readb(this->IO_ADDR_R);
143 * au_write_buf16 - write buffer to chip
144 * @mtd: MTD device structure
146 * @len: number of bytes to write
148 * write function for 16bit buswidth
150 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
153 struct nand_chip *this = mtd->priv;
154 u16 *p = (u16 *) buf;
157 for (i = 0; i < len; i++) {
158 writew(p[i], this->IO_ADDR_W);
165 * au_read_buf16 - read chip data into buffer
166 * @mtd: MTD device structure
167 * @buf: buffer to store date
168 * @len: number of bytes to read
170 * read function for 16bit buswidth
172 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
175 struct nand_chip *this = mtd->priv;
176 u16 *p = (u16 *) buf;
179 for (i = 0; i < len; i++) {
180 p[i] = readw(this->IO_ADDR_R);
185 /* Select the chip by setting nCE to low */
186 #define NAND_CTL_SETNCE 1
187 /* Deselect the chip by setting nCE to high */
188 #define NAND_CTL_CLRNCE 2
189 /* Select the command latch by setting CLE to high */
190 #define NAND_CTL_SETCLE 3
191 /* Deselect the command latch by setting CLE to low */
192 #define NAND_CTL_CLRCLE 4
193 /* Select the address latch by setting ALE to high */
194 #define NAND_CTL_SETALE 5
195 /* Deselect the address latch by setting ALE to low */
196 #define NAND_CTL_CLRALE 6
198 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
200 struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
201 struct nand_chip *this = mtd->priv;
205 case NAND_CTL_SETCLE:
206 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
209 case NAND_CTL_CLRCLE:
210 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
213 case NAND_CTL_SETALE:
214 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
217 case NAND_CTL_CLRALE:
218 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
219 /* FIXME: Nobody knows why this is necessary,
220 * but it works only that way */
224 case NAND_CTL_SETNCE:
225 /* assert (force assert) chip enable */
226 au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
229 case NAND_CTL_CLRNCE:
230 /* deassert chip enable */
231 au_writel(0, MEM_STNDCTL);
235 this->IO_ADDR_R = this->IO_ADDR_W;
237 /* Drain the writebuffer */
241 int au1550_device_ready(struct mtd_info *mtd)
243 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
249 * au1550_select_chip - control -CE line
250 * Forbid driving -CE manually permitting the NAND controller to do this.
251 * Keeping -CE asserted during the whole sector reads interferes with the
252 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
253 * We only have to hold -CE low for the NAND read commands since the flash
254 * chip needs it to be asserted during chip not ready time but the NAND
255 * controller keeps it released.
257 * @mtd: MTD device structure
258 * @chip: chipnumber to select, -1 for deselect
260 static void au1550_select_chip(struct mtd_info *mtd, int chip)
265 * au1550_command - Send command to NAND device
266 * @mtd: MTD device structure
267 * @command: the command to be sent
268 * @column: the column address for this command, -1 if none
269 * @page_addr: the page address for this command, -1 if none
271 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
273 struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
274 struct nand_chip *this = mtd->priv;
275 int ce_override = 0, i;
276 unsigned long flags = 0;
278 /* Begin command latch cycle */
279 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
281 * Write out the command to the device.
283 if (command == NAND_CMD_SEQIN) {
286 if (column >= mtd->writesize) {
288 column -= mtd->writesize;
289 readcmd = NAND_CMD_READOOB;
290 } else if (column < 256) {
291 /* First 256 bytes --> READ0 */
292 readcmd = NAND_CMD_READ0;
295 readcmd = NAND_CMD_READ1;
297 ctx->write_byte(mtd, readcmd);
299 ctx->write_byte(mtd, command);
301 /* Set ALE and clear CLE to start address cycle */
302 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
304 if (column != -1 || page_addr != -1) {
305 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
307 /* Serially input address */
309 /* Adjust columns for 16 bit buswidth */
310 if (this->options & NAND_BUSWIDTH_16 &&
311 !nand_opcode_8bits(command))
313 ctx->write_byte(mtd, column);
315 if (page_addr != -1) {
316 ctx->write_byte(mtd, (u8)(page_addr & 0xff));
318 if (command == NAND_CMD_READ0 ||
319 command == NAND_CMD_READ1 ||
320 command == NAND_CMD_READOOB) {
322 * NAND controller will release -CE after
323 * the last address byte is written, so we'll
324 * have to forcibly assert it. No interrupts
325 * are allowed while we do this as we don't
326 * want the NOR flash or PCMCIA drivers to
327 * steal our precious bytes of data...
330 local_irq_save(flags);
331 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
334 ctx->write_byte(mtd, (u8)(page_addr >> 8));
336 /* One more address cycle for devices > 32MiB */
337 if (this->chipsize > (32 << 20))
339 ((page_addr >> 16) & 0x0f));
341 /* Latch in address */
342 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
346 * Program and erase have their own busy handlers.
347 * Status and sequential in need no delay.
351 case NAND_CMD_PAGEPROG:
352 case NAND_CMD_ERASE1:
353 case NAND_CMD_ERASE2:
355 case NAND_CMD_STATUS:
363 case NAND_CMD_READOOB:
364 /* Check if we're really driving -CE low (just in case) */
365 if (unlikely(!ce_override))
368 /* Apply a short delay always to ensure that we do wait tWB. */
370 /* Wait for a chip to become ready... */
371 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
374 /* Release -CE and re-enable interrupts. */
375 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
376 local_irq_restore(flags);
379 /* Apply this short delay always to ensure that we do wait tWB. */
382 while(!this->dev_ready(mtd));
385 static int find_nand_cs(unsigned long nand_base)
388 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
389 unsigned long addr, staddr, start, mask, end;
392 for (i = 0; i < 4; i++) {
393 addr = 0x1000 + (i * 0x10); /* CSx */
394 staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
395 /* figure out the decoded range of this CS */
396 start = (staddr << 4) & 0xfffc0000;
397 mask = (staddr << 18) & 0xfffc0000;
398 end = (start | (start - 1)) & ~(start ^ mask);
399 if ((nand_base >= start) && (nand_base < end))
406 static int au1550nd_probe(struct platform_device *pdev)
408 struct au1550nd_platdata *pd;
409 struct au1550nd_ctx *ctx;
410 struct nand_chip *this;
414 pd = dev_get_platdata(&pdev->dev);
416 dev_err(&pdev->dev, "missing platform data\n");
420 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
424 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 dev_err(&pdev->dev, "no NAND memory resource\n");
430 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
431 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
436 ctx->base = ioremap_nocache(r->start, 0x1000);
438 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
444 ctx->info.priv = this;
445 ctx->info.owner = THIS_MODULE;
447 /* figure out which CS# r->start belongs to */
448 cs = find_nand_cs(r->start);
450 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
456 this->dev_ready = au1550_device_ready;
457 this->select_chip = au1550_select_chip;
458 this->cmdfunc = au1550_command;
460 /* 30 us command delay time */
461 this->chip_delay = 30;
462 this->ecc.mode = NAND_ECC_SOFT;
465 this->options |= NAND_BUSWIDTH_16;
467 this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
468 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
469 this->read_word = au_read_word;
470 this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
471 this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
473 ret = nand_scan(&ctx->info, 1);
475 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
479 mtd_device_register(&ctx->info, pd->parts, pd->num_parts);
481 platform_set_drvdata(pdev, ctx);
488 release_mem_region(r->start, resource_size(r));
494 static int au1550nd_remove(struct platform_device *pdev)
496 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
497 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
499 nand_release(&ctx->info);
501 release_mem_region(r->start, 0x1000);
506 static struct platform_driver au1550nd_driver = {
508 .name = "au1550-nand",
509 .owner = THIS_MODULE,
511 .probe = au1550nd_probe,
512 .remove = au1550nd_remove,
515 module_platform_driver(au1550nd_driver);
517 MODULE_LICENSE("GPL");
518 MODULE_AUTHOR("Embedded Edge, LLC");
519 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");