2 * drivers/mtd/nand/au1550nd.c
4 * Copyright (C) 2004 Embedded Edge, LLC
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/slab.h>
13 #include <linux/gpio.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/partitions.h>
22 #ifdef CONFIG_MIPS_PB1550
23 #include <asm/mach-pb1x00/pb1550.h>
24 #elif defined(CONFIG_MIPS_DB1550)
25 #include <asm/mach-db1x00/db1x00.h>
27 #include <asm/mach-db1x00/bcsr.h>
30 * MTD structure for NAND controller
32 static struct mtd_info *au1550_mtd = NULL;
33 static void __iomem *p_nand;
34 static int nand_width = 1; /* default x8 */
35 static void (*au1550_write_byte)(struct mtd_info *, u_char);
38 * Define partitions for flash device
40 static const struct mtd_partition partition_info[] = {
44 .size = 8 * 1024 * 1024},
47 .offset = MTDPART_OFS_APPEND,
48 .size = MTDPART_SIZ_FULL}
52 * au_read_byte - read one byte from the chip
53 * @mtd: MTD device structure
55 * read function for 8bit buswith
57 static u_char au_read_byte(struct mtd_info *mtd)
59 struct nand_chip *this = mtd->priv;
60 u_char ret = readb(this->IO_ADDR_R);
66 * au_write_byte - write one byte to the chip
67 * @mtd: MTD device structure
68 * @byte: pointer to data byte to write
70 * write function for 8it buswith
72 static void au_write_byte(struct mtd_info *mtd, u_char byte)
74 struct nand_chip *this = mtd->priv;
75 writeb(byte, this->IO_ADDR_W);
80 * au_read_byte16 - read one byte endianess aware from the chip
81 * @mtd: MTD device structure
83 * read function for 16bit buswith with
84 * endianess conversion
86 static u_char au_read_byte16(struct mtd_info *mtd)
88 struct nand_chip *this = mtd->priv;
89 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
95 * au_write_byte16 - write one byte endianess aware to the chip
96 * @mtd: MTD device structure
97 * @byte: pointer to data byte to write
99 * write function for 16bit buswith with
100 * endianess conversion
102 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
104 struct nand_chip *this = mtd->priv;
105 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
110 * au_read_word - read one word from the chip
111 * @mtd: MTD device structure
113 * read function for 16bit buswith without
114 * endianess conversion
116 static u16 au_read_word(struct mtd_info *mtd)
118 struct nand_chip *this = mtd->priv;
119 u16 ret = readw(this->IO_ADDR_R);
125 * au_write_buf - write buffer to chip
126 * @mtd: MTD device structure
128 * @len: number of bytes to write
130 * write function for 8bit buswith
132 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
135 struct nand_chip *this = mtd->priv;
137 for (i = 0; i < len; i++) {
138 writeb(buf[i], this->IO_ADDR_W);
144 * au_read_buf - read chip data into buffer
145 * @mtd: MTD device structure
146 * @buf: buffer to store date
147 * @len: number of bytes to read
149 * read function for 8bit buswith
151 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
154 struct nand_chip *this = mtd->priv;
156 for (i = 0; i < len; i++) {
157 buf[i] = readb(this->IO_ADDR_R);
163 * au_verify_buf - Verify chip data against buffer
164 * @mtd: MTD device structure
165 * @buf: buffer containing the data to compare
166 * @len: number of bytes to compare
168 * verify function for 8bit buswith
170 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
173 struct nand_chip *this = mtd->priv;
175 for (i = 0; i < len; i++) {
176 if (buf[i] != readb(this->IO_ADDR_R))
185 * au_write_buf16 - write buffer to chip
186 * @mtd: MTD device structure
188 * @len: number of bytes to write
190 * write function for 16bit buswith
192 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
195 struct nand_chip *this = mtd->priv;
196 u16 *p = (u16 *) buf;
199 for (i = 0; i < len; i++) {
200 writew(p[i], this->IO_ADDR_W);
207 * au_read_buf16 - read chip data into buffer
208 * @mtd: MTD device structure
209 * @buf: buffer to store date
210 * @len: number of bytes to read
212 * read function for 16bit buswith
214 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
217 struct nand_chip *this = mtd->priv;
218 u16 *p = (u16 *) buf;
221 for (i = 0; i < len; i++) {
222 p[i] = readw(this->IO_ADDR_R);
228 * au_verify_buf16 - Verify chip data against buffer
229 * @mtd: MTD device structure
230 * @buf: buffer containing the data to compare
231 * @len: number of bytes to compare
233 * verify function for 16bit buswith
235 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
238 struct nand_chip *this = mtd->priv;
239 u16 *p = (u16 *) buf;
242 for (i = 0; i < len; i++) {
243 if (p[i] != readw(this->IO_ADDR_R))
250 /* Select the chip by setting nCE to low */
251 #define NAND_CTL_SETNCE 1
252 /* Deselect the chip by setting nCE to high */
253 #define NAND_CTL_CLRNCE 2
254 /* Select the command latch by setting CLE to high */
255 #define NAND_CTL_SETCLE 3
256 /* Deselect the command latch by setting CLE to low */
257 #define NAND_CTL_CLRCLE 4
258 /* Select the address latch by setting ALE to high */
259 #define NAND_CTL_SETALE 5
260 /* Deselect the address latch by setting ALE to low */
261 #define NAND_CTL_CLRALE 6
263 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
265 register struct nand_chip *this = mtd->priv;
269 case NAND_CTL_SETCLE:
270 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
273 case NAND_CTL_CLRCLE:
274 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
277 case NAND_CTL_SETALE:
278 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
281 case NAND_CTL_CLRALE:
282 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
283 /* FIXME: Nobody knows why this is necessary,
284 * but it works only that way */
288 case NAND_CTL_SETNCE:
289 /* assert (force assert) chip enable */
290 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
293 case NAND_CTL_CLRNCE:
294 /* deassert chip enable */
295 au_writel(0, MEM_STNDCTL);
299 this->IO_ADDR_R = this->IO_ADDR_W;
301 /* Drain the writebuffer */
305 int au1550_device_ready(struct mtd_info *mtd)
307 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
313 * au1550_select_chip - control -CE line
314 * Forbid driving -CE manually permitting the NAND controller to do this.
315 * Keeping -CE asserted during the whole sector reads interferes with the
316 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
317 * We only have to hold -CE low for the NAND read commands since the flash
318 * chip needs it to be asserted during chip not ready time but the NAND
319 * controller keeps it released.
321 * @mtd: MTD device structure
322 * @chip: chipnumber to select, -1 for deselect
324 static void au1550_select_chip(struct mtd_info *mtd, int chip)
329 * au1550_command - Send command to NAND device
330 * @mtd: MTD device structure
331 * @command: the command to be sent
332 * @column: the column address for this command, -1 if none
333 * @page_addr: the page address for this command, -1 if none
335 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
337 register struct nand_chip *this = mtd->priv;
338 int ce_override = 0, i;
341 /* Begin command latch cycle */
342 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
344 * Write out the command to the device.
346 if (command == NAND_CMD_SEQIN) {
349 if (column >= mtd->writesize) {
351 column -= mtd->writesize;
352 readcmd = NAND_CMD_READOOB;
353 } else if (column < 256) {
354 /* First 256 bytes --> READ0 */
355 readcmd = NAND_CMD_READ0;
358 readcmd = NAND_CMD_READ1;
360 au1550_write_byte(mtd, readcmd);
362 au1550_write_byte(mtd, command);
364 /* Set ALE and clear CLE to start address cycle */
365 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
367 if (column != -1 || page_addr != -1) {
368 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
370 /* Serially input address */
372 /* Adjust columns for 16 bit buswidth */
373 if (this->options & NAND_BUSWIDTH_16)
375 au1550_write_byte(mtd, column);
377 if (page_addr != -1) {
378 au1550_write_byte(mtd, (u8)(page_addr & 0xff));
380 if (command == NAND_CMD_READ0 ||
381 command == NAND_CMD_READ1 ||
382 command == NAND_CMD_READOOB) {
384 * NAND controller will release -CE after
385 * the last address byte is written, so we'll
386 * have to forcibly assert it. No interrupts
387 * are allowed while we do this as we don't
388 * want the NOR flash or PCMCIA drivers to
389 * steal our precious bytes of data...
392 local_irq_save(flags);
393 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
396 au1550_write_byte(mtd, (u8)(page_addr >> 8));
398 /* One more address cycle for devices > 32MiB */
399 if (this->chipsize > (32 << 20))
400 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
402 /* Latch in address */
403 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
407 * Program and erase have their own busy handlers.
408 * Status and sequential in need no delay.
412 case NAND_CMD_PAGEPROG:
413 case NAND_CMD_ERASE1:
414 case NAND_CMD_ERASE2:
416 case NAND_CMD_STATUS:
424 case NAND_CMD_READOOB:
425 /* Check if we're really driving -CE low (just in case) */
426 if (unlikely(!ce_override))
429 /* Apply a short delay always to ensure that we do wait tWB. */
431 /* Wait for a chip to become ready... */
432 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
435 /* Release -CE and re-enable interrupts. */
436 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
437 local_irq_restore(flags);
440 /* Apply this short delay always to ensure that we do wait tWB. */
443 while(!this->dev_ready(mtd));
448 * Main initialization routine
450 static int __init au1xxx_nand_init(void)
452 struct nand_chip *this;
453 u16 boot_swapboot = 0; /* default value */
458 /* Allocate memory for MTD device structure and private data */
459 au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
461 printk("Unable to allocate NAND MTD dev structure.\n");
465 /* Get pointer to private data */
466 this = (struct nand_chip *)(&au1550_mtd[1]);
468 /* Link the private data with the MTD structure */
469 au1550_mtd->priv = this;
470 au1550_mtd->owner = THIS_MODULE;
473 /* MEM_STNDCTL: disable ints, disable nand boot */
474 au_writel(0, MEM_STNDCTL);
476 #ifdef CONFIG_MIPS_PB1550
477 /* set gpio206 high */
478 gpio_direction_input(206);
480 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
482 switch (boot_swapboot) {
500 printk("Pb1550 NAND: bad boot:swap\n");
506 /* Configure chip-select; normally done by boot code, e.g. YAMON */
509 au_writel(NAND_STCFG, MEM_STCFG0);
510 au_writel(NAND_STTIME, MEM_STTIME0);
511 au_writel(NAND_STADDR, MEM_STADDR0);
514 au_writel(NAND_STCFG, MEM_STCFG1);
515 au_writel(NAND_STTIME, MEM_STTIME1);
516 au_writel(NAND_STADDR, MEM_STADDR1);
519 au_writel(NAND_STCFG, MEM_STCFG2);
520 au_writel(NAND_STTIME, MEM_STTIME2);
521 au_writel(NAND_STADDR, MEM_STADDR2);
524 au_writel(NAND_STCFG, MEM_STCFG3);
525 au_writel(NAND_STTIME, MEM_STTIME3);
526 au_writel(NAND_STADDR, MEM_STADDR3);
530 /* Locate NAND chip-select in order to determine NAND phys address */
531 mem_staddr = 0x00000000;
532 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
533 mem_staddr = au_readl(MEM_STADDR0);
534 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
535 mem_staddr = au_readl(MEM_STADDR1);
536 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
537 mem_staddr = au_readl(MEM_STADDR2);
538 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
539 mem_staddr = au_readl(MEM_STADDR3);
541 if (mem_staddr == 0x00000000) {
542 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
546 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
548 p_nand = ioremap(nand_phys, 0x1000);
550 /* make controller and MTD agree */
552 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
554 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
556 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
558 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
560 /* Set address of hardware control function */
561 this->dev_ready = au1550_device_ready;
562 this->select_chip = au1550_select_chip;
563 this->cmdfunc = au1550_command;
565 /* 30 us command delay time */
566 this->chip_delay = 30;
567 this->ecc.mode = NAND_ECC_SOFT;
569 this->options = NAND_NO_AUTOINCR;
572 this->options |= NAND_BUSWIDTH_16;
574 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
575 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
576 this->read_word = au_read_word;
577 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
578 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
579 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
581 /* Scan to find existence of the device */
582 if (nand_scan(au1550_mtd, 1)) {
587 /* Register the partitions */
588 mtd_device_register(au1550_mtd, partition_info,
589 ARRAY_SIZE(partition_info));
601 module_init(au1xxx_nand_init);
606 static void __exit au1550_cleanup(void)
608 /* Release resources, unregister device */
609 nand_release(au1550_mtd);
611 /* Free the MTD device structure */
618 module_exit(au1550_cleanup);
620 MODULE_LICENSE("GPL");
621 MODULE_AUTHOR("Embedded Edge, LLC");
622 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");