2 * drivers/mtd/nand/au1550nd.c
4 * Copyright (C) 2004 Embedded Edge, LLC
6 * $Id: au1550nd.c,v 1.13 2005/11/07 11:14:30 gleixner Exp $
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/version.h>
24 /* fixme: this is ugly */
25 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
26 #include <asm/mach-au1x00/au1xxx.h>
28 #include <asm/au1000.h>
29 #ifdef CONFIG_MIPS_PB1550
30 #include <asm/pb1550.h>
32 #ifdef CONFIG_MIPS_DB1550
33 #include <asm/db1x00.h>
38 * MTD structure for NAND controller
40 static struct mtd_info *au1550_mtd = NULL;
41 static void __iomem *p_nand;
42 static int nand_width = 1; /* default x8 */
45 * Define partitions for flash device
47 static const struct mtd_partition partition_info[] = {
51 .size = 8 * 1024 * 1024},
54 .offset = MTDPART_OFS_APPEND,
55 .size = MTDPART_SIZ_FULL}
59 * au_read_byte - read one byte from the chip
60 * @mtd: MTD device structure
62 * read function for 8bit buswith
64 static u_char au_read_byte(struct mtd_info *mtd)
66 struct nand_chip *this = mtd->priv;
67 u_char ret = readb(this->IO_ADDR_R);
73 * au_write_byte - write one byte to the chip
74 * @mtd: MTD device structure
75 * @byte: pointer to data byte to write
77 * write function for 8it buswith
79 static void au_write_byte(struct mtd_info *mtd, u_char byte)
81 struct nand_chip *this = mtd->priv;
82 writeb(byte, this->IO_ADDR_W);
87 * au_read_byte16 - read one byte endianess aware from the chip
88 * @mtd: MTD device structure
90 * read function for 16bit buswith with
91 * endianess conversion
93 static u_char au_read_byte16(struct mtd_info *mtd)
95 struct nand_chip *this = mtd->priv;
96 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
102 * au_write_byte16 - write one byte endianess aware to the chip
103 * @mtd: MTD device structure
104 * @byte: pointer to data byte to write
106 * write function for 16bit buswith with
107 * endianess conversion
109 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
111 struct nand_chip *this = mtd->priv;
112 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
117 * au_read_word - read one word from the chip
118 * @mtd: MTD device structure
120 * read function for 16bit buswith without
121 * endianess conversion
123 static u16 au_read_word(struct mtd_info *mtd)
125 struct nand_chip *this = mtd->priv;
126 u16 ret = readw(this->IO_ADDR_R);
132 * au_write_word - write one word to the chip
133 * @mtd: MTD device structure
134 * @word: data word to write
136 * write function for 16bit buswith without
137 * endianess conversion
139 static void au_write_word(struct mtd_info *mtd, u16 word)
141 struct nand_chip *this = mtd->priv;
142 writew(word, this->IO_ADDR_W);
147 * au_write_buf - write buffer to chip
148 * @mtd: MTD device structure
150 * @len: number of bytes to write
152 * write function for 8bit buswith
154 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
157 struct nand_chip *this = mtd->priv;
159 for (i = 0; i < len; i++) {
160 writeb(buf[i], this->IO_ADDR_W);
166 * au_read_buf - read chip data into buffer
167 * @mtd: MTD device structure
168 * @buf: buffer to store date
169 * @len: number of bytes to read
171 * read function for 8bit buswith
173 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
176 struct nand_chip *this = mtd->priv;
178 for (i = 0; i < len; i++) {
179 buf[i] = readb(this->IO_ADDR_R);
185 * au_verify_buf - Verify chip data against buffer
186 * @mtd: MTD device structure
187 * @buf: buffer containing the data to compare
188 * @len: number of bytes to compare
190 * verify function for 8bit buswith
192 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
195 struct nand_chip *this = mtd->priv;
197 for (i = 0; i < len; i++) {
198 if (buf[i] != readb(this->IO_ADDR_R))
207 * au_write_buf16 - write buffer to chip
208 * @mtd: MTD device structure
210 * @len: number of bytes to write
212 * write function for 16bit buswith
214 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
217 struct nand_chip *this = mtd->priv;
218 u16 *p = (u16 *) buf;
221 for (i = 0; i < len; i++) {
222 writew(p[i], this->IO_ADDR_W);
229 * au_read_buf16 - read chip data into buffer
230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
234 * read function for 16bit buswith
236 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
239 struct nand_chip *this = mtd->priv;
240 u16 *p = (u16 *) buf;
243 for (i = 0; i < len; i++) {
244 p[i] = readw(this->IO_ADDR_R);
250 * au_verify_buf16 - Verify chip data against buffer
251 * @mtd: MTD device structure
252 * @buf: buffer containing the data to compare
253 * @len: number of bytes to compare
255 * verify function for 16bit buswith
257 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
260 struct nand_chip *this = mtd->priv;
261 u16 *p = (u16 *) buf;
264 for (i = 0; i < len; i++) {
265 if (p[i] != readw(this->IO_ADDR_R))
272 /* Select the chip by setting nCE to low */
273 #define NAND_CTL_SETNCE 1
274 /* Deselect the chip by setting nCE to high */
275 #define NAND_CTL_CLRNCE 2
276 /* Select the command latch by setting CLE to high */
277 #define NAND_CTL_SETCLE 3
278 /* Deselect the command latch by setting CLE to low */
279 #define NAND_CTL_CLRCLE 4
280 /* Select the address latch by setting ALE to high */
281 #define NAND_CTL_SETALE 5
282 /* Deselect the address latch by setting ALE to low */
283 #define NAND_CTL_CLRALE 6
285 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
287 register struct nand_chip *this = mtd->priv;
291 case NAND_CTL_SETCLE:
292 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
295 case NAND_CTL_CLRCLE:
296 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
299 case NAND_CTL_SETALE:
300 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
303 case NAND_CTL_CLRALE:
304 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
305 /* FIXME: Nobody knows why this is necessary,
306 * but it works only that way */
310 case NAND_CTL_SETNCE:
311 /* assert (force assert) chip enable */
312 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
315 case NAND_CTL_CLRNCE:
316 /* deassert chip enable */
317 au_writel(0, MEM_STNDCTL);
321 this->IO_ADDR_R = this->IO_ADDR_W;
323 /* Drain the writebuffer */
327 int au1550_device_ready(struct mtd_info *mtd)
329 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
335 * au1550_select_chip - control -CE line
336 * Forbid driving -CE manually permitting the NAND controller to do this.
337 * Keeping -CE asserted during the whole sector reads interferes with the
338 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
339 * We only have to hold -CE low for the NAND read commands since the flash
340 * chip needs it to be asserted during chip not ready time but the NAND
341 * controller keeps it released.
343 * @mtd: MTD device structure
344 * @chip: chipnumber to select, -1 for deselect
346 static void au1550_select_chip(struct mtd_info *mtd, int chip)
351 * au1550_command - Send command to NAND device
352 * @mtd: MTD device structure
353 * @command: the command to be sent
354 * @column: the column address for this command, -1 if none
355 * @page_addr: the page address for this command, -1 if none
357 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
359 register struct nand_chip *this = mtd->priv;
360 int ce_override = 0, i;
363 /* Begin command latch cycle */
364 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
366 * Write out the command to the device.
368 if (command == NAND_CMD_SEQIN) {
371 if (column >= mtd->writesize) {
373 column -= mtd->writesize;
374 readcmd = NAND_CMD_READOOB;
375 } else if (column < 256) {
376 /* First 256 bytes --> READ0 */
377 readcmd = NAND_CMD_READ0;
380 readcmd = NAND_CMD_READ1;
382 this->write_byte(mtd, readcmd);
384 this->write_byte(mtd, command);
386 /* Set ALE and clear CLE to start address cycle */
387 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
389 if (column != -1 || page_addr != -1) {
390 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
392 /* Serially input address */
394 /* Adjust columns for 16 bit buswidth */
395 if (this->options & NAND_BUSWIDTH_16)
397 this->write_byte(mtd, column);
399 if (page_addr != -1) {
400 this->write_byte(mtd, (u8)(page_addr & 0xff));
402 if (command == NAND_CMD_READ0 ||
403 command == NAND_CMD_READ1 ||
404 command == NAND_CMD_READOOB) {
406 * NAND controller will release -CE after
407 * the last address byte is written, so we'll
408 * have to forcibly assert it. No interrupts
409 * are allowed while we do this as we don't
410 * want the NOR flash or PCMCIA drivers to
411 * steal our precious bytes of data...
414 local_irq_save(flags);
415 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
418 this->write_byte(mtd, (u8)(page_addr >> 8));
420 /* One more address cycle for devices > 32MiB */
421 if (this->chipsize > (32 << 20))
422 this->write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
424 /* Latch in address */
425 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
429 * Program and erase have their own busy handlers.
430 * Status and sequential in need no delay.
434 case NAND_CMD_PAGEPROG:
435 case NAND_CMD_ERASE1:
436 case NAND_CMD_ERASE2:
438 case NAND_CMD_STATUS:
446 case NAND_CMD_READOOB:
447 /* Check if we're really driving -CE low (just in case) */
448 if (unlikely(!ce_override))
451 /* Apply a short delay always to ensure that we do wait tWB. */
453 /* Wait for a chip to become ready... */
454 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
457 /* Release -CE and re-enable interrupts. */
458 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
459 local_irq_restore(flags);
462 /* Apply this short delay always to ensure that we do wait tWB. */
465 while(!this->dev_ready(mtd));
470 * Main initialization routine
472 static int __init au1xxx_nand_init(void)
474 struct nand_chip *this;
475 u16 boot_swapboot = 0; /* default value */
480 /* Allocate memory for MTD device structure and private data */
481 au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
483 printk("Unable to allocate NAND MTD dev structure.\n");
487 /* Get pointer to private data */
488 this = (struct nand_chip *)(&au1550_mtd[1]);
490 /* Initialize structures */
491 memset(au1550_mtd, 0, sizeof(struct mtd_info));
492 memset(this, 0, sizeof(struct nand_chip));
494 /* Link the private data with the MTD structure */
495 au1550_mtd->priv = this;
496 au1550_mtd->owner = THIS_MODULE;
499 /* MEM_STNDCTL: disable ints, disable nand boot */
500 au_writel(0, MEM_STNDCTL);
502 #ifdef CONFIG_MIPS_PB1550
503 /* set gpio206 high */
504 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
506 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
507 switch (boot_swapboot) {
525 printk("Pb1550 NAND: bad boot:swap\n");
531 /* Configure chip-select; normally done by boot code, e.g. YAMON */
534 au_writel(NAND_STCFG, MEM_STCFG0);
535 au_writel(NAND_STTIME, MEM_STTIME0);
536 au_writel(NAND_STADDR, MEM_STADDR0);
539 au_writel(NAND_STCFG, MEM_STCFG1);
540 au_writel(NAND_STTIME, MEM_STTIME1);
541 au_writel(NAND_STADDR, MEM_STADDR1);
544 au_writel(NAND_STCFG, MEM_STCFG2);
545 au_writel(NAND_STTIME, MEM_STTIME2);
546 au_writel(NAND_STADDR, MEM_STADDR2);
549 au_writel(NAND_STCFG, MEM_STCFG3);
550 au_writel(NAND_STTIME, MEM_STTIME3);
551 au_writel(NAND_STADDR, MEM_STADDR3);
555 /* Locate NAND chip-select in order to determine NAND phys address */
556 mem_staddr = 0x00000000;
557 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
558 mem_staddr = au_readl(MEM_STADDR0);
559 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
560 mem_staddr = au_readl(MEM_STADDR1);
561 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
562 mem_staddr = au_readl(MEM_STADDR2);
563 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
564 mem_staddr = au_readl(MEM_STADDR3);
566 if (mem_staddr == 0x00000000) {
567 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
571 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
573 p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
575 /* make controller and MTD agree */
577 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
579 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
581 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
583 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
585 /* Set address of hardware control function */
586 this->dev_ready = au1550_device_ready;
587 this->select_chip = au1550_select_chip;
588 this->cmdfunc = au1550_command;
590 /* 30 us command delay time */
591 this->chip_delay = 30;
592 this->ecc.mode = NAND_ECC_SOFT;
594 this->options = NAND_NO_AUTOINCR;
597 this->options |= NAND_BUSWIDTH_16;
599 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
600 this->write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
601 this->write_word = au_write_word;
602 this->read_word = au_read_word;
603 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
604 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
605 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
607 /* Scan to find existence of the device */
608 if (nand_scan(au1550_mtd, 1)) {
613 /* Register the partitions */
614 add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
619 iounmap((void *)p_nand);
626 module_init(au1xxx_nand_init);
631 static void __exit au1550_cleanup(void)
633 struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1];
635 /* Release resources, unregister device */
636 nand_release(au1550_mtd);
638 /* Free the MTD device structure */
642 iounmap((void *)p_nand);
645 module_exit(au1550_cleanup);
647 MODULE_LICENSE("GPL");
648 MODULE_AUTHOR("Embedded Edge, LLC");
649 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");