2 * Copyright © 2010-2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/version.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/err.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/ioport.h>
27 #include <linux/bug.h>
28 #include <linux/kernel.h>
29 #include <linux/bitops.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/mtd/partitions.h>
35 #include <linux/of_mtd.h>
36 #include <linux/of_platform.h>
37 #include <linux/slab.h>
38 #include <linux/list.h>
39 #include <linux/log2.h>
44 * This flag controls if WP stays on between erase/write commands to mitigate
45 * flash corruption due to power glitches. Values:
46 * 0: NAND_WP is not used or not available
47 * 1: NAND_WP is set by default, cleared for erase/write operations
48 * 2: NAND_WP is always cleared
51 module_param(wp_on, int, 0444);
53 /***********************************************************************
55 ***********************************************************************/
57 #define DRV_NAME "brcmnand"
60 #define CMD_PAGE_READ 0x01
61 #define CMD_SPARE_AREA_READ 0x02
62 #define CMD_STATUS_READ 0x03
63 #define CMD_PROGRAM_PAGE 0x04
64 #define CMD_PROGRAM_SPARE_AREA 0x05
65 #define CMD_COPY_BACK 0x06
66 #define CMD_DEVICE_ID_READ 0x07
67 #define CMD_BLOCK_ERASE 0x08
68 #define CMD_FLASH_RESET 0x09
69 #define CMD_BLOCKS_LOCK 0x0a
70 #define CMD_BLOCKS_LOCK_DOWN 0x0b
71 #define CMD_BLOCKS_UNLOCK 0x0c
72 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
73 #define CMD_PARAMETER_READ 0x0e
74 #define CMD_PARAMETER_CHANGE_COL 0x0f
75 #define CMD_LOW_LEVEL_OP 0x10
77 struct brcm_nand_dma_desc {
92 /* Bitfields for brcm_nand_dma_desc::status_valid */
93 #define FLASH_DMA_ECC_ERROR (1 << 8)
94 #define FLASH_DMA_CORR_ERROR (1 << 9)
96 /* 512B flash cache in the NAND controller HW */
99 #define FC_WORDS (FC_BYTES >> 2)
101 #define BRCMNAND_MIN_PAGESIZE 512
102 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
103 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
105 /* Controller feature flags */
107 BRCMNAND_HAS_1K_SECTORS = BIT(0),
108 BRCMNAND_HAS_PREFETCH = BIT(1),
109 BRCMNAND_HAS_CACHE_MODE = BIT(2),
110 BRCMNAND_HAS_WP = BIT(3),
113 struct brcmnand_controller {
115 struct nand_hw_control controller;
116 void __iomem *nand_base;
117 void __iomem *nand_fc; /* flash cache */
118 void __iomem *flash_dma_base;
120 unsigned int dma_irq;
123 /* Some SoCs provide custom interrupt status register(s) */
124 struct brcmnand_soc *soc;
126 /* Some SoCs have a gateable clock for the controller */
131 struct completion done;
132 struct completion dma_done;
134 /* List of NAND hosts (one for each chip-select) */
135 struct list_head host_list;
137 struct brcm_nand_dma_desc *dma_desc;
140 /* in-memory cache of the FLASH_CACHE, used only for some commands */
141 u8 flash_cache[FC_BYTES];
143 /* Controller revision details */
144 const u16 *reg_offsets;
145 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
146 const u8 *cs_offsets; /* within each chip-select */
147 const u8 *cs0_offsets; /* within CS0, if different */
148 unsigned int max_block_size;
149 const unsigned int *block_sizes;
150 unsigned int max_page_size;
151 const unsigned int *page_sizes;
152 unsigned int max_oob;
155 /* for low-power standby/resume only */
156 u32 nand_cs_nand_select;
157 u32 nand_cs_nand_xor;
158 u32 corr_stat_threshold;
162 struct brcmnand_cfg {
164 unsigned int block_size;
165 unsigned int page_size;
166 unsigned int spare_area_size;
167 unsigned int device_width;
168 unsigned int col_adr_bytes;
169 unsigned int blk_adr_bytes;
170 unsigned int ful_adr_bytes;
171 unsigned int sector_size_1k;
172 unsigned int ecc_level;
173 /* use for low-power standby/resume only */
181 struct brcmnand_host {
182 struct list_head node;
184 struct nand_chip chip;
185 struct platform_device *pdev;
188 unsigned int last_cmd;
189 unsigned int last_byte;
191 struct brcmnand_cfg hwcfg;
192 struct brcmnand_controller *ctrl;
196 BRCMNAND_CMD_START = 0,
197 BRCMNAND_CMD_EXT_ADDRESS,
198 BRCMNAND_CMD_ADDRESS,
199 BRCMNAND_INTFC_STATUS,
204 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
205 BRCMNAND_CORR_THRESHOLD,
206 BRCMNAND_CORR_THRESHOLD_EXT,
207 BRCMNAND_UNCORR_COUNT,
209 BRCMNAND_CORR_EXT_ADDR,
211 BRCMNAND_UNCORR_EXT_ADDR,
212 BRCMNAND_UNCORR_ADDR,
217 BRCMNAND_OOB_READ_BASE,
218 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
219 BRCMNAND_OOB_WRITE_BASE,
220 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
225 static const u16 brcmnand_regs_v40[] = {
226 [BRCMNAND_CMD_START] = 0x04,
227 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
228 [BRCMNAND_CMD_ADDRESS] = 0x0c,
229 [BRCMNAND_INTFC_STATUS] = 0x6c,
230 [BRCMNAND_CS_SELECT] = 0x14,
231 [BRCMNAND_CS_XOR] = 0x18,
232 [BRCMNAND_LL_OP] = 0x178,
233 [BRCMNAND_CS0_BASE] = 0x40,
234 [BRCMNAND_CS1_BASE] = 0xd0,
235 [BRCMNAND_CORR_THRESHOLD] = 0x84,
236 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
237 [BRCMNAND_UNCORR_COUNT] = 0,
238 [BRCMNAND_CORR_COUNT] = 0,
239 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
240 [BRCMNAND_CORR_ADDR] = 0x74,
241 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
242 [BRCMNAND_UNCORR_ADDR] = 0x7c,
243 [BRCMNAND_SEMAPHORE] = 0x58,
244 [BRCMNAND_ID] = 0x60,
245 [BRCMNAND_ID_EXT] = 0x64,
246 [BRCMNAND_LL_RDATA] = 0x17c,
247 [BRCMNAND_OOB_READ_BASE] = 0x20,
248 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
249 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
250 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
251 [BRCMNAND_FC_BASE] = 0x200,
255 static const u16 brcmnand_regs_v50[] = {
256 [BRCMNAND_CMD_START] = 0x04,
257 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
258 [BRCMNAND_CMD_ADDRESS] = 0x0c,
259 [BRCMNAND_INTFC_STATUS] = 0x6c,
260 [BRCMNAND_CS_SELECT] = 0x14,
261 [BRCMNAND_CS_XOR] = 0x18,
262 [BRCMNAND_LL_OP] = 0x178,
263 [BRCMNAND_CS0_BASE] = 0x40,
264 [BRCMNAND_CS1_BASE] = 0xd0,
265 [BRCMNAND_CORR_THRESHOLD] = 0x84,
266 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
267 [BRCMNAND_UNCORR_COUNT] = 0,
268 [BRCMNAND_CORR_COUNT] = 0,
269 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
270 [BRCMNAND_CORR_ADDR] = 0x74,
271 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
272 [BRCMNAND_UNCORR_ADDR] = 0x7c,
273 [BRCMNAND_SEMAPHORE] = 0x58,
274 [BRCMNAND_ID] = 0x60,
275 [BRCMNAND_ID_EXT] = 0x64,
276 [BRCMNAND_LL_RDATA] = 0x17c,
277 [BRCMNAND_OOB_READ_BASE] = 0x20,
278 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
279 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
280 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
281 [BRCMNAND_FC_BASE] = 0x200,
284 /* BRCMNAND v6.0 - v7.1 */
285 static const u16 brcmnand_regs_v60[] = {
286 [BRCMNAND_CMD_START] = 0x04,
287 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
288 [BRCMNAND_CMD_ADDRESS] = 0x0c,
289 [BRCMNAND_INTFC_STATUS] = 0x14,
290 [BRCMNAND_CS_SELECT] = 0x18,
291 [BRCMNAND_CS_XOR] = 0x1c,
292 [BRCMNAND_LL_OP] = 0x20,
293 [BRCMNAND_CS0_BASE] = 0x50,
294 [BRCMNAND_CS1_BASE] = 0,
295 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
296 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
297 [BRCMNAND_UNCORR_COUNT] = 0xfc,
298 [BRCMNAND_CORR_COUNT] = 0x100,
299 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
300 [BRCMNAND_CORR_ADDR] = 0x110,
301 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
302 [BRCMNAND_UNCORR_ADDR] = 0x118,
303 [BRCMNAND_SEMAPHORE] = 0x150,
304 [BRCMNAND_ID] = 0x194,
305 [BRCMNAND_ID_EXT] = 0x198,
306 [BRCMNAND_LL_RDATA] = 0x19c,
307 [BRCMNAND_OOB_READ_BASE] = 0x200,
308 [BRCMNAND_OOB_READ_10_BASE] = 0,
309 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
310 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
311 [BRCMNAND_FC_BASE] = 0x400,
315 static const u16 brcmnand_regs_v71[] = {
316 [BRCMNAND_CMD_START] = 0x04,
317 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
318 [BRCMNAND_CMD_ADDRESS] = 0x0c,
319 [BRCMNAND_INTFC_STATUS] = 0x14,
320 [BRCMNAND_CS_SELECT] = 0x18,
321 [BRCMNAND_CS_XOR] = 0x1c,
322 [BRCMNAND_LL_OP] = 0x20,
323 [BRCMNAND_CS0_BASE] = 0x50,
324 [BRCMNAND_CS1_BASE] = 0,
325 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
326 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
327 [BRCMNAND_UNCORR_COUNT] = 0xfc,
328 [BRCMNAND_CORR_COUNT] = 0x100,
329 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
330 [BRCMNAND_CORR_ADDR] = 0x110,
331 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
332 [BRCMNAND_UNCORR_ADDR] = 0x118,
333 [BRCMNAND_SEMAPHORE] = 0x150,
334 [BRCMNAND_ID] = 0x194,
335 [BRCMNAND_ID_EXT] = 0x198,
336 [BRCMNAND_LL_RDATA] = 0x19c,
337 [BRCMNAND_OOB_READ_BASE] = 0x200,
338 [BRCMNAND_OOB_READ_10_BASE] = 0,
339 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
340 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
341 [BRCMNAND_FC_BASE] = 0x400,
344 enum brcmnand_cs_reg {
345 BRCMNAND_CS_CFG_EXT = 0,
347 BRCMNAND_CS_ACC_CONTROL,
352 /* Per chip-select offsets for v7.1 */
353 static const u8 brcmnand_cs_offsets_v71[] = {
354 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
355 [BRCMNAND_CS_CFG_EXT] = 0x04,
356 [BRCMNAND_CS_CFG] = 0x08,
357 [BRCMNAND_CS_TIMING1] = 0x0c,
358 [BRCMNAND_CS_TIMING2] = 0x10,
361 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
362 static const u8 brcmnand_cs_offsets[] = {
363 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
364 [BRCMNAND_CS_CFG_EXT] = 0x04,
365 [BRCMNAND_CS_CFG] = 0x04,
366 [BRCMNAND_CS_TIMING1] = 0x08,
367 [BRCMNAND_CS_TIMING2] = 0x0c,
370 /* Per chip-select offset for <= v5.0 on CS0 only */
371 static const u8 brcmnand_cs_offsets_cs0[] = {
372 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
373 [BRCMNAND_CS_CFG_EXT] = 0x08,
374 [BRCMNAND_CS_CFG] = 0x08,
375 [BRCMNAND_CS_TIMING1] = 0x10,
376 [BRCMNAND_CS_TIMING2] = 0x14,
380 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
381 * one config register, but once the bitfields overflowed, newer controllers
382 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
385 CFG_BLK_ADR_BYTES_SHIFT = 8,
386 CFG_COL_ADR_BYTES_SHIFT = 12,
387 CFG_FUL_ADR_BYTES_SHIFT = 16,
388 CFG_BUS_WIDTH_SHIFT = 23,
389 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
390 CFG_DEVICE_SIZE_SHIFT = 24,
392 /* Only for pre-v7.1 (with no CFG_EXT register) */
393 CFG_PAGE_SIZE_SHIFT = 20,
394 CFG_BLK_SIZE_SHIFT = 28,
396 /* Only for v7.1+ (with CFG_EXT register) */
397 CFG_EXT_PAGE_SIZE_SHIFT = 0,
398 CFG_EXT_BLK_SIZE_SHIFT = 4,
401 /* BRCMNAND_INTFC_STATUS */
403 INTFC_FLASH_STATUS = GENMASK(7, 0),
405 INTFC_ERASED = BIT(27),
406 INTFC_OOB_VALID = BIT(28),
407 INTFC_CACHE_VALID = BIT(29),
408 INTFC_FLASH_READY = BIT(30),
409 INTFC_CTLR_READY = BIT(31),
412 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
414 return brcmnand_readl(ctrl->nand_base + offs);
417 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
420 brcmnand_writel(val, ctrl->nand_base + offs);
423 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
425 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
426 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
427 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
429 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
431 /* Only support v4.0+? */
432 if (ctrl->nand_version < 0x0400) {
433 dev_err(ctrl->dev, "version %#x not supported\n",
438 /* Register offsets */
439 if (ctrl->nand_version >= 0x0701)
440 ctrl->reg_offsets = brcmnand_regs_v71;
441 else if (ctrl->nand_version >= 0x0600)
442 ctrl->reg_offsets = brcmnand_regs_v60;
443 else if (ctrl->nand_version >= 0x0500)
444 ctrl->reg_offsets = brcmnand_regs_v50;
445 else if (ctrl->nand_version >= 0x0400)
446 ctrl->reg_offsets = brcmnand_regs_v40;
448 /* Chip-select stride */
449 if (ctrl->nand_version >= 0x0701)
450 ctrl->reg_spacing = 0x14;
452 ctrl->reg_spacing = 0x10;
454 /* Per chip-select registers */
455 if (ctrl->nand_version >= 0x0701) {
456 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
458 ctrl->cs_offsets = brcmnand_cs_offsets;
460 /* v5.0 and earlier has a different CS0 offset layout */
461 if (ctrl->nand_version <= 0x0500)
462 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
465 /* Page / block sizes */
466 if (ctrl->nand_version >= 0x0701) {
467 /* >= v7.1 use nice power-of-2 values! */
468 ctrl->max_page_size = 16 * 1024;
469 ctrl->max_block_size = 2 * 1024 * 1024;
471 ctrl->page_sizes = page_sizes;
472 if (ctrl->nand_version >= 0x0600)
473 ctrl->block_sizes = block_sizes_v6;
475 ctrl->block_sizes = block_sizes_v4;
477 if (ctrl->nand_version < 0x0400) {
478 ctrl->max_page_size = 4096;
479 ctrl->max_block_size = 512 * 1024;
483 /* Maximum spare area sector size (per 512B) */
484 if (ctrl->nand_version >= 0x0600)
486 else if (ctrl->nand_version >= 0x0500)
491 /* v6.0 and newer (except v6.1) have prefetch support */
492 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
493 ctrl->features |= BRCMNAND_HAS_PREFETCH;
496 * v6.x has cache mode, but it's implemented differently. Ignore it for
499 if (ctrl->nand_version >= 0x0700)
500 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
502 if (ctrl->nand_version >= 0x0500)
503 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
505 if (ctrl->nand_version >= 0x0700)
506 ctrl->features |= BRCMNAND_HAS_WP;
507 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
508 ctrl->features |= BRCMNAND_HAS_WP;
513 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
514 enum brcmnand_reg reg)
516 u16 offs = ctrl->reg_offsets[reg];
519 return nand_readreg(ctrl, offs);
524 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
525 enum brcmnand_reg reg, u32 val)
527 u16 offs = ctrl->reg_offsets[reg];
530 nand_writereg(ctrl, offs, val);
533 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
534 enum brcmnand_reg reg, u32 mask, unsigned
537 u32 tmp = brcmnand_read_reg(ctrl, reg);
541 brcmnand_write_reg(ctrl, reg, tmp);
544 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
546 return __raw_readl(ctrl->nand_fc + word * 4);
549 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
552 __raw_writel(val, ctrl->nand_fc + word * 4);
555 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
556 enum brcmnand_cs_reg reg)
558 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
559 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
562 if (cs == 0 && ctrl->cs0_offsets)
563 cs_offs = ctrl->cs0_offsets[reg];
565 cs_offs = ctrl->cs_offsets[reg];
568 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
570 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
573 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
575 if (ctrl->nand_version < 0x0600)
577 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
580 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
582 struct brcmnand_controller *ctrl = host->ctrl;
583 unsigned int shift = 0, bits;
584 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
587 if (ctrl->nand_version >= 0x0600)
589 else if (ctrl->nand_version >= 0x0500)
594 if (ctrl->nand_version >= 0x0600) {
596 reg = BRCMNAND_CORR_THRESHOLD_EXT;
597 shift = (cs % 5) * bits;
599 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
602 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
604 if (ctrl->nand_version < 0x0700)
609 /***********************************************************************
610 * NAND ACC CONTROL bitfield
612 * Some bits have remained constant throughout hardware revision, while
613 * others have shifted around.
614 ***********************************************************************/
616 /* Constant for all versions (where supported) */
618 /* See BRCMNAND_HAS_CACHE_MODE */
619 ACC_CONTROL_CACHE_MODE = BIT(22),
621 /* See BRCMNAND_HAS_PREFETCH */
622 ACC_CONTROL_PREFETCH = BIT(23),
624 ACC_CONTROL_PAGE_HIT = BIT(24),
625 ACC_CONTROL_WR_PREEMPT = BIT(25),
626 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
627 ACC_CONTROL_RD_ERASED = BIT(27),
628 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
629 ACC_CONTROL_WR_ECC = BIT(30),
630 ACC_CONTROL_RD_ECC = BIT(31),
633 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
635 if (ctrl->nand_version >= 0x0600)
636 return GENMASK(6, 0);
638 return GENMASK(5, 0);
641 #define NAND_ACC_CONTROL_ECC_SHIFT 16
643 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
645 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
647 return mask << NAND_ACC_CONTROL_ECC_SHIFT;
650 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
652 struct brcmnand_controller *ctrl = host->ctrl;
653 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
654 u32 acc_control = nand_readreg(ctrl, offs);
655 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
658 acc_control |= ecc_flags; /* enable RD/WR ECC */
659 acc_control |= host->hwcfg.ecc_level
660 << NAND_ACC_CONTROL_ECC_SHIFT;
662 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
663 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
666 nand_writereg(ctrl, offs, acc_control);
669 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
671 if (ctrl->nand_version >= 0x0600)
673 else if (ctrl->nand_version >= 0x0500)
679 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
681 struct brcmnand_controller *ctrl = host->ctrl;
682 int shift = brcmnand_sector_1k_shift(ctrl);
683 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
684 BRCMNAND_CS_ACC_CONTROL);
689 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
692 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
694 struct brcmnand_controller *ctrl = host->ctrl;
695 int shift = brcmnand_sector_1k_shift(ctrl);
696 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
697 BRCMNAND_CS_ACC_CONTROL);
703 tmp = nand_readreg(ctrl, acc_control_offs);
704 tmp &= ~(1 << shift);
705 tmp |= (!!val) << shift;
706 nand_writereg(ctrl, acc_control_offs, tmp);
709 /***********************************************************************
711 ***********************************************************************/
714 CS_SELECT_NAND_WP = BIT(29),
715 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
718 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
720 u32 val = en ? CS_SELECT_NAND_WP : 0;
722 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
725 /***********************************************************************
727 ***********************************************************************/
730 FLASH_DMA_REVISION = 0x00,
731 FLASH_DMA_FIRST_DESC = 0x04,
732 FLASH_DMA_FIRST_DESC_EXT = 0x08,
733 FLASH_DMA_CTRL = 0x0c,
734 FLASH_DMA_MODE = 0x10,
735 FLASH_DMA_STATUS = 0x14,
736 FLASH_DMA_INTERRUPT_DESC = 0x18,
737 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
738 FLASH_DMA_ERROR_STATUS = 0x20,
739 FLASH_DMA_CURRENT_DESC = 0x24,
740 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
743 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
745 return ctrl->flash_dma_base;
748 static inline bool flash_dma_buf_ok(const void *buf)
750 return buf && !is_vmalloc_addr(buf) &&
751 likely(IS_ALIGNED((uintptr_t)buf, 4));
754 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
757 brcmnand_writel(val, ctrl->flash_dma_base + offs);
760 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
762 return brcmnand_readl(ctrl->flash_dma_base + offs);
765 /* Low-level operation types: command, address, write, or read */
766 enum brcmnand_llop_type {
773 /***********************************************************************
774 * Internal support functions
775 ***********************************************************************/
777 static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
779 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
780 cfg->ecc_level == 15;
784 * Returns a nand_ecclayout strucutre for the given layout/configuration.
785 * Returns NULL on failure.
787 static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
788 struct brcmnand_host *host)
790 struct brcmnand_cfg *cfg = &host->hwcfg;
792 struct nand_ecclayout *layout;
798 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
802 sectors = cfg->page_size / (512 << cfg->sector_size_1k);
803 sas = cfg->spare_area_size << cfg->sector_size_1k;
806 if (is_hamming_ecc(cfg)) {
807 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
808 /* First sector of each page may have BBI */
810 layout->oobfree[idx2].offset = i * sas + 1;
811 /* Small-page NAND use byte 6 for BBI */
812 if (cfg->page_size == 512)
813 layout->oobfree[idx2].offset--;
814 layout->oobfree[idx2].length = 5;
816 layout->oobfree[idx2].offset = i * sas;
817 layout->oobfree[idx2].length = 6;
820 layout->eccpos[idx1++] = i * sas + 6;
821 layout->eccpos[idx1++] = i * sas + 7;
822 layout->eccpos[idx1++] = i * sas + 8;
823 layout->oobfree[idx2].offset = i * sas + 9;
824 layout->oobfree[idx2].length = 7;
826 /* Leave zero-terminated entry for OOBFREE */
827 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
828 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
835 * CONTROLLER_VERSION:
836 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
837 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
838 * But we will just be conservative.
840 req = DIV_ROUND_UP(ecc_level * 14, 8);
842 dev_err(&host->pdev->dev,
843 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
848 layout->eccbytes = req * sectors;
849 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
850 for (j = sas - req; j < sas && idx1 <
851 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
852 layout->eccpos[idx1] = i * sas + j;
854 /* First sector of each page may have BBI */
856 if (cfg->page_size == 512 && (sas - req >= 6)) {
857 /* Small-page NAND use byte 6 for BBI */
858 layout->oobfree[idx2].offset = 0;
859 layout->oobfree[idx2].length = 5;
862 layout->oobfree[idx2].offset = 6;
863 layout->oobfree[idx2].length =
867 } else if (sas > req + 1) {
868 layout->oobfree[idx2].offset = i * sas + 1;
869 layout->oobfree[idx2].length = sas - req - 1;
872 } else if (sas > req) {
873 layout->oobfree[idx2].offset = i * sas;
874 layout->oobfree[idx2].length = sas - req;
877 /* Leave zero-terminated entry for OOBFREE */
878 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
879 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
883 /* Sum available OOB */
884 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
885 layout->oobavail += layout->oobfree[i].length;
889 static struct nand_ecclayout *brcmstb_choose_ecc_layout(
890 struct brcmnand_host *host)
892 struct nand_ecclayout *layout;
893 struct brcmnand_cfg *p = &host->hwcfg;
894 unsigned int ecc_level = p->ecc_level;
896 if (p->sector_size_1k)
899 layout = brcmnand_create_layout(ecc_level, host);
901 dev_err(&host->pdev->dev,
902 "no proper ecc_layout for this NAND cfg\n");
909 static void brcmnand_wp(struct mtd_info *mtd, int wp)
911 struct nand_chip *chip = mtd_to_nand(mtd);
912 struct brcmnand_host *host = nand_get_controller_data(chip);
913 struct brcmnand_controller *ctrl = host->ctrl;
915 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
916 static int old_wp = -1;
919 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
922 brcmnand_set_wp(ctrl, wp);
926 /* Helper functions for reading and writing OOB registers */
927 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
929 u16 offset0, offset10, reg_offs;
931 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
932 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
934 if (offs >= ctrl->max_oob)
937 if (offs >= 16 && offset10)
938 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
940 reg_offs = offset0 + (offs & ~0x03);
942 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
945 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
948 u16 offset0, offset10, reg_offs;
950 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
951 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
953 if (offs >= ctrl->max_oob)
956 if (offs >= 16 && offset10)
957 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
959 reg_offs = offset0 + (offs & ~0x03);
961 nand_writereg(ctrl, reg_offs, data);
965 * read_oob_from_regs - read data from OOB registers
966 * @ctrl: NAND controller
967 * @i: sub-page sector index
968 * @oob: buffer to read to
969 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
970 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
972 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
973 int sas, int sector_1k)
975 int tbytes = sas << sector_1k;
978 /* Adjust OOB values for 1K sector size */
979 if (sector_1k && (i & 0x01))
980 tbytes = max(0, tbytes - (int)ctrl->max_oob);
981 tbytes = min_t(int, tbytes, ctrl->max_oob);
983 for (j = 0; j < tbytes; j++)
984 oob[j] = oob_reg_read(ctrl, j);
989 * write_oob_to_regs - write data to OOB registers
990 * @i: sub-page sector index
991 * @oob: buffer to write from
992 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
993 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
995 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
996 const u8 *oob, int sas, int sector_1k)
998 int tbytes = sas << sector_1k;
1001 /* Adjust OOB values for 1K sector size */
1002 if (sector_1k && (i & 0x01))
1003 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1004 tbytes = min_t(int, tbytes, ctrl->max_oob);
1006 for (j = 0; j < tbytes; j += 4)
1007 oob_reg_write(ctrl, j,
1008 (oob[j + 0] << 24) |
1009 (oob[j + 1] << 16) |
1015 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1017 struct brcmnand_controller *ctrl = data;
1019 /* Discard all NAND_CTLRDY interrupts during DMA */
1020 if (ctrl->dma_pending)
1023 complete(&ctrl->done);
1027 /* Handle SoC-specific interrupt hardware */
1028 static irqreturn_t brcmnand_irq(int irq, void *data)
1030 struct brcmnand_controller *ctrl = data;
1032 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1033 return brcmnand_ctlrdy_irq(irq, data);
1038 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1040 struct brcmnand_controller *ctrl = data;
1042 complete(&ctrl->dma_done);
1047 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1049 struct brcmnand_controller *ctrl = host->ctrl;
1052 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1053 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1054 BUG_ON(ctrl->cmd_pending != 0);
1055 ctrl->cmd_pending = cmd;
1057 intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1058 BUG_ON(!(intfc & INTFC_CTLR_READY));
1060 mb(); /* flush previous writes */
1061 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1062 cmd << brcmnand_cmd_shift(ctrl));
1065 /***********************************************************************
1066 * NAND MTD API: read/program/erase
1067 ***********************************************************************/
1069 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1072 /* intentionally left blank */
1075 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1077 struct nand_chip *chip = mtd_to_nand(mtd);
1078 struct brcmnand_host *host = nand_get_controller_data(chip);
1079 struct brcmnand_controller *ctrl = host->ctrl;
1080 unsigned long timeo = msecs_to_jiffies(100);
1082 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1083 if (ctrl->cmd_pending &&
1084 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1085 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1086 >> brcmnand_cmd_shift(ctrl);
1088 dev_err_ratelimited(ctrl->dev,
1089 "timeout waiting for command %#02x\n", cmd);
1090 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1091 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1093 ctrl->cmd_pending = 0;
1094 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1103 LLOP_RETURN_IDLE = BIT(31),
1105 LLOP_DATA_MASK = GENMASK(15, 0),
1108 static int brcmnand_low_level_op(struct brcmnand_host *host,
1109 enum brcmnand_llop_type type, u32 data,
1112 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1113 struct nand_chip *chip = &host->chip;
1114 struct brcmnand_controller *ctrl = host->ctrl;
1117 tmp = data & LLOP_DATA_MASK;
1120 tmp |= LLOP_WE | LLOP_CLE;
1124 tmp |= LLOP_WE | LLOP_ALE;
1137 tmp |= LLOP_RETURN_IDLE;
1139 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1141 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1142 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1144 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1145 return brcmnand_waitfunc(mtd, chip);
1148 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1149 int column, int page_addr)
1151 struct nand_chip *chip = mtd_to_nand(mtd);
1152 struct brcmnand_host *host = nand_get_controller_data(chip);
1153 struct brcmnand_controller *ctrl = host->ctrl;
1154 u64 addr = (u64)page_addr << chip->page_shift;
1157 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1158 command == NAND_CMD_RNDOUT)
1160 /* Avoid propagating a negative, don't-care address */
1161 else if (page_addr < 0)
1164 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1165 (unsigned long long)addr);
1167 host->last_cmd = command;
1168 host->last_byte = 0;
1169 host->last_addr = addr;
1172 case NAND_CMD_RESET:
1173 native_cmd = CMD_FLASH_RESET;
1175 case NAND_CMD_STATUS:
1176 native_cmd = CMD_STATUS_READ;
1178 case NAND_CMD_READID:
1179 native_cmd = CMD_DEVICE_ID_READ;
1181 case NAND_CMD_READOOB:
1182 native_cmd = CMD_SPARE_AREA_READ;
1184 case NAND_CMD_ERASE1:
1185 native_cmd = CMD_BLOCK_ERASE;
1186 brcmnand_wp(mtd, 0);
1188 case NAND_CMD_PARAM:
1189 native_cmd = CMD_PARAMETER_READ;
1191 case NAND_CMD_SET_FEATURES:
1192 case NAND_CMD_GET_FEATURES:
1193 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1194 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1196 case NAND_CMD_RNDOUT:
1197 native_cmd = CMD_PARAMETER_CHANGE_COL;
1198 addr &= ~((u64)(FC_BYTES - 1));
1200 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1201 * NB: hwcfg.sector_size_1k may not be initialized yet
1203 if (brcmnand_get_sector_size_1k(host)) {
1204 host->hwcfg.sector_size_1k =
1205 brcmnand_get_sector_size_1k(host);
1206 brcmnand_set_sector_size_1k(host, 0);
1214 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1215 (host->cs << 16) | ((addr >> 32) & 0xffff));
1216 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1217 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1218 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1220 brcmnand_send_cmd(host, native_cmd);
1221 brcmnand_waitfunc(mtd, chip);
1223 if (native_cmd == CMD_PARAMETER_READ ||
1224 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1225 /* Copy flash cache word-wise */
1226 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1229 brcmnand_soc_data_bus_prepare(ctrl->soc);
1232 * Must cache the FLASH_CACHE now, since changes in
1233 * SECTOR_SIZE_1K may invalidate it
1235 for (i = 0; i < FC_WORDS; i++)
1237 * Flash cache is big endian for parameter pages, at
1240 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1242 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1244 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1245 if (host->hwcfg.sector_size_1k)
1246 brcmnand_set_sector_size_1k(host,
1247 host->hwcfg.sector_size_1k);
1250 /* Re-enable protection is necessary only after erase */
1251 if (command == NAND_CMD_ERASE1)
1252 brcmnand_wp(mtd, 1);
1255 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1257 struct nand_chip *chip = mtd_to_nand(mtd);
1258 struct brcmnand_host *host = nand_get_controller_data(chip);
1259 struct brcmnand_controller *ctrl = host->ctrl;
1263 switch (host->last_cmd) {
1264 case NAND_CMD_READID:
1265 if (host->last_byte < 4)
1266 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1267 (24 - (host->last_byte << 3));
1268 else if (host->last_byte < 8)
1269 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1270 (56 - (host->last_byte << 3));
1273 case NAND_CMD_READOOB:
1274 ret = oob_reg_read(ctrl, host->last_byte);
1277 case NAND_CMD_STATUS:
1278 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1280 if (wp_on) /* hide WP status */
1281 ret |= NAND_STATUS_WP;
1284 case NAND_CMD_PARAM:
1285 case NAND_CMD_RNDOUT:
1286 addr = host->last_addr + host->last_byte;
1287 offs = addr & (FC_BYTES - 1);
1289 /* At FC_BYTES boundary, switch to next column */
1290 if (host->last_byte > 0 && offs == 0)
1291 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1293 ret = ctrl->flash_cache[offs];
1295 case NAND_CMD_GET_FEATURES:
1296 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1299 bool last = host->last_byte ==
1300 ONFI_SUBFEATURE_PARAM_LEN - 1;
1301 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1302 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1306 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1312 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1316 for (i = 0; i < len; i++, buf++)
1317 *buf = brcmnand_read_byte(mtd);
1320 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1324 struct nand_chip *chip = mtd_to_nand(mtd);
1325 struct brcmnand_host *host = nand_get_controller_data(chip);
1327 switch (host->last_cmd) {
1328 case NAND_CMD_SET_FEATURES:
1329 for (i = 0; i < len; i++)
1330 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1340 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1341 * following ahead of time:
1342 * - Is this descriptor the beginning or end of a linked list?
1343 * - What is the (DMA) address of the next descriptor in the linked list?
1345 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1346 struct brcm_nand_dma_desc *desc, u64 addr,
1347 dma_addr_t buf, u32 len, u8 dma_cmd,
1348 bool begin, bool end,
1349 dma_addr_t next_desc)
1351 memset(desc, 0, sizeof(*desc));
1352 /* Descriptors are written in native byte order (wordwise) */
1353 desc->next_desc = lower_32_bits(next_desc);
1354 desc->next_desc_ext = upper_32_bits(next_desc);
1355 desc->cmd_irq = (dma_cmd << 24) |
1356 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1357 (!!begin) | ((!!end) << 1); /* head, tail */
1358 #ifdef CONFIG_CPU_BIG_ENDIAN
1359 desc->cmd_irq |= 0x01 << 12;
1361 desc->dram_addr = lower_32_bits(buf);
1362 desc->dram_addr_ext = upper_32_bits(buf);
1363 desc->tfr_len = len;
1364 desc->total_len = len;
1365 desc->flash_addr = lower_32_bits(addr);
1366 desc->flash_addr_ext = upper_32_bits(addr);
1367 desc->cs = host->cs;
1368 desc->status_valid = 0x01;
1373 * Kick the FLASH_DMA engine, with a given DMA descriptor
1375 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1377 struct brcmnand_controller *ctrl = host->ctrl;
1378 unsigned long timeo = msecs_to_jiffies(100);
1380 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1381 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1382 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1383 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1385 /* Start FLASH_DMA engine */
1386 ctrl->dma_pending = true;
1387 mb(); /* flush previous writes */
1388 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1390 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1392 "timeout waiting for DMA; status %#x, error status %#x\n",
1393 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1394 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1396 ctrl->dma_pending = false;
1397 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1400 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1401 u32 len, u8 dma_cmd)
1403 struct brcmnand_controller *ctrl = host->ctrl;
1405 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1407 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1408 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1409 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1413 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1414 dma_cmd, true, true, 0);
1416 brcmnand_dma_run(host, ctrl->dma_pa);
1418 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1420 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1422 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1429 * Assumes proper CS is already set
1431 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1432 u64 addr, unsigned int trans, u32 *buf,
1433 u8 *oob, u64 *err_addr)
1435 struct brcmnand_host *host = nand_get_controller_data(chip);
1436 struct brcmnand_controller *ctrl = host->ctrl;
1439 /* Clear error addresses */
1440 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1441 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1442 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1443 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
1445 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1446 (host->cs << 16) | ((addr >> 32) & 0xffff));
1447 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1449 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1450 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1451 lower_32_bits(addr));
1452 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1453 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1454 brcmnand_send_cmd(host, CMD_PAGE_READ);
1455 brcmnand_waitfunc(mtd, chip);
1458 brcmnand_soc_data_bus_prepare(ctrl->soc);
1460 for (j = 0; j < FC_WORDS; j++, buf++)
1461 *buf = brcmnand_read_fc(ctrl, j);
1463 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1467 oob += read_oob_from_regs(ctrl, i, oob,
1468 mtd->oobsize / trans,
1469 host->hwcfg.sector_size_1k);
1472 *err_addr = brcmnand_read_reg(ctrl,
1473 BRCMNAND_UNCORR_ADDR) |
1474 ((u64)(brcmnand_read_reg(ctrl,
1475 BRCMNAND_UNCORR_EXT_ADDR)
1482 *err_addr = brcmnand_read_reg(ctrl,
1483 BRCMNAND_CORR_ADDR) |
1484 ((u64)(brcmnand_read_reg(ctrl,
1485 BRCMNAND_CORR_EXT_ADDR)
1495 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1496 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1498 struct brcmnand_host *host = nand_get_controller_data(chip);
1499 struct brcmnand_controller *ctrl = host->ctrl;
1503 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1505 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1507 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1508 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1511 if (mtd_is_bitflip_or_eccerr(err))
1518 memset(oob, 0x99, mtd->oobsize);
1520 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1524 if (mtd_is_eccerr(err)) {
1525 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1526 (unsigned long long)err_addr);
1527 mtd->ecc_stats.failed++;
1528 /* NAND layer expects zero on ECC errors */
1532 if (mtd_is_bitflip(err)) {
1533 unsigned int corrected = brcmnand_count_corrected(ctrl);
1535 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1536 (unsigned long long)err_addr);
1537 mtd->ecc_stats.corrected += corrected;
1538 /* Always exceed the software-imposed threshold */
1539 return max(mtd->bitflip_threshold, corrected);
1545 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1546 uint8_t *buf, int oob_required, int page)
1548 struct brcmnand_host *host = nand_get_controller_data(chip);
1549 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1551 return brcmnand_read(mtd, chip, host->last_addr,
1552 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1555 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1556 uint8_t *buf, int oob_required, int page)
1558 struct brcmnand_host *host = nand_get_controller_data(chip);
1559 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1562 brcmnand_set_ecc_enabled(host, 0);
1563 ret = brcmnand_read(mtd, chip, host->last_addr,
1564 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1565 brcmnand_set_ecc_enabled(host, 1);
1569 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1572 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1573 mtd->writesize >> FC_SHIFT,
1574 NULL, (u8 *)chip->oob_poi);
1577 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1580 struct brcmnand_host *host = nand_get_controller_data(chip);
1582 brcmnand_set_ecc_enabled(host, 0);
1583 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1584 mtd->writesize >> FC_SHIFT,
1585 NULL, (u8 *)chip->oob_poi);
1586 brcmnand_set_ecc_enabled(host, 1);
1590 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1591 u64 addr, const u32 *buf, u8 *oob)
1593 struct brcmnand_host *host = nand_get_controller_data(chip);
1594 struct brcmnand_controller *ctrl = host->ctrl;
1595 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1596 int status, ret = 0;
1598 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1600 if (unlikely((unsigned long)buf & 0x03)) {
1601 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1602 buf = (u32 *)((unsigned long)buf & ~0x03);
1605 brcmnand_wp(mtd, 0);
1607 for (i = 0; i < ctrl->max_oob; i += 4)
1608 oob_reg_write(ctrl, i, 0xffffffff);
1610 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1611 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1612 mtd->writesize, CMD_PROGRAM_PAGE))
1617 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1618 (host->cs << 16) | ((addr >> 32) & 0xffff));
1619 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1621 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1622 /* full address MUST be set before populating FC */
1623 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1624 lower_32_bits(addr));
1625 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1628 brcmnand_soc_data_bus_prepare(ctrl->soc);
1630 for (j = 0; j < FC_WORDS; j++, buf++)
1631 brcmnand_write_fc(ctrl, j, *buf);
1633 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1635 for (j = 0; j < FC_WORDS; j++)
1636 brcmnand_write_fc(ctrl, j, 0xffffffff);
1640 oob += write_oob_to_regs(ctrl, i, oob,
1641 mtd->oobsize / trans,
1642 host->hwcfg.sector_size_1k);
1645 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1646 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1647 status = brcmnand_waitfunc(mtd, chip);
1649 if (status & NAND_STATUS_FAIL) {
1650 dev_info(ctrl->dev, "program failed at %llx\n",
1651 (unsigned long long)addr);
1657 brcmnand_wp(mtd, 1);
1661 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1662 const uint8_t *buf, int oob_required, int page)
1664 struct brcmnand_host *host = nand_get_controller_data(chip);
1665 void *oob = oob_required ? chip->oob_poi : NULL;
1667 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1671 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1672 struct nand_chip *chip, const uint8_t *buf,
1673 int oob_required, int page)
1675 struct brcmnand_host *host = nand_get_controller_data(chip);
1676 void *oob = oob_required ? chip->oob_poi : NULL;
1678 brcmnand_set_ecc_enabled(host, 0);
1679 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1680 brcmnand_set_ecc_enabled(host, 1);
1684 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1687 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1688 NULL, chip->oob_poi);
1691 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1694 struct brcmnand_host *host = nand_get_controller_data(chip);
1697 brcmnand_set_ecc_enabled(host, 0);
1698 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1699 (u8 *)chip->oob_poi);
1700 brcmnand_set_ecc_enabled(host, 1);
1705 /***********************************************************************
1706 * Per-CS setup (1 NAND device)
1707 ***********************************************************************/
1709 static int brcmnand_set_cfg(struct brcmnand_host *host,
1710 struct brcmnand_cfg *cfg)
1712 struct brcmnand_controller *ctrl = host->ctrl;
1713 struct nand_chip *chip = &host->chip;
1714 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1715 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1716 BRCMNAND_CS_CFG_EXT);
1717 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1718 BRCMNAND_CS_ACC_CONTROL);
1719 u8 block_size = 0, page_size = 0, device_size = 0;
1722 if (ctrl->block_sizes) {
1725 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1726 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1731 dev_warn(ctrl->dev, "invalid block size %u\n",
1736 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1739 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1740 cfg->block_size > ctrl->max_block_size)) {
1741 dev_warn(ctrl->dev, "invalid block size %u\n",
1746 if (ctrl->page_sizes) {
1749 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1750 if (ctrl->page_sizes[i] == cfg->page_size) {
1755 dev_warn(ctrl->dev, "invalid page size %u\n",
1760 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1763 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1764 cfg->page_size > ctrl->max_page_size)) {
1765 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1769 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1770 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1771 (unsigned long long)cfg->device_size);
1774 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1776 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1777 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1778 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1779 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1780 (device_size << CFG_DEVICE_SIZE_SHIFT);
1781 if (cfg_offs == cfg_ext_offs) {
1782 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1783 (block_size << CFG_BLK_SIZE_SHIFT);
1784 nand_writereg(ctrl, cfg_offs, tmp);
1786 nand_writereg(ctrl, cfg_offs, tmp);
1787 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1788 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
1789 nand_writereg(ctrl, cfg_ext_offs, tmp);
1792 tmp = nand_readreg(ctrl, acc_control_offs);
1793 tmp &= ~brcmnand_ecc_level_mask(ctrl);
1794 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1795 tmp &= ~brcmnand_spare_area_mask(ctrl);
1796 tmp |= cfg->spare_area_size;
1797 nand_writereg(ctrl, acc_control_offs, tmp);
1799 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1801 /* threshold = ceil(BCH-level * 0.75) */
1802 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1807 static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1810 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1811 (unsigned long long)cfg->device_size >> 20,
1812 cfg->block_size >> 10,
1813 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1814 cfg->page_size >= 1024 ? "KiB" : "B",
1815 cfg->spare_area_size, cfg->device_width);
1817 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1818 if (is_hamming_ecc(cfg))
1819 sprintf(buf, ", Hamming ECC");
1820 else if (cfg->sector_size_1k)
1821 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1823 sprintf(buf, ", BCH-%u", cfg->ecc_level);
1827 * Minimum number of bytes to address a page. Calculated as:
1828 * roundup(log2(size / page-size) / 8)
1830 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1831 * OK because many other things will break if 'size' is irregular...
1833 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1835 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1838 static int brcmnand_setup_dev(struct brcmnand_host *host)
1840 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1841 struct nand_chip *chip = &host->chip;
1842 struct brcmnand_controller *ctrl = host->ctrl;
1843 struct brcmnand_cfg *cfg = &host->hwcfg;
1845 u32 offs, tmp, oob_sector;
1848 memset(cfg, 0, sizeof(*cfg));
1850 ret = of_property_read_u32(nand_get_flash_node(chip),
1851 "brcm,nand-oob-sector-size",
1854 /* Use detected size */
1855 cfg->spare_area_size = mtd->oobsize /
1856 (mtd->writesize >> FC_SHIFT);
1858 cfg->spare_area_size = oob_sector;
1860 if (cfg->spare_area_size > ctrl->max_oob)
1861 cfg->spare_area_size = ctrl->max_oob;
1863 * Set oobsize to be consistent with controller's spare_area_size, as
1864 * the rest is inaccessible.
1866 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1868 cfg->device_size = mtd->size;
1869 cfg->block_size = mtd->erasesize;
1870 cfg->page_size = mtd->writesize;
1871 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1872 cfg->col_adr_bytes = 2;
1873 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1875 switch (chip->ecc.size) {
1877 if (chip->ecc.strength == 1) /* Hamming */
1878 cfg->ecc_level = 15;
1880 cfg->ecc_level = chip->ecc.strength;
1881 cfg->sector_size_1k = 0;
1884 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1885 dev_err(ctrl->dev, "1KB sectors not supported\n");
1888 if (chip->ecc.strength & 0x1) {
1890 "odd ECC not supported with 1KB sectors\n");
1894 cfg->ecc_level = chip->ecc.strength >> 1;
1895 cfg->sector_size_1k = 1;
1898 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1903 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1904 if (mtd->writesize > 512)
1905 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1907 cfg->ful_adr_bytes += 1;
1909 ret = brcmnand_set_cfg(host, cfg);
1913 brcmnand_set_ecc_enabled(host, 1);
1915 brcmnand_print_cfg(msg, cfg);
1916 dev_info(ctrl->dev, "detected %s\n", msg);
1918 /* Configure ACC_CONTROL */
1919 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1920 tmp = nand_readreg(ctrl, offs);
1921 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1922 tmp &= ~ACC_CONTROL_RD_ERASED;
1923 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1924 if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
1926 * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
1929 if (has_flash_dma(ctrl))
1930 tmp &= ~ACC_CONTROL_PREFETCH;
1932 tmp |= ACC_CONTROL_PREFETCH;
1934 nand_writereg(ctrl, offs, tmp);
1939 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
1941 struct brcmnand_controller *ctrl = host->ctrl;
1942 struct platform_device *pdev = host->pdev;
1943 struct mtd_info *mtd;
1944 struct nand_chip *chip;
1948 ret = of_property_read_u32(dn, "reg", &host->cs);
1950 dev_err(&pdev->dev, "can't get chip-select\n");
1954 mtd = nand_to_mtd(&host->chip);
1957 nand_set_flash_node(chip, dn);
1958 nand_set_controller_data(chip, host);
1959 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1961 mtd->owner = THIS_MODULE;
1962 mtd->dev.parent = &pdev->dev;
1964 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1965 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1967 chip->cmd_ctrl = brcmnand_cmd_ctrl;
1968 chip->cmdfunc = brcmnand_cmdfunc;
1969 chip->waitfunc = brcmnand_waitfunc;
1970 chip->read_byte = brcmnand_read_byte;
1971 chip->read_buf = brcmnand_read_buf;
1972 chip->write_buf = brcmnand_write_buf;
1974 chip->ecc.mode = NAND_ECC_HW;
1975 chip->ecc.read_page = brcmnand_read_page;
1976 chip->ecc.write_page = brcmnand_write_page;
1977 chip->ecc.read_page_raw = brcmnand_read_page_raw;
1978 chip->ecc.write_page_raw = brcmnand_write_page_raw;
1979 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1980 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1981 chip->ecc.read_oob = brcmnand_read_oob;
1982 chip->ecc.write_oob = brcmnand_write_oob;
1984 chip->controller = &ctrl->controller;
1987 * The bootloader might have configured 16bit mode but
1988 * NAND READID command only works in 8bit mode. We force
1989 * 8bit mode here to ensure that NAND READID commands works.
1991 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1992 nand_writereg(ctrl, cfg_offs,
1993 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
1995 if (nand_scan_ident(mtd, 1, NULL))
1998 chip->options |= NAND_NO_SUBPAGE_WRITE;
2000 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2001 * to/from, and have nand_base pass us a bounce buffer instead, as
2004 chip->options |= NAND_USE_BOUNCE_BUFFER;
2006 if (of_get_nand_on_flash_bbt(dn))
2007 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
2009 if (brcmnand_setup_dev(host))
2012 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2013 /* only use our internal HW threshold */
2014 mtd->bitflip_threshold = 1;
2016 chip->ecc.layout = brcmstb_choose_ecc_layout(host);
2017 if (!chip->ecc.layout)
2020 if (nand_scan_tail(mtd))
2023 return mtd_device_register(mtd, NULL, 0);
2026 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2029 struct brcmnand_controller *ctrl = host->ctrl;
2030 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2031 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2032 BRCMNAND_CS_CFG_EXT);
2033 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2034 BRCMNAND_CS_ACC_CONTROL);
2035 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2036 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2039 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2040 if (cfg_offs != cfg_ext_offs)
2041 nand_writereg(ctrl, cfg_ext_offs,
2042 host->hwcfg.config_ext);
2043 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2044 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2045 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2047 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2048 if (cfg_offs != cfg_ext_offs)
2049 host->hwcfg.config_ext =
2050 nand_readreg(ctrl, cfg_ext_offs);
2051 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2052 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2053 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2057 static int brcmnand_suspend(struct device *dev)
2059 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2060 struct brcmnand_host *host;
2062 list_for_each_entry(host, &ctrl->host_list, node)
2063 brcmnand_save_restore_cs_config(host, 0);
2065 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2066 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2067 ctrl->corr_stat_threshold =
2068 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2070 if (has_flash_dma(ctrl))
2071 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2076 static int brcmnand_resume(struct device *dev)
2078 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2079 struct brcmnand_host *host;
2081 if (has_flash_dma(ctrl)) {
2082 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2083 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2086 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2087 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2088 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2089 ctrl->corr_stat_threshold);
2091 /* Clear/re-enable interrupt */
2092 ctrl->soc->ctlrdy_ack(ctrl->soc);
2093 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2096 list_for_each_entry(host, &ctrl->host_list, node) {
2097 struct nand_chip *chip = &host->chip;
2098 struct mtd_info *mtd = nand_to_mtd(chip);
2100 brcmnand_save_restore_cs_config(host, 1);
2102 /* Reset the chip, required by some chips after power-up */
2103 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2109 const struct dev_pm_ops brcmnand_pm_ops = {
2110 .suspend = brcmnand_suspend,
2111 .resume = brcmnand_resume,
2113 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2115 static const struct of_device_id brcmnand_of_match[] = {
2116 { .compatible = "brcm,brcmnand-v4.0" },
2117 { .compatible = "brcm,brcmnand-v5.0" },
2118 { .compatible = "brcm,brcmnand-v6.0" },
2119 { .compatible = "brcm,brcmnand-v6.1" },
2120 { .compatible = "brcm,brcmnand-v7.0" },
2121 { .compatible = "brcm,brcmnand-v7.1" },
2124 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2126 /***********************************************************************
2127 * Platform driver setup (per controller)
2128 ***********************************************************************/
2130 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2132 struct device *dev = &pdev->dev;
2133 struct device_node *dn = dev->of_node, *child;
2134 struct brcmnand_controller *ctrl;
2135 struct resource *res;
2138 /* We only support device-tree instantiation */
2142 if (!of_match_node(brcmnand_of_match, dn))
2145 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2149 dev_set_drvdata(dev, ctrl);
2152 init_completion(&ctrl->done);
2153 init_completion(&ctrl->dma_done);
2154 spin_lock_init(&ctrl->controller.lock);
2155 init_waitqueue_head(&ctrl->controller.wq);
2156 INIT_LIST_HEAD(&ctrl->host_list);
2158 /* NAND register range */
2159 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2160 ctrl->nand_base = devm_ioremap_resource(dev, res);
2161 if (IS_ERR(ctrl->nand_base))
2162 return PTR_ERR(ctrl->nand_base);
2164 /* Enable clock before using NAND registers */
2165 ctrl->clk = devm_clk_get(dev, "nand");
2166 if (!IS_ERR(ctrl->clk)) {
2167 ret = clk_prepare_enable(ctrl->clk);
2171 ret = PTR_ERR(ctrl->clk);
2172 if (ret == -EPROBE_DEFER)
2178 /* Initialize NAND revision */
2179 ret = brcmnand_revision_init(ctrl);
2184 * Most chips have this cache at a fixed offset within 'nand' block.
2185 * Some must specify this region separately.
2187 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2189 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2190 if (IS_ERR(ctrl->nand_fc)) {
2191 ret = PTR_ERR(ctrl->nand_fc);
2195 ctrl->nand_fc = ctrl->nand_base +
2196 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2200 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2202 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2203 if (IS_ERR(ctrl->flash_dma_base)) {
2204 ret = PTR_ERR(ctrl->flash_dma_base);
2208 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2209 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2211 /* Allocate descriptor(s) */
2212 ctrl->dma_desc = dmam_alloc_coherent(dev,
2213 sizeof(*ctrl->dma_desc),
2214 &ctrl->dma_pa, GFP_KERNEL);
2215 if (!ctrl->dma_desc) {
2220 ctrl->dma_irq = platform_get_irq(pdev, 1);
2221 if ((int)ctrl->dma_irq < 0) {
2222 dev_err(dev, "missing FLASH_DMA IRQ\n");
2227 ret = devm_request_irq(dev, ctrl->dma_irq,
2228 brcmnand_dma_irq, 0, DRV_NAME,
2231 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2232 ctrl->dma_irq, ret);
2236 dev_info(dev, "enabling FLASH_DMA\n");
2239 /* Disable automatic device ID config, direct addressing */
2240 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2241 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2242 /* Disable XOR addressing */
2243 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2245 if (ctrl->features & BRCMNAND_HAS_WP) {
2246 /* Permanently disable write protection */
2248 brcmnand_set_wp(ctrl, false);
2254 ctrl->irq = platform_get_irq(pdev, 0);
2255 if ((int)ctrl->irq < 0) {
2256 dev_err(dev, "no IRQ defined\n");
2262 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2268 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2271 /* Enable interrupt */
2272 ctrl->soc->ctlrdy_ack(ctrl->soc);
2273 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2275 /* Use standard interrupt infrastructure */
2276 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2280 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2285 for_each_available_child_of_node(dn, child) {
2286 if (of_device_is_compatible(child, "brcm,nandcs")) {
2287 struct brcmnand_host *host;
2289 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2298 ret = brcmnand_init_cs(host, child);
2300 devm_kfree(dev, host);
2301 continue; /* Try all chip-selects */
2304 list_add_tail(&host->node, &ctrl->host_list);
2308 /* No chip-selects could initialize properly */
2309 if (list_empty(&ctrl->host_list)) {
2317 clk_disable_unprepare(ctrl->clk);
2321 EXPORT_SYMBOL_GPL(brcmnand_probe);
2323 int brcmnand_remove(struct platform_device *pdev)
2325 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2326 struct brcmnand_host *host;
2328 list_for_each_entry(host, &ctrl->host_list, node)
2329 nand_release(nand_to_mtd(&host->chip));
2331 clk_disable_unprepare(ctrl->clk);
2333 dev_set_drvdata(&pdev->dev, NULL);
2337 EXPORT_SYMBOL_GPL(brcmnand_remove);
2339 MODULE_LICENSE("GPL v2");
2340 MODULE_AUTHOR("Kevin Cernekee");
2341 MODULE_AUTHOR("Brian Norris");
2342 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2343 MODULE_ALIAS("platform:brcmnand");