2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
4 * Copyright © 2006 Texas Instruments.
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/err.h>
31 #include <linux/clk.h>
33 #include <linux/mtd/nand.h>
34 #include <linux/mtd/partitions.h>
35 #include <linux/slab.h>
37 #include <mach/nand.h>
38 #include <mach/aemif.h>
40 #include <asm/mach-types.h>
44 * This is a device driver for the NAND flash controller found on the
45 * various DaVinci family chips. It handles up to four SoC chipselects,
46 * and some flavors of secondary chipselect (e.g. based on A12) as used
47 * with multichip packages.
49 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
50 * available on chips like the DM355 and OMAP-L137 and needed with the
51 * more error-prone MLC NAND chips.
53 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
54 * outputs in a "wire-AND" configuration, with no per-chip signals.
56 struct davinci_nand_info {
58 struct nand_chip chip;
59 struct nand_ecclayout ecclayout;
73 uint32_t mask_chipsel;
77 uint32_t core_chipsel;
79 struct davinci_aemif_timing *timing;
82 static DEFINE_SPINLOCK(davinci_nand_lock);
83 static bool ecc4_busy;
85 #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
88 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
91 return __raw_readl(info->base + offset);
94 static inline void davinci_nand_writel(struct davinci_nand_info *info,
95 int offset, unsigned long value)
97 __raw_writel(value, info->base + offset);
100 /*----------------------------------------------------------------------*/
103 * Access to hardware control lines: ALE, CLE, secondary chipselect.
106 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
109 struct davinci_nand_info *info = to_davinci_nand(mtd);
110 uint32_t addr = info->current_cs;
111 struct nand_chip *nand = mtd->priv;
113 /* Did the control lines change? */
114 if (ctrl & NAND_CTRL_CHANGE) {
115 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
116 addr |= info->mask_cle;
117 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
118 addr |= info->mask_ale;
120 nand->IO_ADDR_W = (void __iomem __force *)addr;
123 if (cmd != NAND_CMD_NONE)
124 iowrite8(cmd, nand->IO_ADDR_W);
127 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
129 struct davinci_nand_info *info = to_davinci_nand(mtd);
130 uint32_t addr = info->ioaddr;
132 /* maybe kick in a second chipselect */
134 addr |= info->mask_chipsel;
135 info->current_cs = addr;
137 info->chip.IO_ADDR_W = (void __iomem __force *)addr;
138 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
141 /*----------------------------------------------------------------------*/
144 * 1-bit hardware ECC ... context maintained for each core chipselect
147 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
149 struct davinci_nand_info *info = to_davinci_nand(mtd);
151 return davinci_nand_readl(info, NANDF1ECC_OFFSET
152 + 4 * info->core_chipsel);
155 static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
157 struct davinci_nand_info *info;
161 info = to_davinci_nand(mtd);
163 /* Reset ECC hardware */
164 nand_davinci_readecc_1bit(mtd);
166 spin_lock_irqsave(&davinci_nand_lock, flags);
168 /* Restart ECC hardware */
169 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
170 nandcfr |= BIT(8 + info->core_chipsel);
171 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
173 spin_unlock_irqrestore(&davinci_nand_lock, flags);
177 * Read hardware ECC value and pack into three bytes
179 static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
180 const u_char *dat, u_char *ecc_code)
182 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
183 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
185 /* invert so that erased block ecc is correct */
187 ecc_code[0] = (u_char)(ecc24);
188 ecc_code[1] = (u_char)(ecc24 >> 8);
189 ecc_code[2] = (u_char)(ecc24 >> 16);
194 static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
195 u_char *read_ecc, u_char *calc_ecc)
197 struct nand_chip *chip = mtd->priv;
198 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
200 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
202 uint32_t diff = eccCalc ^ eccNand;
205 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
206 /* Correctable error */
207 if ((diff >> (12 + 3)) < chip->ecc.size) {
208 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
213 } else if (!(diff & (diff - 1))) {
214 /* Single bit ECC error in the ECC itself,
218 /* Uncorrectable error */
226 /*----------------------------------------------------------------------*/
229 * 4-bit hardware ECC ... context maintained over entire AEMIF
231 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
232 * since that forces use of a problematic "infix OOB" layout.
233 * Among other things, it trashes manufacturer bad block markers.
234 * Also, and specific to this hardware, it ECC-protects the "prepad"
235 * in the OOB ... while having ECC protection for parts of OOB would
236 * seem useful, the current MTD stack sometimes wants to update the
237 * OOB without recomputing ECC.
240 static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
242 struct davinci_nand_info *info = to_davinci_nand(mtd);
246 spin_lock_irqsave(&davinci_nand_lock, flags);
248 /* Start 4-bit ECC calculation for read/write */
249 val = davinci_nand_readl(info, NANDFCR_OFFSET);
251 val |= (info->core_chipsel << 4) | BIT(12);
252 davinci_nand_writel(info, NANDFCR_OFFSET, val);
254 info->is_readmode = (mode == NAND_ECC_READ);
256 spin_unlock_irqrestore(&davinci_nand_lock, flags);
259 /* Read raw ECC code after writing to NAND. */
261 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
263 const u32 mask = 0x03ff03ff;
265 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
266 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
267 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
268 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
271 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
272 static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
273 const u_char *dat, u_char *ecc_code)
275 struct davinci_nand_info *info = to_davinci_nand(mtd);
279 /* After a read, terminate ECC calculation by a dummy read
280 * of some 4-bit ECC register. ECC covers everything that
281 * was read; correct() just uses the hardware state, so
282 * ecc_code is not needed.
284 if (info->is_readmode) {
285 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
289 /* Pack eight raw 10-bit ecc values into ten bytes, making
290 * two passes which each convert four values (in upper and
291 * lower halves of two 32-bit words) into five bytes. The
292 * ROM boot loader uses this same packing scheme.
294 nand_davinci_readecc_4bit(info, raw_ecc);
295 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
296 *ecc_code++ = p[0] & 0xff;
297 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
298 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
299 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
300 *ecc_code++ = (p[1] >> 18) & 0xff;
306 /* Correct up to 4 bits in data we just read, using state left in the
307 * hardware plus the ecc_code computed when it was first written.
309 static int nand_davinci_correct_4bit(struct mtd_info *mtd,
310 u_char *data, u_char *ecc_code, u_char *null)
313 struct davinci_nand_info *info = to_davinci_nand(mtd);
314 unsigned short ecc10[8];
315 unsigned short *ecc16;
318 unsigned num_errors, corrected;
319 unsigned long timeo = jiffies + msecs_to_jiffies(100);
321 /* All bytes 0xff? It's an erased page; ignore its ECC. */
322 for (i = 0; i < 10; i++) {
323 if (ecc_code[i] != 0xff)
329 /* Unpack ten bytes into eight 10 bit values. We know we're
330 * little-endian, and use type punning for less shifting/masking.
332 if (WARN_ON(0x01 & (unsigned) ecc_code))
334 ecc16 = (unsigned short *)ecc_code;
336 ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
337 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
338 ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
339 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
340 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
341 ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
342 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
343 ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
345 /* Tell ECC controller about the expected ECC codes. */
346 for (i = 7; i >= 0; i--)
347 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
349 /* Allow time for syndrome calculation ... then read it.
350 * A syndrome of all zeroes 0 means no detected errors.
352 davinci_nand_readl(info, NANDFSR_OFFSET);
353 nand_davinci_readecc_4bit(info, syndrome);
354 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
358 * Clear any previous address calculation by doing a dummy read of an
359 * error address register.
361 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
363 /* Start address calculation, and wait for it to complete.
364 * We _could_ start reading more data while this is working,
365 * to speed up the overall page read.
367 davinci_nand_writel(info, NANDFCR_OFFSET,
368 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
371 * ECC_STATE field reads 0x3 (Error correction complete) immediately
372 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
373 * begin trying to poll for the state, you may fall right out of your
374 * loop without any of the correction calculations having taken place.
375 * The recommendation from the hardware team is to wait till ECC_STATE
376 * reads less than 4, which means ECC HW has entered correction state.
379 ecc_state = (davinci_nand_readl(info,
380 NANDFSR_OFFSET) >> 8) & 0x0f;
382 } while ((ecc_state < 4) && time_before(jiffies, timeo));
385 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
387 switch ((fsr >> 8) & 0x0f) {
388 case 0: /* no error, should not happen */
389 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
391 case 1: /* five or more errors detected */
392 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
394 case 2: /* error addresses computed */
396 num_errors = 1 + ((fsr >> 16) & 0x03);
398 default: /* still working on it */
405 /* correct each error */
406 for (i = 0, corrected = 0; i < num_errors; i++) {
407 int error_address, error_value;
410 error_address = davinci_nand_readl(info,
411 NAND_ERR_ADD2_OFFSET);
412 error_value = davinci_nand_readl(info,
413 NAND_ERR_ERRVAL2_OFFSET);
415 error_address = davinci_nand_readl(info,
416 NAND_ERR_ADD1_OFFSET);
417 error_value = davinci_nand_readl(info,
418 NAND_ERR_ERRVAL1_OFFSET);
422 error_address >>= 16;
425 error_address &= 0x3ff;
426 error_address = (512 + 7) - error_address;
428 if (error_address < 512) {
429 data[error_address] ^= error_value;
437 /*----------------------------------------------------------------------*/
440 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
441 * how these chips are normally wired. This translates to both 8 and 16
442 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
444 * For now we assume that configuration, or any other one which ignores
445 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
446 * and have that transparently morphed into multiple NAND operations.
448 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
450 struct nand_chip *chip = mtd->priv;
452 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
453 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
454 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
455 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
457 ioread8_rep(chip->IO_ADDR_R, buf, len);
460 static void nand_davinci_write_buf(struct mtd_info *mtd,
461 const uint8_t *buf, int len)
463 struct nand_chip *chip = mtd->priv;
465 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
466 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
467 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
468 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
470 iowrite8_rep(chip->IO_ADDR_R, buf, len);
474 * Check hardware register for wait status. Returns 1 if device is ready,
475 * 0 if it is still busy.
477 static int nand_davinci_dev_ready(struct mtd_info *mtd)
479 struct davinci_nand_info *info = to_davinci_nand(mtd);
481 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
484 /*----------------------------------------------------------------------*/
486 /* An ECC layout for using 4-bit ECC with small-page flash, storing
487 * ten ECC bytes plus the manufacturer's bad block marker byte, and
488 * and not overlapping the default BBT markers.
490 static struct nand_ecclayout hwecc4_small __initconst = {
492 .eccpos = { 0, 1, 2, 3, 4,
493 /* offset 5 holds the badblock marker */
497 {.offset = 8, .length = 5, },
502 /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
503 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
504 * and not overlapping the default BBT markers.
506 static struct nand_ecclayout hwecc4_2048 __initconst = {
509 /* at the end of spare sector */
510 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
511 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
512 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
513 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
516 /* 2 bytes at offset 0 hold manufacturer badblock markers */
517 {.offset = 2, .length = 22, },
518 /* 5 bytes at offset 8 hold BBT markers */
519 /* 8 bytes at offset 16 hold JFFS2 clean markers */
523 static int __init nand_davinci_probe(struct platform_device *pdev)
525 struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
526 struct davinci_nand_info *info;
527 struct resource *res1;
528 struct resource *res2;
533 nand_ecc_modes_t ecc_mode;
535 /* insist on board-specific configuration */
539 /* which external chipselect will we be managing? */
540 if (pdev->id < 0 || pdev->id > 3)
543 info = kzalloc(sizeof(*info), GFP_KERNEL);
545 dev_err(&pdev->dev, "unable to allocate memory\n");
550 platform_set_drvdata(pdev, info);
552 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
553 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
554 if (!res1 || !res2) {
555 dev_err(&pdev->dev, "resource missing\n");
560 vaddr = ioremap(res1->start, resource_size(res1));
561 base = ioremap(res2->start, resource_size(res2));
562 if (!vaddr || !base) {
563 dev_err(&pdev->dev, "ioremap failed\n");
568 info->dev = &pdev->dev;
572 info->mtd.priv = &info->chip;
573 info->mtd.name = dev_name(&pdev->dev);
574 info->mtd.owner = THIS_MODULE;
576 info->mtd.dev.parent = &pdev->dev;
578 info->chip.IO_ADDR_R = vaddr;
579 info->chip.IO_ADDR_W = vaddr;
580 info->chip.chip_delay = 0;
581 info->chip.select_chip = nand_davinci_select_chip;
583 /* options such as NAND_USE_FLASH_BBT or 16-bit widths */
584 info->chip.options = pdata->options;
585 info->chip.bbt_td = pdata->bbt_td;
586 info->chip.bbt_md = pdata->bbt_md;
587 info->timing = pdata->timing;
589 info->ioaddr = (uint32_t __force) vaddr;
591 info->current_cs = info->ioaddr;
592 info->core_chipsel = pdev->id;
593 info->mask_chipsel = pdata->mask_chipsel;
595 /* use nandboot-capable ALE/CLE masks by default */
596 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
597 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
599 /* Set address of hardware control function */
600 info->chip.cmd_ctrl = nand_davinci_hwcontrol;
601 info->chip.dev_ready = nand_davinci_dev_ready;
603 /* Speed up buffer I/O */
604 info->chip.read_buf = nand_davinci_read_buf;
605 info->chip.write_buf = nand_davinci_write_buf;
607 /* Use board-specific ECC config */
608 ecc_mode = pdata->ecc_mode;
617 if (pdata->ecc_bits == 4) {
618 /* No sanity checks: CPUs must support this,
619 * and the chips may not use NAND_BUSWIDTH_16.
622 /* No sharing 4-bit hardware between chipselects yet */
623 spin_lock_irq(&davinci_nand_lock);
628 spin_unlock_irq(&davinci_nand_lock);
633 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
634 info->chip.ecc.correct = nand_davinci_correct_4bit;
635 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
636 info->chip.ecc.bytes = 10;
638 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
639 info->chip.ecc.correct = nand_davinci_correct_1bit;
640 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
641 info->chip.ecc.bytes = 3;
643 info->chip.ecc.size = 512;
649 info->chip.ecc.mode = ecc_mode;
651 info->clk = clk_get(&pdev->dev, "aemif");
652 if (IS_ERR(info->clk)) {
653 ret = PTR_ERR(info->clk);
654 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
658 ret = clk_enable(info->clk);
660 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
666 * Setup Async configuration register in case we did not boot from
667 * NAND and so bootloader did not bother to set it up.
669 val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
671 /* Extended Wait is not valid and Select Strobe mode is not used */
672 val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
673 if (info->chip.options & NAND_BUSWIDTH_16)
676 davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
678 ret = davinci_aemif_setup_timing(info->timing, info->base,
681 dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
685 spin_lock_irq(&davinci_nand_lock);
687 /* put CSxNAND into NAND mode */
688 val = davinci_nand_readl(info, NANDFCR_OFFSET);
689 val |= BIT(info->core_chipsel);
690 davinci_nand_writel(info, NANDFCR_OFFSET, val);
692 spin_unlock_irq(&davinci_nand_lock);
694 /* Scan to find existence of the device(s) */
695 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
697 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
701 /* Update ECC layout if needed ... for 1-bit HW ECC, the default
702 * is OK, but it allocates 6 bytes when only 3 are needed (for
703 * each 512 bytes). For the 4-bit HW ECC, that default is not
704 * usable: 10 bytes are needed, not 6.
706 if (pdata->ecc_bits == 4) {
707 int chunks = info->mtd.writesize / 512;
709 if (!chunks || info->mtd.oobsize < 16) {
710 dev_dbg(&pdev->dev, "too small\n");
715 /* For small page chips, preserve the manufacturer's
716 * badblock marking data ... and make sure a flash BBT
717 * table marker fits in the free bytes.
720 info->ecclayout = hwecc4_small;
721 info->ecclayout.oobfree[1].length =
722 info->mtd.oobsize - 16;
726 info->ecclayout = hwecc4_2048;
727 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
731 /* 4KiB page chips are not yet supported. The eccpos from
732 * nand_ecclayout cannot hold 80 bytes and change to eccpos[]
733 * breaks userspace ioctl interface with mtd-utils. Once we
734 * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
735 * for the 4KiB page chips.
737 dev_warn(&pdev->dev, "no 4-bit ECC support yet "
738 "for 4KiB-page NAND\n");
743 info->chip.ecc.layout = &info->ecclayout;
746 ret = nand_scan_tail(&info->mtd);
750 if (mtd_has_partitions()) {
751 struct mtd_partition *mtd_parts = NULL;
752 int mtd_parts_nb = 0;
754 if (mtd_has_cmdlinepart()) {
755 static const char *probes[] __initconst =
756 { "cmdlinepart", NULL };
758 mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
762 if (mtd_parts_nb <= 0) {
763 mtd_parts = pdata->parts;
764 mtd_parts_nb = pdata->nr_parts;
767 /* Register any partitions */
768 if (mtd_parts_nb > 0) {
769 ret = add_mtd_partitions(&info->mtd,
770 mtd_parts, mtd_parts_nb);
772 info->partitioned = true;
775 } else if (pdata->nr_parts) {
776 dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
777 pdata->nr_parts, info->mtd.name);
780 /* If there's no partition info, just package the whole chip
781 * as a single MTD device.
783 if (!info->partitioned)
784 ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;
789 val = davinci_nand_readl(info, NRCSR_OFFSET);
790 dev_info(&pdev->dev, "controller rev. %d.%d\n",
791 (val >> 8) & 0xff, val & 0xff);
797 clk_disable(info->clk);
802 spin_lock_irq(&davinci_nand_lock);
803 if (ecc_mode == NAND_ECC_HW_SYNDROME)
805 spin_unlock_irq(&davinci_nand_lock);
820 static int __exit nand_davinci_remove(struct platform_device *pdev)
822 struct davinci_nand_info *info = platform_get_drvdata(pdev);
825 if (mtd_has_partitions() && info->partitioned)
826 status = del_mtd_partitions(&info->mtd);
828 status = del_mtd_device(&info->mtd);
830 spin_lock_irq(&davinci_nand_lock);
831 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
833 spin_unlock_irq(&davinci_nand_lock);
836 iounmap(info->vaddr);
838 nand_release(&info->mtd);
840 clk_disable(info->clk);
848 static struct platform_driver nand_davinci_driver = {
849 .remove = __exit_p(nand_davinci_remove),
851 .name = "davinci_nand",
854 MODULE_ALIAS("platform:davinci_nand");
856 static int __init nand_davinci_init(void)
858 return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
860 module_init(nand_davinci_init);
862 static void __exit nand_davinci_exit(void)
864 platform_driver_unregister(&nand_davinci_driver);
866 module_exit(nand_davinci_exit);
868 MODULE_LICENSE("GPL");
869 MODULE_AUTHOR("Texas Instruments");
870 MODULE_DESCRIPTION("Davinci NAND flash driver");