2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
4 * Copyright © 2006 Texas Instruments.
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/err.h>
31 #include <linux/clk.h>
33 #include <linux/mtd/nand.h>
34 #include <linux/mtd/partitions.h>
35 #include <linux/slab.h>
37 #include <mach/nand.h>
39 #include <asm/mach-types.h>
43 * This is a device driver for the NAND flash controller found on the
44 * various DaVinci family chips. It handles up to four SoC chipselects,
45 * and some flavors of secondary chipselect (e.g. based on A12) as used
46 * with multichip packages.
48 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
49 * available on chips like the DM355 and OMAP-L137 and needed with the
50 * more error-prone MLC NAND chips.
52 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
53 * outputs in a "wire-AND" configuration, with no per-chip signals.
55 struct davinci_nand_info {
57 struct nand_chip chip;
58 struct nand_ecclayout ecclayout;
72 uint32_t mask_chipsel;
76 uint32_t core_chipsel;
79 static DEFINE_SPINLOCK(davinci_nand_lock);
80 static bool ecc4_busy;
82 #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
85 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
88 return __raw_readl(info->base + offset);
91 static inline void davinci_nand_writel(struct davinci_nand_info *info,
92 int offset, unsigned long value)
94 __raw_writel(value, info->base + offset);
97 /*----------------------------------------------------------------------*/
100 * Access to hardware control lines: ALE, CLE, secondary chipselect.
103 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
106 struct davinci_nand_info *info = to_davinci_nand(mtd);
107 uint32_t addr = info->current_cs;
108 struct nand_chip *nand = mtd->priv;
110 /* Did the control lines change? */
111 if (ctrl & NAND_CTRL_CHANGE) {
112 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
113 addr |= info->mask_cle;
114 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
115 addr |= info->mask_ale;
117 nand->IO_ADDR_W = (void __iomem __force *)addr;
120 if (cmd != NAND_CMD_NONE)
121 iowrite8(cmd, nand->IO_ADDR_W);
124 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
126 struct davinci_nand_info *info = to_davinci_nand(mtd);
127 uint32_t addr = info->ioaddr;
129 /* maybe kick in a second chipselect */
131 addr |= info->mask_chipsel;
132 info->current_cs = addr;
134 info->chip.IO_ADDR_W = (void __iomem __force *)addr;
135 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
138 /*----------------------------------------------------------------------*/
141 * 1-bit hardware ECC ... context maintained for each core chipselect
144 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
146 struct davinci_nand_info *info = to_davinci_nand(mtd);
148 return davinci_nand_readl(info, NANDF1ECC_OFFSET
149 + 4 * info->core_chipsel);
152 static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
154 struct davinci_nand_info *info;
158 info = to_davinci_nand(mtd);
160 /* Reset ECC hardware */
161 nand_davinci_readecc_1bit(mtd);
163 spin_lock_irqsave(&davinci_nand_lock, flags);
165 /* Restart ECC hardware */
166 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
167 nandcfr |= BIT(8 + info->core_chipsel);
168 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
170 spin_unlock_irqrestore(&davinci_nand_lock, flags);
174 * Read hardware ECC value and pack into three bytes
176 static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
177 const u_char *dat, u_char *ecc_code)
179 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
180 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
182 /* invert so that erased block ecc is correct */
184 ecc_code[0] = (u_char)(ecc24);
185 ecc_code[1] = (u_char)(ecc24 >> 8);
186 ecc_code[2] = (u_char)(ecc24 >> 16);
191 static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
192 u_char *read_ecc, u_char *calc_ecc)
194 struct nand_chip *chip = mtd->priv;
195 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
197 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
199 uint32_t diff = eccCalc ^ eccNand;
202 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
203 /* Correctable error */
204 if ((diff >> (12 + 3)) < chip->ecc.size) {
205 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
210 } else if (!(diff & (diff - 1))) {
211 /* Single bit ECC error in the ECC itself,
215 /* Uncorrectable error */
223 /*----------------------------------------------------------------------*/
226 * 4-bit hardware ECC ... context maintained over entire AEMIF
228 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
229 * since that forces use of a problematic "infix OOB" layout.
230 * Among other things, it trashes manufacturer bad block markers.
231 * Also, and specific to this hardware, it ECC-protects the "prepad"
232 * in the OOB ... while having ECC protection for parts of OOB would
233 * seem useful, the current MTD stack sometimes wants to update the
234 * OOB without recomputing ECC.
237 static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
239 struct davinci_nand_info *info = to_davinci_nand(mtd);
243 spin_lock_irqsave(&davinci_nand_lock, flags);
245 /* Start 4-bit ECC calculation for read/write */
246 val = davinci_nand_readl(info, NANDFCR_OFFSET);
248 val |= (info->core_chipsel << 4) | BIT(12);
249 davinci_nand_writel(info, NANDFCR_OFFSET, val);
251 info->is_readmode = (mode == NAND_ECC_READ);
253 spin_unlock_irqrestore(&davinci_nand_lock, flags);
256 /* Read raw ECC code after writing to NAND. */
258 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
260 const u32 mask = 0x03ff03ff;
262 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
263 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
264 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
265 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
268 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
269 static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
270 const u_char *dat, u_char *ecc_code)
272 struct davinci_nand_info *info = to_davinci_nand(mtd);
276 /* After a read, terminate ECC calculation by a dummy read
277 * of some 4-bit ECC register. ECC covers everything that
278 * was read; correct() just uses the hardware state, so
279 * ecc_code is not needed.
281 if (info->is_readmode) {
282 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
286 /* Pack eight raw 10-bit ecc values into ten bytes, making
287 * two passes which each convert four values (in upper and
288 * lower halves of two 32-bit words) into five bytes. The
289 * ROM boot loader uses this same packing scheme.
291 nand_davinci_readecc_4bit(info, raw_ecc);
292 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
293 *ecc_code++ = p[0] & 0xff;
294 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
295 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
296 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
297 *ecc_code++ = (p[1] >> 18) & 0xff;
303 /* Correct up to 4 bits in data we just read, using state left in the
304 * hardware plus the ecc_code computed when it was first written.
306 static int nand_davinci_correct_4bit(struct mtd_info *mtd,
307 u_char *data, u_char *ecc_code, u_char *null)
310 struct davinci_nand_info *info = to_davinci_nand(mtd);
311 unsigned short ecc10[8];
312 unsigned short *ecc16;
315 unsigned num_errors, corrected;
316 unsigned long timeo = jiffies + msecs_to_jiffies(100);
318 /* All bytes 0xff? It's an erased page; ignore its ECC. */
319 for (i = 0; i < 10; i++) {
320 if (ecc_code[i] != 0xff)
326 /* Unpack ten bytes into eight 10 bit values. We know we're
327 * little-endian, and use type punning for less shifting/masking.
329 if (WARN_ON(0x01 & (unsigned) ecc_code))
331 ecc16 = (unsigned short *)ecc_code;
333 ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
334 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
335 ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
336 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
337 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
338 ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
339 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
340 ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
342 /* Tell ECC controller about the expected ECC codes. */
343 for (i = 7; i >= 0; i--)
344 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
346 /* Allow time for syndrome calculation ... then read it.
347 * A syndrome of all zeroes 0 means no detected errors.
349 davinci_nand_readl(info, NANDFSR_OFFSET);
350 nand_davinci_readecc_4bit(info, syndrome);
351 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
355 * Clear any previous address calculation by doing a dummy read of an
356 * error address register.
358 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
360 /* Start address calculation, and wait for it to complete.
361 * We _could_ start reading more data while this is working,
362 * to speed up the overall page read.
364 davinci_nand_writel(info, NANDFCR_OFFSET,
365 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
368 * ECC_STATE field reads 0x3 (Error correction complete) immediately
369 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
370 * begin trying to poll for the state, you may fall right out of your
371 * loop without any of the correction calculations having taken place.
372 * The recommendation from the hardware team is to wait till ECC_STATE
373 * reads less than 4, which means ECC HW has entered correction state.
376 ecc_state = (davinci_nand_readl(info,
377 NANDFSR_OFFSET) >> 8) & 0x0f;
379 } while ((ecc_state < 4) && time_before(jiffies, timeo));
382 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
384 switch ((fsr >> 8) & 0x0f) {
385 case 0: /* no error, should not happen */
386 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
388 case 1: /* five or more errors detected */
389 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
391 case 2: /* error addresses computed */
393 num_errors = 1 + ((fsr >> 16) & 0x03);
395 default: /* still working on it */
402 /* correct each error */
403 for (i = 0, corrected = 0; i < num_errors; i++) {
404 int error_address, error_value;
407 error_address = davinci_nand_readl(info,
408 NAND_ERR_ADD2_OFFSET);
409 error_value = davinci_nand_readl(info,
410 NAND_ERR_ERRVAL2_OFFSET);
412 error_address = davinci_nand_readl(info,
413 NAND_ERR_ADD1_OFFSET);
414 error_value = davinci_nand_readl(info,
415 NAND_ERR_ERRVAL1_OFFSET);
419 error_address >>= 16;
422 error_address &= 0x3ff;
423 error_address = (512 + 7) - error_address;
425 if (error_address < 512) {
426 data[error_address] ^= error_value;
434 /*----------------------------------------------------------------------*/
437 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
438 * how these chips are normally wired. This translates to both 8 and 16
439 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
441 * For now we assume that configuration, or any other one which ignores
442 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
443 * and have that transparently morphed into multiple NAND operations.
445 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
447 struct nand_chip *chip = mtd->priv;
449 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
450 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
451 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
452 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
454 ioread8_rep(chip->IO_ADDR_R, buf, len);
457 static void nand_davinci_write_buf(struct mtd_info *mtd,
458 const uint8_t *buf, int len)
460 struct nand_chip *chip = mtd->priv;
462 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
463 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
464 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
465 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
467 iowrite8_rep(chip->IO_ADDR_R, buf, len);
471 * Check hardware register for wait status. Returns 1 if device is ready,
472 * 0 if it is still busy.
474 static int nand_davinci_dev_ready(struct mtd_info *mtd)
476 struct davinci_nand_info *info = to_davinci_nand(mtd);
478 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
481 static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info)
483 uint32_t regval, a1cr;
486 * NAND FLASH timings @ PLL1 == 459 MHz
487 * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz
488 * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
491 | (0 << 31) /* selectStrobe */
492 | (0 << 30) /* extWait (never with NAND) */
493 | (1 << 26) /* writeSetup 10 ns */
494 | (3 << 20) /* writeStrobe 40 ns */
495 | (1 << 17) /* writeHold 10 ns */
496 | (0 << 13) /* readSetup 10 ns */
497 | (3 << 7) /* readStrobe 60 ns */
498 | (0 << 4) /* readHold 10 ns */
499 | (3 << 2) /* turnAround ?? ns */
500 | (0 << 0) /* asyncSize 8-bit bus */
502 a1cr = davinci_nand_readl(info, A1CR_OFFSET);
503 if (a1cr != regval) {
504 dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \
505 "reg to 0x%08x, was 0x%08x, should be done by " \
506 "bootloader.\n", regval, a1cr);
507 davinci_nand_writel(info, A1CR_OFFSET, regval);
511 /*----------------------------------------------------------------------*/
513 /* An ECC layout for using 4-bit ECC with small-page flash, storing
514 * ten ECC bytes plus the manufacturer's bad block marker byte, and
515 * and not overlapping the default BBT markers.
517 static struct nand_ecclayout hwecc4_small __initconst = {
519 .eccpos = { 0, 1, 2, 3, 4,
520 /* offset 5 holds the badblock marker */
524 {.offset = 8, .length = 5, },
529 /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
530 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
531 * and not overlapping the default BBT markers.
533 static struct nand_ecclayout hwecc4_2048 __initconst = {
536 /* at the end of spare sector */
537 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
538 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
539 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
540 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
543 /* 2 bytes at offset 0 hold manufacturer badblock markers */
544 {.offset = 2, .length = 22, },
545 /* 5 bytes at offset 8 hold BBT markers */
546 /* 8 bytes at offset 16 hold JFFS2 clean markers */
550 static int __init nand_davinci_probe(struct platform_device *pdev)
552 struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
553 struct davinci_nand_info *info;
554 struct resource *res1;
555 struct resource *res2;
560 nand_ecc_modes_t ecc_mode;
562 /* insist on board-specific configuration */
566 /* which external chipselect will we be managing? */
567 if (pdev->id < 0 || pdev->id > 3)
570 info = kzalloc(sizeof(*info), GFP_KERNEL);
572 dev_err(&pdev->dev, "unable to allocate memory\n");
577 platform_set_drvdata(pdev, info);
579 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
580 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
581 if (!res1 || !res2) {
582 dev_err(&pdev->dev, "resource missing\n");
587 vaddr = ioremap(res1->start, resource_size(res1));
588 base = ioremap(res2->start, resource_size(res2));
589 if (!vaddr || !base) {
590 dev_err(&pdev->dev, "ioremap failed\n");
595 info->dev = &pdev->dev;
599 info->mtd.priv = &info->chip;
600 info->mtd.name = dev_name(&pdev->dev);
601 info->mtd.owner = THIS_MODULE;
603 info->mtd.dev.parent = &pdev->dev;
605 info->chip.IO_ADDR_R = vaddr;
606 info->chip.IO_ADDR_W = vaddr;
607 info->chip.chip_delay = 0;
608 info->chip.select_chip = nand_davinci_select_chip;
610 /* options such as NAND_USE_FLASH_BBT or 16-bit widths */
611 info->chip.options = pdata->options;
612 info->chip.bbt_td = pdata->bbt_td;
613 info->chip.bbt_md = pdata->bbt_md;
615 info->ioaddr = (uint32_t __force) vaddr;
617 info->current_cs = info->ioaddr;
618 info->core_chipsel = pdev->id;
619 info->mask_chipsel = pdata->mask_chipsel;
621 /* use nandboot-capable ALE/CLE masks by default */
622 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
623 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
625 /* Set address of hardware control function */
626 info->chip.cmd_ctrl = nand_davinci_hwcontrol;
627 info->chip.dev_ready = nand_davinci_dev_ready;
629 /* Speed up buffer I/O */
630 info->chip.read_buf = nand_davinci_read_buf;
631 info->chip.write_buf = nand_davinci_write_buf;
633 /* Use board-specific ECC config */
634 ecc_mode = pdata->ecc_mode;
643 if (pdata->ecc_bits == 4) {
644 /* No sanity checks: CPUs must support this,
645 * and the chips may not use NAND_BUSWIDTH_16.
648 /* No sharing 4-bit hardware between chipselects yet */
649 spin_lock_irq(&davinci_nand_lock);
654 spin_unlock_irq(&davinci_nand_lock);
659 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
660 info->chip.ecc.correct = nand_davinci_correct_4bit;
661 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
662 info->chip.ecc.bytes = 10;
664 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
665 info->chip.ecc.correct = nand_davinci_correct_1bit;
666 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
667 info->chip.ecc.bytes = 3;
669 info->chip.ecc.size = 512;
675 info->chip.ecc.mode = ecc_mode;
677 info->clk = clk_get(&pdev->dev, "aemif");
678 if (IS_ERR(info->clk)) {
679 ret = PTR_ERR(info->clk);
680 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
684 ret = clk_enable(info->clk);
686 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
691 /* EMIF timings should normally be set by the boot loader,
692 * especially after boot-from-NAND. The *only* reason to
693 * have this special casing for the DM6446 EVM is to work
694 * with boot-from-NOR ... with CS0 manually re-jumpered
695 * (after startup) so it addresses the NAND flash, not NOR.
696 * Even for dev boards, that's unusually rude...
698 if (machine_is_davinci_evm())
699 nand_dm6446evm_flash_init(info);
701 spin_lock_irq(&davinci_nand_lock);
703 /* put CSxNAND into NAND mode */
704 val = davinci_nand_readl(info, NANDFCR_OFFSET);
705 val |= BIT(info->core_chipsel);
706 davinci_nand_writel(info, NANDFCR_OFFSET, val);
708 spin_unlock_irq(&davinci_nand_lock);
710 /* Scan to find existence of the device(s) */
711 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
713 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
717 /* Update ECC layout if needed ... for 1-bit HW ECC, the default
718 * is OK, but it allocates 6 bytes when only 3 are needed (for
719 * each 512 bytes). For the 4-bit HW ECC, that default is not
720 * usable: 10 bytes are needed, not 6.
722 if (pdata->ecc_bits == 4) {
723 int chunks = info->mtd.writesize / 512;
725 if (!chunks || info->mtd.oobsize < 16) {
726 dev_dbg(&pdev->dev, "too small\n");
731 /* For small page chips, preserve the manufacturer's
732 * badblock marking data ... and make sure a flash BBT
733 * table marker fits in the free bytes.
736 info->ecclayout = hwecc4_small;
737 info->ecclayout.oobfree[1].length =
738 info->mtd.oobsize - 16;
742 info->ecclayout = hwecc4_2048;
743 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
747 /* 4KiB page chips are not yet supported. The eccpos from
748 * nand_ecclayout cannot hold 80 bytes and change to eccpos[]
749 * breaks userspace ioctl interface with mtd-utils. Once we
750 * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
751 * for the 4KiB page chips.
753 * TODO: Note that nand_ecclayout has now been expanded and can
754 * hold plenty of OOB entries.
756 dev_warn(&pdev->dev, "no 4-bit ECC support yet "
757 "for 4KiB-page NAND\n");
762 info->chip.ecc.layout = &info->ecclayout;
765 ret = nand_scan_tail(&info->mtd);
769 if (mtd_has_partitions()) {
770 struct mtd_partition *mtd_parts = NULL;
771 int mtd_parts_nb = 0;
773 if (mtd_has_cmdlinepart()) {
774 static const char *probes[] __initconst =
775 { "cmdlinepart", NULL };
777 mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
781 if (mtd_parts_nb <= 0) {
782 mtd_parts = pdata->parts;
783 mtd_parts_nb = pdata->nr_parts;
786 /* Register any partitions */
787 if (mtd_parts_nb > 0) {
788 ret = add_mtd_partitions(&info->mtd,
789 mtd_parts, mtd_parts_nb);
791 info->partitioned = true;
794 } else if (pdata->nr_parts) {
795 dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
796 pdata->nr_parts, info->mtd.name);
799 /* If there's no partition info, just package the whole chip
800 * as a single MTD device.
802 if (!info->partitioned)
803 ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;
808 val = davinci_nand_readl(info, NRCSR_OFFSET);
809 dev_info(&pdev->dev, "controller rev. %d.%d\n",
810 (val >> 8) & 0xff, val & 0xff);
815 clk_disable(info->clk);
820 spin_lock_irq(&davinci_nand_lock);
821 if (ecc_mode == NAND_ECC_HW_SYNDROME)
823 spin_unlock_irq(&davinci_nand_lock);
838 static int __exit nand_davinci_remove(struct platform_device *pdev)
840 struct davinci_nand_info *info = platform_get_drvdata(pdev);
843 if (mtd_has_partitions() && info->partitioned)
844 status = del_mtd_partitions(&info->mtd);
846 status = del_mtd_device(&info->mtd);
848 spin_lock_irq(&davinci_nand_lock);
849 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
851 spin_unlock_irq(&davinci_nand_lock);
854 iounmap(info->vaddr);
856 nand_release(&info->mtd);
858 clk_disable(info->clk);
866 static struct platform_driver nand_davinci_driver = {
867 .remove = __exit_p(nand_davinci_remove),
869 .name = "davinci_nand",
872 MODULE_ALIAS("platform:davinci_nand");
874 static int __init nand_davinci_init(void)
876 return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
878 module_init(nand_davinci_init);
880 static void __exit nand_davinci_exit(void)
882 platform_driver_unregister(&nand_davinci_driver);
884 module_exit(nand_davinci_exit);
886 MODULE_LICENSE("GPL");
887 MODULE_AUTHOR("Texas Instruments");
888 MODULE_DESCRIPTION("Davinci NAND flash driver");