1 /* Freescale Enhanced Local Bus Controller NAND driver
3 * Copyright (c) 2006-2007 Freescale Semiconductor
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/ioport.h>
29 #include <linux/of_platform.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/nand.h>
35 #include <linux/mtd/nand_ecc.h>
36 #include <linux/mtd/partitions.h>
39 #include <asm/fsl_lbc.h>
42 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
43 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
47 /* mtd information per set */
51 struct nand_chip chip;
52 struct fsl_elbc_ctrl *ctrl;
55 int bank; /* Chip select bank number */
56 u8 __iomem *vbase; /* Chip select base virtual address */
57 int page_size; /* NAND page size (0=512, 1=2048) */
58 unsigned int fmr; /* FCM Flash Mode Register value */
61 /* overview of the fsl elbc controller */
63 struct fsl_elbc_ctrl {
64 struct nand_hw_control controller;
65 struct fsl_elbc_mtd *chips[MAX_BANKS];
69 struct fsl_lbc_regs __iomem *regs;
71 wait_queue_head_t irq_wait;
72 unsigned int irq_status; /* status read from LTESR by irq handler */
73 u8 __iomem *addr; /* Address of assigned FCM buffer */
74 unsigned int page; /* Last page written to / read from */
75 unsigned int read_bytes; /* Number of bytes read during command */
76 unsigned int column; /* Saved column from SEQIN */
77 unsigned int index; /* Pointer to next byte to 'read' */
78 unsigned int status; /* status read from LTESR after last op */
79 unsigned int mdr; /* UPM/FCM Data Register value */
80 unsigned int use_mdr; /* Non zero if the MDR is to be set */
81 unsigned int oob; /* Non zero if operating on OOB data */
82 char *oob_poi; /* Place to write ECC after read back */
85 /* These map to the positions used by the FCM hardware ECC generator */
87 /* Small Page FLASH with FMR[ECCM] = 0 */
88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
91 .oobfree = { {0, 5}, {9, 7} },
94 /* Small Page FLASH with FMR[ECCM] = 1 */
95 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
98 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
101 /* Large Page FLASH with FMR[ECCM] = 0 */
102 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
104 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
105 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
108 /* Large Page FLASH with FMR[ECCM] = 1 */
109 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
111 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
112 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
116 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
117 * 1, so we have to adjust bad block pattern. This pattern should be used for
118 * x8 chips only. So far hardware does not support x16 chips anyway.
120 static u8 scan_ff_pattern[] = { 0xff, };
122 static struct nand_bbt_descr largepage_memorybased = {
126 .pattern = scan_ff_pattern,
130 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
131 * interfere with ECC positions, that's why we implement our own descriptors.
132 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
134 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
135 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
137 static struct nand_bbt_descr bbt_main_descr = {
138 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
139 NAND_BBT_2BIT | NAND_BBT_VERSION,
144 .pattern = bbt_pattern,
147 static struct nand_bbt_descr bbt_mirror_descr = {
148 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
149 NAND_BBT_2BIT | NAND_BBT_VERSION,
154 .pattern = mirror_pattern,
157 /*=================================*/
160 * Set up the FCM hardware block and page address fields, and the fcm
161 * structure addr field to point to the correct FCM buffer in memory
163 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
165 struct nand_chip *chip = mtd->priv;
166 struct fsl_elbc_mtd *priv = chip->priv;
167 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
168 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
171 ctrl->page = page_addr;
174 page_addr >> (chip->phys_erase_shift - chip->page_shift));
176 if (priv->page_size) {
178 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
179 (oob ? FPAR_LP_MS : 0) | column);
180 buf_num = (page_addr & 1) << 2;
183 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
184 (oob ? FPAR_SP_MS : 0) | column);
185 buf_num = page_addr & 7;
188 ctrl->addr = priv->vbase + buf_num * 1024;
189 ctrl->index = column;
191 /* for OOB data point to the second half of the buffer */
193 ctrl->index += priv->page_size ? 2048 : 512;
195 dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
196 "index %x, pes %d ps %d\n",
197 buf_num, ctrl->addr, priv->vbase, ctrl->index,
198 chip->phys_erase_shift, chip->page_shift);
202 * execute FCM command and wait for it to complete
204 static int fsl_elbc_run_command(struct mtd_info *mtd)
206 struct nand_chip *chip = mtd->priv;
207 struct fsl_elbc_mtd *priv = chip->priv;
208 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
209 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
211 /* Setup the FMR[OP] to execute without write protection */
212 out_be32(&lbc->fmr, priv->fmr | 3);
214 out_be32(&lbc->mdr, ctrl->mdr);
217 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
218 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
220 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
221 "fbcr=%08x bank=%d\n",
222 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
223 in_be32(&lbc->fbcr), priv->bank);
225 ctrl->irq_status = 0;
226 /* execute special operation */
227 out_be32(&lbc->lsor, priv->bank);
229 /* wait for FCM complete flag or timeout */
230 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
231 FCM_TIMEOUT_MSECS * HZ/1000);
232 ctrl->status = ctrl->irq_status;
234 /* store mdr value in case it was needed */
236 ctrl->mdr = in_be32(&lbc->mdr);
240 if (ctrl->status != LTESR_CC) {
242 "command failed: fir %x fcr %x status %x mdr %x\n",
243 in_be32(&lbc->fir), in_be32(&lbc->fcr),
244 ctrl->status, ctrl->mdr);
251 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
253 struct fsl_elbc_mtd *priv = chip->priv;
254 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
255 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
257 if (priv->page_size) {
259 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
260 (FIR_OP_CA << FIR_OP1_SHIFT) |
261 (FIR_OP_PA << FIR_OP2_SHIFT) |
262 (FIR_OP_CM1 << FIR_OP3_SHIFT) |
263 (FIR_OP_RBW << FIR_OP4_SHIFT));
265 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
266 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
269 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
270 (FIR_OP_CA << FIR_OP1_SHIFT) |
271 (FIR_OP_PA << FIR_OP2_SHIFT) |
272 (FIR_OP_RBW << FIR_OP3_SHIFT));
275 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
277 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
281 /* cmdfunc send commands to the FCM */
282 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
283 int column, int page_addr)
285 struct nand_chip *chip = mtd->priv;
286 struct fsl_elbc_mtd *priv = chip->priv;
287 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
288 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
292 /* clear the read buffer */
293 ctrl->read_bytes = 0;
294 if (command != NAND_CMD_PAGEPROG)
298 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
305 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
306 " 0x%x, column: 0x%x.\n", page_addr, column);
309 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
310 set_addr(mtd, 0, page_addr, 0);
312 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
313 ctrl->index += column;
315 fsl_elbc_do_read(chip, 0);
316 fsl_elbc_run_command(mtd);
319 /* READOOB reads only the OOB because no ECC is performed. */
320 case NAND_CMD_READOOB:
322 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
323 " 0x%x, column: 0x%x.\n", page_addr, column);
325 out_be32(&lbc->fbcr, mtd->oobsize - column);
326 set_addr(mtd, column, page_addr, 1);
328 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
330 fsl_elbc_do_read(chip, 1);
331 fsl_elbc_run_command(mtd);
334 /* READID must read all 5 possible bytes while CEB is active */
335 case NAND_CMD_READID:
336 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
338 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
339 (FIR_OP_UA << FIR_OP1_SHIFT) |
340 (FIR_OP_RBW << FIR_OP2_SHIFT));
341 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
342 /* 5 bytes for manuf, device and exts */
343 out_be32(&lbc->fbcr, 5);
344 ctrl->read_bytes = 5;
348 set_addr(mtd, 0, 0, 0);
349 fsl_elbc_run_command(mtd);
352 /* ERASE1 stores the block and page address */
353 case NAND_CMD_ERASE1:
355 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
356 "page_addr: 0x%x.\n", page_addr);
357 set_addr(mtd, 0, page_addr, 0);
360 /* ERASE2 uses the block and page address from ERASE1 */
361 case NAND_CMD_ERASE2:
362 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
365 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
366 (FIR_OP_PA << FIR_OP1_SHIFT) |
367 (FIR_OP_CM2 << FIR_OP2_SHIFT) |
368 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
369 (FIR_OP_RS << FIR_OP4_SHIFT));
372 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
373 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
374 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
376 out_be32(&lbc->fbcr, 0);
377 ctrl->read_bytes = 0;
380 fsl_elbc_run_command(mtd);
383 /* SEQIN sets up the addr buffer and all registers except the length */
384 case NAND_CMD_SEQIN: {
387 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
388 "page_addr: 0x%x, column: 0x%x.\n",
391 ctrl->column = column;
395 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
396 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
397 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
399 if (priv->page_size) {
401 (FIR_OP_CM2 << FIR_OP0_SHIFT) |
402 (FIR_OP_CA << FIR_OP1_SHIFT) |
403 (FIR_OP_PA << FIR_OP2_SHIFT) |
404 (FIR_OP_WB << FIR_OP3_SHIFT) |
405 (FIR_OP_CM3 << FIR_OP4_SHIFT) |
406 (FIR_OP_CW1 << FIR_OP5_SHIFT) |
407 (FIR_OP_RS << FIR_OP6_SHIFT));
410 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
411 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
412 (FIR_OP_CA << FIR_OP2_SHIFT) |
413 (FIR_OP_PA << FIR_OP3_SHIFT) |
414 (FIR_OP_WB << FIR_OP4_SHIFT) |
415 (FIR_OP_CM3 << FIR_OP5_SHIFT) |
416 (FIR_OP_CW1 << FIR_OP6_SHIFT) |
417 (FIR_OP_RS << FIR_OP7_SHIFT));
419 if (column >= mtd->writesize) {
420 /* OOB area --> READOOB */
421 column -= mtd->writesize;
422 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
425 WARN_ON(column != 0);
426 /* First 256 bytes --> READ0 */
427 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
431 out_be32(&lbc->fcr, fcr);
432 set_addr(mtd, column, page_addr, ctrl->oob);
436 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
437 case NAND_CMD_PAGEPROG: {
440 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
441 "writing %d bytes.\n", ctrl->index);
443 /* if the write did not start at 0 or is not a full page
444 * then set the exact length, otherwise use a full page
445 * write so the HW generates the ECC.
447 if (ctrl->oob || ctrl->column != 0 ||
448 ctrl->index != mtd->writesize + mtd->oobsize) {
449 out_be32(&lbc->fbcr, ctrl->index);
452 out_be32(&lbc->fbcr, 0);
456 fsl_elbc_run_command(mtd);
458 /* Read back the page in order to fill in the ECC for the
459 * caller. Is this really needed?
461 if (full_page && ctrl->oob_poi) {
462 out_be32(&lbc->fbcr, 3);
463 set_addr(mtd, 6, page_addr, 1);
465 ctrl->read_bytes = mtd->writesize + 9;
467 fsl_elbc_do_read(chip, 1);
468 fsl_elbc_run_command(mtd);
470 memcpy_fromio(ctrl->oob_poi + 6,
471 &ctrl->addr[ctrl->index], 3);
475 ctrl->oob_poi = NULL;
479 /* CMD_STATUS must read the status byte while CEB is active */
480 /* Note - it does not wait for the ready line */
481 case NAND_CMD_STATUS:
483 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
484 (FIR_OP_RBW << FIR_OP1_SHIFT));
485 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
486 out_be32(&lbc->fbcr, 1);
487 set_addr(mtd, 0, 0, 0);
488 ctrl->read_bytes = 1;
490 fsl_elbc_run_command(mtd);
492 /* The chip always seems to report that it is
493 * write-protected, even when it is not.
495 setbits8(ctrl->addr, NAND_STATUS_WP);
498 /* RESET without waiting for the ready line */
500 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
501 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
502 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
503 fsl_elbc_run_command(mtd);
508 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
513 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
515 /* The hardware does not seem to support multiple
521 * Write buf to the FCM Controller Data Buffer
523 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
525 struct nand_chip *chip = mtd->priv;
526 struct fsl_elbc_mtd *priv = chip->priv;
527 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
528 unsigned int bufsize = mtd->writesize + mtd->oobsize;
531 dev_err(ctrl->dev, "write_buf of %d bytes", len);
536 if ((unsigned int)len > bufsize - ctrl->index) {
538 "write_buf beyond end of buffer "
539 "(%d requested, %u available)\n",
540 len, bufsize - ctrl->index);
541 len = bufsize - ctrl->index;
544 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
546 * This is workaround for the weird elbc hangs during nand write,
547 * Scott Wood says: "...perhaps difference in how long it takes a
548 * write to make it through the localbus compared to a write to IMMR
549 * is causing problems, and sync isn't helping for some reason."
550 * Reading back the last byte helps though.
552 in_8(&ctrl->addr[ctrl->index] + len - 1);
558 * read a byte from either the FCM hardware buffer if it has any data left
559 * otherwise issue a command to read a single byte.
561 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
563 struct nand_chip *chip = mtd->priv;
564 struct fsl_elbc_mtd *priv = chip->priv;
565 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
567 /* If there are still bytes in the FCM, then use the next byte. */
568 if (ctrl->index < ctrl->read_bytes)
569 return in_8(&ctrl->addr[ctrl->index++]);
571 dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
576 * Read from the FCM Controller Data Buffer
578 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
580 struct nand_chip *chip = mtd->priv;
581 struct fsl_elbc_mtd *priv = chip->priv;
582 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
588 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
589 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
590 ctrl->index += avail;
594 "read_buf beyond end of buffer "
595 "(%d requested, %d available)\n",
600 * Verify buffer against the FCM Controller Data Buffer
602 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
604 struct nand_chip *chip = mtd->priv;
605 struct fsl_elbc_mtd *priv = chip->priv;
606 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
610 dev_err(ctrl->dev, "write_buf of %d bytes", len);
614 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
616 "verify_buf beyond end of buffer "
617 "(%d requested, %u available)\n",
618 len, ctrl->read_bytes - ctrl->index);
620 ctrl->index = ctrl->read_bytes;
624 for (i = 0; i < len; i++)
625 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
629 return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
632 /* This function is called after Program and Erase Operations to
633 * check for success or failure.
635 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
637 struct fsl_elbc_mtd *priv = chip->priv;
638 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
640 if (ctrl->status != LTESR_CC)
641 return NAND_STATUS_FAIL;
643 /* The chip always seems to report that it is
644 * write-protected, even when it is not.
646 return (ctrl->mdr & 0xff) | NAND_STATUS_WP;
649 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
651 struct nand_chip *chip = mtd->priv;
652 struct fsl_elbc_mtd *priv = chip->priv;
653 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
654 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
657 /* calculate FMR Address Length field */
659 if (chip->pagemask & 0xffff0000)
661 if (chip->pagemask & 0xff000000)
664 /* add to ECCM mode set in fsl_elbc_init */
665 priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
666 (al << FMR_AL_SHIFT);
668 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
670 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
672 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
674 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
676 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
678 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
680 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
682 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
683 chip->phys_erase_shift);
684 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
686 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
688 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
690 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
692 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
694 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
696 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
697 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
698 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
700 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
702 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
705 /* adjust Option Register and ECC to match Flash page size */
706 if (mtd->writesize == 512) {
708 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
709 } else if (mtd->writesize == 2048) {
711 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
712 /* adjust ecc setup if needed */
713 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
715 chip->ecc.size = 512;
716 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
717 &fsl_elbc_oob_lp_eccm1 :
718 &fsl_elbc_oob_lp_eccm0;
719 chip->badblock_pattern = &largepage_memorybased;
723 "fsl_elbc_init: page size %d is not supported\n",
731 static int fsl_elbc_read_page(struct mtd_info *mtd,
732 struct nand_chip *chip,
736 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
737 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
739 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
740 mtd->ecc_stats.failed++;
745 /* ECC will be calculated automatically, and errors will be detected in
748 static void fsl_elbc_write_page(struct mtd_info *mtd,
749 struct nand_chip *chip,
752 struct fsl_elbc_mtd *priv = chip->priv;
753 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
755 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
756 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
758 ctrl->oob_poi = chip->oob_poi;
761 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
763 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
764 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
765 struct nand_chip *chip = &priv->chip;
767 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
769 /* Fill in fsl_elbc_mtd structure */
770 priv->mtd.priv = chip;
771 priv->mtd.owner = THIS_MODULE;
773 /* Set the ECCM according to the settings in bootloader.*/
774 priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
776 /* fill in nand_chip structure */
777 /* set up function call table */
778 chip->read_byte = fsl_elbc_read_byte;
779 chip->write_buf = fsl_elbc_write_buf;
780 chip->read_buf = fsl_elbc_read_buf;
781 chip->verify_buf = fsl_elbc_verify_buf;
782 chip->select_chip = fsl_elbc_select_chip;
783 chip->cmdfunc = fsl_elbc_cmdfunc;
784 chip->waitfunc = fsl_elbc_wait;
786 chip->bbt_td = &bbt_main_descr;
787 chip->bbt_md = &bbt_mirror_descr;
789 /* set up nand options */
790 chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
793 chip->controller = &ctrl->controller;
796 chip->ecc.read_page = fsl_elbc_read_page;
797 chip->ecc.write_page = fsl_elbc_write_page;
799 /* If CS Base Register selects full hardware ECC then use it */
800 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
802 chip->ecc.mode = NAND_ECC_HW;
803 /* put in small page settings and adjust later if needed */
804 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
805 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
806 chip->ecc.size = 512;
809 /* otherwise fall back to default software ECC */
810 chip->ecc.mode = NAND_ECC_SOFT;
816 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
818 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
820 nand_release(&priv->mtd);
822 kfree(priv->mtd.name);
825 iounmap(priv->vbase);
827 ctrl->chips[priv->bank] = NULL;
833 static int __devinit fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
834 struct device_node *node)
836 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
837 struct fsl_elbc_mtd *priv;
839 #ifdef CONFIG_MTD_PARTITIONS
840 static const char *part_probe_types[]
841 = { "cmdlinepart", "RedBoot", NULL };
842 struct mtd_partition *parts;
847 /* get, allocate and map the memory resource */
848 ret = of_address_to_resource(node, 0, &res);
850 dev_err(ctrl->dev, "failed to get resource\n");
854 /* find which chip select it is connected to */
855 for (bank = 0; bank < MAX_BANKS; bank++)
856 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
857 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
858 (in_be32(&lbc->bank[bank].br) &
859 in_be32(&lbc->bank[bank].or) & BR_BA)
863 if (bank >= MAX_BANKS) {
864 dev_err(ctrl->dev, "address did not match any chip selects\n");
868 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
872 ctrl->chips[bank] = priv;
875 priv->dev = ctrl->dev;
877 priv->vbase = ioremap(res.start, resource_size(&res));
879 dev_err(ctrl->dev, "failed to map chip region\n");
884 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
885 if (!priv->mtd.name) {
890 ret = fsl_elbc_chip_init(priv);
894 ret = nand_scan_ident(&priv->mtd, 1, NULL);
898 ret = fsl_elbc_chip_init_tail(&priv->mtd);
902 ret = nand_scan_tail(&priv->mtd);
906 #ifdef CONFIG_MTD_PARTITIONS
907 /* First look for RedBoot table or partitions on the command
908 * line, these take precedence over device tree information */
909 ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
913 #ifdef CONFIG_MTD_OF_PARTS
915 ret = of_mtd_parse_partitions(priv->dev, node, &parts);
922 add_mtd_partitions(&priv->mtd, parts, ret);
925 add_mtd_device(&priv->mtd);
927 printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
928 (unsigned long long)res.start, priv->bank);
932 fsl_elbc_chip_remove(priv);
936 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
938 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
941 * NAND transactions can tie up the bus for a long time, so set the
942 * bus timeout to max by clearing LBCR[BMT] (highest base counter
943 * value) and setting LBCR[BMTPS] to the highest prescaler value.
945 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
947 /* clear event registers */
948 setbits32(&lbc->ltesr, LTESR_NAND_MASK);
949 out_be32(&lbc->lteatr, 0);
951 /* Enable interrupts for any detected events */
952 out_be32(&lbc->lteir, LTESR_NAND_MASK);
954 ctrl->read_bytes = 0;
961 static int fsl_elbc_ctrl_remove(struct platform_device *ofdev)
963 struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
966 for (i = 0; i < MAX_BANKS; i++)
968 fsl_elbc_chip_remove(ctrl->chips[i]);
971 free_irq(ctrl->irq, ctrl);
976 dev_set_drvdata(&ofdev->dev, NULL);
981 /* NOTE: This interrupt is also used to report other localbus events,
982 * such as transaction errors on other chipselects. If we want to
983 * capture those, we'll need to move the IRQ code into a shared
987 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
989 struct fsl_elbc_ctrl *ctrl = data;
990 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
991 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
994 out_be32(&lbc->ltesr, status);
995 out_be32(&lbc->lteatr, 0);
997 ctrl->irq_status = status;
999 wake_up(&ctrl->irq_wait);
1007 /* fsl_elbc_ctrl_probe
1009 * called by device layer when it finds a device matching
1010 * one our driver can handled. This code allocates all of
1011 * the resources needed for the controller only. The
1012 * resources for the NAND banks themselves are allocated
1013 * in the chip probe function.
1016 static int __devinit fsl_elbc_ctrl_probe(struct platform_device *ofdev,
1017 const struct of_device_id *match)
1019 struct device_node *child;
1020 struct fsl_elbc_ctrl *ctrl;
1023 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1027 dev_set_drvdata(&ofdev->dev, ctrl);
1029 spin_lock_init(&ctrl->controller.lock);
1030 init_waitqueue_head(&ctrl->controller.wq);
1031 init_waitqueue_head(&ctrl->irq_wait);
1033 ctrl->regs = of_iomap(ofdev->dev.of_node, 0);
1035 dev_err(&ofdev->dev, "failed to get memory region\n");
1040 ctrl->irq = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
1041 if (ctrl->irq == NO_IRQ) {
1042 dev_err(&ofdev->dev, "failed to get irq resource\n");
1047 ctrl->dev = &ofdev->dev;
1049 ret = fsl_elbc_ctrl_init(ctrl);
1053 ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1055 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1061 for_each_child_of_node(ofdev->dev.of_node, child)
1062 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1063 fsl_elbc_chip_probe(ctrl, child);
1068 fsl_elbc_ctrl_remove(ofdev);
1072 static const struct of_device_id fsl_elbc_match[] = {
1074 .compatible = "fsl,elbc",
1079 static struct of_platform_driver fsl_elbc_ctrl_driver = {
1082 .owner = THIS_MODULE,
1083 .of_match_table = fsl_elbc_match,
1085 .probe = fsl_elbc_ctrl_probe,
1086 .remove = fsl_elbc_ctrl_remove,
1089 static int __init fsl_elbc_init(void)
1091 return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1094 static void __exit fsl_elbc_exit(void)
1096 of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1099 module_init(fsl_elbc_init);
1100 module_exit(fsl_elbc_exit);
1102 MODULE_LICENSE("GPL");
1103 MODULE_AUTHOR("Freescale");
1104 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");