drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *          Jack Lan <jack.lan@freescale.com>
   8  *          Roy Zang <tie-fei.zang@freescale.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/types.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/string.h>
  30 #include <linux/ioport.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/interrupt.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/nand_ecc.h>
  39 #include <linux/mtd/partitions.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/fsl_lbc.h>
  43
  44 #define MAX_BANKS 8
  45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  47
  48 /* mtd information per set */
  49
  50 struct fsl_elbc_mtd {
  51         struct mtd_info mtd;
  52         struct nand_chip chip;
  53         struct fsl_lbc_ctrl *ctrl;
  54
  55         struct device *dev;
  56         int bank;               /* Chip select bank number           */
  57         u8 __iomem *vbase;      /* Chip select base virtual address  */
  58         int page_size;          /* NAND page size (0=512, 1=2048)    */
  59         unsigned int fmr;       /* FCM Flash Mode Register value     */
  60 };
  61
  62 /* Freescale eLBC FCM controller information */
  63
  64 struct fsl_elbc_fcm_ctrl {
  65         struct nand_hw_control controller;
  66         struct fsl_elbc_mtd *chips[MAX_BANKS];
  67
  68         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  69         unsigned int page;       /* Last page written to / read from      */
  70         unsigned int read_bytes; /* Number of bytes read during command   */
  71         unsigned int column;     /* Saved column from SEQIN               */
  72         unsigned int index;      /* Pointer to next byte to 'read'        */
  73         unsigned int status;     /* status read from LTESR after last op  */
  74         unsigned int mdr;        /* UPM/FCM Data Register value           */
  75         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  76         unsigned int oob;        /* Non zero if operating on OOB data     */
  77         unsigned int counter;    /* counter for the initializations       */
  78 };
  79
  80 /* These map to the positions used by the FCM hardware ECC generator */
  81
  82 /* Small Page FLASH with FMR[ECCM] = 0 */
  83 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  84         .eccbytes = 3,
  85         .eccpos = {6, 7, 8},
  86         .oobfree = { {0, 5}, {9, 7} },
  87 };
  88
  89 /* Small Page FLASH with FMR[ECCM] = 1 */
  90 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  91         .eccbytes = 3,
  92         .eccpos = {8, 9, 10},
  93         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  94 };
  95
  96 /* Large Page FLASH with FMR[ECCM] = 0 */
  97 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  98         .eccbytes = 12,
  99         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 100         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 101 };
 102
 103 /* Large Page FLASH with FMR[ECCM] = 1 */
 104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 105         .eccbytes = 12,
 106         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 107         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 108 };
 109
 110 /*
 111  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 112  * 1, so we have to adjust bad block pattern. This pattern should be used for
 113  * x8 chips only. So far hardware does not support x16 chips anyway.
 114  */
 115 static u8 scan_ff_pattern[] = { 0xff, };
 116
 117 static struct nand_bbt_descr largepage_memorybased = {
 118         .options = 0,
 119         .offs = 0,
 120         .len = 1,
 121         .pattern = scan_ff_pattern,
 122 };
 123
 124 /*
 125  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 126  * interfere with ECC positions, that's why we implement our own descriptors.
 127  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 128  */
 129 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 130 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 131
 132 static struct nand_bbt_descr bbt_main_descr = {
 133         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 134                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 135         .offs = 11,
 136         .len = 4,
 137         .veroffs = 15,
 138         .maxblocks = 4,
 139         .pattern = bbt_pattern,
 140 };
 141
 142 static struct nand_bbt_descr bbt_mirror_descr = {
 143         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 144                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 145         .offs = 11,
 146         .len = 4,
 147         .veroffs = 15,
 148         .maxblocks = 4,
 149         .pattern = mirror_pattern,
 150 };
 151
 152 /*=================================*/
 153
 154 /*
 155  * Set up the FCM hardware block and page address fields, and the fcm
 156  * structure addr field to point to the correct FCM buffer in memory
 157  */
 158 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 159 {
 160         struct nand_chip *chip = mtd->priv;
 161         struct fsl_elbc_mtd *priv = chip->priv;
 162         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 163         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 164         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 165         int buf_num;
 166
 167         elbc_fcm_ctrl->page = page_addr;
 168
 169         out_be32(&lbc->fbar,
 170                  page_addr >> (chip->phys_erase_shift - chip->page_shift));
 171
 172         if (priv->page_size) {
 173                 out_be32(&lbc->fpar,
 174                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 175                          (oob ? FPAR_LP_MS : 0) | column);
 176                 buf_num = (page_addr & 1) << 2;
 177         } else {
 178                 out_be32(&lbc->fpar,
 179                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 180                          (oob ? FPAR_SP_MS : 0) | column);
 181                 buf_num = page_addr & 7;
 182         }
 183
 184         elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
 185         elbc_fcm_ctrl->index = column;
 186
 187         /* for OOB data point to the second half of the buffer */
 188         if (oob)
 189                 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
 190
 191         dev_vdbg(priv->dev, "set_addr: bank=%d, "
 192                             "elbc_fcm_ctrl->addr=0x%p (0x%p), "
 193                             "index %x, pes %d ps %d\n",
 194                  buf_num, elbc_fcm_ctrl->addr, priv->vbase,
 195                  elbc_fcm_ctrl->index,
 196                  chip->phys_erase_shift, chip->page_shift);
 197 }
 198
 199 /*
 200  * execute FCM command and wait for it to complete
 201  */
 202 static int fsl_elbc_run_command(struct mtd_info *mtd)
 203 {
 204         struct nand_chip *chip = mtd->priv;
 205         struct fsl_elbc_mtd *priv = chip->priv;
 206         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 207         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 208         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 209
 210         /* Setup the FMR[OP] to execute without write protection */
 211         out_be32(&lbc->fmr, priv->fmr | 3);
 212         if (elbc_fcm_ctrl->use_mdr)
 213                 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
 214
 215         dev_vdbg(priv->dev,
 216                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 217                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 218         dev_vdbg(priv->dev,
 219                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 220                  "fbcr=%08x bank=%d\n",
 221                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 222                  in_be32(&lbc->fbcr), priv->bank);
 223
 224         ctrl->irq_status = 0;
 225         /* execute special operation */
 226         out_be32(&lbc->lsor, priv->bank);
 227
 228         /* wait for FCM complete flag or timeout */
 229         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 230                            FCM_TIMEOUT_MSECS * HZ/1000);
 231         elbc_fcm_ctrl->status = ctrl->irq_status;
 232         /* store mdr value in case it was needed */
 233         if (elbc_fcm_ctrl->use_mdr)
 234                 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
 235
 236         elbc_fcm_ctrl->use_mdr = 0;
 237
 238         if (elbc_fcm_ctrl->status != LTESR_CC) {
 239                 dev_info(priv->dev,
 240                          "command failed: fir %x fcr %x status %x mdr %x\n",
 241                          in_be32(&lbc->fir), in_be32(&lbc->fcr),
 242                          elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
 243                 return -EIO;
 244         }
 245
 246         if (chip->ecc.mode != NAND_ECC_HW)
 247                 return 0;
 248
 249         if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
 250                 uint32_t lteccr = in_be32(&lbc->lteccr);
 251                 /*
 252                  * if command was a full page read and the ELBC
 253                  * has the LTECCR register, then bits 12-15 (ppc order) of
 254                  * LTECCR indicates which 512 byte sub-pages had fixed errors.
 255                  * bits 28-31 are uncorrectable errors, marked elsewhere.
 256                  * for small page nand only 1 bit is used.
 257                  * if the ELBC doesn't have the lteccr register it reads 0
 258                  */
 259                 if (lteccr & 0x000F000F)
 260                         out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
 261                 if (lteccr & 0x000F0000)
 262                         mtd->ecc_stats.corrected++;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 269 {
 270         struct fsl_elbc_mtd *priv = chip->priv;
 271         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 272         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 273
 274         if (priv->page_size) {
 275                 out_be32(&lbc->fir,
 276                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 277                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 278                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 279                          (FIR_OP_CM1 << FIR_OP3_SHIFT) |
 280                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 281
 282                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 283                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 284         } else {
 285                 out_be32(&lbc->fir,
 286                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 287                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 288                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 289                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 290
 291                 if (oob)
 292                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 293                 else
 294                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 295         }
 296 }
 297
 298 /* cmdfunc send commands to the FCM */
 299 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 300                              int column, int page_addr)
 301 {
 302         struct nand_chip *chip = mtd->priv;
 303         struct fsl_elbc_mtd *priv = chip->priv;
 304         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 305         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 306         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 307
 308         elbc_fcm_ctrl->use_mdr = 0;
 309
 310         /* clear the read buffer */
 311         elbc_fcm_ctrl->read_bytes = 0;
 312         if (command != NAND_CMD_PAGEPROG)
 313                 elbc_fcm_ctrl->index = 0;
 314
 315         switch (command) {
 316         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 317         case NAND_CMD_READ1:
 318                 column += 256;
 319
 320         /* fall-through */
 321         case NAND_CMD_READ0:
 322                 dev_dbg(priv->dev,
 323                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 324                         " 0x%x, column: 0x%x.\n", page_addr, column);
 325
 326
 327                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 328                 set_addr(mtd, 0, page_addr, 0);
 329
 330                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 331                 elbc_fcm_ctrl->index += column;
 332
 333                 fsl_elbc_do_read(chip, 0);
 334                 fsl_elbc_run_command(mtd);
 335                 return;
 336
 337         /* READOOB reads only the OOB because no ECC is performed. */
 338         case NAND_CMD_READOOB:
 339                 dev_vdbg(priv->dev,
 340                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 341                          " 0x%x, column: 0x%x.\n", page_addr, column);
 342
 343                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 344                 set_addr(mtd, column, page_addr, 1);
 345
 346                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 347
 348                 fsl_elbc_do_read(chip, 1);
 349                 fsl_elbc_run_command(mtd);
 350                 return;
 351
 352         /* READID must read all 5 possible bytes while CEB is active */
 353         case NAND_CMD_READID:
 354                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 355
 356                 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 357                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 358                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 359                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 360                 /* nand_get_flash_type() reads 8 bytes of entire ID string */
 361                 out_be32(&lbc->fbcr, 8);
 362                 elbc_fcm_ctrl->read_bytes = 8;
 363                 elbc_fcm_ctrl->use_mdr = 1;
 364                 elbc_fcm_ctrl->mdr = 0;
 365
 366                 set_addr(mtd, 0, 0, 0);
 367                 fsl_elbc_run_command(mtd);
 368                 return;
 369
 370         /* ERASE1 stores the block and page address */
 371         case NAND_CMD_ERASE1:
 372                 dev_vdbg(priv->dev,
 373                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 374                          "page_addr: 0x%x.\n", page_addr);
 375                 set_addr(mtd, 0, page_addr, 0);
 376                 return;
 377
 378         /* ERASE2 uses the block and page address from ERASE1 */
 379         case NAND_CMD_ERASE2:
 380                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 381
 382                 out_be32(&lbc->fir,
 383                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 384                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 385                          (FIR_OP_CM2 << FIR_OP2_SHIFT) |
 386                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 387                          (FIR_OP_RS  << FIR_OP4_SHIFT));
 388
 389                 out_be32(&lbc->fcr,
 390                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 391                          (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
 392                          (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
 393
 394                 out_be32(&lbc->fbcr, 0);
 395                 elbc_fcm_ctrl->read_bytes = 0;
 396                 elbc_fcm_ctrl->use_mdr = 1;
 397
 398                 fsl_elbc_run_command(mtd);
 399                 return;
 400
 401         /* SEQIN sets up the addr buffer and all registers except the length */
 402         case NAND_CMD_SEQIN: {
 403                 __be32 fcr;
 404                 dev_vdbg(priv->dev,
 405                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 406                          "page_addr: 0x%x, column: 0x%x.\n",
 407                          page_addr, column);
 408
 409                 elbc_fcm_ctrl->column = column;
 410                 elbc_fcm_ctrl->use_mdr = 1;
 411
 412                 if (column >= mtd->writesize) {
 413                         /* OOB area */
 414                         column -= mtd->writesize;
 415                         elbc_fcm_ctrl->oob = 1;
 416                 } else {
 417                         WARN_ON(column != 0);
 418                         elbc_fcm_ctrl->oob = 0;
 419                 }
 420
 421                 fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
 422                       (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
 423                       (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
 424
 425                 if (priv->page_size) {
 426                         out_be32(&lbc->fir,
 427                                  (FIR_OP_CM2 << FIR_OP0_SHIFT) |
 428                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 429                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 430                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 431                                  (FIR_OP_CM3 << FIR_OP4_SHIFT) |
 432                                  (FIR_OP_CW1 << FIR_OP5_SHIFT) |
 433                                  (FIR_OP_RS  << FIR_OP6_SHIFT));
 434                 } else {
 435                         out_be32(&lbc->fir,
 436                                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 437                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 438                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 439                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 440                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 441                                  (FIR_OP_CM3 << FIR_OP5_SHIFT) |
 442                                  (FIR_OP_CW1 << FIR_OP6_SHIFT) |
 443                                  (FIR_OP_RS  << FIR_OP7_SHIFT));
 444
 445                         if (elbc_fcm_ctrl->oob)
 446                                 /* OOB area --> READOOB */
 447                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 448                         else
 449                                 /* First 256 bytes --> READ0 */
 450                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 451                 }
 452
 453                 out_be32(&lbc->fcr, fcr);
 454                 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
 455                 return;
 456         }
 457
 458         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 459         case NAND_CMD_PAGEPROG: {
 460                 dev_vdbg(priv->dev,
 461                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 462                          "writing %d bytes.\n", elbc_fcm_ctrl->index);
 463
 464                 /* if the write did not start at 0 or is not a full page
 465                  * then set the exact length, otherwise use a full page
 466                  * write so the HW generates the ECC.
 467                  */
 468                 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
 469                     elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
 470                         out_be32(&lbc->fbcr, elbc_fcm_ctrl->index);
 471                 else
 472                         out_be32(&lbc->fbcr, 0);
 473
 474                 fsl_elbc_run_command(mtd);
 475                 return;
 476         }
 477
 478         /* CMD_STATUS must read the status byte while CEB is active */
 479         /* Note - it does not wait for the ready line */
 480         case NAND_CMD_STATUS:
 481                 out_be32(&lbc->fir,
 482                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 483                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 484                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 485                 out_be32(&lbc->fbcr, 1);
 486                 set_addr(mtd, 0, 0, 0);
 487                 elbc_fcm_ctrl->read_bytes = 1;
 488
 489                 fsl_elbc_run_command(mtd);
 490
 491                 /* The chip always seems to report that it is
 492                  * write-protected, even when it is not.
 493                  */
 494                 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
 495                 return;
 496
 497         /* RESET without waiting for the ready line */
 498         case NAND_CMD_RESET:
 499                 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 500                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 501                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 502                 fsl_elbc_run_command(mtd);
 503                 return;
 504
 505         default:
 506                 dev_err(priv->dev,
 507                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 508                         command);
 509         }
 510 }
 511
 512 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 513 {
 514         /* The hardware does not seem to support multiple
 515          * chips per bank.
 516          */
 517 }
 518
 519 /*
 520  * Write buf to the FCM Controller Data Buffer
 521  */
 522 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 523 {
 524         struct nand_chip *chip = mtd->priv;
 525         struct fsl_elbc_mtd *priv = chip->priv;
 526         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 527         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 528
 529         if (len <= 0) {
 530                 dev_err(priv->dev, "write_buf of %d bytes", len);
 531                 elbc_fcm_ctrl->status = 0;
 532                 return;
 533         }
 534
 535         if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
 536                 dev_err(priv->dev,
 537                         "write_buf beyond end of buffer "
 538                         "(%d requested, %u available)\n",
 539                         len, bufsize - elbc_fcm_ctrl->index);
 540                 len = bufsize - elbc_fcm_ctrl->index;
 541         }
 542
 543         memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
 544         /*
 545          * This is workaround for the weird elbc hangs during nand write,
 546          * Scott Wood says: "...perhaps difference in how long it takes a
 547          * write to make it through the localbus compared to a write to IMMR
 548          * is causing problems, and sync isn't helping for some reason."
 549          * Reading back the last byte helps though.
 550          */
 551         in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
 552
 553         elbc_fcm_ctrl->index += len;
 554 }
 555
 556 /*
 557  * read a byte from either the FCM hardware buffer if it has any data left
 558  * otherwise issue a command to read a single byte.
 559  */
 560 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 561 {
 562         struct nand_chip *chip = mtd->priv;
 563         struct fsl_elbc_mtd *priv = chip->priv;
 564         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 565
 566         /* If there are still bytes in the FCM, then use the next byte. */
 567         if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
 568                 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
 569
 570         dev_err(priv->dev, "read_byte beyond end of buffer\n");
 571         return ERR_BYTE;
 572 }
 573
 574 /*
 575  * Read from the FCM Controller Data Buffer
 576  */
 577 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 578 {
 579         struct nand_chip *chip = mtd->priv;
 580         struct fsl_elbc_mtd *priv = chip->priv;
 581         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 582         int avail;
 583
 584         if (len < 0)
 585                 return;
 586
 587         avail = min((unsigned int)len,
 588                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 589         memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
 590         elbc_fcm_ctrl->index += avail;
 591
 592         if (len > avail)
 593                 dev_err(priv->dev,
 594                         "read_buf beyond end of buffer "
 595                         "(%d requested, %d available)\n",
 596                         len, avail);
 597 }
 598
 599 /*
 600  * Verify buffer against the FCM Controller Data Buffer
 601  */
 602 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 603 {
 604         struct nand_chip *chip = mtd->priv;
 605         struct fsl_elbc_mtd *priv = chip->priv;
 606         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 607         int i;
 608
 609         if (len < 0) {
 610                 dev_err(priv->dev, "write_buf of %d bytes", len);
 611                 return -EINVAL;
 612         }
 613
 614         if ((unsigned int)len >
 615                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
 616                 dev_err(priv->dev,
 617                         "verify_buf beyond end of buffer "
 618                         "(%d requested, %u available)\n",
 619                         len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 620
 621                 elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
 622                 return -EINVAL;
 623         }
 624
 625         for (i = 0; i < len; i++)
 626                 if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
 627                                 != buf[i])
 628                         break;
 629
 630         elbc_fcm_ctrl->index += len;
 631         return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
 632 }
 633
 634 /* This function is called after Program and Erase Operations to
 635  * check for success or failure.
 636  */
 637 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 638 {
 639         struct fsl_elbc_mtd *priv = chip->priv;
 640         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 641
 642         if (elbc_fcm_ctrl->status != LTESR_CC)
 643                 return NAND_STATUS_FAIL;
 644
 645         /* The chip always seems to report that it is
 646          * write-protected, even when it is not.
 647          */
 648         return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
 649 }
 650
 651 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 652 {
 653         struct nand_chip *chip = mtd->priv;
 654         struct fsl_elbc_mtd *priv = chip->priv;
 655         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 656         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 657         unsigned int al;
 658
 659         /* calculate FMR Address Length field */
 660         al = 0;
 661         if (chip->pagemask & 0xffff0000)
 662                 al++;
 663         if (chip->pagemask & 0xff000000)
 664                 al++;
 665
 666         /* add to ECCM mode set in fsl_elbc_init */
 667         priv->fmr |= (12 << FMR_CWTO_SHIFT) |  /* Timeout > 12 ms */
 668                      (al << FMR_AL_SHIFT);
 669
 670         dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
 671                 chip->numchips);
 672         dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
 673                 chip->chipsize);
 674         dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 675                 chip->pagemask);
 676         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 677                 chip->chip_delay);
 678         dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 679                 chip->badblockpos);
 680         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 681                 chip->chip_shift);
 682         dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 683                 chip->page_shift);
 684         dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 685                 chip->phys_erase_shift);
 686         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 687                 chip->ecclayout);
 688         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 689                 chip->ecc.mode);
 690         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 691                 chip->ecc.steps);
 692         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 693                 chip->ecc.bytes);
 694         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 695                 chip->ecc.total);
 696         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 697                 chip->ecc.layout);
 698         dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 699         dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
 700         dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 701                 mtd->erasesize);
 702         dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 703                 mtd->writesize);
 704         dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 705                 mtd->oobsize);
 706
 707         /* adjust Option Register and ECC to match Flash page size */
 708         if (mtd->writesize == 512) {
 709                 priv->page_size = 0;
 710                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 711         } else if (mtd->writesize == 2048) {
 712                 priv->page_size = 1;
 713                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 714                 /* adjust ecc setup if needed */
 715                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 716                     BR_DECC_CHK_GEN) {
 717                         chip->ecc.size = 512;
 718                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 719                                            &fsl_elbc_oob_lp_eccm1 :
 720                                            &fsl_elbc_oob_lp_eccm0;
 721                         chip->badblock_pattern = &largepage_memorybased;
 722                 }
 723         } else {
 724                 dev_err(priv->dev,
 725                         "fsl_elbc_init: page size %d is not supported\n",
 726                         mtd->writesize);
 727                 return -1;
 728         }
 729
 730         return 0;
 731 }
 732
 733 static int fsl_elbc_read_page(struct mtd_info *mtd,
 734                               struct nand_chip *chip,
 735                               uint8_t *buf,
 736                               int page)
 737 {
 738         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 739         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 740
 741         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 742                 mtd->ecc_stats.failed++;
 743
 744         return 0;
 745 }
 746
 747 /* ECC will be calculated automatically, and errors will be detected in
 748  * waitfunc.
 749  */
 750 static void fsl_elbc_write_page(struct mtd_info *mtd,
 751                                 struct nand_chip *chip,
 752                                 const uint8_t *buf)
 753 {
 754         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 755         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 756 }
 757
 758 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 759 {
 760         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 761         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 762         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 763         struct nand_chip *chip = &priv->chip;
 764
 765         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 766
 767         /* Fill in fsl_elbc_mtd structure */
 768         priv->mtd.priv = chip;
 769         priv->mtd.owner = THIS_MODULE;
 770
 771         /* Set the ECCM according to the settings in bootloader.*/
 772         priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
 773
 774         /* fill in nand_chip structure */
 775         /* set up function call table */
 776         chip->read_byte = fsl_elbc_read_byte;
 777         chip->write_buf = fsl_elbc_write_buf;
 778         chip->read_buf = fsl_elbc_read_buf;
 779         chip->verify_buf = fsl_elbc_verify_buf;
 780         chip->select_chip = fsl_elbc_select_chip;
 781         chip->cmdfunc = fsl_elbc_cmdfunc;
 782         chip->waitfunc = fsl_elbc_wait;
 783
 784         chip->bbt_td = &bbt_main_descr;
 785         chip->bbt_md = &bbt_mirror_descr;
 786
 787         /* set up nand options */
 788         chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
 789         chip->bbt_options = NAND_BBT_USE_FLASH;
 790
 791         chip->controller = &elbc_fcm_ctrl->controller;
 792         chip->priv = priv;
 793
 794         chip->ecc.read_page = fsl_elbc_read_page;
 795         chip->ecc.write_page = fsl_elbc_write_page;
 796
 797         /* If CS Base Register selects full hardware ECC then use it */
 798         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 799             BR_DECC_CHK_GEN) {
 800                 chip->ecc.mode = NAND_ECC_HW;
 801                 /* put in small page settings and adjust later if needed */
 802                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 803                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 804                 chip->ecc.size = 512;
 805                 chip->ecc.bytes = 3;
 806         } else {
 807                 /* otherwise fall back to default software ECC */
 808                 chip->ecc.mode = NAND_ECC_SOFT;
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 815 {
 816         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 817         nand_release(&priv->mtd);
 818
 819         kfree(priv->mtd.name);
 820
 821         if (priv->vbase)
 822                 iounmap(priv->vbase);
 823
 824         elbc_fcm_ctrl->chips[priv->bank] = NULL;
 825         kfree(priv);
 826         return 0;
 827 }
 828
 829 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
 830
 831 static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
 832 {
 833         struct fsl_lbc_regs __iomem *lbc;
 834         struct fsl_elbc_mtd *priv;
 835         struct resource res;
 836         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
 837         static const char *part_probe_types[]
 838                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
 839         int ret;
 840         int bank;
 841         struct device *dev;
 842         struct device_node *node = pdev->dev.of_node;
 843         struct mtd_part_parser_data ppdata;
 844
 845         ppdata.of_node = pdev->dev.of_node;
 846         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
 847                 return -ENODEV;
 848         lbc = fsl_lbc_ctrl_dev->regs;
 849         dev = fsl_lbc_ctrl_dev->dev;
 850
 851         /* get, allocate and map the memory resource */
 852         ret = of_address_to_resource(node, 0, &res);
 853         if (ret) {
 854                 dev_err(dev, "failed to get resource\n");
 855                 return ret;
 856         }
 857
 858         /* find which chip select it is connected to */
 859         for (bank = 0; bank < MAX_BANKS; bank++)
 860                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 861                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 862                     (in_be32(&lbc->bank[bank].br) &
 863                      in_be32(&lbc->bank[bank].or) & BR_BA)
 864                      == fsl_lbc_addr(res.start))
 865                         break;
 866
 867         if (bank >= MAX_BANKS) {
 868                 dev_err(dev, "address did not match any chip selects\n");
 869                 return -ENODEV;
 870         }
 871
 872         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 873         if (!priv)
 874                 return -ENOMEM;
 875
 876         mutex_lock(&fsl_elbc_nand_mutex);
 877         if (!fsl_lbc_ctrl_dev->nand) {
 878                 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
 879                 if (!elbc_fcm_ctrl) {
 880                         dev_err(dev, "failed to allocate memory\n");
 881                         mutex_unlock(&fsl_elbc_nand_mutex);
 882                         ret = -ENOMEM;
 883                         goto err;
 884                 }
 885                 elbc_fcm_ctrl->counter++;
 886
 887                 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
 888                 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
 889                 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
 890         } else {
 891                 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 892         }
 893         mutex_unlock(&fsl_elbc_nand_mutex);
 894
 895         elbc_fcm_ctrl->chips[bank] = priv;
 896         priv->bank = bank;
 897         priv->ctrl = fsl_lbc_ctrl_dev;
 898         priv->dev = dev;
 899
 900         priv->vbase = ioremap(res.start, resource_size(&res));
 901         if (!priv->vbase) {
 902                 dev_err(dev, "failed to map chip region\n");
 903                 ret = -ENOMEM;
 904                 goto err;
 905         }
 906
 907         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
 908         if (!priv->mtd.name) {
 909                 ret = -ENOMEM;
 910                 goto err;
 911         }
 912
 913         ret = fsl_elbc_chip_init(priv);
 914         if (ret)
 915                 goto err;
 916
 917         ret = nand_scan_ident(&priv->mtd, 1, NULL);
 918         if (ret)
 919                 goto err;
 920
 921         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 922         if (ret)
 923                 goto err;
 924
 925         ret = nand_scan_tail(&priv->mtd);
 926         if (ret)
 927                 goto err;
 928
 929         /* First look for RedBoot table or partitions on the command
 930          * line, these take precedence over device tree information */
 931         mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
 932                                   NULL, 0);
 933
 934         printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
 935                (unsigned long long)res.start, priv->bank);
 936         return 0;
 937
 938 err:
 939         fsl_elbc_chip_remove(priv);
 940         return ret;
 941 }
 942
 943 static int fsl_elbc_nand_remove(struct platform_device *pdev)
 944 {
 945         int i;
 946         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 947         for (i = 0; i < MAX_BANKS; i++)
 948                 if (elbc_fcm_ctrl->chips[i])
 949                         fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]);
 950
 951         mutex_lock(&fsl_elbc_nand_mutex);
 952         elbc_fcm_ctrl->counter--;
 953         if (!elbc_fcm_ctrl->counter) {
 954                 fsl_lbc_ctrl_dev->nand = NULL;
 955                 kfree(elbc_fcm_ctrl);
 956         }
 957         mutex_unlock(&fsl_elbc_nand_mutex);
 958
 959         return 0;
 960
 961 }
 962
 963 static const struct of_device_id fsl_elbc_nand_match[] = {
 964         { .compatible = "fsl,elbc-fcm-nand", },
 965         {}
 966 };
 967
 968 static struct platform_driver fsl_elbc_nand_driver = {
 969         .driver = {
 970                 .name = "fsl,elbc-fcm-nand",
 971                 .owner = THIS_MODULE,
 972                 .of_match_table = fsl_elbc_nand_match,
 973         },
 974         .probe = fsl_elbc_nand_probe,
 975         .remove = fsl_elbc_nand_remove,
 976 };
 977
 978 module_platform_driver(fsl_elbc_nand_driver);
 979
 980 MODULE_LICENSE("GPL");
 981 MODULE_AUTHOR("Freescale");
 982 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");