drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 #define FSMC_NAND_BW8           1
  42 #define FSMC_NAND_BW16          2
  43
  44 #define FSMC_MAX_NOR_BANKS      4
  45 #define FSMC_MAX_NAND_BANKS     4
  46
  47 #define FSMC_FLASH_WIDTH8       1
  48 #define FSMC_FLASH_WIDTH16      2
  49
  50 /* fsmc controller registers for NOR flash */
  51 #define CTRL                    0x0
  52         /* ctrl register definitions */
  53         #define BANK_ENABLE             (1 << 0)
  54         #define MUXED                   (1 << 1)
  55         #define NOR_DEV                 (2 << 2)
  56         #define WIDTH_8                 (0 << 4)
  57         #define WIDTH_16                (1 << 4)
  58         #define RSTPWRDWN               (1 << 6)
  59         #define WPROT                   (1 << 7)
  60         #define WRT_ENABLE              (1 << 12)
  61         #define WAIT_ENB                (1 << 13)
  62
  63 #define CTRL_TIM                0x4
  64         /* ctrl_tim register definitions */
  65
  66 #define FSMC_NOR_BANK_SZ        0x8
  67 #define FSMC_NOR_REG_SIZE       0x40
  68
  69 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  70                                                 FSMC_NOR_BANK_SZ * (bank) + \
  71                                                 reg)
  72
  73 /* fsmc controller registers for NAND flash */
  74 #define PC                      0x00
  75         /* pc register definitions */
  76         #define FSMC_RESET              (1 << 0)
  77         #define FSMC_WAITON             (1 << 1)
  78         #define FSMC_ENABLE             (1 << 2)
  79         #define FSMC_DEVTYPE_NAND       (1 << 3)
  80         #define FSMC_DEVWID_8           (0 << 4)
  81         #define FSMC_DEVWID_16          (1 << 4)
  82         #define FSMC_ECCEN              (1 << 6)
  83         #define FSMC_ECCPLEN_512        (0 << 7)
  84         #define FSMC_ECCPLEN_256        (1 << 7)
  85         #define FSMC_TCLR_1             (1)
  86         #define FSMC_TCLR_SHIFT         (9)
  87         #define FSMC_TCLR_MASK          (0xF)
  88         #define FSMC_TAR_1              (1)
  89         #define FSMC_TAR_SHIFT          (13)
  90         #define FSMC_TAR_MASK           (0xF)
  91 #define STS                     0x04
  92         /* sts register definitions */
  93         #define FSMC_CODE_RDY           (1 << 15)
  94 #define COMM                    0x08
  95         /* comm register definitions */
  96         #define FSMC_TSET_0             0
  97         #define FSMC_TSET_SHIFT         0
  98         #define FSMC_TSET_MASK          0xFF
  99         #define FSMC_TWAIT_6            6
 100         #define FSMC_TWAIT_SHIFT        8
 101         #define FSMC_TWAIT_MASK         0xFF
 102         #define FSMC_THOLD_4            4
 103         #define FSMC_THOLD_SHIFT        16
 104         #define FSMC_THOLD_MASK         0xFF
 105         #define FSMC_THIZ_1             1
 106         #define FSMC_THIZ_SHIFT         24
 107         #define FSMC_THIZ_MASK          0xFF
 108 #define ATTRIB                  0x0C
 109 #define IOATA                   0x10
 110 #define ECC1                    0x14
 111 #define ECC2                    0x18
 112 #define ECC3                    0x1C
 113 #define FSMC_NAND_BANK_SZ       0x20
 114
 115 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 116                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 117                                                 reg)
 118
 119 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 120
 121 struct fsmc_nand_timings {
 122         uint8_t tclr;
 123         uint8_t tar;
 124         uint8_t thiz;
 125         uint8_t thold;
 126         uint8_t twait;
 127         uint8_t tset;
 128 };
 129
 130 enum access_mode {
 131         USE_DMA_ACCESS = 1,
 132         USE_WORD_ACCESS,
 133 };
 134
 135 /**
 136  * fsmc_nand_platform_data - platform specific NAND controller config
 137  * @nand_timings: timing setup for the physical NAND interface
 138  * @partitions: partition table for the platform, use a default fallback
 139  * if this is NULL
 140  * @nr_partitions: the number of partitions in the previous entry
 141  * @options: different options for the driver
 142  * @width: bus width
 143  * @bank: default bank
 144  * platform-specific. If the controller only supports one bank
 145  * this may be set to NULL
 146  */
 147 struct fsmc_nand_platform_data {
 148         struct fsmc_nand_timings *nand_timings;
 149         struct mtd_partition    *partitions;
 150         unsigned int            nr_partitions;
 151         unsigned int            options;
 152         unsigned int            bank;
 153
 154         enum access_mode        mode;
 155
 156         /* priv structures for dma accesses */
 157         void                    *read_dma_priv;
 158         void                    *write_dma_priv;
 159 };
 160
 161 /**
 162  * struct fsmc_nand_data - structure for FSMC NAND device state
 163  *
 164  * @pid:                Part ID on the AMBA PrimeCell format
 165  * @mtd:                MTD info for a NAND flash.
 166  * @nand:               Chip related info for a NAND flash.
 167  * @partitions:         Partition info for a NAND Flash.
 168  * @nr_partitions:      Total number of partition of a NAND flash.
 169  *
 170  * @bank:               Bank number for probed device.
 171  * @clk:                Clock structure for FSMC.
 172  *
 173  * @read_dma_chan:      DMA channel for read access
 174  * @write_dma_chan:     DMA channel for write access to NAND
 175  * @dma_access_complete: Completion structure
 176  *
 177  * @data_pa:            NAND Physical port for Data.
 178  * @data_va:            NAND port for Data.
 179  * @cmd_va:             NAND port for Command.
 180  * @addr_va:            NAND port for Address.
 181  * @regs_va:            FSMC regs base address.
 182  */
 183 struct fsmc_nand_data {
 184         u32                     pid;
 185         struct nand_chip        nand;
 186         struct mtd_partition    *partitions;
 187         unsigned int            nr_partitions;
 188
 189         unsigned int            bank;
 190         struct device           *dev;
 191         enum access_mode        mode;
 192         struct clk              *clk;
 193
 194         /* DMA related objects */
 195         struct dma_chan         *read_dma_chan;
 196         struct dma_chan         *write_dma_chan;
 197         struct completion       dma_access_complete;
 198
 199         struct fsmc_nand_timings *dev_timings;
 200
 201         dma_addr_t              data_pa;
 202         void __iomem            *data_va;
 203         void __iomem            *cmd_va;
 204         void __iomem            *addr_va;
 205         void __iomem            *regs_va;
 206
 207         void                    (*select_chip)(uint32_t bank, uint32_t busw);
 208 };
 209
 210 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 211                                    struct mtd_oob_region *oobregion)
 212 {
 213         struct nand_chip *chip = mtd_to_nand(mtd);
 214
 215         if (section >= chip->ecc.steps)
 216                 return -ERANGE;
 217
 218         oobregion->offset = (section * 16) + 2;
 219         oobregion->length = 3;
 220
 221         return 0;
 222 }
 223
 224 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 225                                     struct mtd_oob_region *oobregion)
 226 {
 227         struct nand_chip *chip = mtd_to_nand(mtd);
 228
 229         if (section >= chip->ecc.steps)
 230                 return -ERANGE;
 231
 232         oobregion->offset = (section * 16) + 8;
 233
 234         if (section < chip->ecc.steps - 1)
 235                 oobregion->length = 8;
 236         else
 237                 oobregion->length = mtd->oobsize - oobregion->offset;
 238
 239         return 0;
 240 }
 241
 242 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 243         .ecc = fsmc_ecc1_ooblayout_ecc,
 244         .free = fsmc_ecc1_ooblayout_free,
 245 };
 246
 247 /*
 248  * ECC placement definitions in oobfree type format.
 249  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 250  * consecutively and immediately after the 512 byte data block for hardware to
 251  * generate the error bit offsets in 512 byte data.
 252  */
 253 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 254                                    struct mtd_oob_region *oobregion)
 255 {
 256         struct nand_chip *chip = mtd_to_nand(mtd);
 257
 258         if (section >= chip->ecc.steps)
 259                 return -ERANGE;
 260
 261         oobregion->length = chip->ecc.bytes;
 262
 263         if (!section && mtd->writesize <= 512)
 264                 oobregion->offset = 0;
 265         else
 266                 oobregion->offset = (section * 16) + 2;
 267
 268         return 0;
 269 }
 270
 271 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 272                                     struct mtd_oob_region *oobregion)
 273 {
 274         struct nand_chip *chip = mtd_to_nand(mtd);
 275
 276         if (section >= chip->ecc.steps)
 277                 return -ERANGE;
 278
 279         oobregion->offset = (section * 16) + 15;
 280
 281         if (section < chip->ecc.steps - 1)
 282                 oobregion->length = 3;
 283         else
 284                 oobregion->length = mtd->oobsize - oobregion->offset;
 285
 286         return 0;
 287 }
 288
 289 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 290         .ecc = fsmc_ecc4_ooblayout_ecc,
 291         .free = fsmc_ecc4_ooblayout_free,
 292 };
 293
 294 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 295 {
 296         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 297 }
 298
 299 /* Assert CS signal based on chipnr */
 300 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
 301 {
 302         struct nand_chip *chip = mtd_to_nand(mtd);
 303         struct fsmc_nand_data *host;
 304
 305         host = mtd_to_fsmc(mtd);
 306
 307         switch (chipnr) {
 308         case -1:
 309                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 310                 break;
 311         case 0:
 312         case 1:
 313         case 2:
 314         case 3:
 315                 if (host->select_chip)
 316                         host->select_chip(chipnr,
 317                                         chip->options & NAND_BUSWIDTH_16);
 318                 break;
 319
 320         default:
 321                 dev_err(host->dev, "unsupported chip-select %d\n", chipnr);
 322         }
 323 }
 324
 325 /*
 326  * fsmc_cmd_ctrl - For facilitaing Hardware access
 327  * This routine allows hardware specific access to control-lines(ALE,CLE)
 328  */
 329 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 330 {
 331         struct nand_chip *this = mtd_to_nand(mtd);
 332         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 333         void __iomem *regs = host->regs_va;
 334         unsigned int bank = host->bank;
 335
 336         if (ctrl & NAND_CTRL_CHANGE) {
 337                 u32 pc;
 338
 339                 if (ctrl & NAND_CLE) {
 340                         this->IO_ADDR_R = host->cmd_va;
 341                         this->IO_ADDR_W = host->cmd_va;
 342                 } else if (ctrl & NAND_ALE) {
 343                         this->IO_ADDR_R = host->addr_va;
 344                         this->IO_ADDR_W = host->addr_va;
 345                 } else {
 346                         this->IO_ADDR_R = host->data_va;
 347                         this->IO_ADDR_W = host->data_va;
 348                 }
 349
 350                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 351                 if (ctrl & NAND_NCE)
 352                         pc |= FSMC_ENABLE;
 353                 else
 354                         pc &= ~FSMC_ENABLE;
 355                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 356         }
 357
 358         mb();
 359
 360         if (cmd != NAND_CMD_NONE)
 361                 writeb_relaxed(cmd, this->IO_ADDR_W);
 362 }
 363
 364 /*
 365  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 366  *
 367  * This routine initializes timing parameters related to NAND memory access in
 368  * FSMC registers
 369  */
 370 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
 371                            uint32_t busw, struct fsmc_nand_timings *timings)
 372 {
 373         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 374         uint32_t tclr, tar, thiz, thold, twait, tset;
 375         struct fsmc_nand_timings *tims;
 376         struct fsmc_nand_timings default_timings = {
 377                 .tclr   = FSMC_TCLR_1,
 378                 .tar    = FSMC_TAR_1,
 379                 .thiz   = FSMC_THIZ_1,
 380                 .thold  = FSMC_THOLD_4,
 381                 .twait  = FSMC_TWAIT_6,
 382                 .tset   = FSMC_TSET_0,
 383         };
 384
 385         if (timings)
 386                 tims = timings;
 387         else
 388                 tims = &default_timings;
 389
 390         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 391         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 392         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 393         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 394         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 395         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 396
 397         if (busw)
 398                 writel_relaxed(value | FSMC_DEVWID_16,
 399                                 FSMC_NAND_REG(regs, bank, PC));
 400         else
 401                 writel_relaxed(value | FSMC_DEVWID_8,
 402                                 FSMC_NAND_REG(regs, bank, PC));
 403
 404         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 405                         FSMC_NAND_REG(regs, bank, PC));
 406         writel_relaxed(thiz | thold | twait | tset,
 407                         FSMC_NAND_REG(regs, bank, COMM));
 408         writel_relaxed(thiz | thold | twait | tset,
 409                         FSMC_NAND_REG(regs, bank, ATTRIB));
 410 }
 411
 412 /*
 413  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 414  */
 415 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 416 {
 417         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 418         void __iomem *regs = host->regs_va;
 419         uint32_t bank = host->bank;
 420
 421         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 422                         FSMC_NAND_REG(regs, bank, PC));
 423         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 424                         FSMC_NAND_REG(regs, bank, PC));
 425         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 426                         FSMC_NAND_REG(regs, bank, PC));
 427 }
 428
 429 /*
 430  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 431  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 432  * max of 8-bits)
 433  */
 434 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 435                                 uint8_t *ecc)
 436 {
 437         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 438         void __iomem *regs = host->regs_va;
 439         uint32_t bank = host->bank;
 440         uint32_t ecc_tmp;
 441         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 442
 443         do {
 444                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 445                         break;
 446                 else
 447                         cond_resched();
 448         } while (!time_after_eq(jiffies, deadline));
 449
 450         if (time_after_eq(jiffies, deadline)) {
 451                 dev_err(host->dev, "calculate ecc timed out\n");
 452                 return -ETIMEDOUT;
 453         }
 454
 455         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 456         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 457         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 458         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 459         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 460
 461         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 462         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 463         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 464         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 465         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 466
 467         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 468         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 469         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 470         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 471         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 472
 473         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 474         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 475
 476         return 0;
 477 }
 478
 479 /*
 480  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 481  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 482  * max of 1-bit)
 483  */
 484 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 485                                 uint8_t *ecc)
 486 {
 487         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 488         void __iomem *regs = host->regs_va;
 489         uint32_t bank = host->bank;
 490         uint32_t ecc_tmp;
 491
 492         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 493         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 494         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 495         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 496
 497         return 0;
 498 }
 499
 500 /* Count the number of 0's in buff upto a max of max_bits */
 501 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 502 {
 503         int k, written_bits = 0;
 504
 505         for (k = 0; k < size; k++) {
 506                 written_bits += hweight8(~buff[k]);
 507                 if (written_bits > max_bits)
 508                         break;
 509         }
 510
 511         return written_bits;
 512 }
 513
 514 static void dma_complete(void *param)
 515 {
 516         struct fsmc_nand_data *host = param;
 517
 518         complete(&host->dma_access_complete);
 519 }
 520
 521 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 522                 enum dma_data_direction direction)
 523 {
 524         struct dma_chan *chan;
 525         struct dma_device *dma_dev;
 526         struct dma_async_tx_descriptor *tx;
 527         dma_addr_t dma_dst, dma_src, dma_addr;
 528         dma_cookie_t cookie;
 529         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 530         int ret;
 531         unsigned long time_left;
 532
 533         if (direction == DMA_TO_DEVICE)
 534                 chan = host->write_dma_chan;
 535         else if (direction == DMA_FROM_DEVICE)
 536                 chan = host->read_dma_chan;
 537         else
 538                 return -EINVAL;
 539
 540         dma_dev = chan->device;
 541         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 542
 543         if (direction == DMA_TO_DEVICE) {
 544                 dma_src = dma_addr;
 545                 dma_dst = host->data_pa;
 546         } else {
 547                 dma_src = host->data_pa;
 548                 dma_dst = dma_addr;
 549         }
 550
 551         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 552                         len, flags);
 553         if (!tx) {
 554                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 555                 ret = -EIO;
 556                 goto unmap_dma;
 557         }
 558
 559         tx->callback = dma_complete;
 560         tx->callback_param = host;
 561         cookie = tx->tx_submit(tx);
 562
 563         ret = dma_submit_error(cookie);
 564         if (ret) {
 565                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 566                 goto unmap_dma;
 567         }
 568
 569         dma_async_issue_pending(chan);
 570
 571         time_left =
 572         wait_for_completion_timeout(&host->dma_access_complete,
 573                                 msecs_to_jiffies(3000));
 574         if (time_left == 0) {
 575                 dmaengine_terminate_all(chan);
 576                 dev_err(host->dev, "wait_for_completion_timeout\n");
 577                 ret = -ETIMEDOUT;
 578                 goto unmap_dma;
 579         }
 580
 581         ret = 0;
 582
 583 unmap_dma:
 584         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 585
 586         return ret;
 587 }
 588
 589 /*
 590  * fsmc_write_buf - write buffer to chip
 591  * @mtd:        MTD device structure
 592  * @buf:        data buffer
 593  * @len:        number of bytes to write
 594  */
 595 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 596 {
 597         int i;
 598         struct nand_chip *chip = mtd_to_nand(mtd);
 599
 600         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 601                         IS_ALIGNED(len, sizeof(uint32_t))) {
 602                 uint32_t *p = (uint32_t *)buf;
 603                 len = len >> 2;
 604                 for (i = 0; i < len; i++)
 605                         writel_relaxed(p[i], chip->IO_ADDR_W);
 606         } else {
 607                 for (i = 0; i < len; i++)
 608                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 609         }
 610 }
 611
 612 /*
 613  * fsmc_read_buf - read chip data into buffer
 614  * @mtd:        MTD device structure
 615  * @buf:        buffer to store date
 616  * @len:        number of bytes to read
 617  */
 618 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 619 {
 620         int i;
 621         struct nand_chip *chip = mtd_to_nand(mtd);
 622
 623         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 624                         IS_ALIGNED(len, sizeof(uint32_t))) {
 625                 uint32_t *p = (uint32_t *)buf;
 626                 len = len >> 2;
 627                 for (i = 0; i < len; i++)
 628                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 629         } else {
 630                 for (i = 0; i < len; i++)
 631                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 632         }
 633 }
 634
 635 /*
 636  * fsmc_read_buf_dma - read chip data into buffer
 637  * @mtd:        MTD device structure
 638  * @buf:        buffer to store date
 639  * @len:        number of bytes to read
 640  */
 641 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 642 {
 643         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 644
 645         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 646 }
 647
 648 /*
 649  * fsmc_write_buf_dma - write buffer to chip
 650  * @mtd:        MTD device structure
 651  * @buf:        data buffer
 652  * @len:        number of bytes to write
 653  */
 654 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 655                 int len)
 656 {
 657         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 658
 659         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 660 }
 661
 662 /*
 663  * fsmc_read_page_hwecc
 664  * @mtd:        mtd info structure
 665  * @chip:       nand chip info structure
 666  * @buf:        buffer to store read data
 667  * @oob_required:       caller expects OOB data read to chip->oob_poi
 668  * @page:       page number to read
 669  *
 670  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 671  * performed in a strict sequence as follows:
 672  * data(512 byte) -> ecc(13 byte)
 673  * After this read, fsmc hardware generates and reports error data bits(up to a
 674  * max of 8 bits)
 675  */
 676 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 677                                  uint8_t *buf, int oob_required, int page)
 678 {
 679         int i, j, s, stat, eccsize = chip->ecc.size;
 680         int eccbytes = chip->ecc.bytes;
 681         int eccsteps = chip->ecc.steps;
 682         uint8_t *p = buf;
 683         uint8_t *ecc_calc = chip->buffers->ecccalc;
 684         uint8_t *ecc_code = chip->buffers->ecccode;
 685         int off, len, group = 0;
 686         /*
 687          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 688          * end up reading 14 bytes (7 words) from oob. The local array is
 689          * to maintain word alignment
 690          */
 691         uint16_t ecc_oob[7];
 692         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 693         unsigned int max_bitflips = 0;
 694
 695         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 696                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 697                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 698                 chip->read_buf(mtd, p, eccsize);
 699
 700                 for (j = 0; j < eccbytes;) {
 701                         struct mtd_oob_region oobregion;
 702                         int ret;
 703
 704                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 705                         if (ret)
 706                                 return ret;
 707
 708                         off = oobregion.offset;
 709                         len = oobregion.length;
 710
 711                         /*
 712                          * length is intentionally kept a higher multiple of 2
 713                          * to read at least 13 bytes even in case of 16 bit NAND
 714                          * devices
 715                          */
 716                         if (chip->options & NAND_BUSWIDTH_16)
 717                                 len = roundup(len, 2);
 718
 719                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 720                         chip->read_buf(mtd, oob + j, len);
 721                         j += len;
 722                 }
 723
 724                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 725                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 726
 727                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 728                 if (stat < 0) {
 729                         mtd->ecc_stats.failed++;
 730                 } else {
 731                         mtd->ecc_stats.corrected += stat;
 732                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 733                 }
 734         }
 735
 736         return max_bitflips;
 737 }
 738
 739 /*
 740  * fsmc_bch8_correct_data
 741  * @mtd:        mtd info structure
 742  * @dat:        buffer of read data
 743  * @read_ecc:   ecc read from device spare area
 744  * @calc_ecc:   ecc calculated from read data
 745  *
 746  * calc_ecc is a 104 bit information containing maximum of 8 error
 747  * offset informations of 13 bits each in 512 bytes of read data.
 748  */
 749 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 750                              uint8_t *read_ecc, uint8_t *calc_ecc)
 751 {
 752         struct nand_chip *chip = mtd_to_nand(mtd);
 753         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 754         void __iomem *regs = host->regs_va;
 755         unsigned int bank = host->bank;
 756         uint32_t err_idx[8];
 757         uint32_t num_err, i;
 758         uint32_t ecc1, ecc2, ecc3, ecc4;
 759
 760         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 761
 762         /* no bit flipping */
 763         if (likely(num_err == 0))
 764                 return 0;
 765
 766         /* too many errors */
 767         if (unlikely(num_err > 8)) {
 768                 /*
 769                  * This is a temporary erase check. A newly erased page read
 770                  * would result in an ecc error because the oob data is also
 771                  * erased to FF and the calculated ecc for an FF data is not
 772                  * FF..FF.
 773                  * This is a workaround to skip performing correction in case
 774                  * data is FF..FF
 775                  *
 776                  * Logic:
 777                  * For every page, each bit written as 0 is counted until these
 778                  * number of bits are greater than 8 (the maximum correction
 779                  * capability of FSMC for each 512 + 13 bytes)
 780                  */
 781
 782                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 783                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 784
 785                 if ((bits_ecc + bits_data) <= 8) {
 786                         if (bits_data)
 787                                 memset(dat, 0xff, chip->ecc.size);
 788                         return bits_data;
 789                 }
 790
 791                 return -EBADMSG;
 792         }
 793
 794         /*
 795          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 796          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 797          *
 798          * calc_ecc is a 104 bit information containing maximum of 8 error
 799          * offset informations of 13 bits each. calc_ecc is copied into a
 800          * uint64_t array and error offset indexes are populated in err_idx
 801          * array
 802          */
 803         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 804         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 805         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 806         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 807
 808         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 809         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 810         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 811         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 812         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 813         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 814         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 815         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 816
 817         i = 0;
 818         while (num_err--) {
 819                 change_bit(0, (unsigned long *)&err_idx[i]);
 820                 change_bit(1, (unsigned long *)&err_idx[i]);
 821
 822                 if (err_idx[i] < chip->ecc.size * 8) {
 823                         change_bit(err_idx[i], (unsigned long *)dat);
 824                         i++;
 825                 }
 826         }
 827         return i;
 828 }
 829
 830 static bool filter(struct dma_chan *chan, void *slave)
 831 {
 832         chan->private = slave;
 833         return true;
 834 }
 835
 836 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 837                                      struct device_node *np)
 838 {
 839         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 840         u32 val;
 841         int ret;
 842
 843         pdata->options = 0;
 844
 845         if (!of_property_read_u32(np, "bank-width", &val)) {
 846                 if (val == 2) {
 847                         pdata->options |= NAND_BUSWIDTH_16;
 848                 } else if (val != 1) {
 849                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 850                         return -EINVAL;
 851                 }
 852         }
 853
 854         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 855                 pdata->options |= NAND_SKIP_BBTSCAN;
 856
 857         pdata->nand_timings = devm_kzalloc(&pdev->dev,
 858                                 sizeof(*pdata->nand_timings), GFP_KERNEL);
 859         if (!pdata->nand_timings)
 860                 return -ENOMEM;
 861         ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
 862                                                 sizeof(*pdata->nand_timings));
 863         if (ret) {
 864                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 865                 pdata->nand_timings = NULL;
 866         }
 867
 868         /* Set default NAND bank to 0 */
 869         pdata->bank = 0;
 870         if (!of_property_read_u32(np, "bank", &val)) {
 871                 if (val > 3) {
 872                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 873                         return -EINVAL;
 874                 }
 875                 pdata->bank = val;
 876         }
 877         return 0;
 878 }
 879
 880 /*
 881  * fsmc_nand_probe - Probe function
 882  * @pdev:       platform device structure
 883  */
 884 static int __init fsmc_nand_probe(struct platform_device *pdev)
 885 {
 886         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 887         struct device_node __maybe_unused *np = pdev->dev.of_node;
 888         struct fsmc_nand_data *host;
 889         struct mtd_info *mtd;
 890         struct nand_chip *nand;
 891         struct resource *res;
 892         dma_cap_mask_t mask;
 893         int ret = 0;
 894         u32 pid;
 895         int i;
 896
 897         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 898         if (!pdata)
 899                 return -ENOMEM;
 900
 901         pdev->dev.platform_data = pdata;
 902         ret = fsmc_nand_probe_config_dt(pdev, np);
 903         if (ret) {
 904                 dev_err(&pdev->dev, "no platform data\n");
 905                 return -ENODEV;
 906         }
 907
 908         /* Allocate memory for the device structure (and zero it) */
 909         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 910         if (!host)
 911                 return -ENOMEM;
 912
 913         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 914         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 915         if (IS_ERR(host->data_va))
 916                 return PTR_ERR(host->data_va);
 917
 918         host->data_pa = (dma_addr_t)res->start;
 919
 920         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 921         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 922         if (IS_ERR(host->addr_va))
 923                 return PTR_ERR(host->addr_va);
 924
 925         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 926         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 927         if (IS_ERR(host->cmd_va))
 928                 return PTR_ERR(host->cmd_va);
 929
 930         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 931         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 932         if (IS_ERR(host->regs_va))
 933                 return PTR_ERR(host->regs_va);
 934
 935         host->clk = clk_get(&pdev->dev, NULL);
 936         if (IS_ERR(host->clk)) {
 937                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 938                 return PTR_ERR(host->clk);
 939         }
 940
 941         ret = clk_prepare_enable(host->clk);
 942         if (ret)
 943                 goto err_clk_prepare_enable;
 944
 945         /*
 946          * This device ID is actually a common AMBA ID as used on the
 947          * AMBA PrimeCell bus. However it is not a PrimeCell.
 948          */
 949         for (pid = 0, i = 0; i < 4; i++)
 950                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 951         host->pid = pid;
 952         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 953                  "revision %02x, config %02x\n",
 954                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 955                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 956
 957         host->bank = pdata->bank;
 958         host->partitions = pdata->partitions;
 959         host->nr_partitions = pdata->nr_partitions;
 960         host->dev = &pdev->dev;
 961         host->dev_timings = pdata->nand_timings;
 962         host->mode = pdata->mode;
 963
 964         if (host->mode == USE_DMA_ACCESS)
 965                 init_completion(&host->dma_access_complete);
 966
 967         /* Link all private pointers */
 968         mtd = nand_to_mtd(&host->nand);
 969         nand = &host->nand;
 970         nand_set_controller_data(nand, host);
 971         nand_set_flash_node(nand, np);
 972
 973         mtd->dev.parent = &pdev->dev;
 974         nand->IO_ADDR_R = host->data_va;
 975         nand->IO_ADDR_W = host->data_va;
 976         nand->cmd_ctrl = fsmc_cmd_ctrl;
 977         nand->chip_delay = 30;
 978
 979         /*
 980          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 981          * can overwrite this value if the DT provides a different value.
 982          */
 983         nand->ecc.mode = NAND_ECC_HW;
 984         nand->ecc.hwctl = fsmc_enable_hwecc;
 985         nand->ecc.size = 512;
 986         nand->options = pdata->options;
 987         nand->select_chip = fsmc_select_chip;
 988         nand->badblockbits = 7;
 989         nand_set_flash_node(nand, np);
 990
 991         switch (host->mode) {
 992         case USE_DMA_ACCESS:
 993                 dma_cap_zero(mask);
 994                 dma_cap_set(DMA_MEMCPY, mask);
 995                 host->read_dma_chan = dma_request_channel(mask, filter,
 996                                 pdata->read_dma_priv);
 997                 if (!host->read_dma_chan) {
 998                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
 999                         goto err_req_read_chnl;
1000                 }
1001                 host->write_dma_chan = dma_request_channel(mask, filter,
1002                                 pdata->write_dma_priv);
1003                 if (!host->write_dma_chan) {
1004                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1005                         goto err_req_write_chnl;
1006                 }
1007                 nand->read_buf = fsmc_read_buf_dma;
1008                 nand->write_buf = fsmc_write_buf_dma;
1009                 break;
1010
1011         default:
1012         case USE_WORD_ACCESS:
1013                 nand->read_buf = fsmc_read_buf;
1014                 nand->write_buf = fsmc_write_buf;
1015                 break;
1016         }
1017
1018         fsmc_nand_setup(host->regs_va, host->bank,
1019                         nand->options & NAND_BUSWIDTH_16,
1020                         host->dev_timings);
1021
1022         if (AMBA_REV_BITS(host->pid) >= 8) {
1023                 nand->ecc.read_page = fsmc_read_page_hwecc;
1024                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1025                 nand->ecc.correct = fsmc_bch8_correct_data;
1026                 nand->ecc.bytes = 13;
1027                 nand->ecc.strength = 8;
1028         }
1029
1030         /*
1031          * Scan to find existence of the device
1032          */
1033         ret = nand_scan_ident(mtd, 1, NULL);
1034         if (ret) {
1035                 dev_err(&pdev->dev, "No NAND Device found!\n");
1036                 goto err_scan_ident;
1037         }
1038
1039         if (AMBA_REV_BITS(host->pid) >= 8) {
1040                 switch (mtd->oobsize) {
1041                 case 16:
1042                 case 64:
1043                 case 128:
1044                 case 224:
1045                 case 256:
1046                         break;
1047                 default:
1048                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1049                                  mtd->oobsize);
1050                         ret = -EINVAL;
1051                         goto err_probe;
1052                 }
1053
1054                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1055         } else {
1056                 switch (nand->ecc.mode) {
1057                 case NAND_ECC_HW:
1058                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1059                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1060                         nand->ecc.correct = nand_correct_data;
1061                         nand->ecc.bytes = 3;
1062                         nand->ecc.strength = 1;
1063                         break;
1064
1065                 case NAND_ECC_SOFT:
1066                         if (nand->ecc.algo == NAND_ECC_BCH) {
1067                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1068                                 break;
1069                         }
1070
1071                 default:
1072                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1073                         goto err_probe;
1074                 }
1075
1076                 /*
1077                  * Don't set layout for BCH4 SW ECC. This will be
1078                  * generated later in nand_bch_init() later.
1079                  */
1080                 if (nand->ecc.mode == NAND_ECC_HW) {
1081                         switch (mtd->oobsize) {
1082                         case 16:
1083                         case 64:
1084                         case 128:
1085                                 mtd_set_ooblayout(mtd,
1086                                                   &fsmc_ecc1_ooblayout_ops);
1087                                 break;
1088                         default:
1089                                 dev_warn(&pdev->dev,
1090                                          "No oob scheme defined for oobsize %d\n",
1091                                          mtd->oobsize);
1092                                 ret = -EINVAL;
1093                                 goto err_probe;
1094                         }
1095                 }
1096         }
1097
1098         /* Second stage of scan to fill MTD data-structures */
1099         ret = nand_scan_tail(mtd);
1100         if (ret)
1101                 goto err_probe;
1102
1103         /*
1104          * The partition information can is accessed by (in the same precedence)
1105          *
1106          * command line through Bootloader,
1107          * platform data,
1108          * default partition information present in driver.
1109          */
1110         /*
1111          * Check for partition info passed
1112          */
1113         mtd->name = "nand";
1114         ret = mtd_device_register(mtd, host->partitions, host->nr_partitions);
1115         if (ret)
1116                 goto err_probe;
1117
1118         platform_set_drvdata(pdev, host);
1119         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1120         return 0;
1121
1122 err_probe:
1123 err_scan_ident:
1124         if (host->mode == USE_DMA_ACCESS)
1125                 dma_release_channel(host->write_dma_chan);
1126 err_req_write_chnl:
1127         if (host->mode == USE_DMA_ACCESS)
1128                 dma_release_channel(host->read_dma_chan);
1129 err_req_read_chnl:
1130         clk_disable_unprepare(host->clk);
1131 err_clk_prepare_enable:
1132         clk_put(host->clk);
1133         return ret;
1134 }
1135
1136 /*
1137  * Clean up routine
1138  */
1139 static int fsmc_nand_remove(struct platform_device *pdev)
1140 {
1141         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1142
1143         if (host) {
1144                 nand_release(nand_to_mtd(&host->nand));
1145
1146                 if (host->mode == USE_DMA_ACCESS) {
1147                         dma_release_channel(host->write_dma_chan);
1148                         dma_release_channel(host->read_dma_chan);
1149                 }
1150                 clk_disable_unprepare(host->clk);
1151                 clk_put(host->clk);
1152         }
1153
1154         return 0;
1155 }
1156
1157 #ifdef CONFIG_PM_SLEEP
1158 static int fsmc_nand_suspend(struct device *dev)
1159 {
1160         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1161         if (host)
1162                 clk_disable_unprepare(host->clk);
1163         return 0;
1164 }
1165
1166 static int fsmc_nand_resume(struct device *dev)
1167 {
1168         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1169         if (host) {
1170                 clk_prepare_enable(host->clk);
1171                 fsmc_nand_setup(host->regs_va, host->bank,
1172                                 host->nand.options & NAND_BUSWIDTH_16,
1173                                 host->dev_timings);
1174         }
1175         return 0;
1176 }
1177 #endif
1178
1179 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1180
1181 #ifdef CONFIG_OF
1182 static const struct of_device_id fsmc_nand_id_table[] = {
1183         { .compatible = "st,spear600-fsmc-nand" },
1184         { .compatible = "stericsson,fsmc-nand" },
1185         {}
1186 };
1187 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1188 #endif
1189
1190 static struct platform_driver fsmc_nand_driver = {
1191         .remove = fsmc_nand_remove,
1192         .driver = {
1193                 .name = "fsmc-nand",
1194                 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1195                 .pm = &fsmc_nand_pm_ops,
1196         },
1197 };
1198
1199 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1200
1201 MODULE_LICENSE("GPL");
1202 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1203 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");