drivers/mtd/nand/gpmi-nand/gpmi-lib.c

   1 /*
   2  * Freescale GPMI NAND Flash Driver
   3  *
   4  * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2008 Embedded Alley Solutions, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21 #include <linux/delay.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24
  25 #include "gpmi-nand.h"
  26 #include "gpmi-regs.h"
  27 #include "bch-regs.h"
  28
  29 static struct timing_threshod timing_default_threshold = {
  30         .max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
  31                                                 BP_GPMI_TIMING0_DATA_SETUP),
  32         .internal_data_setup_in_ns   = 0,
  33         .max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
  34                                                 BP_GPMI_CTRL1_RDN_DELAY),
  35         .max_dll_clock_period_in_ns  = 32,
  36         .max_dll_delay_in_ns         = 16,
  37 };
  38
  39 #define MXS_SET_ADDR            0x4
  40 #define MXS_CLR_ADDR            0x8
  41 /*
  42  * Clear the bit and poll it cleared.  This is usually called with
  43  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
  44  * (bit 30).
  45  */
  46 static int clear_poll_bit(void __iomem *addr, u32 mask)
  47 {
  48         int timeout = 0x400;
  49
  50         /* clear the bit */
  51         writel(mask, addr + MXS_CLR_ADDR);
  52
  53         /*
  54          * SFTRST needs 3 GPMI clocks to settle, the reference manual
  55          * recommends to wait 1us.
  56          */
  57         udelay(1);
  58
  59         /* poll the bit becoming clear */
  60         while ((readl(addr) & mask) && --timeout)
  61                 /* nothing */;
  62
  63         return !timeout;
  64 }
  65
  66 #define MODULE_CLKGATE          (1 << 30)
  67 #define MODULE_SFTRST           (1 << 31)
  68 /*
  69  * The current mxs_reset_block() will do two things:
  70  *  [1] enable the module.
  71  *  [2] reset the module.
  72  *
  73  * In most of the cases, it's ok.
  74  * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
  75  * If you try to soft reset the BCH block, it becomes unusable until
  76  * the next hard reset. This case occurs in the NAND boot mode. When the board
  77  * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
  78  * So If the driver tries to reset the BCH again, the BCH will not work anymore.
  79  * You will see a DMA timeout in this case. The bug has been fixed
  80  * in the following chips, such as MX28.
  81  *
  82  * To avoid this bug, just add a new parameter `just_enable` for
  83  * the mxs_reset_block(), and rewrite it here.
  84  */
  85 static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
  86 {
  87         int ret;
  88         int timeout = 0x400;
  89
  90         /* clear and poll SFTRST */
  91         ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
  92         if (unlikely(ret))
  93                 goto error;
  94
  95         /* clear CLKGATE */
  96         writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
  97
  98         if (!just_enable) {
  99                 /* set SFTRST to reset the block */
 100                 writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
 101                 udelay(1);
 102
 103                 /* poll CLKGATE becoming set */
 104                 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
 105                         /* nothing */;
 106                 if (unlikely(!timeout))
 107                         goto error;
 108         }
 109
 110         /* clear and poll SFTRST */
 111         ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
 112         if (unlikely(ret))
 113                 goto error;
 114
 115         /* clear and poll CLKGATE */
 116         ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
 117         if (unlikely(ret))
 118                 goto error;
 119
 120         return 0;
 121
 122 error:
 123         pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
 124         return -ETIMEDOUT;
 125 }
 126
 127 static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
 128 {
 129         struct clk *clk;
 130         int ret;
 131         int i;
 132
 133         for (i = 0; i < GPMI_CLK_MAX; i++) {
 134                 clk = this->resources.clock[i];
 135                 if (!clk)
 136                         break;
 137
 138                 if (v) {
 139                         ret = clk_prepare_enable(clk);
 140                         if (ret)
 141                                 goto err_clk;
 142                 } else {
 143                         clk_disable_unprepare(clk);
 144                 }
 145         }
 146         return 0;
 147
 148 err_clk:
 149         for (; i > 0; i--)
 150                 clk_disable_unprepare(this->resources.clock[i - 1]);
 151         return ret;
 152 }
 153
 154 #define gpmi_enable_clk(x) __gpmi_enable_clk(x, true)
 155 #define gpmi_disable_clk(x) __gpmi_enable_clk(x, false)
 156
 157 int gpmi_init(struct gpmi_nand_data *this)
 158 {
 159         struct resources *r = &this->resources;
 160         int ret;
 161
 162         ret = gpmi_enable_clk(this);
 163         if (ret)
 164                 goto err_out;
 165         ret = gpmi_reset_block(r->gpmi_regs, false);
 166         if (ret)
 167                 goto err_out;
 168
 169         /*
 170          * Reset BCH here, too. We got failures otherwise :(
 171          * See later BCH reset for explanation of MX23 handling
 172          */
 173         ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
 174         if (ret)
 175                 goto err_out;
 176
 177
 178         /* Choose NAND mode. */
 179         writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
 180
 181         /* Set the IRQ polarity. */
 182         writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
 183                                 r->gpmi_regs + HW_GPMI_CTRL1_SET);
 184
 185         /* Disable Write-Protection. */
 186         writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
 187
 188         /* Select BCH ECC. */
 189         writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
 190
 191         /*
 192          * Decouple the chip select from dma channel. We use dma0 for all
 193          * the chips.
 194          */
 195         writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
 196
 197         gpmi_disable_clk(this);
 198         return 0;
 199 err_out:
 200         return ret;
 201 }
 202
 203 /* This function is very useful. It is called only when the bug occur. */
 204 void gpmi_dump_info(struct gpmi_nand_data *this)
 205 {
 206         struct resources *r = &this->resources;
 207         struct bch_geometry *geo = &this->bch_geometry;
 208         u32 reg;
 209         int i;
 210
 211         dev_err(this->dev, "Show GPMI registers :\n");
 212         for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
 213                 reg = readl(r->gpmi_regs + i * 0x10);
 214                 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
 215         }
 216
 217         /* start to print out the BCH info */
 218         dev_err(this->dev, "Show BCH registers :\n");
 219         for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) {
 220                 reg = readl(r->bch_regs + i * 0x10);
 221                 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
 222         }
 223         dev_err(this->dev, "BCH Geometry :\n"
 224                 "GF length              : %u\n"
 225                 "ECC Strength           : %u\n"
 226                 "Page Size in Bytes     : %u\n"
 227                 "Metadata Size in Bytes : %u\n"
 228                 "ECC Chunk Size in Bytes: %u\n"
 229                 "ECC Chunk Count        : %u\n"
 230                 "Payload Size in Bytes  : %u\n"
 231                 "Auxiliary Size in Bytes: %u\n"
 232                 "Auxiliary Status Offset: %u\n"
 233                 "Block Mark Byte Offset : %u\n"
 234                 "Block Mark Bit Offset  : %u\n",
 235                 geo->gf_len,
 236                 geo->ecc_strength,
 237                 geo->page_size,
 238                 geo->metadata_size,
 239                 geo->ecc_chunk_size,
 240                 geo->ecc_chunk_count,
 241                 geo->payload_size,
 242                 geo->auxiliary_size,
 243                 geo->auxiliary_status_offset,
 244                 geo->block_mark_byte_offset,
 245                 geo->block_mark_bit_offset);
 246 }
 247
 248 /* Configures the geometry for BCH.  */
 249 int bch_set_geometry(struct gpmi_nand_data *this)
 250 {
 251         struct resources *r = &this->resources;
 252         struct bch_geometry *bch_geo = &this->bch_geometry;
 253         unsigned int block_count;
 254         unsigned int block_size;
 255         unsigned int metadata_size;
 256         unsigned int ecc_strength;
 257         unsigned int page_size;
 258         unsigned int gf_len;
 259         int ret;
 260
 261         if (common_nfc_set_geometry(this))
 262                 return !0;
 263
 264         block_count   = bch_geo->ecc_chunk_count - 1;
 265         block_size    = bch_geo->ecc_chunk_size;
 266         metadata_size = bch_geo->metadata_size;
 267         ecc_strength  = bch_geo->ecc_strength >> 1;
 268         page_size     = bch_geo->page_size;
 269         gf_len        = bch_geo->gf_len;
 270
 271         ret = gpmi_enable_clk(this);
 272         if (ret)
 273                 goto err_out;
 274
 275         /*
 276         * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
 277         * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
 278         * On the other hand, the MX28 needs the reset, because one case has been
 279         * seen where the BCH produced ECC errors constantly after 10000
 280         * consecutive reboots. The latter case has not been seen on the MX23
 281         * yet, still we don't know if it could happen there as well.
 282         */
 283         ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
 284         if (ret)
 285                 goto err_out;
 286
 287         /* Configure layout 0. */
 288         writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
 289                         | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
 290                         | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
 291                         | BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
 292                         | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
 293                         r->bch_regs + HW_BCH_FLASH0LAYOUT0);
 294
 295         writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
 296                         | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
 297                         | BF_BCH_FLASH0LAYOUT1_GF(gf_len, this)
 298                         | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
 299                         r->bch_regs + HW_BCH_FLASH0LAYOUT1);
 300
 301         /* Set *all* chip selects to use layout 0. */
 302         writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
 303
 304         /* Enable interrupts. */
 305         writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
 306                                 r->bch_regs + HW_BCH_CTRL_SET);
 307
 308         gpmi_disable_clk(this);
 309         return 0;
 310 err_out:
 311         return ret;
 312 }
 313
 314 /* Converts time in nanoseconds to cycles. */
 315 static unsigned int ns_to_cycles(unsigned int time,
 316                         unsigned int period, unsigned int min)
 317 {
 318         unsigned int k;
 319
 320         k = (time + period - 1) / period;
 321         return max(k, min);
 322 }
 323
 324 #define DEF_MIN_PROP_DELAY      5
 325 #define DEF_MAX_PROP_DELAY      9
 326 /* Apply timing to current hardware conditions. */
 327 static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
 328                                         struct gpmi_nfc_hardware_timing *hw)
 329 {
 330         struct timing_threshod *nfc = &timing_default_threshold;
 331         struct resources *r = &this->resources;
 332         struct nand_chip *nand = &this->nand;
 333         struct nand_timing target = this->timing;
 334         bool improved_timing_is_available;
 335         unsigned long clock_frequency_in_hz;
 336         unsigned int clock_period_in_ns;
 337         bool dll_use_half_periods;
 338         unsigned int dll_delay_shift;
 339         unsigned int max_sample_delay_in_ns;
 340         unsigned int address_setup_in_cycles;
 341         unsigned int data_setup_in_ns;
 342         unsigned int data_setup_in_cycles;
 343         unsigned int data_hold_in_cycles;
 344         int ideal_sample_delay_in_ns;
 345         unsigned int sample_delay_factor;
 346         int tEYE;
 347         unsigned int min_prop_delay_in_ns = DEF_MIN_PROP_DELAY;
 348         unsigned int max_prop_delay_in_ns = DEF_MAX_PROP_DELAY;
 349
 350         /*
 351          * If there are multiple chips, we need to relax the timings to allow
 352          * for signal distortion due to higher capacitance.
 353          */
 354         if (nand->numchips > 2) {
 355                 target.data_setup_in_ns    += 10;
 356                 target.data_hold_in_ns     += 10;
 357                 target.address_setup_in_ns += 10;
 358         } else if (nand->numchips > 1) {
 359                 target.data_setup_in_ns    += 5;
 360                 target.data_hold_in_ns     += 5;
 361                 target.address_setup_in_ns += 5;
 362         }
 363
 364         /* Check if improved timing information is available. */
 365         improved_timing_is_available =
 366                 (target.tREA_in_ns  >= 0) &&
 367                 (target.tRLOH_in_ns >= 0) &&
 368                 (target.tRHOH_in_ns >= 0);
 369
 370         /* Inspect the clock. */
 371         nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
 372         clock_frequency_in_hz = nfc->clock_frequency_in_hz;
 373         clock_period_in_ns    = NSEC_PER_SEC / clock_frequency_in_hz;
 374
 375         /*
 376          * The NFC quantizes setup and hold parameters in terms of clock cycles.
 377          * Here, we quantize the setup and hold timing parameters to the
 378          * next-highest clock period to make sure we apply at least the
 379          * specified times.
 380          *
 381          * For data setup and data hold, the hardware interprets a value of zero
 382          * as the largest possible delay. This is not what's intended by a zero
 383          * in the input parameter, so we impose a minimum of one cycle.
 384          */
 385         data_setup_in_cycles    = ns_to_cycles(target.data_setup_in_ns,
 386                                                         clock_period_in_ns, 1);
 387         data_hold_in_cycles     = ns_to_cycles(target.data_hold_in_ns,
 388                                                         clock_period_in_ns, 1);
 389         address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
 390                                                         clock_period_in_ns, 0);
 391
 392         /*
 393          * The clock's period affects the sample delay in a number of ways:
 394          *
 395          * (1) The NFC HAL tells us the maximum clock period the sample delay
 396          *     DLL can tolerate. If the clock period is greater than half that
 397          *     maximum, we must configure the DLL to be driven by half periods.
 398          *
 399          * (2) We need to convert from an ideal sample delay, in ns, to a
 400          *     "sample delay factor," which the NFC uses. This factor depends on
 401          *     whether we're driving the DLL with full or half periods.
 402          *     Paraphrasing the reference manual:
 403          *
 404          *         AD = SDF x 0.125 x RP
 405          *
 406          * where:
 407          *
 408          *     AD   is the applied delay, in ns.
 409          *     SDF  is the sample delay factor, which is dimensionless.
 410          *     RP   is the reference period, in ns, which is a full clock period
 411          *          if the DLL is being driven by full periods, or half that if
 412          *          the DLL is being driven by half periods.
 413          *
 414          * Let's re-arrange this in a way that's more useful to us:
 415          *
 416          *                        8
 417          *         SDF  =  AD x ----
 418          *                       RP
 419          *
 420          * The reference period is either the clock period or half that, so this
 421          * is:
 422          *
 423          *                        8       AD x DDF
 424          *         SDF  =  AD x -----  =  --------
 425          *                      f x P        P
 426          *
 427          * where:
 428          *
 429          *       f  is 1 or 1/2, depending on how we're driving the DLL.
 430          *       P  is the clock period.
 431          *     DDF  is the DLL Delay Factor, a dimensionless value that
 432          *          incorporates all the constants in the conversion.
 433          *
 434          * DDF will be either 8 or 16, both of which are powers of two. We can
 435          * reduce the cost of this conversion by using bit shifts instead of
 436          * multiplication or division. Thus:
 437          *
 438          *                 AD << DDS
 439          *         SDF  =  ---------
 440          *                     P
 441          *
 442          *     or
 443          *
 444          *         AD  =  (SDF >> DDS) x P
 445          *
 446          * where:
 447          *
 448          *     DDS  is the DLL Delay Shift, the logarithm to base 2 of the DDF.
 449          */
 450         if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
 451                 dll_use_half_periods = true;
 452                 dll_delay_shift      = 3 + 1;
 453         } else {
 454                 dll_use_half_periods = false;
 455                 dll_delay_shift      = 3;
 456         }
 457
 458         /*
 459          * Compute the maximum sample delay the NFC allows, under current
 460          * conditions. If the clock is running too slowly, no sample delay is
 461          * possible.
 462          */
 463         if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
 464                 max_sample_delay_in_ns = 0;
 465         else {
 466                 /*
 467                  * Compute the delay implied by the largest sample delay factor
 468                  * the NFC allows.
 469                  */
 470                 max_sample_delay_in_ns =
 471                         (nfc->max_sample_delay_factor * clock_period_in_ns) >>
 472                                                                 dll_delay_shift;
 473
 474                 /*
 475                  * Check if the implied sample delay larger than the NFC
 476                  * actually allows.
 477                  */
 478                 if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
 479                         max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
 480         }
 481
 482         /*
 483          * Check if improved timing information is available. If not, we have to
 484          * use a less-sophisticated algorithm.
 485          */
 486         if (!improved_timing_is_available) {
 487                 /*
 488                  * Fold the read setup time required by the NFC into the ideal
 489                  * sample delay.
 490                  */
 491                 ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
 492                                                 nfc->internal_data_setup_in_ns;
 493
 494                 /*
 495                  * The ideal sample delay may be greater than the maximum
 496                  * allowed by the NFC. If so, we can trade off sample delay time
 497                  * for more data setup time.
 498                  *
 499                  * In each iteration of the following loop, we add a cycle to
 500                  * the data setup time and subtract a corresponding amount from
 501                  * the sample delay until we've satisified the constraints or
 502                  * can't do any better.
 503                  */
 504                 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
 505                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 506
 507                         data_setup_in_cycles++;
 508                         ideal_sample_delay_in_ns -= clock_period_in_ns;
 509
 510                         if (ideal_sample_delay_in_ns < 0)
 511                                 ideal_sample_delay_in_ns = 0;
 512
 513                 }
 514
 515                 /*
 516                  * Compute the sample delay factor that corresponds most closely
 517                  * to the ideal sample delay. If the result is too large for the
 518                  * NFC, use the maximum value.
 519                  *
 520                  * Notice that we use the ns_to_cycles function to compute the
 521                  * sample delay factor. We do this because the form of the
 522                  * computation is the same as that for calculating cycles.
 523                  */
 524                 sample_delay_factor =
 525                         ns_to_cycles(
 526                                 ideal_sample_delay_in_ns << dll_delay_shift,
 527                                                         clock_period_in_ns, 0);
 528
 529                 if (sample_delay_factor > nfc->max_sample_delay_factor)
 530                         sample_delay_factor = nfc->max_sample_delay_factor;
 531
 532                 /* Skip to the part where we return our results. */
 533                 goto return_results;
 534         }
 535
 536         /*
 537          * If control arrives here, we have more detailed timing information,
 538          * so we can use a better algorithm.
 539          */
 540
 541         /*
 542          * Fold the read setup time required by the NFC into the maximum
 543          * propagation delay.
 544          */
 545         max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
 546
 547         /*
 548          * Earlier, we computed the number of clock cycles required to satisfy
 549          * the data setup time. Now, we need to know the actual nanoseconds.
 550          */
 551         data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
 552
 553         /*
 554          * Compute tEYE, the width of the data eye when reading from the NAND
 555          * Flash. The eye width is fundamentally determined by the data setup
 556          * time, perturbed by propagation delays and some characteristics of the
 557          * NAND Flash device.
 558          *
 559          * start of the eye = max_prop_delay + tREA
 560          * end of the eye   = min_prop_delay + tRHOH + data_setup
 561          */
 562         tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
 563                                                         (int)data_setup_in_ns;
 564
 565         tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
 566
 567         /*
 568          * The eye must be open. If it's not, we can try to open it by
 569          * increasing its main forcer, the data setup time.
 570          *
 571          * In each iteration of the following loop, we increase the data setup
 572          * time by a single clock cycle. We do this until either the eye is
 573          * open or we run into NFC limits.
 574          */
 575         while ((tEYE <= 0) &&
 576                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 577                 /* Give a cycle to data setup. */
 578                 data_setup_in_cycles++;
 579                 /* Synchronize the data setup time with the cycles. */
 580                 data_setup_in_ns += clock_period_in_ns;
 581                 /* Adjust tEYE accordingly. */
 582                 tEYE += clock_period_in_ns;
 583         }
 584
 585         /*
 586          * When control arrives here, the eye is open. The ideal time to sample
 587          * the data is in the center of the eye:
 588          *
 589          *     end of the eye + start of the eye
 590          *     ---------------------------------  -  data_setup
 591          *                    2
 592          *
 593          * After some algebra, this simplifies to the code immediately below.
 594          */
 595         ideal_sample_delay_in_ns =
 596                 ((int)max_prop_delay_in_ns +
 597                         (int)target.tREA_in_ns +
 598                                 (int)min_prop_delay_in_ns +
 599                                         (int)target.tRHOH_in_ns -
 600                                                 (int)data_setup_in_ns) >> 1;
 601
 602         /*
 603          * The following figure illustrates some aspects of a NAND Flash read:
 604          *
 605          *
 606          *           __                   _____________________________________
 607          * RDN         \_________________/
 608          *
 609          *                                         <---- tEYE ----->
 610          *                                        /-----------------\
 611          * Read Data ----------------------------<                   >---------
 612          *                                        \-----------------/
 613          *             ^                 ^                 ^              ^
 614          *             |                 |                 |              |
 615          *             |<--Data Setup -->|<--Delay Time -->|              |
 616          *             |                 |                 |              |
 617          *             |                 |                                |
 618          *             |                 |<--   Quantized Delay Time   -->|
 619          *             |                 |                                |
 620          *
 621          *
 622          * We have some issues we must now address:
 623          *
 624          * (1) The *ideal* sample delay time must not be negative. If it is, we
 625          *     jam it to zero.
 626          *
 627          * (2) The *ideal* sample delay time must not be greater than that
 628          *     allowed by the NFC. If it is, we can increase the data setup
 629          *     time, which will reduce the delay between the end of the data
 630          *     setup and the center of the eye. It will also make the eye
 631          *     larger, which might help with the next issue...
 632          *
 633          * (3) The *quantized* sample delay time must not fall either before the
 634          *     eye opens or after it closes (the latter is the problem
 635          *     illustrated in the above figure).
 636          */
 637
 638         /* Jam a negative ideal sample delay to zero. */
 639         if (ideal_sample_delay_in_ns < 0)
 640                 ideal_sample_delay_in_ns = 0;
 641
 642         /*
 643          * Extend the data setup as needed to reduce the ideal sample delay
 644          * below the maximum permitted by the NFC.
 645          */
 646         while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
 647                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 648
 649                 /* Give a cycle to data setup. */
 650                 data_setup_in_cycles++;
 651                 /* Synchronize the data setup time with the cycles. */
 652                 data_setup_in_ns += clock_period_in_ns;
 653                 /* Adjust tEYE accordingly. */
 654                 tEYE += clock_period_in_ns;
 655
 656                 /*
 657                  * Decrease the ideal sample delay by one half cycle, to keep it
 658                  * in the middle of the eye.
 659                  */
 660                 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
 661
 662                 /* Jam a negative ideal sample delay to zero. */
 663                 if (ideal_sample_delay_in_ns < 0)
 664                         ideal_sample_delay_in_ns = 0;
 665         }
 666
 667         /*
 668          * Compute the sample delay factor that corresponds to the ideal sample
 669          * delay. If the result is too large, then use the maximum allowed
 670          * value.
 671          *
 672          * Notice that we use the ns_to_cycles function to compute the sample
 673          * delay factor. We do this because the form of the computation is the
 674          * same as that for calculating cycles.
 675          */
 676         sample_delay_factor =
 677                 ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
 678                                                         clock_period_in_ns, 0);
 679
 680         if (sample_delay_factor > nfc->max_sample_delay_factor)
 681                 sample_delay_factor = nfc->max_sample_delay_factor;
 682
 683         /*
 684          * These macros conveniently encapsulate a computation we'll use to
 685          * continuously evaluate whether or not the data sample delay is inside
 686          * the eye.
 687          */
 688         #define IDEAL_DELAY  ((int) ideal_sample_delay_in_ns)
 689
 690         #define QUANTIZED_DELAY  \
 691                 ((int) ((sample_delay_factor * clock_period_in_ns) >> \
 692                                                         dll_delay_shift))
 693
 694         #define DELAY_ERROR  (abs(QUANTIZED_DELAY - IDEAL_DELAY))
 695
 696         #define SAMPLE_IS_NOT_WITHIN_THE_EYE  (DELAY_ERROR > (tEYE >> 1))
 697
 698         /*
 699          * While the quantized sample time falls outside the eye, reduce the
 700          * sample delay or extend the data setup to move the sampling point back
 701          * toward the eye. Do not allow the number of data setup cycles to
 702          * exceed the maximum allowed by the NFC.
 703          */
 704         while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
 705                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 706                 /*
 707                  * If control arrives here, the quantized sample delay falls
 708                  * outside the eye. Check if it's before the eye opens, or after
 709                  * the eye closes.
 710                  */
 711                 if (QUANTIZED_DELAY > IDEAL_DELAY) {
 712                         /*
 713                          * If control arrives here, the quantized sample delay
 714                          * falls after the eye closes. Decrease the quantized
 715                          * delay time and then go back to re-evaluate.
 716                          */
 717                         if (sample_delay_factor != 0)
 718                                 sample_delay_factor--;
 719                         continue;
 720                 }
 721
 722                 /*
 723                  * If control arrives here, the quantized sample delay falls
 724                  * before the eye opens. Shift the sample point by increasing
 725                  * data setup time. This will also make the eye larger.
 726                  */
 727
 728                 /* Give a cycle to data setup. */
 729                 data_setup_in_cycles++;
 730                 /* Synchronize the data setup time with the cycles. */
 731                 data_setup_in_ns += clock_period_in_ns;
 732                 /* Adjust tEYE accordingly. */
 733                 tEYE += clock_period_in_ns;
 734
 735                 /*
 736                  * Decrease the ideal sample delay by one half cycle, to keep it
 737                  * in the middle of the eye.
 738                  */
 739                 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
 740
 741                 /* ...and one less period for the delay time. */
 742                 ideal_sample_delay_in_ns -= clock_period_in_ns;
 743
 744                 /* Jam a negative ideal sample delay to zero. */
 745                 if (ideal_sample_delay_in_ns < 0)
 746                         ideal_sample_delay_in_ns = 0;
 747
 748                 /*
 749                  * We have a new ideal sample delay, so re-compute the quantized
 750                  * delay.
 751                  */
 752                 sample_delay_factor =
 753                         ns_to_cycles(
 754                                 ideal_sample_delay_in_ns << dll_delay_shift,
 755                                                         clock_period_in_ns, 0);
 756
 757                 if (sample_delay_factor > nfc->max_sample_delay_factor)
 758                         sample_delay_factor = nfc->max_sample_delay_factor;
 759         }
 760
 761         /* Control arrives here when we're ready to return our results. */
 762 return_results:
 763         hw->data_setup_in_cycles    = data_setup_in_cycles;
 764         hw->data_hold_in_cycles     = data_hold_in_cycles;
 765         hw->address_setup_in_cycles = address_setup_in_cycles;
 766         hw->use_half_periods        = dll_use_half_periods;
 767         hw->sample_delay_factor     = sample_delay_factor;
 768         hw->device_busy_timeout     = GPMI_DEFAULT_BUSY_TIMEOUT;
 769         hw->wrn_dly_sel             = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
 770
 771         /* Return success. */
 772         return 0;
 773 }
 774
 775 /*
 776  * <1> Firstly, we should know what's the GPMI-clock means.
 777  *     The GPMI-clock is the internal clock in the gpmi nand controller.
 778  *     If you set 100MHz to gpmi nand controller, the GPMI-clock's period
 779  *     is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
 780  *
 781  * <2> Secondly, we should know what's the frequency on the nand chip pins.
 782  *     The frequency on the nand chip pins is derived from the GPMI-clock.
 783  *     We can get it from the following equation:
 784  *
 785  *         F = G / (DS + DH)
 786  *
 787  *         F  : the frequency on the nand chip pins.
 788  *         G  : the GPMI clock, such as 100MHz.
 789  *         DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
 790  *         DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
 791  *
 792  * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
 793  *     the nand EDO(extended Data Out) timing could be applied.
 794  *     The GPMI implements a feedback read strobe to sample the read data.
 795  *     The feedback read strobe can be delayed to support the nand EDO timing
 796  *     where the read strobe may deasserts before the read data is valid, and
 797  *     read data is valid for some time after read strobe.
 798  *
 799  *     The following figure illustrates some aspects of a NAND Flash read:
 800  *
 801  *                   |<---tREA---->|
 802  *                   |             |
 803  *                   |         |   |
 804  *                   |<--tRP-->|   |
 805  *                   |         |   |
 806  *                  __          ___|__________________________________
 807  *     RDN            \________/   |
 808  *                                 |
 809  *                                 /---------\
 810  *     Read Data    --------------<           >---------
 811  *                                 \---------/
 812  *                                |     |
 813  *                                |<-D->|
 814  *     FeedbackRDN  ________             ____________
 815  *                          \___________/
 816  *
 817  *          D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
 818  *
 819  *
 820  * <4> Now, we begin to describe how to compute the right RDN_DELAY.
 821  *
 822  *  4.1) From the aspect of the nand chip pins:
 823  *        Delay = (tREA + C - tRP)               {1}
 824  *
 825  *        tREA : the maximum read access time. From the ONFI nand standards,
 826  *               we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4.
 827  *               Please check it in : www.onfi.org
 828  *        C    : a constant for adjust the delay. default is 4.
 829  *        tRP  : the read pulse width.
 830  *               Specified by the HW_GPMI_TIMING0:DATA_SETUP:
 831  *                    tRP = (GPMI-clock-period) * DATA_SETUP
 832  *
 833  *  4.2) From the aspect of the GPMI nand controller:
 834  *         Delay = RDN_DELAY * 0.125 * RP        {2}
 835  *
 836  *         RP   : the DLL reference period.
 837  *            if (GPMI-clock-period > DLL_THRETHOLD)
 838  *                   RP = GPMI-clock-period / 2;
 839  *            else
 840  *                   RP = GPMI-clock-period;
 841  *
 842  *            Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
 843  *            is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
 844  *            is 16ns, but in mx6q, we use 12ns.
 845  *
 846  *  4.3) since {1} equals {2}, we get:
 847  *
 848  *                    (tREA + 4 - tRP) * 8
 849  *         RDN_DELAY = ---------------------     {3}
 850  *                           RP
 851  *
 852  *  4.4) We only support the fastest asynchronous mode of ONFI nand.
 853  *       For some ONFI nand, the mode 4 is the fastest mode;
 854  *       while for some ONFI nand, the mode 5 is the fastest mode.
 855  *       So we only support the mode 4 and mode 5. It is no need to
 856  *       support other modes.
 857  */
 858 static void gpmi_compute_edo_timing(struct gpmi_nand_data *this,
 859                         struct gpmi_nfc_hardware_timing *hw)
 860 {
 861         struct resources *r = &this->resources;
 862         unsigned long rate = clk_get_rate(r->clock[0]);
 863         int mode = this->timing_mode;
 864         int dll_threshold = 16; /* in ns */
 865         unsigned long delay;
 866         unsigned long clk_period;
 867         int t_rea;
 868         int c = 4;
 869         int t_rp;
 870         int rp;
 871
 872         /*
 873          * [1] for GPMI_HW_GPMI_TIMING0:
 874          *     The async mode requires 40MHz for mode 4, 50MHz for mode 5.
 875          *     The GPMI can support 100MHz at most. So if we want to
 876          *     get the 40MHz or 50MHz, we have to set DS=1, DH=1.
 877          *     Set the ADDRESS_SETUP to 0 in mode 4.
 878          */
 879         hw->data_setup_in_cycles = 1;
 880         hw->data_hold_in_cycles = 1;
 881         hw->address_setup_in_cycles = ((mode == 5) ? 1 : 0);
 882
 883         /* [2] for GPMI_HW_GPMI_TIMING1 */
 884         hw->device_busy_timeout = 0x9000;
 885
 886         /* [3] for GPMI_HW_GPMI_CTRL1 */
 887         hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
 888
 889         if (GPMI_IS_MX6Q(this))
 890                 dll_threshold = 12;
 891
 892         /*
 893          * Enlarge 10 times for the numerator and denominator in {3}.
 894          * This make us to get more accurate result.
 895          */
 896         clk_period = NSEC_PER_SEC / (rate / 10);
 897         dll_threshold *= 10;
 898         t_rea = ((mode == 5) ? 16 : 20) * 10;
 899         c *= 10;
 900
 901         t_rp = clk_period * 1; /* DATA_SETUP is 1 */
 902
 903         if (clk_period > dll_threshold) {
 904                 hw->use_half_periods = 1;
 905                 rp = clk_period / 2;
 906         } else {
 907                 hw->use_half_periods = 0;
 908                 rp = clk_period;
 909         }
 910
 911         /*
 912          * Multiply the numerator with 10, we could do a round off:
 913          *      7.8 round up to 8; 7.4 round down to 7.
 914          */
 915         delay  = (((t_rea + c - t_rp) * 8) * 10) / rp;
 916         delay = (delay + 5) / 10;
 917
 918         hw->sample_delay_factor = delay;
 919 }
 920
 921 static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
 922 {
 923         struct resources  *r = &this->resources;
 924         struct nand_chip *nand = &this->nand;
 925         struct mtd_info  *mtd = &this->mtd;
 926         uint8_t *feature;
 927         unsigned long rate;
 928         int ret;
 929
 930         feature = kzalloc(ONFI_SUBFEATURE_PARAM_LEN, GFP_KERNEL);
 931         if (!feature)
 932                 return -ENOMEM;
 933
 934         nand->select_chip(mtd, 0);
 935
 936         /* [1] send SET FEATURE commond to NAND */
 937         feature[0] = mode;
 938         ret = nand->onfi_set_features(mtd, nand,
 939                                 ONFI_FEATURE_ADDR_TIMING_MODE, feature);
 940         if (ret)
 941                 goto err_out;
 942
 943         /* [2] send GET FEATURE command to double-check the timing mode */
 944         memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN);
 945         ret = nand->onfi_get_features(mtd, nand,
 946                                 ONFI_FEATURE_ADDR_TIMING_MODE, feature);
 947         if (ret || feature[0] != mode)
 948                 goto err_out;
 949
 950         nand->select_chip(mtd, -1);
 951
 952         /* [3] set the main IO clock, 100MHz for mode 5, 80MHz for mode 4. */
 953         rate = (mode == 5) ? 100000000 : 80000000;
 954         clk_set_rate(r->clock[0], rate);
 955
 956         /* Let the gpmi_begin() re-compute the timing again. */
 957         this->flags &= ~GPMI_TIMING_INIT_OK;
 958
 959         this->flags |= GPMI_ASYNC_EDO_ENABLED;
 960         this->timing_mode = mode;
 961         kfree(feature);
 962         dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode);
 963         return 0;
 964
 965 err_out:
 966         nand->select_chip(mtd, -1);
 967         kfree(feature);
 968         dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode);
 969         return -EINVAL;
 970 }
 971
 972 int gpmi_extra_init(struct gpmi_nand_data *this)
 973 {
 974         struct nand_chip *chip = &this->nand;
 975
 976         /* Enable the asynchronous EDO feature. */
 977         if (GPMI_IS_MX6Q(this) && chip->onfi_version) {
 978                 int mode = onfi_get_async_timing_mode(chip);
 979
 980                 /* We only support the timing mode 4 and mode 5. */
 981                 if (mode & ONFI_TIMING_MODE_5)
 982                         mode = 5;
 983                 else if (mode & ONFI_TIMING_MODE_4)
 984                         mode = 4;
 985                 else
 986                         return 0;
 987
 988                 return enable_edo_mode(this, mode);
 989         }
 990         return 0;
 991 }
 992
 993 /* Begin the I/O */
 994 void gpmi_begin(struct gpmi_nand_data *this)
 995 {
 996         struct resources *r = &this->resources;
 997         void __iomem *gpmi_regs = r->gpmi_regs;
 998         unsigned int   clock_period_in_ns;
 999         uint32_t       reg;
1000         unsigned int   dll_wait_time_in_us;
1001         struct gpmi_nfc_hardware_timing  hw;
1002         int ret;
1003
1004         /* Enable the clock. */
1005         ret = gpmi_enable_clk(this);
1006         if (ret) {
1007                 dev_err(this->dev, "We failed in enable the clk\n");
1008                 goto err_out;
1009         }
1010
1011         /* Only initialize the timing once */
1012         if (this->flags & GPMI_TIMING_INIT_OK)
1013                 return;
1014         this->flags |= GPMI_TIMING_INIT_OK;
1015
1016         if (this->flags & GPMI_ASYNC_EDO_ENABLED)
1017                 gpmi_compute_edo_timing(this, &hw);
1018         else
1019                 gpmi_nfc_compute_hardware_timing(this, &hw);
1020
1021         /* [1] Set HW_GPMI_TIMING0 */
1022         reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
1023                 BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
1024                 BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles);
1025
1026         writel(reg, gpmi_regs + HW_GPMI_TIMING0);
1027
1028         /* [2] Set HW_GPMI_TIMING1 */
1029         writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
1030                 gpmi_regs + HW_GPMI_TIMING1);
1031
1032         /* [3] The following code is to set the HW_GPMI_CTRL1. */
1033
1034         /* Set the WRN_DLY_SEL */
1035         writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
1036         writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
1037                                         gpmi_regs + HW_GPMI_CTRL1_SET);
1038
1039         /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
1040         writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
1041
1042         /* Clear out the DLL control fields. */
1043         reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
1044         writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
1045
1046         /* If no sample delay is called for, return immediately. */
1047         if (!hw.sample_delay_factor)
1048                 return;
1049
1050         /* Set RDN_DELAY or HALF_PERIOD. */
1051         reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
1052                 | BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
1053
1054         writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
1055
1056         /* At last, we enable the DLL. */
1057         writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
1058
1059         /*
1060          * After we enable the GPMI DLL, we have to wait 64 clock cycles before
1061          * we can use the GPMI. Calculate the amount of time we need to wait,
1062          * in microseconds.
1063          */
1064         clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]);
1065         dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
1066
1067         if (!dll_wait_time_in_us)
1068                 dll_wait_time_in_us = 1;
1069
1070         /* Wait for the DLL to settle. */
1071         udelay(dll_wait_time_in_us);
1072
1073 err_out:
1074         return;
1075 }
1076
1077 void gpmi_end(struct gpmi_nand_data *this)
1078 {
1079         gpmi_disable_clk(this);
1080 }
1081
1082 /* Clears a BCH interrupt. */
1083 void gpmi_clear_bch(struct gpmi_nand_data *this)
1084 {
1085         struct resources *r = &this->resources;
1086         writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
1087 }
1088
1089 /* Returns the Ready/Busy status of the given chip. */
1090 int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
1091 {
1092         struct resources *r = &this->resources;
1093         uint32_t mask = 0;
1094         uint32_t reg = 0;
1095
1096         if (GPMI_IS_MX23(this)) {
1097                 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
1098                 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
1099         } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6Q(this)) {
1100                 /*
1101                  * In the imx6, all the ready/busy pins are bound
1102                  * together. So we only need to check chip 0.
1103                  */
1104                 if (GPMI_IS_MX6Q(this))
1105                         chip = 0;
1106
1107                 /* MX28 shares the same R/B register as MX6Q. */
1108                 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
1109                 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
1110         } else
1111                 dev_err(this->dev, "unknow arch.\n");
1112         return reg & mask;
1113 }
1114
1115 static inline void set_dma_type(struct gpmi_nand_data *this,
1116                                         enum dma_ops_type type)
1117 {
1118         this->last_dma_type = this->dma_type;
1119         this->dma_type = type;
1120 }
1121
1122 int gpmi_send_command(struct gpmi_nand_data *this)
1123 {
1124         struct dma_chan *channel = get_dma_chan(this);
1125         struct dma_async_tx_descriptor *desc;
1126         struct scatterlist *sgl;
1127         int chip = this->current_chip;
1128         u32 pio[3];
1129
1130         /* [1] send out the PIO words */
1131         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
1132                 | BM_GPMI_CTRL0_WORD_LENGTH
1133                 | BF_GPMI_CTRL0_CS(chip, this)
1134                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1135                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
1136                 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
1137                 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
1138         pio[1] = pio[2] = 0;
1139         desc = dmaengine_prep_slave_sg(channel,
1140                                         (struct scatterlist *)pio,
1141                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
1142         if (!desc)
1143                 return -EINVAL;
1144
1145         /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
1146         sgl = &this->cmd_sgl;
1147
1148         sg_init_one(sgl, this->cmd_buffer, this->command_length);
1149         dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
1150         desc = dmaengine_prep_slave_sg(channel,
1151                                 sgl, 1, DMA_MEM_TO_DEV,
1152                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1153         if (!desc)
1154                 return -EINVAL;
1155
1156         /* [3] submit the DMA */
1157         set_dma_type(this, DMA_FOR_COMMAND);
1158         return start_dma_without_bch_irq(this, desc);
1159 }
1160
1161 int gpmi_send_data(struct gpmi_nand_data *this)
1162 {
1163         struct dma_async_tx_descriptor *desc;
1164         struct dma_chan *channel = get_dma_chan(this);
1165         int chip = this->current_chip;
1166         uint32_t command_mode;
1167         uint32_t address;
1168         u32 pio[2];
1169
1170         /* [1] PIO */
1171         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
1172         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1173
1174         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1175                 | BM_GPMI_CTRL0_WORD_LENGTH
1176                 | BF_GPMI_CTRL0_CS(chip, this)
1177                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1178                 | BF_GPMI_CTRL0_ADDRESS(address)
1179                 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
1180         pio[1] = 0;
1181         desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
1182                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
1183         if (!desc)
1184                 return -EINVAL;
1185
1186         /* [2] send DMA request */
1187         prepare_data_dma(this, DMA_TO_DEVICE);
1188         desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
1189                                         1, DMA_MEM_TO_DEV,
1190                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1191         if (!desc)
1192                 return -EINVAL;
1193
1194         /* [3] submit the DMA */
1195         set_dma_type(this, DMA_FOR_WRITE_DATA);
1196         return start_dma_without_bch_irq(this, desc);
1197 }
1198
1199 int gpmi_read_data(struct gpmi_nand_data *this)
1200 {
1201         struct dma_async_tx_descriptor *desc;
1202         struct dma_chan *channel = get_dma_chan(this);
1203         int chip = this->current_chip;
1204         u32 pio[2];
1205
1206         /* [1] : send PIO */
1207         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
1208                 | BM_GPMI_CTRL0_WORD_LENGTH
1209                 | BF_GPMI_CTRL0_CS(chip, this)
1210                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1211                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
1212                 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
1213         pio[1] = 0;
1214         desc = dmaengine_prep_slave_sg(channel,
1215                                         (struct scatterlist *)pio,
1216                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
1217         if (!desc)
1218                 return -EINVAL;
1219
1220         /* [2] : send DMA request */
1221         prepare_data_dma(this, DMA_FROM_DEVICE);
1222         desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
1223                                         1, DMA_DEV_TO_MEM,
1224                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1225         if (!desc)
1226                 return -EINVAL;
1227
1228         /* [3] : submit the DMA */
1229         set_dma_type(this, DMA_FOR_READ_DATA);
1230         return start_dma_without_bch_irq(this, desc);
1231 }
1232
1233 int gpmi_send_page(struct gpmi_nand_data *this,
1234                         dma_addr_t payload, dma_addr_t auxiliary)
1235 {
1236         struct bch_geometry *geo = &this->bch_geometry;
1237         uint32_t command_mode;
1238         uint32_t address;
1239         uint32_t ecc_command;
1240         uint32_t buffer_mask;
1241         struct dma_async_tx_descriptor *desc;
1242         struct dma_chan *channel = get_dma_chan(this);
1243         int chip = this->current_chip;
1244         u32 pio[6];
1245
1246         /* A DMA descriptor that does an ECC page read. */
1247         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
1248         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1249         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
1250         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
1251                                 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1252
1253         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1254                 | BM_GPMI_CTRL0_WORD_LENGTH
1255                 | BF_GPMI_CTRL0_CS(chip, this)
1256                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1257                 | BF_GPMI_CTRL0_ADDRESS(address)
1258                 | BF_GPMI_CTRL0_XFER_COUNT(0);
1259         pio[1] = 0;
1260         pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1261                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1262                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1263         pio[3] = geo->page_size;
1264         pio[4] = payload;
1265         pio[5] = auxiliary;
1266
1267         desc = dmaengine_prep_slave_sg(channel,
1268                                         (struct scatterlist *)pio,
1269                                         ARRAY_SIZE(pio), DMA_TRANS_NONE,
1270                                         DMA_CTRL_ACK);
1271         if (!desc)
1272                 return -EINVAL;
1273
1274         set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
1275         return start_dma_with_bch_irq(this, desc);
1276 }
1277
1278 int gpmi_read_page(struct gpmi_nand_data *this,
1279                                 dma_addr_t payload, dma_addr_t auxiliary)
1280 {
1281         struct bch_geometry *geo = &this->bch_geometry;
1282         uint32_t command_mode;
1283         uint32_t address;
1284         uint32_t ecc_command;
1285         uint32_t buffer_mask;
1286         struct dma_async_tx_descriptor *desc;
1287         struct dma_chan *channel = get_dma_chan(this);
1288         int chip = this->current_chip;
1289         u32 pio[6];
1290
1291         /* [1] Wait for the chip to report ready. */
1292         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1293         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1294
1295         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1296                 | BM_GPMI_CTRL0_WORD_LENGTH
1297                 | BF_GPMI_CTRL0_CS(chip, this)
1298                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1299                 | BF_GPMI_CTRL0_ADDRESS(address)
1300                 | BF_GPMI_CTRL0_XFER_COUNT(0);
1301         pio[1] = 0;
1302         desc = dmaengine_prep_slave_sg(channel,
1303                                 (struct scatterlist *)pio, 2,
1304                                 DMA_TRANS_NONE, 0);
1305         if (!desc)
1306                 return -EINVAL;
1307
1308         /* [2] Enable the BCH block and read. */
1309         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
1310         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1311         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
1312         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1313                         | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1314
1315         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1316                 | BM_GPMI_CTRL0_WORD_LENGTH
1317                 | BF_GPMI_CTRL0_CS(chip, this)
1318                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1319                 | BF_GPMI_CTRL0_ADDRESS(address)
1320                 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1321
1322         pio[1] = 0;
1323         pio[2] =  BM_GPMI_ECCCTRL_ENABLE_ECC
1324                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1325                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1326         pio[3] = geo->page_size;
1327         pio[4] = payload;
1328         pio[5] = auxiliary;
1329         desc = dmaengine_prep_slave_sg(channel,
1330                                         (struct scatterlist *)pio,
1331                                         ARRAY_SIZE(pio), DMA_TRANS_NONE,
1332                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1333         if (!desc)
1334                 return -EINVAL;
1335
1336         /* [3] Disable the BCH block */
1337         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1338         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1339
1340         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1341                 | BM_GPMI_CTRL0_WORD_LENGTH
1342                 | BF_GPMI_CTRL0_CS(chip, this)
1343                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1344                 | BF_GPMI_CTRL0_ADDRESS(address)
1345                 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1346         pio[1] = 0;
1347         pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
1348         desc = dmaengine_prep_slave_sg(channel,
1349                                 (struct scatterlist *)pio, 3,
1350                                 DMA_TRANS_NONE,
1351                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1352         if (!desc)
1353                 return -EINVAL;
1354
1355         /* [4] submit the DMA */
1356         set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
1357         return start_dma_with_bch_irq(this, desc);
1358 }