drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/completion.h>
  35
  36 #include <asm/mach/flash.h>
  37 #include <mach/mxc_nand.h>
  38 #include <mach/hardware.h>
  39
  40 #define DRIVER_NAME "mxc_nand"
  41
  42 #define nfc_is_v21()            (cpu_is_mx25() || cpu_is_mx35())
  43 #define nfc_is_v1()             (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
  44 #define nfc_is_v3_2()           (cpu_is_mx51() || cpu_is_mx53())
  45 #define nfc_is_v3()             nfc_is_v3_2()
  46
  47 /* Addresses for NFC registers */
  48 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
  49 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
  50 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
  51 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
  52 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
  53 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
  54 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
  55 #define NFC_V1_V2_RSLTSPARE_AREA        (host->regs + 0x10)
  56 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
  57 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
  58 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
  59 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
  60 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
  61 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
  62 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
  63 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
  64 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
  65 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
  66 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
  67 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
  68 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
  69 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
  70
  71 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
  72 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
  73 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
  74 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
  75 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
  76 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
  77 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
  78 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
  79 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
  80 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
  81
  82 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
  83
  84 /*
  85  * Operation modes for the NFC. Valid for v1, v2 and v3
  86  * type controllers.
  87  */
  88 #define NFC_CMD                         (1 << 0)
  89 #define NFC_ADDR                        (1 << 1)
  90 #define NFC_INPUT                       (1 << 2)
  91 #define NFC_OUTPUT                      (1 << 3)
  92 #define NFC_ID                          (1 << 4)
  93 #define NFC_STATUS                      (1 << 5)
  94
  95 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
  96 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
  97
  98 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
  99 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
 100 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
 101
 102 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
 103
 104 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
 105
 106 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
 107 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
 108 #define NFC_V3_WRPROT_LOCK              (1 << 1)
 109 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
 110 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
 111
 112 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
 113
 114 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
 115 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
 116 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
 117 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
 118 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
 119 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
 120 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
 121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
 122 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
 123 #define NFC_V3_CONFIG2_PPB(x)                   (((x) & 0x3) << 7)
 124 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
 125 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
 126 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
 127 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
 128
 129 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
 130 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
 131 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
 132 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
 133 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
 134 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
 135 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
 136
 137 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
 138 #define NFC_V3_IPC_CREQ                 (1 << 0)
 139 #define NFC_V3_IPC_INT                  (1 << 31)
 140
 141 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
 142
 143 struct mxc_nand_host;
 144
 145 struct mxc_nand_devtype_data {
 146         void (*preset)(struct mtd_info *);
 147         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
 148         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
 149         void (*send_page)(struct mtd_info *, unsigned int);
 150         void (*send_read_id)(struct mxc_nand_host *);
 151         uint16_t (*get_dev_status)(struct mxc_nand_host *);
 152         int (*check_int)(struct mxc_nand_host *);
 153         void (*irq_control)(struct mxc_nand_host *, int);
 154         u32 (*get_ecc_status)(struct mxc_nand_host *);
 155         struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
 156         void (*select_chip)(struct mtd_info *mtd, int chip);
 157         int (*correct_data)(struct mtd_info *mtd, u_char *dat,
 158                         u_char *read_ecc, u_char *calc_ecc);
 159 };
 160
 161 struct mxc_nand_host {
 162         struct mtd_info         mtd;
 163         struct nand_chip        nand;
 164         struct device           *dev;
 165
 166         void                    *spare0;
 167         void                    *main_area0;
 168
 169         void __iomem            *base;
 170         void __iomem            *regs;
 171         void __iomem            *regs_axi;
 172         void __iomem            *regs_ip;
 173         int                     status_request;
 174         struct clk              *clk;
 175         int                     clk_act;
 176         int                     irq;
 177         int                     eccsize;
 178         int                     active_cs;
 179
 180         struct completion       op_completion;
 181
 182         uint8_t                 *data_buf;
 183         unsigned int            buf_start;
 184         int                     spare_len;
 185
 186         const struct mxc_nand_devtype_data *devtype_data;
 187
 188         /*
 189          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
 190          * (CONFIG1:INT_MSK is set). To handle this the driver uses
 191          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
 192          */
 193         int irqpending_quirk;
 194 };
 195
 196 /* OOB placement block for use with hardware ecc generation */
 197 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
 198         .eccbytes = 5,
 199         .eccpos = {6, 7, 8, 9, 10},
 200         .oobfree = {{0, 5}, {12, 4}, }
 201 };
 202
 203 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
 204         .eccbytes = 20,
 205         .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
 206                    38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
 207         .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
 208 };
 209
 210 /* OOB description for 512 byte pages with 16 byte OOB */
 211 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
 212         .eccbytes = 1 * 9,
 213         .eccpos = {
 214                  7,  8,  9, 10, 11, 12, 13, 14, 15
 215         },
 216         .oobfree = {
 217                 {.offset = 0, .length = 5}
 218         }
 219 };
 220
 221 /* OOB description for 2048 byte pages with 64 byte OOB */
 222 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
 223         .eccbytes = 4 * 9,
 224         .eccpos = {
 225                  7,  8,  9, 10, 11, 12, 13, 14, 15,
 226                 23, 24, 25, 26, 27, 28, 29, 30, 31,
 227                 39, 40, 41, 42, 43, 44, 45, 46, 47,
 228                 55, 56, 57, 58, 59, 60, 61, 62, 63
 229         },
 230         .oobfree = {
 231                 {.offset = 2, .length = 4},
 232                 {.offset = 16, .length = 7},
 233                 {.offset = 32, .length = 7},
 234                 {.offset = 48, .length = 7}
 235         }
 236 };
 237
 238 /* OOB description for 4096 byte pages with 128 byte OOB */
 239 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
 240         .eccbytes = 8 * 9,
 241         .eccpos = {
 242                 7,  8,  9, 10, 11, 12, 13, 14, 15,
 243                 23, 24, 25, 26, 27, 28, 29, 30, 31,
 244                 39, 40, 41, 42, 43, 44, 45, 46, 47,
 245                 55, 56, 57, 58, 59, 60, 61, 62, 63,
 246                 71, 72, 73, 74, 75, 76, 77, 78, 79,
 247                 87, 88, 89, 90, 91, 92, 93, 94, 95,
 248                 103, 104, 105, 106, 107, 108, 109, 110, 111,
 249                 119, 120, 121, 122, 123, 124, 125, 126, 127,
 250         },
 251         .oobfree = {
 252                 {.offset = 2, .length = 4},
 253                 {.offset = 16, .length = 7},
 254                 {.offset = 32, .length = 7},
 255                 {.offset = 48, .length = 7},
 256                 {.offset = 64, .length = 7},
 257                 {.offset = 80, .length = 7},
 258                 {.offset = 96, .length = 7},
 259                 {.offset = 112, .length = 7},
 260         }
 261 };
 262
 263 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
 264
 265 static int check_int_v3(struct mxc_nand_host *host)
 266 {
 267         uint32_t tmp;
 268
 269         tmp = readl(NFC_V3_IPC);
 270         if (!(tmp & NFC_V3_IPC_INT))
 271                 return 0;
 272
 273         tmp &= ~NFC_V3_IPC_INT;
 274         writel(tmp, NFC_V3_IPC);
 275
 276         return 1;
 277 }
 278
 279 static int check_int_v1_v2(struct mxc_nand_host *host)
 280 {
 281         uint32_t tmp;
 282
 283         tmp = readw(NFC_V1_V2_CONFIG2);
 284         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
 285                 return 0;
 286
 287         if (!host->irqpending_quirk)
 288                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
 289
 290         return 1;
 291 }
 292
 293 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
 294 {
 295         uint16_t tmp;
 296
 297         tmp = readw(NFC_V1_V2_CONFIG1);
 298
 299         if (activate)
 300                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
 301         else
 302                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
 303
 304         writew(tmp, NFC_V1_V2_CONFIG1);
 305 }
 306
 307 static void irq_control_v3(struct mxc_nand_host *host, int activate)
 308 {
 309         uint32_t tmp;
 310
 311         tmp = readl(NFC_V3_CONFIG2);
 312
 313         if (activate)
 314                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
 315         else
 316                 tmp |= NFC_V3_CONFIG2_INT_MSK;
 317
 318         writel(tmp, NFC_V3_CONFIG2);
 319 }
 320
 321 static void irq_control(struct mxc_nand_host *host, int activate)
 322 {
 323         if (host->irqpending_quirk) {
 324                 if (activate)
 325                         enable_irq(host->irq);
 326                 else
 327                         disable_irq_nosync(host->irq);
 328         } else {
 329                 host->devtype_data->irq_control(host, activate);
 330         }
 331 }
 332
 333 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
 334 {
 335         return readw(NFC_V1_V2_ECC_STATUS_RESULT);
 336 }
 337
 338 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
 339 {
 340         return readl(NFC_V1_V2_ECC_STATUS_RESULT);
 341 }
 342
 343 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
 344 {
 345         return readl(NFC_V3_ECC_STATUS_RESULT);
 346 }
 347
 348 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 349 {
 350         struct mxc_nand_host *host = dev_id;
 351
 352         if (!host->devtype_data->check_int(host))
 353                 return IRQ_NONE;
 354
 355         irq_control(host, 0);
 356
 357         complete(&host->op_completion);
 358
 359         return IRQ_HANDLED;
 360 }
 361
 362 /* This function polls the NANDFC to wait for the basic operation to
 363  * complete by checking the INT bit of config2 register.
 364  */
 365 static void wait_op_done(struct mxc_nand_host *host, int useirq)
 366 {
 367         int max_retries = 8000;
 368
 369         if (useirq) {
 370                 if (!host->devtype_data->check_int(host)) {
 371                         INIT_COMPLETION(host->op_completion);
 372                         irq_control(host, 1);
 373                         wait_for_completion(&host->op_completion);
 374                 }
 375         } else {
 376                 while (max_retries-- > 0) {
 377                         if (host->devtype_data->check_int(host))
 378                                 break;
 379
 380                         udelay(1);
 381                 }
 382                 if (max_retries < 0)
 383                         pr_debug("%s: INT not set\n", __func__);
 384         }
 385 }
 386
 387 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 388 {
 389         /* fill command */
 390         writel(cmd, NFC_V3_FLASH_CMD);
 391
 392         /* send out command */
 393         writel(NFC_CMD, NFC_V3_LAUNCH);
 394
 395         /* Wait for operation to complete */
 396         wait_op_done(host, useirq);
 397 }
 398
 399 /* This function issues the specified command to the NAND device and
 400  * waits for completion. */
 401 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 402 {
 403         pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 404
 405         writew(cmd, NFC_V1_V2_FLASH_CMD);
 406         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
 407
 408         if (host->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
 409                 int max_retries = 100;
 410                 /* Reset completion is indicated by NFC_CONFIG2 */
 411                 /* being set to 0 */
 412                 while (max_retries-- > 0) {
 413                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
 414                                 break;
 415                         }
 416                         udelay(1);
 417                 }
 418                 if (max_retries < 0)
 419                         pr_debug("%s: RESET failed\n", __func__);
 420         } else {
 421                 /* Wait for operation to complete */
 422                 wait_op_done(host, useirq);
 423         }
 424 }
 425
 426 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
 427 {
 428         /* fill address */
 429         writel(addr, NFC_V3_FLASH_ADDR0);
 430
 431         /* send out address */
 432         writel(NFC_ADDR, NFC_V3_LAUNCH);
 433
 434         wait_op_done(host, 0);
 435 }
 436
 437 /* This function sends an address (or partial address) to the
 438  * NAND device. The address is used to select the source/destination for
 439  * a NAND command. */
 440 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
 441 {
 442         pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
 443
 444         writew(addr, NFC_V1_V2_FLASH_ADDR);
 445         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
 446
 447         /* Wait for operation to complete */
 448         wait_op_done(host, islast);
 449 }
 450
 451 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
 452 {
 453         struct nand_chip *nand_chip = mtd->priv;
 454         struct mxc_nand_host *host = nand_chip->priv;
 455         uint32_t tmp;
 456
 457         tmp = readl(NFC_V3_CONFIG1);
 458         tmp &= ~(7 << 4);
 459         writel(tmp, NFC_V3_CONFIG1);
 460
 461         /* transfer data from NFC ram to nand */
 462         writel(ops, NFC_V3_LAUNCH);
 463
 464         wait_op_done(host, false);
 465 }
 466
 467 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
 468 {
 469         struct nand_chip *nand_chip = mtd->priv;
 470         struct mxc_nand_host *host = nand_chip->priv;
 471
 472         /* NANDFC buffer 0 is used for page read/write */
 473         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 474
 475         writew(ops, NFC_V1_V2_CONFIG2);
 476
 477         /* Wait for operation to complete */
 478         wait_op_done(host, true);
 479 }
 480
 481 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
 482 {
 483         struct nand_chip *nand_chip = mtd->priv;
 484         struct mxc_nand_host *host = nand_chip->priv;
 485         int bufs, i;
 486
 487         if (mtd->writesize > 512)
 488                 bufs = 4;
 489         else
 490                 bufs = 1;
 491
 492         for (i = 0; i < bufs; i++) {
 493
 494                 /* NANDFC buffer 0 is used for page read/write */
 495                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 496
 497                 writew(ops, NFC_V1_V2_CONFIG2);
 498
 499                 /* Wait for operation to complete */
 500                 wait_op_done(host, true);
 501         }
 502 }
 503
 504 static void send_read_id_v3(struct mxc_nand_host *host)
 505 {
 506         /* Read ID into main buffer */
 507         writel(NFC_ID, NFC_V3_LAUNCH);
 508
 509         wait_op_done(host, true);
 510
 511         memcpy(host->data_buf, host->main_area0, 16);
 512 }
 513
 514 /* Request the NANDFC to perform a read of the NAND device ID. */
 515 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 516 {
 517         struct nand_chip *this = &host->nand;
 518
 519         /* NANDFC buffer 0 is used for device ID output */
 520         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 521
 522         writew(NFC_ID, NFC_V1_V2_CONFIG2);
 523
 524         /* Wait for operation to complete */
 525         wait_op_done(host, true);
 526
 527         memcpy(host->data_buf, host->main_area0, 16);
 528
 529         if (this->options & NAND_BUSWIDTH_16) {
 530                 /* compress the ID info */
 531                 host->data_buf[1] = host->data_buf[2];
 532                 host->data_buf[2] = host->data_buf[4];
 533                 host->data_buf[3] = host->data_buf[6];
 534                 host->data_buf[4] = host->data_buf[8];
 535                 host->data_buf[5] = host->data_buf[10];
 536         }
 537 }
 538
 539 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
 540 {
 541         writew(NFC_STATUS, NFC_V3_LAUNCH);
 542         wait_op_done(host, true);
 543
 544         return readl(NFC_V3_CONFIG1) >> 16;
 545 }
 546
 547 /* This function requests the NANDFC to perform a read of the
 548  * NAND device status and returns the current status. */
 549 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
 550 {
 551         void __iomem *main_buf = host->main_area0;
 552         uint32_t store;
 553         uint16_t ret;
 554
 555         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 556
 557         /*
 558          * The device status is stored in main_area0. To
 559          * prevent corruption of the buffer save the value
 560          * and restore it afterwards.
 561          */
 562         store = readl(main_buf);
 563
 564         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
 565         wait_op_done(host, true);
 566
 567         ret = readw(main_buf);
 568
 569         writel(store, main_buf);
 570
 571         return ret;
 572 }
 573
 574 /* This functions is used by upper layer to checks if device is ready */
 575 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 576 {
 577         /*
 578          * NFC handles R/B internally. Therefore, this function
 579          * always returns status as ready.
 580          */
 581         return 1;
 582 }
 583
 584 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 585 {
 586         /*
 587          * If HW ECC is enabled, we turn it on during init. There is
 588          * no need to enable again here.
 589          */
 590 }
 591
 592 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
 593                                  u_char *read_ecc, u_char *calc_ecc)
 594 {
 595         struct nand_chip *nand_chip = mtd->priv;
 596         struct mxc_nand_host *host = nand_chip->priv;
 597
 598         /*
 599          * 1-Bit errors are automatically corrected in HW.  No need for
 600          * additional correction.  2-Bit errors cannot be corrected by
 601          * HW ECC, so we need to return failure
 602          */
 603         uint16_t ecc_status = get_ecc_status_v1(host);
 604
 605         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 606                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 607                 return -1;
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
 614                                  u_char *read_ecc, u_char *calc_ecc)
 615 {
 616         struct nand_chip *nand_chip = mtd->priv;
 617         struct mxc_nand_host *host = nand_chip->priv;
 618         u32 ecc_stat, err;
 619         int no_subpages = 1;
 620         int ret = 0;
 621         u8 ecc_bit_mask, err_limit;
 622
 623         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
 624         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
 625
 626         no_subpages = mtd->writesize >> 9;
 627
 628         ecc_stat = host->devtype_data->get_ecc_status(host);
 629
 630         do {
 631                 err = ecc_stat & ecc_bit_mask;
 632                 if (err > err_limit) {
 633                         printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
 634                         return -1;
 635                 } else {
 636                         ret += err;
 637                 }
 638                 ecc_stat >>= 4;
 639         } while (--no_subpages);
 640
 641         mtd->ecc_stats.corrected += ret;
 642         pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
 643
 644         return ret;
 645 }
 646
 647 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 648                                   u_char *ecc_code)
 649 {
 650         return 0;
 651 }
 652
 653 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 654 {
 655         struct nand_chip *nand_chip = mtd->priv;
 656         struct mxc_nand_host *host = nand_chip->priv;
 657         uint8_t ret;
 658
 659         /* Check for status request */
 660         if (host->status_request)
 661                 return host->devtype_data->get_dev_status(host) & 0xFF;
 662
 663         ret = *(uint8_t *)(host->data_buf + host->buf_start);
 664         host->buf_start++;
 665
 666         return ret;
 667 }
 668
 669 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 670 {
 671         struct nand_chip *nand_chip = mtd->priv;
 672         struct mxc_nand_host *host = nand_chip->priv;
 673         uint16_t ret;
 674
 675         ret = *(uint16_t *)(host->data_buf + host->buf_start);
 676         host->buf_start += 2;
 677
 678         return ret;
 679 }
 680
 681 /* Write data of length len to buffer buf. The data to be
 682  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 683  * Operation by the NFC, the data is written to NAND Flash */
 684 static void mxc_nand_write_buf(struct mtd_info *mtd,
 685                                 const u_char *buf, int len)
 686 {
 687         struct nand_chip *nand_chip = mtd->priv;
 688         struct mxc_nand_host *host = nand_chip->priv;
 689         u16 col = host->buf_start;
 690         int n = mtd->oobsize + mtd->writesize - col;
 691
 692         n = min(n, len);
 693
 694         memcpy(host->data_buf + col, buf, n);
 695
 696         host->buf_start += n;
 697 }
 698
 699 /* Read the data buffer from the NAND Flash. To read the data from NAND
 700  * Flash first the data output cycle is initiated by the NFC, which copies
 701  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 702  */
 703 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 704 {
 705         struct nand_chip *nand_chip = mtd->priv;
 706         struct mxc_nand_host *host = nand_chip->priv;
 707         u16 col = host->buf_start;
 708         int n = mtd->oobsize + mtd->writesize - col;
 709
 710         n = min(n, len);
 711
 712         memcpy(buf, host->data_buf + col, n);
 713
 714         host->buf_start += n;
 715 }
 716
 717 /* Used by the upper layer to verify the data in NAND Flash
 718  * with the data in the buf. */
 719 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 720                                 const u_char *buf, int len)
 721 {
 722         return -EFAULT;
 723 }
 724
 725 /* This function is used by upper layer for select and
 726  * deselect of the NAND chip */
 727 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
 728 {
 729         struct nand_chip *nand_chip = mtd->priv;
 730         struct mxc_nand_host *host = nand_chip->priv;
 731
 732         if (chip == -1) {
 733                 /* Disable the NFC clock */
 734                 if (host->clk_act) {
 735                         clk_disable(host->clk);
 736                         host->clk_act = 0;
 737                 }
 738                 return;
 739         }
 740
 741         if (!host->clk_act) {
 742                 /* Enable the NFC clock */
 743                 clk_enable(host->clk);
 744                 host->clk_act = 1;
 745         }
 746 }
 747
 748 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
 749 {
 750         struct nand_chip *nand_chip = mtd->priv;
 751         struct mxc_nand_host *host = nand_chip->priv;
 752
 753         if (chip == -1) {
 754                 /* Disable the NFC clock */
 755                 if (host->clk_act) {
 756                         clk_disable(host->clk);
 757                         host->clk_act = 0;
 758                 }
 759                 return;
 760         }
 761
 762         if (!host->clk_act) {
 763                 /* Enable the NFC clock */
 764                 clk_enable(host->clk);
 765                 host->clk_act = 1;
 766         }
 767
 768         host->active_cs = chip;
 769         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 770 }
 771
 772 /*
 773  * Function to transfer data to/from spare area.
 774  */
 775 static void copy_spare(struct mtd_info *mtd, bool bfrom)
 776 {
 777         struct nand_chip *this = mtd->priv;
 778         struct mxc_nand_host *host = this->priv;
 779         u16 i, j;
 780         u16 n = mtd->writesize >> 9;
 781         u8 *d = host->data_buf + mtd->writesize;
 782         u8 *s = host->spare0;
 783         u16 t = host->spare_len;
 784
 785         j = (mtd->oobsize / n >> 1) << 1;
 786
 787         if (bfrom) {
 788                 for (i = 0; i < n - 1; i++)
 789                         memcpy(d + i * j, s + i * t, j);
 790
 791                 /* the last section */
 792                 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
 793         } else {
 794                 for (i = 0; i < n - 1; i++)
 795                         memcpy(&s[i * t], &d[i * j], j);
 796
 797                 /* the last section */
 798                 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
 799         }
 800 }
 801
 802 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 803 {
 804         struct nand_chip *nand_chip = mtd->priv;
 805         struct mxc_nand_host *host = nand_chip->priv;
 806
 807         /* Write out column address, if necessary */
 808         if (column != -1) {
 809                 /*
 810                  * MXC NANDFC can only perform full page+spare or
 811                  * spare-only read/write.  When the upper layers
 812                  * perform a read/write buf operation, the saved column
 813                   * address is used to index into the full page.
 814                  */
 815                 host->devtype_data->send_addr(host, 0, page_addr == -1);
 816                 if (mtd->writesize > 512)
 817                         /* another col addr cycle for 2k page */
 818                         host->devtype_data->send_addr(host, 0, false);
 819         }
 820
 821         /* Write out page address, if necessary */
 822         if (page_addr != -1) {
 823                 /* paddr_0 - p_addr_7 */
 824                 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
 825
 826                 if (mtd->writesize > 512) {
 827                         if (mtd->size >= 0x10000000) {
 828                                 /* paddr_8 - paddr_15 */
 829                                 host->devtype_data->send_addr(host,
 830                                                 (page_addr >> 8) & 0xff,
 831                                                 false);
 832                                 host->devtype_data->send_addr(host,
 833                                                 (page_addr >> 16) & 0xff,
 834                                                 true);
 835                         } else
 836                                 /* paddr_8 - paddr_15 */
 837                                 host->devtype_data->send_addr(host,
 838                                                 (page_addr >> 8) & 0xff, true);
 839                 } else {
 840                         /* One more address cycle for higher density devices */
 841                         if (mtd->size >= 0x4000000) {
 842                                 /* paddr_8 - paddr_15 */
 843                                 host->devtype_data->send_addr(host,
 844                                                 (page_addr >> 8) & 0xff,
 845                                                 false);
 846                                 host->devtype_data->send_addr(host,
 847                                                 (page_addr >> 16) & 0xff,
 848                                                 true);
 849                         } else
 850                                 /* paddr_8 - paddr_15 */
 851                                 host->devtype_data->send_addr(host,
 852                                                 (page_addr >> 8) & 0xff, true);
 853                 }
 854         }
 855 }
 856
 857 /*
 858  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
 859  * on how much oob the nand chip has. For 8bit ecc we need at least
 860  * 26 bytes of oob data per 512 byte block.
 861  */
 862 static int get_eccsize(struct mtd_info *mtd)
 863 {
 864         int oobbytes_per_512 = 0;
 865
 866         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
 867
 868         if (oobbytes_per_512 < 26)
 869                 return 4;
 870         else
 871                 return 8;
 872 }
 873
 874 static void preset_v1(struct mtd_info *mtd)
 875 {
 876         struct nand_chip *nand_chip = mtd->priv;
 877         struct mxc_nand_host *host = nand_chip->priv;
 878         uint16_t config1 = 0;
 879
 880         if (nand_chip->ecc.mode == NAND_ECC_HW)
 881                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 882
 883         if (!host->irqpending_quirk)
 884                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
 885
 886         host->eccsize = 1;
 887
 888         writew(config1, NFC_V1_V2_CONFIG1);
 889         /* preset operation */
 890
 891         /* Unlock the internal RAM Buffer */
 892         writew(0x2, NFC_V1_V2_CONFIG);
 893
 894         /* Blocks to be unlocked */
 895         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
 896         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
 897
 898         /* Unlock Block Command for given address range */
 899         writew(0x4, NFC_V1_V2_WRPROT);
 900 }
 901
 902 static void preset_v2(struct mtd_info *mtd)
 903 {
 904         struct nand_chip *nand_chip = mtd->priv;
 905         struct mxc_nand_host *host = nand_chip->priv;
 906         uint16_t config1 = 0;
 907
 908         if (nand_chip->ecc.mode == NAND_ECC_HW)
 909                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 910
 911         config1 |= NFC_V2_CONFIG1_FP_INT;
 912
 913         if (!host->irqpending_quirk)
 914                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
 915
 916         if (mtd->writesize) {
 917                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
 918
 919                 host->eccsize = get_eccsize(mtd);
 920                 if (host->eccsize == 4)
 921                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
 922
 923                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
 924         } else {
 925                 host->eccsize = 1;
 926         }
 927
 928         writew(config1, NFC_V1_V2_CONFIG1);
 929         /* preset operation */
 930
 931         /* Unlock the internal RAM Buffer */
 932         writew(0x2, NFC_V1_V2_CONFIG);
 933
 934         /* Blocks to be unlocked */
 935         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
 936         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
 937         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
 938         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
 939         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
 940         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
 941         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
 942         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
 943
 944         /* Unlock Block Command for given address range */
 945         writew(0x4, NFC_V1_V2_WRPROT);
 946 }
 947
 948 static void preset_v3(struct mtd_info *mtd)
 949 {
 950         struct nand_chip *chip = mtd->priv;
 951         struct mxc_nand_host *host = chip->priv;
 952         uint32_t config2, config3;
 953         int i, addr_phases;
 954
 955         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
 956         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
 957
 958         /* Unlock the internal RAM Buffer */
 959         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
 960                         NFC_V3_WRPROT);
 961
 962         /* Blocks to be unlocked */
 963         for (i = 0; i < NAND_MAX_CHIPS; i++)
 964                 writel(0x0 |    (0xffff << 16),
 965                                 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
 966
 967         writel(0, NFC_V3_IPC);
 968
 969         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
 970                 NFC_V3_CONFIG2_2CMD_PHASES |
 971                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
 972                 NFC_V3_CONFIG2_ST_CMD(0x70) |
 973                 NFC_V3_CONFIG2_INT_MSK |
 974                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
 975
 976         if (chip->ecc.mode == NAND_ECC_HW)
 977                 config2 |= NFC_V3_CONFIG2_ECC_EN;
 978
 979         addr_phases = fls(chip->pagemask) >> 3;
 980
 981         if (mtd->writesize == 2048) {
 982                 config2 |= NFC_V3_CONFIG2_PS_2048;
 983                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
 984         } else if (mtd->writesize == 4096) {
 985                 config2 |= NFC_V3_CONFIG2_PS_4096;
 986                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
 987         } else {
 988                 config2 |= NFC_V3_CONFIG2_PS_512;
 989                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
 990         }
 991
 992         if (mtd->writesize) {
 993                 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
 994                 host->eccsize = get_eccsize(mtd);
 995                 if (host->eccsize == 8)
 996                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
 997         }
 998
 999         writel(config2, NFC_V3_CONFIG2);
1000
1001         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1002                         NFC_V3_CONFIG3_NO_SDMA |
1003                         NFC_V3_CONFIG3_RBB_MODE |
1004                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1005                         NFC_V3_CONFIG3_ADD_OP(0);
1006
1007         if (!(chip->options & NAND_BUSWIDTH_16))
1008                 config3 |= NFC_V3_CONFIG3_FW8;
1009
1010         writel(config3, NFC_V3_CONFIG3);
1011
1012         writel(0, NFC_V3_DELAY_LINE);
1013 }
1014
1015 /* Used by the upper layer to write command to NAND Flash for
1016  * different operations to be carried out on NAND Flash */
1017 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1018                                 int column, int page_addr)
1019 {
1020         struct nand_chip *nand_chip = mtd->priv;
1021         struct mxc_nand_host *host = nand_chip->priv;
1022
1023         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1024               command, column, page_addr);
1025
1026         /* Reset command state information */
1027         host->status_request = false;
1028
1029         /* Command pre-processing step */
1030         switch (command) {
1031         case NAND_CMD_RESET:
1032                 host->devtype_data->preset(mtd);
1033                 host->devtype_data->send_cmd(host, command, false);
1034                 break;
1035
1036         case NAND_CMD_STATUS:
1037                 host->buf_start = 0;
1038                 host->status_request = true;
1039
1040                 host->devtype_data->send_cmd(host, command, true);
1041                 mxc_do_addr_cycle(mtd, column, page_addr);
1042                 break;
1043
1044         case NAND_CMD_READ0:
1045         case NAND_CMD_READOOB:
1046                 if (command == NAND_CMD_READ0)
1047                         host->buf_start = column;
1048                 else
1049                         host->buf_start = column + mtd->writesize;
1050
1051                 command = NAND_CMD_READ0; /* only READ0 is valid */
1052
1053                 host->devtype_data->send_cmd(host, command, false);
1054                 mxc_do_addr_cycle(mtd, column, page_addr);
1055
1056                 if (mtd->writesize > 512)
1057                         host->devtype_data->send_cmd(host,
1058                                         NAND_CMD_READSTART, true);
1059
1060                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1061
1062                 memcpy(host->data_buf, host->main_area0, mtd->writesize);
1063                 copy_spare(mtd, true);
1064                 break;
1065
1066         case NAND_CMD_SEQIN:
1067                 if (column >= mtd->writesize)
1068                         /* call ourself to read a page */
1069                         mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1070
1071                 host->buf_start = column;
1072
1073                 host->devtype_data->send_cmd(host, command, false);
1074                 mxc_do_addr_cycle(mtd, column, page_addr);
1075                 break;
1076
1077         case NAND_CMD_PAGEPROG:
1078                 memcpy(host->main_area0, host->data_buf, mtd->writesize);
1079                 copy_spare(mtd, false);
1080                 host->devtype_data->send_page(mtd, NFC_INPUT);
1081                 host->devtype_data->send_cmd(host, command, true);
1082                 mxc_do_addr_cycle(mtd, column, page_addr);
1083                 break;
1084
1085         case NAND_CMD_READID:
1086                 host->devtype_data->send_cmd(host, command, true);
1087                 mxc_do_addr_cycle(mtd, column, page_addr);
1088                 host->devtype_data->send_read_id(host);
1089                 host->buf_start = column;
1090                 break;
1091
1092         case NAND_CMD_ERASE1:
1093         case NAND_CMD_ERASE2:
1094                 host->devtype_data->send_cmd(host, command, false);
1095                 mxc_do_addr_cycle(mtd, column, page_addr);
1096
1097                 break;
1098         }
1099 }
1100
1101 /*
1102  * The generic flash bbt decriptors overlap with our ecc
1103  * hardware, so define some i.MX specific ones.
1104  */
1105 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1106 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1107
1108 static struct nand_bbt_descr bbt_main_descr = {
1109         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1110             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1111         .offs = 0,
1112         .len = 4,
1113         .veroffs = 4,
1114         .maxblocks = 4,
1115         .pattern = bbt_pattern,
1116 };
1117
1118 static struct nand_bbt_descr bbt_mirror_descr = {
1119         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1120             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1121         .offs = 0,
1122         .len = 4,
1123         .veroffs = 4,
1124         .maxblocks = 4,
1125         .pattern = mirror_pattern,
1126 };
1127
1128 /* v1: i.MX21, i.MX27, i.MX31 */
1129 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1130         .preset = preset_v1,
1131         .send_cmd = send_cmd_v1_v2,
1132         .send_addr = send_addr_v1_v2,
1133         .send_page = send_page_v1,
1134         .send_read_id = send_read_id_v1_v2,
1135         .get_dev_status = get_dev_status_v1_v2,
1136         .check_int = check_int_v1_v2,
1137         .irq_control = irq_control_v1_v2,
1138         .get_ecc_status = get_ecc_status_v1,
1139         .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1140         .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1141         .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1142         .select_chip = mxc_nand_select_chip_v1_v3,
1143         .correct_data = mxc_nand_correct_data_v1,
1144 };
1145
1146 /* v21: i.MX25, i.MX35 */
1147 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1148         .preset = preset_v2,
1149         .send_cmd = send_cmd_v1_v2,
1150         .send_addr = send_addr_v1_v2,
1151         .send_page = send_page_v2,
1152         .send_read_id = send_read_id_v1_v2,
1153         .get_dev_status = get_dev_status_v1_v2,
1154         .check_int = check_int_v1_v2,
1155         .irq_control = irq_control_v1_v2,
1156         .get_ecc_status = get_ecc_status_v2,
1157         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1158         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1159         .ecclayout_4k = &nandv2_hw_eccoob_4k,
1160         .select_chip = mxc_nand_select_chip_v2,
1161         .correct_data = mxc_nand_correct_data_v2_v3,
1162 };
1163
1164 /* v3: i.MX51, i.MX53 */
1165 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1166         .preset = preset_v3,
1167         .send_cmd = send_cmd_v3,
1168         .send_addr = send_addr_v3,
1169         .send_page = send_page_v3,
1170         .send_read_id = send_read_id_v3,
1171         .get_dev_status = get_dev_status_v3,
1172         .check_int = check_int_v3,
1173         .irq_control = irq_control_v3,
1174         .get_ecc_status = get_ecc_status_v3,
1175         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1176         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1177         .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1178         .select_chip = mxc_nand_select_chip_v1_v3,
1179         .correct_data = mxc_nand_correct_data_v2_v3,
1180 };
1181
1182 static int __init mxcnd_probe(struct platform_device *pdev)
1183 {
1184         struct nand_chip *this;
1185         struct mtd_info *mtd;
1186         struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1187         struct mxc_nand_host *host;
1188         struct resource *res;
1189         int err = 0;
1190
1191         /* Allocate memory for MTD device structure and private data */
1192         host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1193                         NAND_MAX_OOBSIZE, GFP_KERNEL);
1194         if (!host)
1195                 return -ENOMEM;
1196
1197         host->data_buf = (uint8_t *)(host + 1);
1198
1199         host->dev = &pdev->dev;
1200         /* structures must be linked */
1201         this = &host->nand;
1202         mtd = &host->mtd;
1203         mtd->priv = this;
1204         mtd->owner = THIS_MODULE;
1205         mtd->dev.parent = &pdev->dev;
1206         mtd->name = DRIVER_NAME;
1207
1208         /* 50 us command delay time */
1209         this->chip_delay = 5;
1210
1211         this->priv = host;
1212         this->dev_ready = mxc_nand_dev_ready;
1213         this->cmdfunc = mxc_nand_command;
1214         this->read_byte = mxc_nand_read_byte;
1215         this->read_word = mxc_nand_read_word;
1216         this->write_buf = mxc_nand_write_buf;
1217         this->read_buf = mxc_nand_read_buf;
1218         this->verify_buf = mxc_nand_verify_buf;
1219
1220         host->clk = clk_get(&pdev->dev, "nfc");
1221         if (IS_ERR(host->clk)) {
1222                 err = PTR_ERR(host->clk);
1223                 goto eclk;
1224         }
1225
1226         clk_enable(host->clk);
1227         host->clk_act = 1;
1228
1229         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1230         if (!res) {
1231                 err = -ENODEV;
1232                 goto eres;
1233         }
1234
1235         host->base = ioremap(res->start, resource_size(res));
1236         if (!host->base) {
1237                 err = -ENOMEM;
1238                 goto eres;
1239         }
1240
1241         host->main_area0 = host->base;
1242
1243         if (nfc_is_v1()) {
1244                 host->devtype_data = &imx21_nand_devtype_data;
1245                 if (cpu_is_mx21())
1246                         host->irqpending_quirk = 1;
1247                 host->regs = host->base + 0xe00;
1248                 host->spare0 = host->base + 0x800;
1249                 host->spare_len = 16;
1250                 this->ecc.bytes = 3;
1251                 host->eccsize = 1;
1252         } else if (nfc_is_v21()) {
1253                 host->devtype_data = &imx25_nand_devtype_data;
1254                 host->regs = host->base + 0x1e00;
1255                 host->spare0 = host->base + 0x1000;
1256                 host->spare_len = 64;
1257                 this->ecc.bytes = 9;
1258         } else if (nfc_is_v3_2()) {
1259                 host->devtype_data = &imx51_nand_devtype_data;
1260                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1261                 if (!res) {
1262                         err = -ENODEV;
1263                         goto eirq;
1264                 }
1265                 host->regs_ip = ioremap(res->start, resource_size(res));
1266                 if (!host->regs_ip) {
1267                         err = -ENOMEM;
1268                         goto eirq;
1269                 }
1270                 host->regs_axi = host->base + 0x1e00;
1271                 host->spare0 = host->base + 0x1000;
1272                 host->spare_len = 64;
1273         } else
1274                 BUG();
1275
1276         this->select_chip = host->devtype_data->select_chip;
1277         this->ecc.size = 512;
1278         this->ecc.layout = host->devtype_data->ecclayout_512;
1279
1280         if (pdata->hw_ecc) {
1281                 this->ecc.calculate = mxc_nand_calculate_ecc;
1282                 this->ecc.hwctl = mxc_nand_enable_hwecc;
1283                 this->ecc.correct = host->devtype_data->correct_data;
1284                 this->ecc.mode = NAND_ECC_HW;
1285         } else {
1286                 this->ecc.mode = NAND_ECC_SOFT;
1287         }
1288
1289         /* NAND bus width determines access funtions used by upper layer */
1290         if (pdata->width == 2)
1291                 this->options |= NAND_BUSWIDTH_16;
1292
1293         if (pdata->flash_bbt) {
1294                 this->bbt_td = &bbt_main_descr;
1295                 this->bbt_md = &bbt_mirror_descr;
1296                 /* update flash based bbt */
1297                 this->bbt_options |= NAND_BBT_USE_FLASH;
1298         }
1299
1300         init_completion(&host->op_completion);
1301
1302         host->irq = platform_get_irq(pdev, 0);
1303
1304         /*
1305          * Use host->devtype_data->irq_control() here instead of irq_control()
1306          * because we must not disable_irq_nosync without having requested the
1307          * irq.
1308          */
1309         host->devtype_data->irq_control(host, 0);
1310
1311         err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1312         if (err)
1313                 goto eirq;
1314
1315         /*
1316          * Now that we "own" the interrupt make sure the interrupt mask bit is
1317          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1318          * on this machine.
1319          */
1320         if (host->irqpending_quirk) {
1321                 disable_irq_nosync(host->irq);
1322                 host->devtype_data->irq_control(host, 1);
1323         }
1324
1325         /* first scan to find the device and get the page size */
1326         if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1327                 err = -ENXIO;
1328                 goto escan;
1329         }
1330
1331         /* Call preset again, with correct writesize this time */
1332         host->devtype_data->preset(mtd);
1333
1334         if (mtd->writesize == 2048)
1335                 this->ecc.layout = host->devtype_data->ecclayout_2k;
1336         else if (mtd->writesize == 4096)
1337                 this->ecc.layout = host->devtype_data->ecclayout_4k;
1338
1339         /* second phase scan */
1340         if (nand_scan_tail(mtd)) {
1341                 err = -ENXIO;
1342                 goto escan;
1343         }
1344
1345         if (this->ecc.mode == NAND_ECC_HW) {
1346                 if (nfc_is_v1())
1347                         this->ecc.strength = 1;
1348                 else
1349                         this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1350         }
1351
1352         /* Register the partitions */
1353         mtd_device_parse_register(mtd, part_probes, NULL, pdata->parts,
1354                                   pdata->nr_parts);
1355
1356         platform_set_drvdata(pdev, host);
1357
1358         return 0;
1359
1360 escan:
1361         free_irq(host->irq, host);
1362 eirq:
1363         if (host->regs_ip)
1364                 iounmap(host->regs_ip);
1365         iounmap(host->base);
1366 eres:
1367         clk_put(host->clk);
1368 eclk:
1369         kfree(host);
1370
1371         return err;
1372 }
1373
1374 static int __devexit mxcnd_remove(struct platform_device *pdev)
1375 {
1376         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1377
1378         clk_put(host->clk);
1379
1380         platform_set_drvdata(pdev, NULL);
1381
1382         nand_release(&host->mtd);
1383         free_irq(host->irq, host);
1384         if (host->regs_ip)
1385                 iounmap(host->regs_ip);
1386         iounmap(host->base);
1387         kfree(host);
1388
1389         return 0;
1390 }
1391
1392 static struct platform_driver mxcnd_driver = {
1393         .driver = {
1394                    .name = DRIVER_NAME,
1395                    .owner = THIS_MODULE,
1396         },
1397         .remove = __devexit_p(mxcnd_remove),
1398 };
1399
1400 static int __init mxc_nd_init(void)
1401 {
1402         return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1403 }
1404
1405 static void __exit mxc_nd_cleanup(void)
1406 {
1407         /* Unregister the device structure */
1408         platform_driver_unregister(&mxcnd_driver);
1409 }
1410
1411 module_init(mxc_nd_init);
1412 module_exit(mxc_nd_cleanup);
1413
1414 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1415 MODULE_DESCRIPTION("MXC NAND MTD driver");
1416 MODULE_LICENSE("GPL");