2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #include <linux/err.h>
28 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
29 defined(CONFIG_MX51) || defined(CONFIG_MX53)
30 #include <asm/arch/imx-regs.h>
33 static struct mxc_nand_host mxc_host;
34 static struct mxc_nand_host *host = &mxc_host;
37 static int is_16bit_nand(void)
39 struct system_control_regs *sc_regs =
40 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
42 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
47 #elif defined(CONFIG_MX31)
48 static int is_16bit_nand(void)
50 struct clock_control_regs *sc_regs =
51 (struct clock_control_regs *)CCM_BASE;
53 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
58 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
59 static int is_16bit_nand(void)
61 struct ccm_regs *ccm =
62 (struct ccm_regs *)IMX_CCM_BASE;
64 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
69 #elif defined(CONFIG_MX51)
70 static int is_16bit_nand(void)
72 struct src *src = (struct src *)SRC_BASE_ADDR;
74 if (readl(&src->sbmr) & (1 << 2))
79 #elif defined(CONFIG_MX53)
80 /* BOOT_CFG[1..3][0..7] */
81 #define SRC_BOOT_CFG(m, n) (1 << ((m) * 8 + (n)))
82 static int is_16bit_nand(void)
84 struct src *src = (struct src *)SRC_BASE_ADDR;
86 if (readl(&src->sbmr) & SRC_BOOT_CFG(2, 5))
92 #warning "8/16 bit NAND autodetection not supported"
93 static int is_16bit_nand(void)
99 #define MXC_NAND_TIMEOUT (1 * HZ)
101 #define DRIVER_NAME "mxc_nand"
103 #ifndef CONFIG_MXC_NAND_REGS_BASE
104 #error CONFIG_MXC_NAND_REGS_BASE not defined
107 #if defined(CONFIG_MX27) || defined(CONFIG_MX31)
108 #define nfc_is_v1() 1
109 #define nfc_is_v21() 0
110 #define nfc_is_v3_2() 0
111 #define nfc_is_v3() nfc_is_v3_2()
112 #define NFC_VERSION "V1"
113 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
114 #define nfc_is_v1() 0
115 #define nfc_is_v21() 1
116 #define nfc_is_v3_2() 0
117 #define nfc_is_v3() nfc_is_v3_2()
118 #define NFC_VERSION "V2"
119 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
120 #define nfc_is_v1() 0
121 #define nfc_is_v21() 0
122 #define nfc_is_v3_2() 1
123 #define nfc_is_v3() nfc_is_v3_2()
124 #define NFC_VERSION "V3"
125 #ifndef CONFIG_MXC_NAND_IP_REGS_BASE
126 #error CONFIG_MXC_NAND_IP_REGS_BASE not defined
129 #error mxc_nand driver not supported on this platform
130 #define NFC_VERSION "unknown"
133 #ifndef CONFIG_MXC_NAND_IP_REGS_BASE
134 #define CONFIG_MXC_NAND_IP_REGS_BASE 0
137 /* Addresses for NFC registers */
138 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
139 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
140 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
141 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
142 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
143 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
144 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
145 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
146 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
147 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
148 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
149 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
150 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
151 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
152 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
153 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
154 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
155 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
156 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
157 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
158 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
159 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
161 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
162 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
163 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
164 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
165 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
166 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
167 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
168 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
169 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
170 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
172 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
175 * Operation modes for the NFC. Valid for v1, v2 and v3
178 #define NFC_CMD (1 << 0)
179 #define NFC_ADDR (1 << 1)
180 #define NFC_INPUT (1 << 2)
181 #define NFC_OUTPUT (1 << 3)
182 #define NFC_ID (1 << 4)
183 #define NFC_STATUS (1 << 5)
185 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
186 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
188 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
189 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
190 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
192 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
194 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
196 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
197 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
198 #define NFC_V3_WRPROT_LOCK (1 << 1)
199 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
200 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
202 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
204 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
205 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
206 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
207 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
208 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
209 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
210 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
211 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
212 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
213 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
214 #define MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8)
215 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
216 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
217 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
218 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
220 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
221 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
222 #define NFC_V3_CONFIG3_FW8 (1 << 3)
223 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
224 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
225 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
226 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
228 #define NFC_V3_IPC (host->regs_ip + 0x2C)
229 #define NFC_V3_IPC_CREQ (1 << 0)
230 #define NFC_V3_IPC_CACK (1 << 1)
231 #define NFC_V3_IPC_INT (1 << 31)
233 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
235 struct mxc_nand_host {
237 struct nand_chip nand;
244 void __iomem *regs_axi;
245 void __iomem *regs_ip;
251 unsigned int buf_start;
254 void (*preset)(struct mtd_info *);
255 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
256 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
257 void (*send_page)(struct mtd_info *, unsigned int);
258 void (*send_read_id)(struct mxc_nand_host *);
259 uint16_t (*get_dev_status)(struct mxc_nand_host *);
260 int (*check_int)(struct mxc_nand_host *);
263 /* OOB placement block for use with hardware ecc generation */
264 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
266 .eccpos = {6, 7, 8, 9, 10},
267 .oobfree = {{0, 5}, {12, 4}, }
270 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
272 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
273 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
274 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
277 /* OOB description for 512 byte pages with 16 byte OOB */
278 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
281 7, 8, 9, 10, 11, 12, 13, 14, 15
284 {.offset = 0, .length = 5}
288 /* OOB description for 2048 byte pages with 64 byte OOB */
289 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
292 7, 8, 9, 10, 11, 12, 13, 14, 15,
293 23, 24, 25, 26, 27, 28, 29, 30, 31,
294 39, 40, 41, 42, 43, 44, 45, 46, 47,
295 55, 56, 57, 58, 59, 60, 61, 62, 63
298 {.offset = 2, .length = 4},
299 {.offset = 16, .length = 7},
300 {.offset = 32, .length = 7},
301 {.offset = 48, .length = 7}
305 /* OOB description for 4096 byte pages with 128 byte OOB */
306 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
309 7, 8, 9, 10, 11, 12, 13, 14, 15,
310 23, 24, 25, 26, 27, 28, 29, 30, 31,
311 39, 40, 41, 42, 43, 44, 45, 46, 47,
312 55, 56, 57, 58, 59, 60, 61, 62, 63,
313 71, 72, 73, 74, 75, 76, 77, 78, 79,
314 87, 88, 89, 90, 91, 92, 93, 94, 95,
315 103, 104, 105, 106, 107, 108, 109, 110, 111,
316 119, 120, 121, 122, 123, 124, 125, 126, 127,
319 {.offset = 2, .length = 4},
320 {.offset = 16, .length = 7},
321 {.offset = 32, .length = 7},
322 {.offset = 48, .length = 7},
323 {.offset = 64, .length = 7},
324 {.offset = 80, .length = 7},
325 {.offset = 96, .length = 7},
326 {.offset = 112, .length = 7},
330 static int check_int_v3(struct mxc_nand_host *host)
334 tmp = readl(NFC_V3_IPC);
335 if (!(tmp & NFC_V3_IPC_INT))
338 tmp &= ~NFC_V3_IPC_INT;
339 writel(tmp, NFC_V3_IPC);
344 static int check_int_v1_v2(struct mxc_nand_host *host)
348 tmp = readw(NFC_V1_V2_CONFIG2);
349 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
352 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
357 /* This function polls the NANDFC to wait for the basic operation to
358 * complete by checking the INT bit of config2 register.
360 static void wait_op_done(struct mxc_nand_host *host, bool useirq)
362 int max_retries = 8000;
364 while (max_retries-- > 0) {
365 if (host->check_int(host))
371 pr_debug("%s: INT not set\n", __func__);
374 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
377 writel(cmd, NFC_V3_FLASH_CMD);
379 /* send out command */
380 writel(NFC_CMD, NFC_V3_LAUNCH);
382 /* Wait for operation to complete */
383 wait_op_done(host, useirq);
386 /* This function issues the specified command to the NAND device and
387 * waits for completion. */
388 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
390 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
392 writew(cmd, NFC_V1_V2_FLASH_CMD);
393 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
395 /* Wait for operation to complete */
396 wait_op_done(host, useirq);
399 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
402 writel(addr, NFC_V3_FLASH_ADDR0);
404 /* send out address */
405 writel(NFC_ADDR, NFC_V3_LAUNCH);
407 wait_op_done(host, islast);
410 /* This function sends an address (or partial address) to the
411 * NAND device. The address is used to select the source/destination for
413 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
415 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
417 writew(addr, NFC_V1_V2_FLASH_ADDR);
418 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
420 /* Wait for operation to complete */
421 wait_op_done(host, islast);
424 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
426 struct nand_chip *nand_chip = mtd->priv;
427 struct mxc_nand_host *host = nand_chip->priv;
430 tmp = readl(NFC_V3_CONFIG1);
432 writel(tmp, NFC_V3_CONFIG1);
434 /* transfer data from NFC ram to nand */
435 writel(ops, NFC_V3_LAUNCH);
437 wait_op_done(host, false);
440 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
442 struct nand_chip *nand_chip = mtd->priv;
443 struct mxc_nand_host *host = nand_chip->priv;
446 if (nfc_is_v1() && mtd->writesize > 512)
451 for (i = 0; i < bufs; i++) {
453 /* NANDFC buffer 0 is used for page read/write */
454 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
456 writew(ops, NFC_V1_V2_CONFIG2);
458 /* Wait for operation to complete */
459 wait_op_done(host, true);
463 static void send_read_id_v3(struct mxc_nand_host *host)
465 /* Read ID into main buffer */
466 writel(NFC_ID, NFC_V3_LAUNCH);
468 wait_op_done(host, true);
470 memcpy(host->data_buf, host->main_area0, 16);
472 pr_debug("read ID %02x %02x %02x %02x\n",
473 host->data_buf[0], host->data_buf[1],
474 host->data_buf[2], host->data_buf[3]);
477 /* Request the NANDFC to perform a read of the NAND device ID. */
478 static void send_read_id_v1_v2(struct mxc_nand_host *host)
480 struct nand_chip *this = &host->nand;
482 /* NANDFC buffer 0 is used for device ID output */
483 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
485 writew(NFC_ID, NFC_V1_V2_CONFIG2);
487 /* Wait for operation to complete */
488 wait_op_done(host, true);
490 memcpy(host->data_buf, host->main_area0, 16);
492 if (this->options & NAND_BUSWIDTH_16) {
493 /* compress the ID info */
494 host->data_buf[1] = host->data_buf[2];
495 host->data_buf[2] = host->data_buf[4];
496 host->data_buf[3] = host->data_buf[6];
497 host->data_buf[4] = host->data_buf[8];
498 host->data_buf[5] = host->data_buf[10];
502 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
504 writel(NFC_STATUS, NFC_V3_LAUNCH);
505 wait_op_done(host, true);
507 return readl(NFC_V3_CONFIG1) >> 16;
510 /* This function requests the NANDFC to perform a read of the
511 * NAND device status and returns the current status. */
512 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
514 void __iomem *main_buf = host->main_area0;
518 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
521 * The device status is stored in main_area0. To
522 * prevent corruption of the buffer save the value
523 * and restore it afterwards.
525 store = readl(main_buf);
527 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
528 wait_op_done(host, true);
530 ret = readw(main_buf);
532 writel(store, main_buf);
537 /* This functions is used by upper layer to checks if device is ready */
538 static int mxc_nand_dev_ready(struct mtd_info *mtd)
541 * NFC handles R/B internally. Therefore, this function
542 * always returns status as ready.
547 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
550 * If HW ECC is enabled, we turn it on during init. There is
551 * no need to enable again here.
555 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
556 u_char *read_ecc, u_char *calc_ecc)
558 struct nand_chip *nand_chip = mtd->priv;
559 struct mxc_nand_host *host = nand_chip->priv;
562 * 1-Bit errors are automatically corrected in HW. No need for
563 * additional correction. 2-Bit errors cannot be corrected by
564 * HW ECC, so we need to return failure
566 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
568 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
569 printk("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
576 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
577 u_char *read_ecc, u_char *calc_ecc)
579 struct nand_chip *nand_chip = mtd->priv;
580 struct mxc_nand_host *host = nand_chip->priv;
584 u8 ecc_bit_mask, err_limit;
586 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
587 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
589 no_subpages = mtd->writesize >> 9;
592 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
594 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
597 err = ecc_stat & ecc_bit_mask;
598 if (err > err_limit) {
599 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
605 } while (--no_subpages);
607 mtd->ecc_stats.corrected += ret;
609 pr_debug("%d Symbol Correctable RS-ECC Errors\n", ret);
614 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
620 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
622 struct nand_chip *nand_chip = mtd->priv;
623 struct mxc_nand_host *host = nand_chip->priv;
626 /* Check for status request */
627 if (host->status_request)
628 return host->get_dev_status(host) & 0xFF;
630 ret = *(uint8_t *)(host->data_buf + host->buf_start);
636 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
638 struct nand_chip *nand_chip = mtd->priv;
639 struct mxc_nand_host *host = nand_chip->priv;
642 ret = *(uint16_t *)(host->data_buf + host->buf_start);
643 host->buf_start += 2;
648 /* Write data of length len to buffer buf. The data to be
649 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
650 * Operation by the NFC, the data is written to NAND Flash */
651 static void mxc_nand_write_buf(struct mtd_info *mtd,
652 const u_char *buf, int len)
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
656 u16 col = host->buf_start;
657 int n = mtd->oobsize + mtd->writesize - col;
661 memcpy(host->data_buf + col, buf, n);
663 host->buf_start += n;
666 /* Read the data buffer from the NAND Flash. To read the data from NAND
667 * Flash first the data output cycle is initiated by the NFC, which copies
668 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
670 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
672 struct nand_chip *nand_chip = mtd->priv;
673 struct mxc_nand_host *host = nand_chip->priv;
674 u16 col = host->buf_start;
675 int n = mtd->oobsize + mtd->writesize - col;
679 memcpy(buf, host->data_buf + col, n);
681 host->buf_start += n;
684 /* Used by the upper layer to verify the data in NAND Flash
685 * with the data in the buf. */
686 static int mxc_nand_verify_buf(struct mtd_info *mtd,
687 const u_char *buf, int len)
692 /* This function is used by upper layer for select and
693 * deselect of the NAND chip */
694 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
696 struct nand_chip *nand_chip = mtd->priv;
697 struct mxc_nand_host *host = nand_chip->priv;
700 host->active_cs = chip;
701 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
706 * Function to transfer data to/from spare area.
708 static void copy_spare(struct mtd_info *mtd, bool bfrom)
710 struct nand_chip *this = mtd->priv;
711 struct mxc_nand_host *host = this->priv;
713 u16 n = mtd->writesize >> 9;
714 u8 *d = host->data_buf + mtd->writesize;
715 u8 *s = host->spare0;
716 u16 t = host->spare_len;
718 j = (mtd->oobsize / n >> 1) << 1;
721 for (i = 0; i < n - 1; i++)
722 memcpy(d + i * j, s + i * t, j);
724 /* the last section */
725 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
727 for (i = 0; i < n - 1; i++)
728 memcpy(&s[i * t], &d[i * j], j);
730 /* the last section */
731 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
735 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
737 struct nand_chip *nand_chip = mtd->priv;
738 struct mxc_nand_host *host = nand_chip->priv;
740 /* Write out column address, if necessary */
743 * MXC NANDFC can only perform full page+spare or
744 * spare-only read/write. When the upper layers
745 * perform a read/write buf operation, the saved column
746 * address is used to index into the full page.
748 host->send_addr(host, 0, page_addr == -1);
749 if (mtd->writesize > 512)
750 /* another col addr cycle for 2k page */
751 host->send_addr(host, 0, false);
754 /* Write out page address, if necessary */
755 if (page_addr != -1) {
756 /* paddr_0 - p_addr_7 */
757 host->send_addr(host, (page_addr & 0xff), false);
759 if (mtd->writesize > 512) {
760 if (mtd->size >= 0x10000000) {
761 /* paddr_8 - paddr_15 */
762 host->send_addr(host, (page_addr >> 8) & 0xff, false);
763 host->send_addr(host, (page_addr >> 16) & 0xff, true);
765 /* paddr_8 - paddr_15 */
766 host->send_addr(host, (page_addr >> 8) & 0xff, true);
768 /* One more address cycle for higher density devices */
769 if (mtd->size >= 0x4000000) {
770 /* paddr_8 - paddr_15 */
771 host->send_addr(host, (page_addr >> 8) & 0xff, false);
772 host->send_addr(host, (page_addr >> 16) & 0xff, true);
774 /* paddr_8 - paddr_15 */
775 host->send_addr(host, (page_addr >> 8) & 0xff, true);
781 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
782 * on how much oob the nand chip has. For 8bit ecc we need at least
783 * 26 bytes of oob data per 512 byte block.
785 static int get_eccsize(struct mtd_info *mtd)
787 int oobbytes_per_512 = 0;
789 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
791 if (oobbytes_per_512 < 26)
797 static void preset_v1_v2(struct mtd_info *mtd)
799 struct nand_chip *nand_chip = mtd->priv;
800 struct mxc_nand_host *host = nand_chip->priv;
801 uint16_t config1 = 0;
803 if (nand_chip->ecc.mode == NAND_ECC_HW)
804 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
807 config1 |= NFC_V2_CONFIG1_FP_INT;
809 if (nfc_is_v21() && mtd->writesize) {
810 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
812 host->eccsize = get_eccsize(mtd);
813 if (host->eccsize == 4)
814 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
816 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
821 writew(config1, NFC_V1_V2_CONFIG1);
822 /* preset operation */
824 /* Unlock the internal RAM Buffer */
825 writew(0x2, NFC_V1_V2_CONFIG);
827 /* Blocks to be unlocked */
829 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
830 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
831 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
832 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
833 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
834 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
835 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
836 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
837 } else if (nfc_is_v1()) {
838 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
839 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
843 /* Unlock Block Command for given address range */
844 writew(0x4, NFC_V1_V2_WRPROT);
847 static void preset_v3(struct mtd_info *mtd)
849 struct nand_chip *chip = mtd->priv;
850 struct mxc_nand_host *host = chip->priv;
851 uint32_t config2, config3;
854 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
855 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
856 WARN_ON(!(readl(NFC_V3_IPC) & NFC_V3_IPC_CACK));
858 /* Unlock the internal RAM Buffer */
859 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
862 /* Blocks to be unlocked */
863 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++)
864 writel(0x0 | (0xffff << 16),
865 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
867 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
868 NFC_V3_CONFIG2_2CMD_PHASES |
869 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
870 NFC_V3_CONFIG2_ST_CMD(0x70) |
871 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
873 if (chip->ecc.mode == NAND_ECC_HW)
874 config2 |= NFC_V3_CONFIG2_ECC_EN;
876 addr_phases = fls(chip->pagemask) >> 3;
878 if (mtd->writesize == 2048) {
879 config2 |= NFC_V3_CONFIG2_PS_2048;
880 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
881 } else if (mtd->writesize == 4096) {
882 config2 |= NFC_V3_CONFIG2_PS_4096;
883 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
885 config2 |= NFC_V3_CONFIG2_PS_512;
886 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
889 if (mtd->writesize) {
890 #if defined CONFIG_MX53
891 config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
893 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
895 host->eccsize = get_eccsize(mtd);
896 if (host->eccsize == 8)
897 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
900 writel(config2, NFC_V3_CONFIG2);
902 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
903 NFC_V3_CONFIG3_NO_SDMA |
904 NFC_V3_CONFIG3_RBB_MODE |
905 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
906 NFC_V3_CONFIG3_ADD_OP(0);
908 if (!(chip->options & NAND_BUSWIDTH_16))
909 config3 |= NFC_V3_CONFIG3_FW8;
911 writel(config3, NFC_V3_CONFIG3);
913 writel(0, NFC_V3_DELAY_LINE);
914 writel(0, NFC_V3_IPC);
917 /* Used by the upper layer to write command to NAND Flash for
918 * different operations to be carried out on NAND Flash */
919 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
920 int column, int page_addr)
922 struct nand_chip *nand_chip = mtd->priv;
923 struct mxc_nand_host *host = nand_chip->priv;
925 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
926 command, column, page_addr);
928 /* Reset command state information */
929 host->status_request = false;
931 /* Command pre-processing step */
935 host->send_cmd(host, command, false);
938 case NAND_CMD_STATUS:
940 host->status_request = true;
942 host->send_cmd(host, command, true);
943 mxc_do_addr_cycle(mtd, column, page_addr);
947 case NAND_CMD_READOOB:
948 if (command == NAND_CMD_READ0)
949 host->buf_start = column;
951 host->buf_start = column + mtd->writesize;
953 command = NAND_CMD_READ0; /* only READ0 is valid */
955 host->send_cmd(host, command, false);
956 mxc_do_addr_cycle(mtd, column, page_addr);
958 if (mtd->writesize > 512)
959 host->send_cmd(host, NAND_CMD_READSTART, true);
961 host->send_page(mtd, NFC_OUTPUT);
963 memcpy(host->data_buf, host->main_area0, mtd->writesize);
964 copy_spare(mtd, true);
968 if (column >= mtd->writesize)
969 /* call ourself to read a page */
970 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
972 host->buf_start = column;
974 host->send_cmd(host, command, false);
975 mxc_do_addr_cycle(mtd, column, page_addr);
978 case NAND_CMD_PAGEPROG:
979 memcpy(host->main_area0, host->data_buf, mtd->writesize);
980 copy_spare(mtd, false);
981 host->send_page(mtd, NFC_INPUT);
982 host->send_cmd(host, command, true);
983 mxc_do_addr_cycle(mtd, column, page_addr);
986 case NAND_CMD_READID:
987 host->send_cmd(host, command, true);
988 mxc_do_addr_cycle(mtd, column, page_addr);
989 host->send_read_id(host);
990 host->buf_start = column;
993 case NAND_CMD_ERASE1:
994 case NAND_CMD_ERASE2:
995 host->send_cmd(host, command, false);
996 mxc_do_addr_cycle(mtd, column, page_addr);
1003 * The generic flash bbt decriptors overlap with our ecc
1004 * hardware, so define some i.MX specific ones.
1006 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1007 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1009 static struct nand_bbt_descr bbt_main_descr = {
1010 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
1011 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1016 .pattern = bbt_pattern,
1019 static struct nand_bbt_descr bbt_mirror_descr = {
1020 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
1021 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1026 .pattern = mirror_pattern,
1029 static void mxc_nand_chip_init(int devno)
1032 struct nand_chip *this;
1033 struct mtd_info *mtd = &nand_info[devno];
1034 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1036 /* allocate a minimal buffer for the read_id command */
1037 host->data_buf = malloc(16);
1038 if (!host->data_buf) {
1039 printk("Failed to allocate ID buffer\n");
1043 /* structures must be linked */
1047 mtd->name = DRIVER_NAME;
1049 /* 50 us command delay time */
1050 this->chip_delay = 5;
1053 this->dev_ready = mxc_nand_dev_ready;
1054 this->cmdfunc = mxc_nand_command;
1055 this->select_chip = mxc_nand_select_chip;
1056 this->read_byte = mxc_nand_read_byte;
1057 this->read_word = mxc_nand_read_word;
1058 this->write_buf = mxc_nand_write_buf;
1059 this->read_buf = mxc_nand_read_buf;
1060 this->verify_buf = mxc_nand_verify_buf;
1062 host->base = (void __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1067 host->main_area0 = host->base;
1069 if (nfc_is_v1() || nfc_is_v21()) {
1070 host->preset = preset_v1_v2;
1071 host->send_cmd = send_cmd_v1_v2;
1072 host->send_addr = send_addr_v1_v2;
1073 host->send_page = send_page_v1_v2;
1074 host->send_read_id = send_read_id_v1_v2;
1075 host->get_dev_status = get_dev_status_v1_v2;
1076 host->check_int = check_int_v1_v2;
1080 host->regs = host->base + 0x1e00;
1081 host->spare0 = host->base + 0x1000;
1082 host->spare_len = 64;
1083 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1084 oob_largepage = &nandv2_hw_eccoob_largepage;
1085 this->ecc.bytes = 9;
1086 } else if (nfc_is_v1()) {
1087 host->regs = host->base + 0xe00;
1088 host->spare0 = host->base + 0x800;
1089 host->spare_len = 16;
1090 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1091 oob_largepage = &nandv1_hw_eccoob_largepage;
1092 this->ecc.bytes = 3;
1094 } else if (nfc_is_v3_2()) {
1095 host->regs_ip = (void __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1096 host->regs_axi = host->base + 0x1e00;
1097 host->spare0 = host->base + 0x1000;
1098 host->spare_len = 64;
1099 host->preset = preset_v3;
1100 host->send_cmd = send_cmd_v3;
1101 host->send_addr = send_addr_v3;
1102 host->send_page = send_page_v3;
1103 host->send_read_id = send_read_id_v3;
1104 host->check_int = check_int_v3;
1105 host->get_dev_status = get_dev_status_v3;
1106 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1107 oob_largepage = &nandv2_hw_eccoob_largepage;
1108 this->ecc.strength = 4;
1112 this->ecc.size = 512;
1113 this->ecc.layout = oob_smallpage;
1115 #ifdef CONFIG_MXC_NAND_HWECC
1116 this->ecc.calculate = mxc_nand_calculate_ecc;
1117 this->ecc.hwctl = mxc_nand_enable_hwecc;
1119 this->ecc.correct = mxc_nand_correct_data_v1;
1121 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1122 this->ecc.mode = NAND_ECC_HW;
1124 this->ecc.mode = NAND_ECC_SOFT;
1126 /* NAND bus width determines access funtions used by upper layer */
1127 if (is_16bit_nand())
1128 this->options |= NAND_BUSWIDTH_16;
1130 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1131 this->bbt_options |= NAND_BBT_USE_FLASH;
1132 this->bbt_td = &bbt_main_descr;
1133 this->bbt_md = &bbt_mirror_descr;
1134 this->bbt_td->options |= NAND_BBT_CREATE;
1135 this->bbt_md->options |= NAND_BBT_CREATE;
1138 /* first scan to find the device and get the page size */
1139 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1143 host->data_buf = realloc(host->data_buf,
1144 mtd->writesize + mtd->oobsize);
1145 if (!host->data_buf) {
1146 printk("Failed to allocate data buffer of %u byte\n",
1147 mtd->writesize + mtd->oobsize);
1150 pr_debug("Allocated %u byte data buffer\n",
1151 mtd->writesize + mtd->oobsize);
1153 /* Call preset again, with correct writesize this time */
1156 if (mtd->writesize == 2048)
1157 this->ecc.layout = oob_largepage;
1158 if (nfc_is_v21() && mtd->writesize == 4096)
1159 this->ecc.layout = &nandv2_hw_eccoob_4k;
1161 /* second phase scan */
1162 err = nand_scan_tail(mtd);
1164 printk("Nand scan failed: %d\n", err);
1168 err = nand_register(devno);
1173 void board_nand_init(void)
1177 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1178 mxc_nand_chip_init(i);