2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
38 #define DRIVER_NAME "mxc_nand"
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
43 /* Addresses for NFC registers */
44 #define NFC_BUF_SIZE 0x00
45 #define NFC_BUF_ADDR 0x04
46 #define NFC_FLASH_ADDR 0x06
47 #define NFC_FLASH_CMD 0x08
48 #define NFC_CONFIG 0x0a
49 #define NFC_ECC_STATUS_RESULT 0x0c
50 #define NFC_RSLTMAIN_AREA 0x0e
51 #define NFC_RSLTSPARE_AREA 0x10
52 #define NFC_WRPROT 0x12
53 #define NFC_V1_UNLOCKSTART_BLKADDR 0x14
54 #define NFC_V1_UNLOCKEND_BLKADDR 0x16
55 #define NFC_V21_UNLOCKSTART_BLKADDR 0x20
56 #define NFC_V21_UNLOCKEND_BLKADDR 0x22
57 #define NFC_NF_WRPRST 0x18
58 #define NFC_CONFIG1 0x1a
59 #define NFC_CONFIG2 0x1c
61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
62 * for Command operation */
65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
66 * for Address operation */
69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
70 * for Input operation */
73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
74 * for Data Output operation */
75 #define NFC_OUTPUT 0x8
77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
78 * for Read ID operation */
81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
82 * for Read Status operation */
83 #define NFC_STATUS 0x20
85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
87 #define NFC_INT 0x8000
89 #define NFC_SP_EN (1 << 2)
90 #define NFC_ECC_EN (1 << 3)
91 #define NFC_INT_MSK (1 << 4)
92 #define NFC_BIG (1 << 5)
93 #define NFC_RST (1 << 6)
94 #define NFC_CE (1 << 7)
95 #define NFC_ONE_CYCLE (1 << 8)
97 struct mxc_nand_host {
99 struct nand_chip nand;
100 struct mtd_partition *parts;
113 wait_queue_head_t irq_waitq;
116 unsigned int buf_start;
119 void (*preset)(struct mtd_info *);
120 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
121 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
122 void (*send_page)(struct mtd_info *, unsigned int);
123 void (*send_read_id)(struct mxc_nand_host *);
124 uint16_t (*get_dev_status)(struct mxc_nand_host *);
125 int (*check_int)(struct mxc_nand_host *);
128 /* OOB placement block for use with hardware ecc generation */
129 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
131 .eccpos = {6, 7, 8, 9, 10},
132 .oobfree = {{0, 5}, {12, 4}, }
135 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
137 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
138 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
139 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
142 /* OOB description for 512 byte pages with 16 byte OOB */
143 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
146 7, 8, 9, 10, 11, 12, 13, 14, 15
149 {.offset = 0, .length = 5}
153 /* OOB description for 2048 byte pages with 64 byte OOB */
154 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
157 7, 8, 9, 10, 11, 12, 13, 14, 15,
158 23, 24, 25, 26, 27, 28, 29, 30, 31,
159 39, 40, 41, 42, 43, 44, 45, 46, 47,
160 55, 56, 57, 58, 59, 60, 61, 62, 63
163 {.offset = 2, .length = 4},
164 {.offset = 16, .length = 7},
165 {.offset = 32, .length = 7},
166 {.offset = 48, .length = 7}
170 #ifdef CONFIG_MTD_PARTITIONS
171 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
174 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
176 struct mxc_nand_host *host = dev_id;
178 disable_irq_nosync(irq);
180 wake_up(&host->irq_waitq);
185 static int check_int_v1_v2(struct mxc_nand_host *host)
189 tmp = readw(host->regs + NFC_CONFIG2);
190 if (!(tmp & NFC_INT))
193 writew(tmp & ~NFC_INT, NFC_CONFIG2);
198 /* This function polls the NANDFC to wait for the basic operation to
199 * complete by checking the INT bit of config2 register.
201 static void wait_op_done(struct mxc_nand_host *host, int useirq)
203 int max_retries = 8000;
206 if (!host->check_int(host)) {
208 enable_irq(host->irq);
210 wait_event(host->irq_waitq, host->check_int(host));
213 while (max_retries-- > 0) {
214 if (host->check_int(host))
220 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
225 /* This function issues the specified command to the NAND device and
226 * waits for completion. */
227 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
229 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
231 writew(cmd, host->regs + NFC_FLASH_CMD);
232 writew(NFC_CMD, host->regs + NFC_CONFIG2);
234 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
235 int max_retries = 100;
236 /* Reset completion is indicated by NFC_CONFIG2 */
238 while (max_retries-- > 0) {
239 if (readw(host->regs + NFC_CONFIG2) == 0) {
245 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
248 /* Wait for operation to complete */
249 wait_op_done(host, useirq);
253 /* This function sends an address (or partial address) to the
254 * NAND device. The address is used to select the source/destination for
256 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
258 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
260 writew(addr, host->regs + NFC_FLASH_ADDR);
261 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
263 /* Wait for operation to complete */
264 wait_op_done(host, islast);
267 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
269 struct nand_chip *nand_chip = mtd->priv;
270 struct mxc_nand_host *host = nand_chip->priv;
273 if (nfc_is_v1() && mtd->writesize > 512)
278 for (i = 0; i < bufs; i++) {
280 /* NANDFC buffer 0 is used for page read/write */
281 writew(i, host->regs + NFC_BUF_ADDR);
283 writew(ops, host->regs + NFC_CONFIG2);
285 /* Wait for operation to complete */
286 wait_op_done(host, true);
290 /* Request the NANDFC to perform a read of the NAND device ID. */
291 static void send_read_id_v1_v2(struct mxc_nand_host *host)
293 struct nand_chip *this = &host->nand;
295 /* NANDFC buffer 0 is used for device ID output */
296 writew(0x0, host->regs + NFC_BUF_ADDR);
298 writew(NFC_ID, host->regs + NFC_CONFIG2);
300 /* Wait for operation to complete */
301 wait_op_done(host, true);
303 if (this->options & NAND_BUSWIDTH_16) {
304 void __iomem *main_buf = host->main_area0;
305 /* compress the ID info */
306 writeb(readb(main_buf + 2), main_buf + 1);
307 writeb(readb(main_buf + 4), main_buf + 2);
308 writeb(readb(main_buf + 6), main_buf + 3);
309 writeb(readb(main_buf + 8), main_buf + 4);
310 writeb(readb(main_buf + 10), main_buf + 5);
312 memcpy(host->data_buf, host->main_area0, 16);
315 /* This function requests the NANDFC to perform a read of the
316 * NAND device status and returns the current status. */
317 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
319 void __iomem *main_buf = host->main_area0;
323 writew(0x0, NFC_V1_V2_BUF_ADDR);
326 * The device status is stored in main_area0. To
327 * prevent corruption of the buffer save the value
328 * and restore it afterwards.
330 store = readl(main_buf);
332 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
333 wait_op_done(host, true);
335 ret = readw(main_buf);
337 writel(store, main_buf);
342 /* This functions is used by upper layer to checks if device is ready */
343 static int mxc_nand_dev_ready(struct mtd_info *mtd)
346 * NFC handles R/B internally. Therefore, this function
347 * always returns status as ready.
352 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
355 * If HW ECC is enabled, we turn it on during init. There is
356 * no need to enable again here.
360 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
361 u_char *read_ecc, u_char *calc_ecc)
363 struct nand_chip *nand_chip = mtd->priv;
364 struct mxc_nand_host *host = nand_chip->priv;
367 * 1-Bit errors are automatically corrected in HW. No need for
368 * additional correction. 2-Bit errors cannot be corrected by
369 * HW ECC, so we need to return failure
371 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
373 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
374 DEBUG(MTD_DEBUG_LEVEL0,
375 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
382 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
388 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
390 struct nand_chip *nand_chip = mtd->priv;
391 struct mxc_nand_host *host = nand_chip->priv;
394 /* Check for status request */
395 if (host->status_request)
396 return host->get_dev_status(host) & 0xFF;
398 ret = *(uint8_t *)(host->data_buf + host->buf_start);
404 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
406 struct nand_chip *nand_chip = mtd->priv;
407 struct mxc_nand_host *host = nand_chip->priv;
410 ret = *(uint16_t *)(host->data_buf + host->buf_start);
411 host->buf_start += 2;
416 /* Write data of length len to buffer buf. The data to be
417 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
418 * Operation by the NFC, the data is written to NAND Flash */
419 static void mxc_nand_write_buf(struct mtd_info *mtd,
420 const u_char *buf, int len)
422 struct nand_chip *nand_chip = mtd->priv;
423 struct mxc_nand_host *host = nand_chip->priv;
424 u16 col = host->buf_start;
425 int n = mtd->oobsize + mtd->writesize - col;
429 memcpy(host->data_buf + col, buf, n);
431 host->buf_start += n;
434 /* Read the data buffer from the NAND Flash. To read the data from NAND
435 * Flash first the data output cycle is initiated by the NFC, which copies
436 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
438 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
440 struct nand_chip *nand_chip = mtd->priv;
441 struct mxc_nand_host *host = nand_chip->priv;
442 u16 col = host->buf_start;
443 int n = mtd->oobsize + mtd->writesize - col;
447 memcpy(buf, host->data_buf + col, len);
449 host->buf_start += len;
452 /* Used by the upper layer to verify the data in NAND Flash
453 * with the data in the buf. */
454 static int mxc_nand_verify_buf(struct mtd_info *mtd,
455 const u_char *buf, int len)
460 /* This function is used by upper layer for select and
461 * deselect of the NAND chip */
462 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
464 struct nand_chip *nand_chip = mtd->priv;
465 struct mxc_nand_host *host = nand_chip->priv;
469 /* Disable the NFC clock */
471 clk_disable(host->clk);
476 /* Enable the NFC clock */
477 if (!host->clk_act) {
478 clk_enable(host->clk);
489 * Function to transfer data to/from spare area.
491 static void copy_spare(struct mtd_info *mtd, bool bfrom)
493 struct nand_chip *this = mtd->priv;
494 struct mxc_nand_host *host = this->priv;
496 u16 n = mtd->writesize >> 9;
497 u8 *d = host->data_buf + mtd->writesize;
498 u8 *s = host->spare0;
499 u16 t = host->spare_len;
501 j = (mtd->oobsize / n >> 1) << 1;
504 for (i = 0; i < n - 1; i++)
505 memcpy(d + i * j, s + i * t, j);
507 /* the last section */
508 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
510 for (i = 0; i < n - 1; i++)
511 memcpy(&s[i * t], &d[i * j], j);
513 /* the last section */
514 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
518 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
520 struct nand_chip *nand_chip = mtd->priv;
521 struct mxc_nand_host *host = nand_chip->priv;
523 /* Write out column address, if necessary */
526 * MXC NANDFC can only perform full page+spare or
527 * spare-only read/write. When the upper layers
528 * layers perform a read/write buf operation,
529 * we will used the saved column address to index into
532 host->send_addr(host, 0, page_addr == -1);
533 if (mtd->writesize > 512)
534 /* another col addr cycle for 2k page */
535 host->send_addr(host, 0, false);
538 /* Write out page address, if necessary */
539 if (page_addr != -1) {
540 /* paddr_0 - p_addr_7 */
541 host->send_addr(host, (page_addr & 0xff), false);
543 if (mtd->writesize > 512) {
544 if (mtd->size >= 0x10000000) {
545 /* paddr_8 - paddr_15 */
546 host->send_addr(host, (page_addr >> 8) & 0xff, false);
547 host->send_addr(host, (page_addr >> 16) & 0xff, true);
549 /* paddr_8 - paddr_15 */
550 host->send_addr(host, (page_addr >> 8) & 0xff, true);
552 /* One more address cycle for higher density devices */
553 if (mtd->size >= 0x4000000) {
554 /* paddr_8 - paddr_15 */
555 host->send_addr(host, (page_addr >> 8) & 0xff, false);
556 host->send_addr(host, (page_addr >> 16) & 0xff, true);
558 /* paddr_8 - paddr_15 */
559 host->send_addr(host, (page_addr >> 8) & 0xff, true);
564 static void preset_v1_v2(struct mtd_info *mtd)
566 struct nand_chip *nand_chip = mtd->priv;
567 struct mxc_nand_host *host = nand_chip->priv;
570 /* enable interrupt, disable spare enable */
571 tmp = readw(host->regs + NFC_CONFIG1);
574 if (nand_chip->ecc.mode == NAND_ECC_HW) {
579 writew(tmp, host->regs + NFC_CONFIG1);
580 /* preset operation */
582 /* Unlock the internal RAM Buffer */
583 writew(0x2, host->regs + NFC_CONFIG);
585 /* Blocks to be unlocked */
587 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
588 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
589 } else if (nfc_is_v1()) {
590 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
591 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
595 /* Unlock Block Command for given address range */
596 writew(0x4, host->regs + NFC_WRPROT);
599 /* Used by the upper layer to write command to NAND Flash for
600 * different operations to be carried out on NAND Flash */
601 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
602 int column, int page_addr)
604 struct nand_chip *nand_chip = mtd->priv;
605 struct mxc_nand_host *host = nand_chip->priv;
607 DEBUG(MTD_DEBUG_LEVEL3,
608 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
609 command, column, page_addr);
611 /* Reset command state information */
612 host->status_request = false;
614 /* Command pre-processing step */
618 host->send_cmd(host, command, false);
621 case NAND_CMD_STATUS:
623 host->status_request = true;
625 host->send_cmd(host, command, true);
626 mxc_do_addr_cycle(mtd, column, page_addr);
630 case NAND_CMD_READOOB:
631 if (command == NAND_CMD_READ0)
632 host->buf_start = column;
634 host->buf_start = column + mtd->writesize;
636 command = NAND_CMD_READ0; /* only READ0 is valid */
638 host->send_cmd(host, command, false);
639 mxc_do_addr_cycle(mtd, column, page_addr);
641 if (mtd->writesize > 512)
642 host->send_cmd(host, NAND_CMD_READSTART, true);
644 host->send_page(mtd, NFC_OUTPUT);
646 memcpy(host->data_buf, host->main_area0, mtd->writesize);
647 copy_spare(mtd, true);
651 if (column >= mtd->writesize)
652 /* call ourself to read a page */
653 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
655 host->buf_start = column;
657 host->send_cmd(host, command, false);
658 mxc_do_addr_cycle(mtd, column, page_addr);
661 case NAND_CMD_PAGEPROG:
662 memcpy(host->main_area0, host->data_buf, mtd->writesize);
663 copy_spare(mtd, false);
664 host->send_page(mtd, NFC_INPUT);
665 host->send_cmd(host, command, true);
666 mxc_do_addr_cycle(mtd, column, page_addr);
669 case NAND_CMD_READID:
670 host->send_cmd(host, command, true);
671 mxc_do_addr_cycle(mtd, column, page_addr);
672 host->send_read_id(host);
673 host->buf_start = column;
676 case NAND_CMD_ERASE1:
677 case NAND_CMD_ERASE2:
678 host->send_cmd(host, command, false);
679 mxc_do_addr_cycle(mtd, column, page_addr);
686 * The generic flash bbt decriptors overlap with our ecc
687 * hardware, so define some i.MX specific ones.
689 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
690 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
692 static struct nand_bbt_descr bbt_main_descr = {
693 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
694 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
699 .pattern = bbt_pattern,
702 static struct nand_bbt_descr bbt_mirror_descr = {
703 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
704 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
709 .pattern = mirror_pattern,
712 static int __init mxcnd_probe(struct platform_device *pdev)
714 struct nand_chip *this;
715 struct mtd_info *mtd;
716 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
717 struct mxc_nand_host *host;
718 struct resource *res;
719 int err = 0, nr_parts = 0;
720 struct nand_ecclayout *oob_smallpage, *oob_largepage;
722 /* Allocate memory for MTD device structure and private data */
723 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
724 NAND_MAX_OOBSIZE, GFP_KERNEL);
728 host->data_buf = (uint8_t *)(host + 1);
730 host->dev = &pdev->dev;
731 /* structures must be linked */
735 mtd->owner = THIS_MODULE;
736 mtd->dev.parent = &pdev->dev;
737 mtd->name = DRIVER_NAME;
739 /* 50 us command delay time */
740 this->chip_delay = 5;
743 this->dev_ready = mxc_nand_dev_ready;
744 this->cmdfunc = mxc_nand_command;
745 this->select_chip = mxc_nand_select_chip;
746 this->read_byte = mxc_nand_read_byte;
747 this->read_word = mxc_nand_read_word;
748 this->write_buf = mxc_nand_write_buf;
749 this->read_buf = mxc_nand_read_buf;
750 this->verify_buf = mxc_nand_verify_buf;
752 host->clk = clk_get(&pdev->dev, "nfc");
753 if (IS_ERR(host->clk)) {
754 err = PTR_ERR(host->clk);
758 clk_enable(host->clk);
761 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
767 host->base = ioremap(res->start, resource_size(res));
773 host->main_area0 = host->base;
775 if (nfc_is_v1() || nfc_is_v21()) {
776 host->preset = preset_v1_v2;
777 host->send_cmd = send_cmd_v1_v2;
778 host->send_addr = send_addr_v1_v2;
779 host->send_page = send_page_v1_v2;
780 host->send_read_id = send_read_id_v1_v2;
781 host->get_dev_status = get_dev_status_v1_v2;
782 host->check_int = check_int_v1_v2;
786 host->regs = host->base + 0x1e00;
787 host->spare0 = host->base + 0x1000;
788 host->spare_len = 64;
789 oob_smallpage = &nandv2_hw_eccoob_smallpage;
790 oob_largepage = &nandv2_hw_eccoob_largepage;
792 } else if (nfc_is_v1()) {
793 host->regs = host->base + 0xe00;
794 host->spare0 = host->base + 0x800;
795 host->spare_len = 16;
796 oob_smallpage = &nandv1_hw_eccoob_smallpage;
797 oob_largepage = &nandv1_hw_eccoob_largepage;
802 this->ecc.size = 512;
803 this->ecc.layout = oob_smallpage;
806 this->ecc.calculate = mxc_nand_calculate_ecc;
807 this->ecc.hwctl = mxc_nand_enable_hwecc;
808 this->ecc.correct = mxc_nand_correct_data;
809 this->ecc.mode = NAND_ECC_HW;
811 this->ecc.mode = NAND_ECC_SOFT;
814 /* NAND bus width determines access funtions used by upper layer */
815 if (pdata->width == 2)
816 this->options |= NAND_BUSWIDTH_16;
818 if (pdata->flash_bbt) {
819 this->bbt_td = &bbt_main_descr;
820 this->bbt_md = &bbt_mirror_descr;
821 /* update flash based bbt */
822 this->options |= NAND_USE_FLASH_BBT;
825 init_waitqueue_head(&host->irq_waitq);
827 host->irq = platform_get_irq(pdev, 0);
829 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
833 /* first scan to find the device and get the page size */
834 if (nand_scan_ident(mtd, 1, NULL)) {
839 if (mtd->writesize == 2048)
840 this->ecc.layout = oob_largepage;
842 /* second phase scan */
843 if (nand_scan_tail(mtd)) {
848 /* Register the partitions */
849 #ifdef CONFIG_MTD_PARTITIONS
851 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
853 add_mtd_partitions(mtd, host->parts, nr_parts);
857 pr_info("Registering %s as whole device\n", mtd->name);
861 platform_set_drvdata(pdev, host);
866 free_irq(host->irq, host);
877 static int __devexit mxcnd_remove(struct platform_device *pdev)
879 struct mxc_nand_host *host = platform_get_drvdata(pdev);
883 platform_set_drvdata(pdev, NULL);
885 nand_release(&host->mtd);
886 free_irq(host->irq, host);
893 static struct platform_driver mxcnd_driver = {
897 .remove = __devexit_p(mxcnd_remove),
900 static int __init mxc_nd_init(void)
902 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
905 static void __exit mxc_nd_cleanup(void)
907 /* Unregister the device structure */
908 platform_driver_unregister(&mxcnd_driver);
911 module_init(mxc_nd_init);
912 module_exit(mxc_nd_cleanup);
914 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
915 MODULE_DESCRIPTION("MXC NAND MTD driver");
916 MODULE_LICENSE("GPL");