2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
38 #define DRIVER_NAME "mxc_nand"
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
43 /* Addresses for NFC registers */
44 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
45 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
46 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
47 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
48 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
49 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
50 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
51 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
52 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
53 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
54 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
55 #define NFC_V21_UNLOCKSTART_BLKADDR (host->regs + 0x20)
56 #define NFC_V21_UNLOCKEND_BLKADDR (host->regs + 0x22)
57 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
58 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
59 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
61 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
62 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
63 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
64 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
65 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
66 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
67 #define NFC_V1_V2_CONFIG1_ONE_CYCLE (1 << 8)
69 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
72 * Operation modes for the NFC. Valid for v1, v2 and v3
75 #define NFC_CMD (1 << 0)
76 #define NFC_ADDR (1 << 1)
77 #define NFC_INPUT (1 << 2)
78 #define NFC_OUTPUT (1 << 3)
79 #define NFC_ID (1 << 4)
80 #define NFC_STATUS (1 << 5)
82 struct mxc_nand_host {
84 struct nand_chip nand;
85 struct mtd_partition *parts;
99 wait_queue_head_t irq_waitq;
102 unsigned int buf_start;
105 void (*preset)(struct mtd_info *);
106 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
107 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
108 void (*send_page)(struct mtd_info *, unsigned int);
109 void (*send_read_id)(struct mxc_nand_host *);
110 uint16_t (*get_dev_status)(struct mxc_nand_host *);
111 int (*check_int)(struct mxc_nand_host *);
114 /* OOB placement block for use with hardware ecc generation */
115 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
117 .eccpos = {6, 7, 8, 9, 10},
118 .oobfree = {{0, 5}, {12, 4}, }
121 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
123 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
124 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
125 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
128 /* OOB description for 512 byte pages with 16 byte OOB */
129 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
132 7, 8, 9, 10, 11, 12, 13, 14, 15
135 {.offset = 0, .length = 5}
139 /* OOB description for 2048 byte pages with 64 byte OOB */
140 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
143 7, 8, 9, 10, 11, 12, 13, 14, 15,
144 23, 24, 25, 26, 27, 28, 29, 30, 31,
145 39, 40, 41, 42, 43, 44, 45, 46, 47,
146 55, 56, 57, 58, 59, 60, 61, 62, 63
149 {.offset = 2, .length = 4},
150 {.offset = 16, .length = 7},
151 {.offset = 32, .length = 7},
152 {.offset = 48, .length = 7}
156 #ifdef CONFIG_MTD_PARTITIONS
157 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
160 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
162 struct mxc_nand_host *host = dev_id;
164 disable_irq_nosync(irq);
166 wake_up(&host->irq_waitq);
171 static int check_int_v1_v2(struct mxc_nand_host *host)
175 tmp = readw(NFC_V1_V2_CONFIG2);
176 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
179 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
184 /* This function polls the NANDFC to wait for the basic operation to
185 * complete by checking the INT bit of config2 register.
187 static void wait_op_done(struct mxc_nand_host *host, int useirq)
189 int max_retries = 8000;
192 if (!host->check_int(host)) {
194 enable_irq(host->irq);
196 wait_event(host->irq_waitq, host->check_int(host));
199 while (max_retries-- > 0) {
200 if (host->check_int(host))
206 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
211 /* This function issues the specified command to the NAND device and
212 * waits for completion. */
213 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
215 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
217 writew(cmd, NFC_V1_V2_FLASH_CMD);
218 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
220 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
221 int max_retries = 100;
222 /* Reset completion is indicated by NFC_CONFIG2 */
224 while (max_retries-- > 0) {
225 if (readw(NFC_V1_V2_CONFIG2) == 0) {
231 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
234 /* Wait for operation to complete */
235 wait_op_done(host, useirq);
239 /* This function sends an address (or partial address) to the
240 * NAND device. The address is used to select the source/destination for
242 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
244 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
246 writew(addr, NFC_V1_V2_FLASH_ADDR);
247 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
249 /* Wait for operation to complete */
250 wait_op_done(host, islast);
253 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
255 struct nand_chip *nand_chip = mtd->priv;
256 struct mxc_nand_host *host = nand_chip->priv;
259 if (nfc_is_v1() && mtd->writesize > 512)
264 for (i = 0; i < bufs; i++) {
266 /* NANDFC buffer 0 is used for page read/write */
267 writew(i, NFC_V1_V2_BUF_ADDR);
269 writew(ops, NFC_V1_V2_CONFIG2);
271 /* Wait for operation to complete */
272 wait_op_done(host, true);
276 /* Request the NANDFC to perform a read of the NAND device ID. */
277 static void send_read_id_v1_v2(struct mxc_nand_host *host)
279 struct nand_chip *this = &host->nand;
281 /* NANDFC buffer 0 is used for device ID output */
282 writew(0x0, NFC_V1_V2_BUF_ADDR);
284 writew(NFC_ID, NFC_V1_V2_CONFIG2);
286 /* Wait for operation to complete */
287 wait_op_done(host, true);
289 if (this->options & NAND_BUSWIDTH_16) {
290 void __iomem *main_buf = host->main_area0;
291 /* compress the ID info */
292 writeb(readb(main_buf + 2), main_buf + 1);
293 writeb(readb(main_buf + 4), main_buf + 2);
294 writeb(readb(main_buf + 6), main_buf + 3);
295 writeb(readb(main_buf + 8), main_buf + 4);
296 writeb(readb(main_buf + 10), main_buf + 5);
298 memcpy(host->data_buf, host->main_area0, 16);
301 /* This function requests the NANDFC to perform a read of the
302 * NAND device status and returns the current status. */
303 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
305 void __iomem *main_buf = host->main_area0;
309 writew(0x0, NFC_V1_V2_BUF_ADDR);
312 * The device status is stored in main_area0. To
313 * prevent corruption of the buffer save the value
314 * and restore it afterwards.
316 store = readl(main_buf);
318 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
319 wait_op_done(host, true);
321 ret = readw(main_buf);
323 writel(store, main_buf);
328 /* This functions is used by upper layer to checks if device is ready */
329 static int mxc_nand_dev_ready(struct mtd_info *mtd)
332 * NFC handles R/B internally. Therefore, this function
333 * always returns status as ready.
338 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
341 * If HW ECC is enabled, we turn it on during init. There is
342 * no need to enable again here.
346 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
347 u_char *read_ecc, u_char *calc_ecc)
349 struct nand_chip *nand_chip = mtd->priv;
350 struct mxc_nand_host *host = nand_chip->priv;
353 * 1-Bit errors are automatically corrected in HW. No need for
354 * additional correction. 2-Bit errors cannot be corrected by
355 * HW ECC, so we need to return failure
357 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
359 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
360 DEBUG(MTD_DEBUG_LEVEL0,
361 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
368 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
369 u_char *read_ecc, u_char *calc_ecc)
371 struct nand_chip *nand_chip = mtd->priv;
372 struct mxc_nand_host *host = nand_chip->priv;
376 u8 ecc_bit_mask, err_limit;
378 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
379 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
381 no_subpages = mtd->writesize >> 9;
383 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
386 err = ecc_stat & ecc_bit_mask;
387 if (err > err_limit) {
388 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
394 } while (--no_subpages);
396 mtd->ecc_stats.corrected += ret;
397 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
402 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
408 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
410 struct nand_chip *nand_chip = mtd->priv;
411 struct mxc_nand_host *host = nand_chip->priv;
414 /* Check for status request */
415 if (host->status_request)
416 return host->get_dev_status(host) & 0xFF;
418 ret = *(uint8_t *)(host->data_buf + host->buf_start);
424 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
426 struct nand_chip *nand_chip = mtd->priv;
427 struct mxc_nand_host *host = nand_chip->priv;
430 ret = *(uint16_t *)(host->data_buf + host->buf_start);
431 host->buf_start += 2;
436 /* Write data of length len to buffer buf. The data to be
437 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
438 * Operation by the NFC, the data is written to NAND Flash */
439 static void mxc_nand_write_buf(struct mtd_info *mtd,
440 const u_char *buf, int len)
442 struct nand_chip *nand_chip = mtd->priv;
443 struct mxc_nand_host *host = nand_chip->priv;
444 u16 col = host->buf_start;
445 int n = mtd->oobsize + mtd->writesize - col;
449 memcpy(host->data_buf + col, buf, n);
451 host->buf_start += n;
454 /* Read the data buffer from the NAND Flash. To read the data from NAND
455 * Flash first the data output cycle is initiated by the NFC, which copies
456 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
458 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
460 struct nand_chip *nand_chip = mtd->priv;
461 struct mxc_nand_host *host = nand_chip->priv;
462 u16 col = host->buf_start;
463 int n = mtd->oobsize + mtd->writesize - col;
467 memcpy(buf, host->data_buf + col, len);
469 host->buf_start += len;
472 /* Used by the upper layer to verify the data in NAND Flash
473 * with the data in the buf. */
474 static int mxc_nand_verify_buf(struct mtd_info *mtd,
475 const u_char *buf, int len)
480 /* This function is used by upper layer for select and
481 * deselect of the NAND chip */
482 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
484 struct nand_chip *nand_chip = mtd->priv;
485 struct mxc_nand_host *host = nand_chip->priv;
489 /* Disable the NFC clock */
491 clk_disable(host->clk);
496 /* Enable the NFC clock */
497 if (!host->clk_act) {
498 clk_enable(host->clk);
509 * Function to transfer data to/from spare area.
511 static void copy_spare(struct mtd_info *mtd, bool bfrom)
513 struct nand_chip *this = mtd->priv;
514 struct mxc_nand_host *host = this->priv;
516 u16 n = mtd->writesize >> 9;
517 u8 *d = host->data_buf + mtd->writesize;
518 u8 *s = host->spare0;
519 u16 t = host->spare_len;
521 j = (mtd->oobsize / n >> 1) << 1;
524 for (i = 0; i < n - 1; i++)
525 memcpy(d + i * j, s + i * t, j);
527 /* the last section */
528 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
530 for (i = 0; i < n - 1; i++)
531 memcpy(&s[i * t], &d[i * j], j);
533 /* the last section */
534 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
538 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
540 struct nand_chip *nand_chip = mtd->priv;
541 struct mxc_nand_host *host = nand_chip->priv;
543 /* Write out column address, if necessary */
546 * MXC NANDFC can only perform full page+spare or
547 * spare-only read/write. When the upper layers
548 * layers perform a read/write buf operation,
549 * we will used the saved column address to index into
552 host->send_addr(host, 0, page_addr == -1);
553 if (mtd->writesize > 512)
554 /* another col addr cycle for 2k page */
555 host->send_addr(host, 0, false);
558 /* Write out page address, if necessary */
559 if (page_addr != -1) {
560 /* paddr_0 - p_addr_7 */
561 host->send_addr(host, (page_addr & 0xff), false);
563 if (mtd->writesize > 512) {
564 if (mtd->size >= 0x10000000) {
565 /* paddr_8 - paddr_15 */
566 host->send_addr(host, (page_addr >> 8) & 0xff, false);
567 host->send_addr(host, (page_addr >> 16) & 0xff, true);
569 /* paddr_8 - paddr_15 */
570 host->send_addr(host, (page_addr >> 8) & 0xff, true);
572 /* One more address cycle for higher density devices */
573 if (mtd->size >= 0x4000000) {
574 /* paddr_8 - paddr_15 */
575 host->send_addr(host, (page_addr >> 8) & 0xff, false);
576 host->send_addr(host, (page_addr >> 16) & 0xff, true);
578 /* paddr_8 - paddr_15 */
579 host->send_addr(host, (page_addr >> 8) & 0xff, true);
584 static void preset_v1_v2(struct mtd_info *mtd)
586 struct nand_chip *nand_chip = mtd->priv;
587 struct mxc_nand_host *host = nand_chip->priv;
590 /* enable interrupt, disable spare enable */
591 tmp = readw(NFC_V1_V2_CONFIG1);
592 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
593 tmp &= ~NFC_V1_V2_CONFIG1_SP_EN;
594 if (nand_chip->ecc.mode == NAND_ECC_HW) {
595 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
597 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
599 writew(tmp, NFC_V1_V2_CONFIG1);
600 /* preset operation */
602 /* Unlock the internal RAM Buffer */
603 writew(0x2, NFC_V1_V2_CONFIG);
605 /* Blocks to be unlocked */
607 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR);
608 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR);
609 } else if (nfc_is_v1()) {
610 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
611 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
615 /* Unlock Block Command for given address range */
616 writew(0x4, NFC_V1_V2_WRPROT);
619 /* Used by the upper layer to write command to NAND Flash for
620 * different operations to be carried out on NAND Flash */
621 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
622 int column, int page_addr)
624 struct nand_chip *nand_chip = mtd->priv;
625 struct mxc_nand_host *host = nand_chip->priv;
627 DEBUG(MTD_DEBUG_LEVEL3,
628 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
629 command, column, page_addr);
631 /* Reset command state information */
632 host->status_request = false;
634 /* Command pre-processing step */
638 host->send_cmd(host, command, false);
641 case NAND_CMD_STATUS:
643 host->status_request = true;
645 host->send_cmd(host, command, true);
646 mxc_do_addr_cycle(mtd, column, page_addr);
650 case NAND_CMD_READOOB:
651 if (command == NAND_CMD_READ0)
652 host->buf_start = column;
654 host->buf_start = column + mtd->writesize;
656 command = NAND_CMD_READ0; /* only READ0 is valid */
658 host->send_cmd(host, command, false);
659 mxc_do_addr_cycle(mtd, column, page_addr);
661 if (mtd->writesize > 512)
662 host->send_cmd(host, NAND_CMD_READSTART, true);
664 host->send_page(mtd, NFC_OUTPUT);
666 memcpy(host->data_buf, host->main_area0, mtd->writesize);
667 copy_spare(mtd, true);
671 if (column >= mtd->writesize)
672 /* call ourself to read a page */
673 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
675 host->buf_start = column;
677 host->send_cmd(host, command, false);
678 mxc_do_addr_cycle(mtd, column, page_addr);
681 case NAND_CMD_PAGEPROG:
682 memcpy(host->main_area0, host->data_buf, mtd->writesize);
683 copy_spare(mtd, false);
684 host->send_page(mtd, NFC_INPUT);
685 host->send_cmd(host, command, true);
686 mxc_do_addr_cycle(mtd, column, page_addr);
689 case NAND_CMD_READID:
690 host->send_cmd(host, command, true);
691 mxc_do_addr_cycle(mtd, column, page_addr);
692 host->send_read_id(host);
693 host->buf_start = column;
696 case NAND_CMD_ERASE1:
697 case NAND_CMD_ERASE2:
698 host->send_cmd(host, command, false);
699 mxc_do_addr_cycle(mtd, column, page_addr);
706 * The generic flash bbt decriptors overlap with our ecc
707 * hardware, so define some i.MX specific ones.
709 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
710 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
712 static struct nand_bbt_descr bbt_main_descr = {
713 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
714 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
719 .pattern = bbt_pattern,
722 static struct nand_bbt_descr bbt_mirror_descr = {
723 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
724 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
729 .pattern = mirror_pattern,
732 static int __init mxcnd_probe(struct platform_device *pdev)
734 struct nand_chip *this;
735 struct mtd_info *mtd;
736 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
737 struct mxc_nand_host *host;
738 struct resource *res;
739 int err = 0, nr_parts = 0;
740 struct nand_ecclayout *oob_smallpage, *oob_largepage;
742 /* Allocate memory for MTD device structure and private data */
743 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
744 NAND_MAX_OOBSIZE, GFP_KERNEL);
748 host->data_buf = (uint8_t *)(host + 1);
750 host->dev = &pdev->dev;
751 /* structures must be linked */
755 mtd->owner = THIS_MODULE;
756 mtd->dev.parent = &pdev->dev;
757 mtd->name = DRIVER_NAME;
759 /* 50 us command delay time */
760 this->chip_delay = 5;
763 this->dev_ready = mxc_nand_dev_ready;
764 this->cmdfunc = mxc_nand_command;
765 this->select_chip = mxc_nand_select_chip;
766 this->read_byte = mxc_nand_read_byte;
767 this->read_word = mxc_nand_read_word;
768 this->write_buf = mxc_nand_write_buf;
769 this->read_buf = mxc_nand_read_buf;
770 this->verify_buf = mxc_nand_verify_buf;
772 host->clk = clk_get(&pdev->dev, "nfc");
773 if (IS_ERR(host->clk)) {
774 err = PTR_ERR(host->clk);
778 clk_enable(host->clk);
781 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
787 host->base = ioremap(res->start, resource_size(res));
793 host->main_area0 = host->base;
795 if (nfc_is_v1() || nfc_is_v21()) {
796 host->preset = preset_v1_v2;
797 host->send_cmd = send_cmd_v1_v2;
798 host->send_addr = send_addr_v1_v2;
799 host->send_page = send_page_v1_v2;
800 host->send_read_id = send_read_id_v1_v2;
801 host->get_dev_status = get_dev_status_v1_v2;
802 host->check_int = check_int_v1_v2;
806 host->regs = host->base + 0x1e00;
807 host->spare0 = host->base + 0x1000;
808 host->spare_len = 64;
809 oob_smallpage = &nandv2_hw_eccoob_smallpage;
810 oob_largepage = &nandv2_hw_eccoob_largepage;
812 } else if (nfc_is_v1()) {
813 host->regs = host->base + 0xe00;
814 host->spare0 = host->base + 0x800;
815 host->spare_len = 16;
816 oob_smallpage = &nandv1_hw_eccoob_smallpage;
817 oob_largepage = &nandv1_hw_eccoob_largepage;
822 this->ecc.size = 512;
823 this->ecc.layout = oob_smallpage;
826 this->ecc.calculate = mxc_nand_calculate_ecc;
827 this->ecc.hwctl = mxc_nand_enable_hwecc;
829 this->ecc.correct = mxc_nand_correct_data_v1;
831 this->ecc.correct = mxc_nand_correct_data_v2_v3;
832 this->ecc.mode = NAND_ECC_HW;
834 this->ecc.mode = NAND_ECC_SOFT;
837 /* NAND bus width determines access funtions used by upper layer */
838 if (pdata->width == 2)
839 this->options |= NAND_BUSWIDTH_16;
841 if (pdata->flash_bbt) {
842 this->bbt_td = &bbt_main_descr;
843 this->bbt_md = &bbt_mirror_descr;
844 /* update flash based bbt */
845 this->options |= NAND_USE_FLASH_BBT;
848 init_waitqueue_head(&host->irq_waitq);
850 host->irq = platform_get_irq(pdev, 0);
852 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
856 /* first scan to find the device and get the page size */
857 if (nand_scan_ident(mtd, 1, NULL)) {
862 if (mtd->writesize == 2048)
863 this->ecc.layout = oob_largepage;
865 /* second phase scan */
866 if (nand_scan_tail(mtd)) {
871 /* Register the partitions */
872 #ifdef CONFIG_MTD_PARTITIONS
874 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
876 add_mtd_partitions(mtd, host->parts, nr_parts);
880 pr_info("Registering %s as whole device\n", mtd->name);
884 platform_set_drvdata(pdev, host);
889 free_irq(host->irq, host);
900 static int __devexit mxcnd_remove(struct platform_device *pdev)
902 struct mxc_nand_host *host = platform_get_drvdata(pdev);
906 platform_set_drvdata(pdev, NULL);
908 nand_release(&host->mtd);
909 free_irq(host->irq, host);
916 static struct platform_driver mxcnd_driver = {
920 .remove = __devexit_p(mxcnd_remove),
923 static int __init mxc_nd_init(void)
925 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
928 static void __exit mxc_nd_cleanup(void)
930 /* Unregister the device structure */
931 platform_driver_unregister(&mxcnd_driver);
934 module_init(mxc_nd_init);
935 module_exit(mxc_nd_cleanup);
937 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
938 MODULE_DESCRIPTION("MXC NAND MTD driver");
939 MODULE_LICENSE("GPL");