2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/types.h>
22 #include <asm/errno.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/imx-common/regs-bch.h>
27 #include <asm/imx-common/regs-gpmi.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/imx-common/dma.h>
31 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
33 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
34 #if defined(CONFIG_SOC_MX6)
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
39 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
41 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
43 /* BCH timeout in microseconds */
44 #define MXS_NAND_BCH_TIMEOUT 10000
46 static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS;
47 static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS;
48 struct mxs_nand_info {
51 uint32_t cmd_queue_len;
52 uint32_t data_buf_size;
58 uint8_t marking_block_bad;
61 /* Functions with altered behaviour */
62 int (*hooked_read_oob)(struct mtd_info *mtd,
63 loff_t from, struct mtd_oob_ops *ops);
64 int (*hooked_write_oob)(struct mtd_info *mtd,
65 loff_t to, struct mtd_oob_ops *ops);
66 int (*hooked_block_markbad)(struct mtd_info *mtd,
70 struct mxs_dma_desc **desc;
75 #define dump_reg(b, r) __dump_reg(&b->r, #r)
76 static inline void __dump_reg(void *addr, const char *name)
78 printf("%16s[%p]=%08x\n", name, addr, readl(addr));
81 #define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n)
82 #define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n)
83 static inline void dump_regs(void)
87 dump_bch_reg(status0);
90 dump_bch_reg(dbgkesread);
91 dump_bch_reg(dbgcsferead);
92 dump_bch_reg(dbgsyndegread);
93 dump_bch_reg(dbgahbmread);
94 dump_bch_reg(blockname);
95 dump_bch_reg(version);
99 dump_gpmi_reg(eccctrl);
100 dump_gpmi_reg(ecccount);
101 dump_gpmi_reg(payload);
102 dump_gpmi_reg(auxiliary);
103 dump_gpmi_reg(ctrl1);
106 dump_gpmi_reg(debug);
107 dump_gpmi_reg(version);
108 dump_gpmi_reg(debug2);
109 dump_gpmi_reg(debug3);
112 static inline int dbg_addr(void *addr)
114 if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS)
119 static inline u32 mxs_readl(void *addr,
120 const char *fn, int ln)
122 u32 val = readl(addr);
123 static void *last_addr;
129 if (addr != last_addr || last_val != val) {
130 printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
137 static inline void mxs_writel(u32 val, void *addr,
138 const char *fn, int ln)
141 printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
144 printf(" result: %08x\n", readl(addr));
148 #define readl(a) mxs_readl(a, __func__, __LINE__)
151 #define writel(v, a) mxs_writel(v, a, __func__, __LINE__)
152 static inline void memdump(const void *addr, size_t len)
154 const char *buf = addr;
157 for (i = 0; i < len; i++) {
161 printf("%p:", &buf[i]);
163 printf(" %02x", buf[i]);
168 static inline void memdump(void *addr, size_t len)
172 static inline void dump_regs(void)
177 struct nand_ecclayout fake_ecc_layout;
178 static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
179 static int galois_field = 13;
182 * Cache management functions
184 #ifndef CONFIG_SYS_DCACHE_OFF
185 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
187 uint32_t addr = (uint32_t)info->data_buf;
189 flush_dcache_range(addr, addr + info->data_buf_size);
192 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
194 uint32_t addr = (uint32_t)info->data_buf;
196 invalidate_dcache_range(addr, addr + info->data_buf_size);
199 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
201 uint32_t addr = (uint32_t)info->cmd_buf;
203 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
206 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
207 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
208 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
211 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
213 struct mxs_dma_desc *desc;
215 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
216 printf("MXS NAND: Too many DMA descriptors requested\n");
220 desc = info->desc[info->desc_index];
226 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
229 struct mxs_dma_desc *desc;
231 for (i = 0; i < info->desc_index; i++) {
232 desc = info->desc[i];
233 memset(desc, 0, sizeof(struct mxs_dma_desc));
234 desc->address = (dma_addr_t)desc;
237 info->desc_index = 0;
240 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
242 return page_data_size / chunk_data_size;
245 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
247 return ecc_strength * galois_field;
250 static uint32_t mxs_nand_aux_status_offset(void)
252 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
255 static int mxs_nand_gpmi_init(void)
259 /* Reset the GPMI block. */
260 ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
262 printf("Failed to reset GPMI block\n");
266 ret = mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
268 printf("Failed to reset BCH block\n");
273 * Choose NAND mode, set IRQ polarity, disable write protection and
276 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
277 GPMI_CTRL1_GPMI_MODE,
278 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
279 GPMI_CTRL1_BCH_MODE);
280 writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1);
284 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
285 uint32_t page_oob_size)
290 * Determine the ECC layout with the formula:
291 * ECC bits per chunk = (total page spare data bits) /
292 * (bits per ECC level) / (chunks per page)
294 * total page spare data bits =
295 * (page oob size - meta data size) * (bits per byte)
297 ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
299 mxs_nand_ecc_chunk_cnt(page_data_size));
301 return round_down(ecc_strength, 2);
304 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
305 uint32_t ecc_strength)
307 uint32_t chunk_data_size_in_bits;
308 uint32_t chunk_ecc_size_in_bits;
309 uint32_t chunk_total_size_in_bits;
310 uint32_t block_mark_chunk_number;
311 uint32_t block_mark_chunk_bit_offset;
312 uint32_t block_mark_bit_offset;
314 chunk_data_size_in_bits = chunk_data_size * 8;
315 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
317 chunk_total_size_in_bits =
318 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
320 /* Compute the bit offset of the block mark within the physical page. */
321 block_mark_bit_offset = page_data_size * 8;
323 /* Subtract the metadata bits. */
324 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
327 * Compute the chunk number (starting at zero) in which the block mark
330 block_mark_chunk_number =
331 block_mark_bit_offset / chunk_total_size_in_bits;
334 * Compute the bit offset of the block mark within its chunk, and
337 block_mark_chunk_bit_offset = block_mark_bit_offset -
338 (block_mark_chunk_number * chunk_total_size_in_bits);
340 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
344 * Now that we know the chunk number in which the block mark appears,
345 * we can subtract all the ECC bits that appear before it.
347 block_mark_bit_offset -=
348 block_mark_chunk_number * chunk_ecc_size_in_bits;
350 return block_mark_bit_offset;
353 static inline uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
355 uint32_t ecc_strength;
356 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
357 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
360 static inline uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
362 uint32_t ecc_strength;
363 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
364 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
368 * Wait for BCH complete IRQ and clear the IRQ
370 static int mxs_nand_wait_for_bch_complete(void)
372 int timeout = MXS_NAND_BCH_TIMEOUT;
375 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
376 BCH_CTRL_COMPLETE_IRQ, timeout);
378 debug("%s@%d: %d\n", __func__, __LINE__, ret);
379 mxs_nand_gpmi_init();
382 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
388 * This is the function that we install in the cmd_ctrl function pointer of the
389 * owning struct nand_chip. The only functions in the reference implementation
390 * that use these functions pointers are cmdfunc and select_chip.
392 * In this driver, we implement our own select_chip, so this function will only
393 * be called by the reference implementation's cmdfunc. For this reason, we can
394 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
397 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
399 struct nand_chip *nand = mtd->priv;
400 struct mxs_nand_info *nand_info = nand->priv;
401 struct mxs_dma_desc *d;
402 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
406 * If this condition is true, something is _VERY_ wrong in MTD
409 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
410 printf("MXS NAND: Command queue too long\n");
415 * Every operation begins with a command byte and a series of zero or
416 * more address bytes. These are distinguished by either the Address
417 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
418 * asserted. When MTD is ready to execute the command, it will
419 * deasert both latch enables.
421 * Rather than run a separate DMA operation for every single byte, we
422 * queue them up and run a single DMA operation for the entire series
423 * of command and data bytes.
425 if (ctrl & (NAND_ALE | NAND_CLE)) {
426 if (data != NAND_CMD_NONE)
427 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
432 * If control arrives here, MTD has deasserted both the ALE and CLE,
433 * which means it's ready to run an operation. Check if we have any
436 if (nand_info->cmd_queue_len == 0)
439 /* Compile the DMA descriptor -- a descriptor that sends command. */
440 d = mxs_nand_get_dma_desc(nand_info);
442 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
443 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
444 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
445 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
447 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
449 d->cmd.pio_words[0] =
450 GPMI_CTRL0_COMMAND_MODE_WRITE |
451 GPMI_CTRL0_WORD_LENGTH |
452 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
453 GPMI_CTRL0_ADDRESS_NAND_CLE |
454 GPMI_CTRL0_ADDRESS_INCREMENT |
455 nand_info->cmd_queue_len;
457 mxs_dma_desc_append(channel, d);
460 mxs_nand_flush_cmd_buf(nand_info);
462 /* Execute the DMA chain. */
463 ret = mxs_dma_go(channel);
467 printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]);
468 for (i = 0; i < nand_info->cmd_queue_len; i++) {
469 printf("%02x ", nand_info->cmd_buf[i]);
474 mxs_nand_return_dma_descs(nand_info);
476 /* Reset the command queue. */
477 nand_info->cmd_queue_len = 0;
481 * Test if the NAND flash is ready.
483 static int mxs_nand_device_ready(struct mtd_info *mtd)
485 struct nand_chip *chip = mtd->priv;
486 struct mxs_nand_info *nand_info = chip->priv;
489 tmp = readl(&gpmi_regs->hw_gpmi_stat);
490 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
496 * Select the NAND chip.
498 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
500 struct nand_chip *nand = mtd->priv;
501 struct mxs_nand_info *nand_info = nand->priv;
503 nand_info->cur_chip = chip;
507 * Handle block mark swapping.
509 * Note that, when this function is called, it doesn't know whether it's
510 * swapping the block mark, or swapping it *back* -- but it doesn't matter
511 * because the the operation is the same.
513 #ifndef CONFIG_NAND_MXS_NO_BBM_SWAP
514 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
515 uint8_t *data_buf, uint8_t *oob_buf)
523 bit_offset = mxs_nand_mark_bit_offset(mtd);
524 buf_offset = mxs_nand_mark_byte_offset(mtd);
527 * Get the byte from the data area that overlays the block mark. Since
528 * the ECC engine applies its own view to the bits in the page, the
529 * physical block mark won't (in general) appear on a byte boundary in
532 src = data_buf[buf_offset] >> bit_offset;
533 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
537 debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n",
538 src & 0xff, buf_offset, bit_offset, dst & 0xff, 0);
542 data_buf[buf_offset] &= ~(0xff << bit_offset);
543 data_buf[buf_offset + 1] &= 0xff << bit_offset;
545 data_buf[buf_offset] |= dst << bit_offset;
546 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
549 static inline void mxs_nand_swap_block_mark(struct mtd_info *mtd,
550 uint8_t *data_buf, uint8_t *oob_buf)
556 * Read data from NAND.
558 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
560 struct nand_chip *nand = mtd->priv;
561 struct mxs_nand_info *nand_info = nand->priv;
562 struct mxs_dma_desc *d;
563 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
566 if (length > NAND_MAX_PAGESIZE) {
567 printf("MXS NAND: DMA buffer too big\n");
572 printf("MXS NAND: DMA buffer is NULL\n");
576 /* Compile the DMA descriptor - a descriptor that reads data. */
577 d = mxs_nand_get_dma_desc(nand_info);
579 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
580 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
581 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
582 (length << MXS_DMA_DESC_BYTES_OFFSET);
584 d->cmd.address = (dma_addr_t)nand_info->data_buf;
586 d->cmd.pio_words[0] =
587 GPMI_CTRL0_COMMAND_MODE_READ |
588 GPMI_CTRL0_WORD_LENGTH |
589 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
590 GPMI_CTRL0_ADDRESS_NAND_DATA |
593 mxs_dma_desc_append(channel, d);
595 #ifndef CONFIG_SOC_MX6Q
597 * A DMA descriptor that waits for the command to end and the chip to
600 * I think we actually should *not* be waiting for the chip to become
601 * ready because, after all, we don't care. I think the original code
602 * did that and no one has re-thought it yet.
604 d = mxs_nand_get_dma_desc(nand_info);
606 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
607 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
608 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
612 d->cmd.pio_words[0] =
613 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
614 GPMI_CTRL0_WORD_LENGTH |
615 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
616 GPMI_CTRL0_ADDRESS_NAND_DATA;
618 mxs_dma_desc_append(channel, d);
621 /* Invalidate caches */
622 mxs_nand_inval_data_buf(nand_info);
624 /* Execute the DMA chain. */
625 ret = mxs_dma_go(channel);
627 printf("%s: DMA read error\n", __func__);
631 /* Invalidate caches */
632 mxs_nand_inval_data_buf(nand_info);
634 memcpy(buf, nand_info->data_buf, length);
637 mxs_nand_return_dma_descs(nand_info);
641 * Write data to NAND.
643 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
646 struct nand_chip *nand = mtd->priv;
647 struct mxs_nand_info *nand_info = nand->priv;
648 struct mxs_dma_desc *d;
649 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
652 if (length > NAND_MAX_PAGESIZE) {
653 printf("MXS NAND: DMA buffer too big\n");
658 printf("MXS NAND: DMA buffer is NULL\n");
662 memcpy(nand_info->data_buf, buf, length);
664 /* Compile the DMA descriptor - a descriptor that writes data. */
665 d = mxs_nand_get_dma_desc(nand_info);
667 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
668 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
669 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
670 (length << MXS_DMA_DESC_BYTES_OFFSET);
672 d->cmd.address = (dma_addr_t)nand_info->data_buf;
674 d->cmd.pio_words[0] =
675 GPMI_CTRL0_COMMAND_MODE_WRITE |
676 GPMI_CTRL0_WORD_LENGTH |
677 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
678 GPMI_CTRL0_ADDRESS_NAND_DATA |
681 mxs_dma_desc_append(channel, d);
684 mxs_nand_flush_data_buf(nand_info);
686 /* Execute the DMA chain. */
687 ret = mxs_dma_go(channel);
689 printf("%s: DMA write error\n", __func__);
691 mxs_nand_return_dma_descs(nand_info);
695 * Read a single byte from NAND.
697 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
700 mxs_nand_read_buf(mtd, &buf, 1);
704 static void flush_buffers(struct mtd_info *mtd, struct mxs_nand_info *nand_info)
706 flush_dcache_range((unsigned long)nand_info->data_buf,
707 (unsigned long)nand_info->data_buf +
709 flush_dcache_range((unsigned long)nand_info->oob_buf,
710 (unsigned long)nand_info->oob_buf +
715 * Read a page from NAND.
717 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
718 uint8_t *buf, int oob_required,
721 struct mxs_nand_info *nand_info = nand->priv;
722 struct mxs_dma_desc *d;
723 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
724 uint32_t corrected = 0, failed = 0;
728 /* Compile the DMA descriptor - wait for ready. */
729 d = mxs_nand_get_dma_desc(nand_info);
731 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
732 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
733 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
737 d->cmd.pio_words[0] =
738 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
739 GPMI_CTRL0_WORD_LENGTH |
740 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
741 GPMI_CTRL0_ADDRESS_NAND_DATA;
743 mxs_dma_desc_append(channel, d);
745 /* Compile the DMA descriptor - enable the BCH block and read. */
746 d = mxs_nand_get_dma_desc(nand_info);
748 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
749 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
753 d->cmd.pio_words[0] =
754 GPMI_CTRL0_COMMAND_MODE_READ |
755 GPMI_CTRL0_WORD_LENGTH |
756 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
757 GPMI_CTRL0_ADDRESS_NAND_DATA |
758 (mtd->writesize + mtd->oobsize);
759 d->cmd.pio_words[1] = 0;
760 d->cmd.pio_words[2] =
761 GPMI_ECCCTRL_ENABLE_ECC |
762 GPMI_ECCCTRL_ECC_CMD_DECODE |
763 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
764 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
765 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
766 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
768 flush_buffers(mtd, nand_info);
770 mxs_dma_desc_append(channel, d);
772 /* Compile the DMA descriptor - disable the BCH block. */
773 d = mxs_nand_get_dma_desc(nand_info);
775 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
776 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
777 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
781 d->cmd.pio_words[0] =
782 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
783 GPMI_CTRL0_WORD_LENGTH |
784 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
785 GPMI_CTRL0_ADDRESS_NAND_DATA |
786 (mtd->writesize + mtd->oobsize);
787 d->cmd.pio_words[1] = 0;
788 d->cmd.pio_words[2] = 0;
790 mxs_dma_desc_append(channel, d);
792 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
793 d = mxs_nand_get_dma_desc(nand_info);
795 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
796 MXS_DMA_DESC_DEC_SEM;
800 mxs_dma_desc_append(channel, d);
802 /* Invalidate caches */
803 mxs_nand_inval_data_buf(nand_info);
805 /* Execute the DMA chain. */
806 ret = mxs_dma_go(channel);
808 printf("%s: DMA read error\n", __func__);
812 ret = mxs_nand_wait_for_bch_complete();
814 printf("MXS NAND: BCH read timeout\n");
818 /* Invalidate caches */
819 mxs_nand_inval_data_buf(nand_info);
821 /* Read DMA completed, now do the mark swapping. */
822 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
824 /* Loop over status bytes, accumulating ECC status. */
825 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
826 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
827 if (status[i] == 0x00)
830 if (status[i] == 0xff)
833 if (status[i] == 0xfe) {
838 corrected += status[i];
841 /* Propagate ECC status to the owning MTD. */
842 mtd->ecc_stats.failed += failed;
843 mtd->ecc_stats.corrected += corrected;
846 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
847 * details about our policy for delivering the OOB.
849 * We fill the caller's buffer with set bits, and then copy the block
850 * mark to the caller's buffer. Note that, if block mark swapping was
851 * necessary, it has already been done, so we can rely on the first
852 * byte of the auxiliary buffer to contain the block mark.
854 memset(nand->oob_poi, 0xff, mtd->oobsize);
856 nand->oob_poi[0] = nand_info->oob_buf[0];
858 memcpy(buf, nand_info->data_buf, mtd->writesize);
861 mxs_nand_return_dma_descs(nand_info);
867 * Write a page to NAND.
869 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
870 struct nand_chip *nand, const uint8_t *buf,
873 struct mxs_nand_info *nand_info = nand->priv;
874 struct mxs_dma_desc *d;
875 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
878 memcpy(nand_info->data_buf, buf, mtd->writesize);
879 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
881 /* Handle block mark swapping. */
882 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
884 /* Compile the DMA descriptor - write data. */
885 d = mxs_nand_get_dma_desc(nand_info);
887 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
888 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
889 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
893 d->cmd.pio_words[0] =
894 GPMI_CTRL0_COMMAND_MODE_WRITE |
895 GPMI_CTRL0_WORD_LENGTH |
896 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
897 GPMI_CTRL0_ADDRESS_NAND_DATA;
898 d->cmd.pio_words[1] = 0;
899 d->cmd.pio_words[2] =
900 GPMI_ECCCTRL_ENABLE_ECC |
901 GPMI_ECCCTRL_ECC_CMD_ENCODE |
902 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
903 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
904 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
905 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
907 flush_buffers(mtd, nand_info);
909 mxs_dma_desc_append(channel, d);
912 mxs_nand_flush_data_buf(nand_info);
914 /* Execute the DMA chain. */
915 ret = mxs_dma_go(channel);
917 printf("%s: DMA write error\n", __func__);
921 ret = mxs_nand_wait_for_bch_complete();
923 printf("%s: BCH write timeout\n", __func__);
928 mxs_nand_return_dma_descs(nand_info);
933 * Read OOB from NAND.
935 * This function is a veneer that replaces the function originally installed by
936 * the NAND Flash MTD code.
938 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
939 struct mtd_oob_ops *ops)
941 struct nand_chip *chip = mtd->priv;
942 struct mxs_nand_info *nand_info = chip->priv;
945 if (ops->mode == MTD_OPS_RAW)
946 nand_info->raw_oob_mode = 1;
948 nand_info->raw_oob_mode = 0;
950 ret = nand_info->hooked_read_oob(mtd, from, ops);
952 nand_info->raw_oob_mode = 0;
960 * This function is a veneer that replaces the function originally installed by
961 * the NAND Flash MTD code.
963 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
964 struct mtd_oob_ops *ops)
966 struct nand_chip *chip = mtd->priv;
967 struct mxs_nand_info *nand_info = chip->priv;
970 if (ops->mode == MTD_OPS_RAW)
971 nand_info->raw_oob_mode = 1;
973 nand_info->raw_oob_mode = 0;
975 ret = nand_info->hooked_write_oob(mtd, to, ops);
977 nand_info->raw_oob_mode = 0;
983 * Mark a block bad in NAND.
985 * This function is a veneer that replaces the function originally installed by
986 * the NAND Flash MTD code.
988 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
990 struct nand_chip *chip = mtd->priv;
991 struct mxs_nand_info *nand_info = chip->priv;
994 nand_info->marking_block_bad = 1;
996 ret = nand_info->hooked_block_markbad(mtd, ofs);
998 nand_info->marking_block_bad = 0;
1004 * There are several places in this driver where we have to handle the OOB and
1005 * block marks. This is the function where things are the most complicated, so
1006 * this is where we try to explain it all. All the other places refer back to
1009 * These are the rules, in order of decreasing importance:
1011 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
1012 * write operations take measures to protect it.
1014 * 2) In read operations, the first byte of the OOB we return must reflect the
1015 * true state of the block mark, no matter where that block mark appears in
1016 * the physical page.
1018 * 3) ECC-based read operations return an OOB full of set bits (since we never
1019 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1022 * 4) "Raw" read operations return a direct view of the physical bytes in the
1023 * page, using the conventional definition of which bytes are data and which
1024 * are OOB. This gives the caller a way to see the actual, physical bytes
1025 * in the page, without the distortions applied by our ECC engine.
1027 * What we do for this specific read operation depends on whether we're doing
1028 * "raw" read, or an ECC-based read.
1030 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1031 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1032 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1033 * ECC-based or raw view of the page is implicit in which function it calls
1034 * (there is a similar pair of ECC-based/raw functions for writing).
1036 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
1037 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
1038 * caller wants an ECC-based or raw view of the page is not propagated down to
1041 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
1042 * ecc.read_oob and ecc.write_oob function pointers in the owning
1043 * struct mtd_info with our own functions. These hook functions set the
1044 * raw_oob_mode field so that, when control finally arrives here, we'll know
1047 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
1050 struct mxs_nand_info *nand_info = nand->priv;
1053 * First, fill in the OOB buffer. If we're doing a raw read, we need to
1054 * get the bytes from the physical page. If we're not doing a raw read,
1055 * we need to fill the buffer with set bits.
1057 if (nand_info->raw_oob_mode) {
1059 * If control arrives here, we're doing a "raw" read. Send the
1060 * command to read the conventional OOB and read it.
1062 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1063 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
1066 * If control arrives here, we're not doing a "raw" read. Fill
1067 * the OOB buffer with set bits and correct the block mark.
1069 memset(nand->oob_poi, 0xff, mtd->oobsize);
1071 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1072 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
1080 * Write OOB data to NAND.
1082 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1085 struct mxs_nand_info *nand_info = nand->priv;
1086 uint8_t block_mark = 0;
1089 * There are fundamental incompatibilities between the i.MX GPMI NFC and
1090 * the NAND Flash MTD model that make it essentially impossible to write
1091 * the out-of-band bytes.
1093 * We permit *ONE* exception. If the *intent* of writing the OOB is to
1094 * mark a block bad, we can do that.
1097 if (!nand_info->marking_block_bad) {
1098 printf("NXS NAND: Writing OOB isn't supported\n");
1102 /* Write the block mark. */
1103 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1104 nand->write_buf(mtd, &block_mark, 1);
1105 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1107 /* Check if it worked. */
1108 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1115 * Claims all blocks are good.
1117 * In principle, this function is *only* called when the NAND Flash MTD system
1118 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1119 * the driver for bad block information.
1121 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1122 * this function is *only* called when we take it away.
1124 * Thus, this function is only called when we want *all* blocks to look good,
1125 * so it *always* return success.
1127 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
1133 * Nominally, the purpose of this function is to look for or create the bad
1134 * block table. In fact, since the we call this function at the very end of
1135 * the initialization process started by nand_scan(), and we don't have a
1136 * more formal mechanism, we "hook" this function to continue init process.
1138 * At this point, the physical NAND Flash chips have been identified and
1139 * counted, so we know the physical geometry. This enables us to make some
1140 * important configuration decisions.
1142 * The return value of this function propogates directly back to this driver's
1143 * call to nand_scan(). Anything other than zero will cause this driver to
1144 * tear everything down and declare failure.
1146 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
1148 struct nand_chip *nand = mtd->priv;
1149 struct mxs_nand_info *nand_info = nand->priv;
1152 if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
1154 chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
1157 if (mtd->oobsize > chunk_data_size) {
1158 printf("OOB size of chip (%u bytes) is larger than max. supported size (%u bytes)\n",
1159 mtd->oobsize, chunk_data_size);
1163 /* Configure BCH and set NFC geometry */
1164 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1166 debug("mtd->writesize=%d\n", mtd->writesize);
1167 debug("mtd->oobsize=%d\n", mtd->oobsize);
1168 debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize));
1170 /* Configure layout 0 */
1171 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
1172 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1173 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1174 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1175 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1176 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1177 tmp |= (14 == galois_field ? 1 : 0) <<
1178 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1179 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1181 tmp = (mtd->writesize + mtd->oobsize)
1182 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1183 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1184 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1185 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1186 tmp |= (14 == galois_field ? 1 : 0) <<
1187 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1188 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1190 /* Set *all* chip selects to use layout 0 */
1191 writel(0, &bch_regs->hw_bch_layoutselect);
1193 /* Enable BCH complete interrupt */
1194 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1196 /* Hook some operations at the MTD level. */
1197 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1198 nand_info->hooked_read_oob = mtd->_read_oob;
1199 mtd->_read_oob = mxs_nand_hook_read_oob;
1202 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1203 nand_info->hooked_write_oob = mtd->_write_oob;
1204 mtd->_write_oob = mxs_nand_hook_write_oob;
1207 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1208 nand_info->hooked_block_markbad = mtd->_block_markbad;
1209 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1212 /* We use the reference implementation for bad block management. */
1213 return nand_default_bbt(mtd);
1217 * Allocate DMA buffers
1219 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1222 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1224 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1227 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1229 printf("%s: Error allocating DMA buffers\n", __func__);
1233 memset(buf, 0, nand_info->data_buf_size);
1235 nand_info->data_buf = buf;
1236 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1237 /* Command buffers */
1238 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1239 MXS_NAND_COMMAND_BUFFER_SIZE);
1240 if (!nand_info->cmd_buf) {
1242 printf("MXS NAND: Error allocating command buffers\n");
1245 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1246 nand_info->cmd_queue_len = 0;
1252 * Initializes the NFC hardware.
1254 int mxs_nand_init(struct mxs_nand_info *info)
1259 info->desc = calloc(MXS_NAND_DMA_DESCRIPTOR_COUNT,
1260 sizeof(struct mxs_dma_desc *));
1263 printf("MXS NAND: Unable to allocate DMA descriptor table\n");
1270 /* Allocate the DMA descriptors. */
1271 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1272 info->desc[i] = mxs_dma_desc_alloc();
1273 if (!info->desc[i]) {
1274 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1280 /* Init the DMA controller. */
1281 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) {
1282 const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i;
1284 ret = mxs_dma_init_channel(chan);
1286 printf("Failed to initialize DMA channel %d\n", chan);
1291 ret = mxs_nand_gpmi_init();
1298 for (--i; i >= 0; i--)
1299 mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0);
1300 i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1;
1303 for (--i; i >= 0; i--)
1304 mxs_dma_desc_free(info->desc[i]);
1310 * This function is called during the driver binding process.
1312 * @param pdev the device structure used to store device specific
1313 * information that is used by the suspend, resume and
1316 * @return 0 for success; errno value in case of error
1318 int board_nand_init(struct nand_chip *nand)
1320 struct mxs_nand_info *nand_info;
1323 nand_info = kzalloc(sizeof(struct mxs_nand_info), 0);
1325 printf("MXS NAND: Failed to allocate private data\n");
1329 err = mxs_nand_alloc_buffers(nand_info);
1333 err = mxs_nand_init(nand_info);
1337 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1339 nand->priv = nand_info;
1340 nand->options |= NAND_NO_SUBPAGE_WRITE;
1341 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1342 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1344 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1346 nand->dev_ready = mxs_nand_device_ready;
1347 nand->select_chip = mxs_nand_select_chip;
1348 nand->block_bad = mxs_nand_block_bad;
1349 nand->scan_bbt = mxs_nand_scan_bbt;
1351 nand->read_byte = mxs_nand_read_byte;
1353 nand->read_buf = mxs_nand_read_buf;
1354 nand->write_buf = mxs_nand_write_buf;
1356 nand->ecc.read_page = mxs_nand_ecc_read_page;
1357 nand->ecc.write_page = mxs_nand_ecc_write_page;
1358 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1359 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1361 nand->ecc.layout = &fake_ecc_layout;
1362 nand->ecc.mode = NAND_ECC_HW;
1363 nand->ecc.bytes = 9;
1364 nand->ecc.size = 512;
1365 nand->ecc.strength = 8;
1370 free(nand_info->data_buf);
1371 free(nand_info->cmd_buf);