2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/types.h>
22 #include <asm/errno.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/imx-common/regs-bch.h>
27 #include <asm/imx-common/regs-gpmi.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/imx-common/dma.h>
31 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
33 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
34 #if defined(CONFIG_SOC_MX6)
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
39 #define MXS_NAND_METADATA_SIZE 10
41 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
43 /* BCH timeout in microseconds */
44 #define MXS_NAND_BCH_TIMEOUT 10000
46 static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS;
47 static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS;
48 struct mxs_nand_info {
51 uint32_t cmd_queue_len;
52 uint32_t data_buf_size;
58 uint8_t marking_block_bad;
61 /* Functions with altered behaviour */
62 int (*hooked_read_oob)(struct mtd_info *mtd,
63 loff_t from, struct mtd_oob_ops *ops);
64 int (*hooked_write_oob)(struct mtd_info *mtd,
65 loff_t to, struct mtd_oob_ops *ops);
66 int (*hooked_block_markbad)(struct mtd_info *mtd,
70 struct mxs_dma_desc **desc;
75 #define dump_reg(b, r) __dump_reg(&b->r, #r)
76 static inline void __dump_reg(void *addr, const char *name)
78 printf("%16s[%p]=%08x\n", name, addr, readl(addr));
81 #define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n)
82 #define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n)
83 static inline void dump_regs(void)
87 dump_bch_reg(status0);
90 dump_bch_reg(dbgkesread);
91 dump_bch_reg(dbgcsferead);
92 dump_bch_reg(dbgsyndegread);
93 dump_bch_reg(dbgahbmread);
94 dump_bch_reg(blockname);
95 dump_bch_reg(version);
99 dump_gpmi_reg(eccctrl);
100 dump_gpmi_reg(ecccount);
101 dump_gpmi_reg(payload);
102 dump_gpmi_reg(auxiliary);
103 dump_gpmi_reg(ctrl1);
106 dump_gpmi_reg(debug);
107 dump_gpmi_reg(version);
108 dump_gpmi_reg(debug2);
109 dump_gpmi_reg(debug3);
112 static inline int dbg_addr(void *addr)
114 if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS)
119 static inline u32 mxs_readl(void *addr,
120 const char *fn, int ln)
122 u32 val = readl(addr);
123 static void *last_addr;
129 if (addr != last_addr || last_val != val) {
130 printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
137 static inline void mxs_writel(u32 val, void *addr,
138 const char *fn, int ln)
141 printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
144 printf(" result: %08x\n", readl(addr));
148 #define readl(a) mxs_readl(a, __func__, __LINE__)
151 #define writel(v, a) mxs_writel(v, a, __func__, __LINE__)
152 static inline void memdump(const void *addr, size_t len)
154 const char *buf = addr;
157 for (i = 0; i < len; i++) {
161 printf("%p:", &buf[i]);
163 printf(" %02x", buf[i]);
168 static inline void memdump(void *addr, size_t len)
172 static inline void dump_regs(void)
177 struct nand_ecclayout fake_ecc_layout;
180 * Cache management functions
182 #ifndef CONFIG_SYS_DCACHE_OFF
183 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
185 uint32_t addr = (uint32_t)info->data_buf;
187 flush_dcache_range(addr, addr + info->data_buf_size);
190 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
192 uint32_t addr = (uint32_t)info->data_buf;
194 invalidate_dcache_range(addr, addr + info->data_buf_size);
197 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
199 uint32_t addr = (uint32_t)info->cmd_buf;
201 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
204 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
205 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
206 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
209 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
211 struct mxs_dma_desc *desc;
213 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
214 printf("MXS NAND: Too many DMA descriptors requested\n");
218 desc = info->desc[info->desc_index];
224 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
227 struct mxs_dma_desc *desc;
229 for (i = 0; i < info->desc_index; i++) {
230 desc = info->desc[i];
231 memset(desc, 0, sizeof(struct mxs_dma_desc));
232 desc->address = (dma_addr_t)desc;
235 info->desc_index = 0;
238 static uint32_t mxs_nand_ecc_chunk_cnt(struct mtd_info *mtd)
240 struct nand_chip *nand = mtd->priv;
241 return mtd->writesize / nand->ecc.size;
244 static inline uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
246 return ecc_strength * 13;
249 static uint32_t mxs_nand_aux_status_offset(void)
251 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
254 static int mxs_nand_gpmi_init(void)
258 /* Reset the GPMI block. */
259 ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
264 * Choose NAND mode, set IRQ polarity, disable write protection and
267 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
268 GPMI_CTRL1_GPMI_MODE,
269 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
270 GPMI_CTRL1_BCH_MODE);
271 writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1);
275 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
276 uint32_t page_oob_size)
278 if (page_data_size == 2048) {
279 if (page_oob_size == 64)
282 if (page_oob_size == 112)
286 if (page_data_size == 4096) {
287 if (page_oob_size == 128)
290 if (page_oob_size == 218)
293 if (page_oob_size == 224)
300 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
301 uint32_t ecc_strength)
303 uint32_t chunk_data_size_in_bits;
304 uint32_t chunk_ecc_size_in_bits;
305 uint32_t chunk_total_size_in_bits;
306 uint32_t block_mark_chunk_number;
307 uint32_t block_mark_chunk_bit_offset;
308 uint32_t block_mark_bit_offset;
310 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
311 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
313 chunk_total_size_in_bits =
314 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
316 /* Compute the bit offset of the block mark within the physical page. */
317 block_mark_bit_offset = page_data_size * 8;
319 /* Subtract the metadata bits. */
320 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
323 * Compute the chunk number (starting at zero) in which the block mark
326 block_mark_chunk_number =
327 block_mark_bit_offset / chunk_total_size_in_bits;
330 * Compute the bit offset of the block mark within its chunk, and
333 block_mark_chunk_bit_offset = block_mark_bit_offset -
334 (block_mark_chunk_number * chunk_total_size_in_bits);
336 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
340 * Now that we know the chunk number in which the block mark appears,
341 * we can subtract all the ECC bits that appear before it.
343 block_mark_bit_offset -=
344 block_mark_chunk_number * chunk_ecc_size_in_bits;
346 return block_mark_bit_offset;
349 static inline uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
351 uint32_t ecc_strength;
352 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
353 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
356 static inline uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
358 uint32_t ecc_strength;
359 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
360 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
364 * Wait for BCH complete IRQ and clear the IRQ
366 static int mxs_nand_wait_for_bch_complete(void)
368 int timeout = MXS_NAND_BCH_TIMEOUT;
371 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
372 BCH_CTRL_COMPLETE_IRQ, timeout);
374 debug("%s@%d: %d\n", __func__, __LINE__, ret);
375 mxs_nand_gpmi_init();
378 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
384 * This is the function that we install in the cmd_ctrl function pointer of the
385 * owning struct nand_chip. The only functions in the reference implementation
386 * that use these functions pointers are cmdfunc and select_chip.
388 * In this driver, we implement our own select_chip, so this function will only
389 * be called by the reference implementation's cmdfunc. For this reason, we can
390 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
393 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
395 struct nand_chip *nand = mtd->priv;
396 struct mxs_nand_info *nand_info = nand->priv;
397 struct mxs_dma_desc *d;
398 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
402 * If this condition is true, something is _VERY_ wrong in MTD
405 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
406 printf("MXS NAND: Command queue too long\n");
411 * Every operation begins with a command byte and a series of zero or
412 * more address bytes. These are distinguished by either the Address
413 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
414 * asserted. When MTD is ready to execute the command, it will
415 * deasert both latch enables.
417 * Rather than run a separate DMA operation for every single byte, we
418 * queue them up and run a single DMA operation for the entire series
419 * of command and data bytes.
421 if (ctrl & (NAND_ALE | NAND_CLE)) {
422 if (data != NAND_CMD_NONE)
423 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
428 * If control arrives here, MTD has deasserted both the ALE and CLE,
429 * which means it's ready to run an operation. Check if we have any
432 if (nand_info->cmd_queue_len == 0)
435 /* Compile the DMA descriptor -- a descriptor that sends command. */
436 d = mxs_nand_get_dma_desc(nand_info);
438 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
439 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
440 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
441 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
443 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
445 d->cmd.pio_words[0] =
446 GPMI_CTRL0_COMMAND_MODE_WRITE |
447 GPMI_CTRL0_WORD_LENGTH |
448 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
449 GPMI_CTRL0_ADDRESS_NAND_CLE |
450 GPMI_CTRL0_ADDRESS_INCREMENT |
451 nand_info->cmd_queue_len;
453 mxs_dma_desc_append(channel, d);
456 mxs_nand_flush_cmd_buf(nand_info);
458 /* Execute the DMA chain. */
459 ret = mxs_dma_go(channel);
463 printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]);
464 for (i = 0; i < nand_info->cmd_queue_len; i++) {
465 printf("%02x ", nand_info->cmd_buf[i]);
470 mxs_nand_return_dma_descs(nand_info);
472 /* Reset the command queue. */
473 nand_info->cmd_queue_len = 0;
477 * Test if the NAND flash is ready.
479 static int mxs_nand_device_ready(struct mtd_info *mtd)
481 struct nand_chip *chip = mtd->priv;
482 struct mxs_nand_info *nand_info = chip->priv;
485 tmp = readl(&gpmi_regs->hw_gpmi_stat);
486 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
492 * Select the NAND chip.
494 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
496 struct nand_chip *nand = mtd->priv;
497 struct mxs_nand_info *nand_info = nand->priv;
499 nand_info->cur_chip = chip;
503 * Handle block mark swapping.
505 * Note that, when this function is called, it doesn't know whether it's
506 * swapping the block mark, or swapping it *back* -- but it doesn't matter
507 * because the the operation is the same.
509 #ifndef CONFIG_NAND_MXS_NO_BBM_SWAP
510 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
511 uint8_t *data_buf, uint8_t *oob_buf)
519 bit_offset = mxs_nand_mark_bit_offset(mtd);
520 buf_offset = mxs_nand_mark_byte_offset(mtd);
523 * Get the byte from the data area that overlays the block mark. Since
524 * the ECC engine applies its own view to the bits in the page, the
525 * physical block mark won't (in general) appear on a byte boundary in
528 src = data_buf[buf_offset] >> bit_offset;
529 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
533 debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n",
534 src & 0xff, buf_offset, bit_offset, dst & 0xff, 0);
538 data_buf[buf_offset] &= ~(0xff << bit_offset);
539 data_buf[buf_offset + 1] &= 0xff << bit_offset;
541 data_buf[buf_offset] |= dst << bit_offset;
542 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
545 static inline void mxs_nand_swap_block_mark(struct mtd_info *mtd,
546 uint8_t *data_buf, uint8_t *oob_buf)
552 * Read data from NAND.
554 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
556 struct nand_chip *nand = mtd->priv;
557 struct mxs_nand_info *nand_info = nand->priv;
558 struct mxs_dma_desc *d;
559 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
562 if (length > NAND_MAX_PAGESIZE) {
563 printf("MXS NAND: DMA buffer too big\n");
568 printf("MXS NAND: DMA buffer is NULL\n");
572 memset(buf, 0xee, length);
574 /* Compile the DMA descriptor - a descriptor that reads data. */
575 d = mxs_nand_get_dma_desc(nand_info);
577 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
578 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
579 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
580 (length << MXS_DMA_DESC_BYTES_OFFSET);
582 d->cmd.address = (dma_addr_t)nand_info->data_buf;
584 d->cmd.pio_words[0] =
585 GPMI_CTRL0_COMMAND_MODE_READ |
586 GPMI_CTRL0_WORD_LENGTH |
587 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
588 GPMI_CTRL0_ADDRESS_NAND_DATA |
591 mxs_dma_desc_append(channel, d);
592 #ifndef CONFIG_SOC_MX6Q
594 * A DMA descriptor that waits for the command to end and the chip to
597 * I think we actually should *not* be waiting for the chip to become
598 * ready because, after all, we don't care. I think the original code
599 * did that and no one has re-thought it yet.
601 d = mxs_nand_get_dma_desc(nand_info);
603 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
604 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
605 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
609 d->cmd.pio_words[0] =
610 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
611 GPMI_CTRL0_WORD_LENGTH |
612 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
613 GPMI_CTRL0_ADDRESS_NAND_DATA;
615 mxs_dma_desc_append(channel, d);
617 /* Execute the DMA chain. */
618 ret = mxs_dma_go(channel);
620 printf("%s: DMA read error\n", __func__);
624 /* Invalidate caches */
625 mxs_nand_inval_data_buf(nand_info);
627 memcpy(buf, nand_info->data_buf, length);
630 mxs_nand_return_dma_descs(nand_info);
634 * Write data to NAND.
636 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
639 struct nand_chip *nand = mtd->priv;
640 struct mxs_nand_info *nand_info = nand->priv;
641 struct mxs_dma_desc *d;
642 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
645 if (length > NAND_MAX_PAGESIZE) {
646 printf("MXS NAND: DMA buffer too big\n");
651 printf("MXS NAND: DMA buffer is NULL\n");
655 memcpy(nand_info->data_buf, buf, length);
657 /* Compile the DMA descriptor - a descriptor that writes data. */
658 d = mxs_nand_get_dma_desc(nand_info);
660 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
661 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
662 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
663 (length << MXS_DMA_DESC_BYTES_OFFSET);
665 d->cmd.address = (dma_addr_t)nand_info->data_buf;
667 d->cmd.pio_words[0] =
668 GPMI_CTRL0_COMMAND_MODE_WRITE |
669 GPMI_CTRL0_WORD_LENGTH |
670 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
671 GPMI_CTRL0_ADDRESS_NAND_DATA |
674 mxs_dma_desc_append(channel, d);
677 mxs_nand_flush_data_buf(nand_info);
679 /* Execute the DMA chain. */
680 ret = mxs_dma_go(channel);
682 printf("%s: DMA write error\n", __func__);
684 mxs_nand_return_dma_descs(nand_info);
688 * Read a single byte from NAND.
690 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
693 mxs_nand_read_buf(mtd, &buf, 1);
697 static void flush_buffers(struct mtd_info *mtd, struct mxs_nand_info *nand_info)
699 flush_dcache_range((unsigned long)nand_info->data_buf,
700 (unsigned long)nand_info->data_buf +
702 flush_dcache_range((unsigned long)nand_info->oob_buf,
703 (unsigned long)nand_info->oob_buf +
708 * Read a page from NAND.
710 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
711 uint8_t *buf, int oob_required,
714 struct mxs_nand_info *nand_info = nand->priv;
715 struct mxs_dma_desc *d;
716 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
717 uint32_t corrected = 0, failed = 0;
721 /* Compile the DMA descriptor - wait for ready. */
722 d = mxs_nand_get_dma_desc(nand_info);
724 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
725 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
726 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
730 d->cmd.pio_words[0] =
731 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
732 GPMI_CTRL0_WORD_LENGTH |
733 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
734 GPMI_CTRL0_ADDRESS_NAND_DATA;
736 mxs_dma_desc_append(channel, d);
738 /* Compile the DMA descriptor - enable the BCH block and read. */
739 d = mxs_nand_get_dma_desc(nand_info);
741 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
742 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
746 d->cmd.pio_words[0] =
747 GPMI_CTRL0_COMMAND_MODE_READ |
748 GPMI_CTRL0_WORD_LENGTH |
749 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
750 GPMI_CTRL0_ADDRESS_NAND_DATA |
751 (mtd->writesize + mtd->oobsize);
752 d->cmd.pio_words[1] = 0;
753 d->cmd.pio_words[2] =
754 GPMI_ECCCTRL_ENABLE_ECC |
755 GPMI_ECCCTRL_ECC_CMD_DECODE |
756 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
757 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
758 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
759 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
761 flush_buffers(mtd, nand_info);
763 mxs_dma_desc_append(channel, d);
765 /* Compile the DMA descriptor - disable the BCH block. */
766 d = mxs_nand_get_dma_desc(nand_info);
768 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
769 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
770 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
774 d->cmd.pio_words[0] =
775 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
776 GPMI_CTRL0_WORD_LENGTH |
777 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
778 GPMI_CTRL0_ADDRESS_NAND_DATA |
779 (mtd->writesize + mtd->oobsize);
780 d->cmd.pio_words[1] = 0;
781 d->cmd.pio_words[2] = 0;
783 mxs_dma_desc_append(channel, d);
785 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
786 d = mxs_nand_get_dma_desc(nand_info);
788 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
789 MXS_DMA_DESC_DEC_SEM;
793 mxs_dma_desc_append(channel, d);
795 /* Execute the DMA chain. */
796 ret = mxs_dma_go(channel);
798 printf("%s: DMA read error\n", __func__);
802 ret = mxs_nand_wait_for_bch_complete();
804 printf("MXS NAND: BCH read timeout\n");
808 /* Invalidate caches */
809 mxs_nand_inval_data_buf(nand_info);
811 /* Read DMA completed, now do the mark swapping. */
812 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
814 /* Loop over status bytes, accumulating ECC status. */
815 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
816 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd); i++) {
817 if (status[i] == 0x00)
820 if (status[i] == 0xff)
823 if (status[i] == 0xfe) {
828 corrected += status[i];
831 /* Propagate ECC status to the owning MTD. */
832 mtd->ecc_stats.failed += failed;
833 mtd->ecc_stats.corrected += corrected;
836 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
837 * details about our policy for delivering the OOB.
839 * We fill the caller's buffer with set bits, and then copy the block
840 * mark to the caller's buffer. Note that, if block mark swapping was
841 * necessary, it has already been done, so we can rely on the first
842 * byte of the auxiliary buffer to contain the block mark.
844 memset(nand->oob_poi, 0xff, mtd->oobsize);
846 nand->oob_poi[0] = nand_info->oob_buf[0];
848 memcpy(buf, nand_info->data_buf, mtd->writesize);
851 mxs_nand_return_dma_descs(nand_info);
857 * Write a page to NAND.
859 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
860 struct nand_chip *nand, const uint8_t *buf,
863 struct mxs_nand_info *nand_info = nand->priv;
864 struct mxs_dma_desc *d;
865 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
868 memcpy(nand_info->data_buf, buf, mtd->writesize);
869 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
871 /* Handle block mark swapping. */
872 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
874 /* Compile the DMA descriptor - write data. */
875 d = mxs_nand_get_dma_desc(nand_info);
877 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
878 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
879 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
883 d->cmd.pio_words[0] =
884 GPMI_CTRL0_COMMAND_MODE_WRITE |
885 GPMI_CTRL0_WORD_LENGTH |
886 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
887 GPMI_CTRL0_ADDRESS_NAND_DATA;
888 d->cmd.pio_words[1] = 0;
889 d->cmd.pio_words[2] =
890 GPMI_ECCCTRL_ENABLE_ECC |
891 GPMI_ECCCTRL_ECC_CMD_ENCODE |
892 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
893 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
894 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
895 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
897 flush_buffers(mtd, nand_info);
899 mxs_dma_desc_append(channel, d);
902 mxs_nand_flush_data_buf(nand_info);
904 /* Execute the DMA chain. */
905 ret = mxs_dma_go(channel);
907 printf("%s: DMA write error\n", __func__);
911 ret = mxs_nand_wait_for_bch_complete();
913 printf("%s: BCH write timeout\n", __func__);
918 mxs_nand_return_dma_descs(nand_info);
923 * Read OOB from NAND.
925 * This function is a veneer that replaces the function originally installed by
926 * the NAND Flash MTD code.
928 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
929 struct mtd_oob_ops *ops)
931 struct nand_chip *chip = mtd->priv;
932 struct mxs_nand_info *nand_info = chip->priv;
935 if (ops->mode == MTD_OPS_RAW)
936 nand_info->raw_oob_mode = 1;
938 nand_info->raw_oob_mode = 0;
940 ret = nand_info->hooked_read_oob(mtd, from, ops);
942 nand_info->raw_oob_mode = 0;
950 * This function is a veneer that replaces the function originally installed by
951 * the NAND Flash MTD code.
953 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
954 struct mtd_oob_ops *ops)
956 struct nand_chip *chip = mtd->priv;
957 struct mxs_nand_info *nand_info = chip->priv;
960 if (ops->mode == MTD_OPS_RAW)
961 nand_info->raw_oob_mode = 1;
963 nand_info->raw_oob_mode = 0;
965 ret = nand_info->hooked_write_oob(mtd, to, ops);
967 nand_info->raw_oob_mode = 0;
973 * Mark a block bad in NAND.
975 * This function is a veneer that replaces the function originally installed by
976 * the NAND Flash MTD code.
978 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
980 struct nand_chip *chip = mtd->priv;
981 struct mxs_nand_info *nand_info = chip->priv;
984 nand_info->marking_block_bad = 1;
986 ret = nand_info->hooked_block_markbad(mtd, ofs);
988 nand_info->marking_block_bad = 0;
994 * There are several places in this driver where we have to handle the OOB and
995 * block marks. This is the function where things are the most complicated, so
996 * this is where we try to explain it all. All the other places refer back to
999 * These are the rules, in order of decreasing importance:
1001 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
1002 * write operations take measures to protect it.
1004 * 2) In read operations, the first byte of the OOB we return must reflect the
1005 * true state of the block mark, no matter where that block mark appears in
1006 * the physical page.
1008 * 3) ECC-based read operations return an OOB full of set bits (since we never
1009 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1012 * 4) "Raw" read operations return a direct view of the physical bytes in the
1013 * page, using the conventional definition of which bytes are data and which
1014 * are OOB. This gives the caller a way to see the actual, physical bytes
1015 * in the page, without the distortions applied by our ECC engine.
1017 * What we do for this specific read operation depends on whether we're doing
1018 * "raw" read, or an ECC-based read.
1020 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1021 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1022 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1023 * ECC-based or raw view of the page is implicit in which function it calls
1024 * (there is a similar pair of ECC-based/raw functions for writing).
1026 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
1027 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
1028 * caller wants an ECC-based or raw view of the page is not propagated down to
1031 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
1032 * ecc.read_oob and ecc.write_oob function pointers in the owning
1033 * struct mtd_info with our own functions. These hook functions set the
1034 * raw_oob_mode field so that, when control finally arrives here, we'll know
1037 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
1040 struct mxs_nand_info *nand_info = nand->priv;
1043 * First, fill in the OOB buffer. If we're doing a raw read, we need to
1044 * get the bytes from the physical page. If we're not doing a raw read,
1045 * we need to fill the buffer with set bits.
1047 if (nand_info->raw_oob_mode) {
1049 * If control arrives here, we're doing a "raw" read. Send the
1050 * command to read the conventional OOB and read it.
1052 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1053 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
1056 * If control arrives here, we're not doing a "raw" read. Fill
1057 * the OOB buffer with set bits and correct the block mark.
1059 memset(nand->oob_poi, 0xff, mtd->oobsize);
1061 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1062 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
1070 * Write OOB data to NAND.
1072 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1075 struct mxs_nand_info *nand_info = nand->priv;
1076 uint8_t block_mark = 0;
1079 * There are fundamental incompatibilities between the i.MX GPMI NFC and
1080 * the NAND Flash MTD model that make it essentially impossible to write
1081 * the out-of-band bytes.
1083 * We permit *ONE* exception. If the *intent* of writing the OOB is to
1084 * mark a block bad, we can do that.
1087 if (!nand_info->marking_block_bad) {
1088 printf("NXS NAND: Writing OOB isn't supported\n");
1092 /* Write the block mark. */
1093 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1094 nand->write_buf(mtd, &block_mark, 1);
1095 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1097 /* Check if it worked. */
1098 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1105 * Claims all blocks are good.
1107 * In principle, this function is *only* called when the NAND Flash MTD system
1108 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1109 * the driver for bad block information.
1111 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1112 * this function is *only* called when we take it away.
1114 * Thus, this function is only called when we want *all* blocks to look good,
1115 * so it *always* return success.
1117 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
1123 * Nominally, the purpose of this function is to look for or create the bad
1124 * block table. In fact, since the we call this function at the very end of
1125 * the initialization process started by nand_scan(), and we don't have a
1126 * more formal mechanism, we "hook" this function to continue init process.
1128 * At this point, the physical NAND Flash chips have been identified and
1129 * counted, so we know the physical geometry. This enables us to make some
1130 * important configuration decisions.
1132 * The return value of this function propogates directly back to this driver's
1133 * call to nand_scan(). Anything other than zero will cause this driver to
1134 * tear everything down and declare failure.
1136 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
1138 struct nand_chip *nand = mtd->priv;
1139 struct mxs_nand_info *nand_info = nand->priv;
1142 /* Configure BCH and set NFC geometry */
1143 if (readl(&bch_regs->hw_bch_ctrl_reg) &
1144 (BCH_CTRL_SFTRST | BCH_CTRL_CLKGATE))
1145 /* When booting from NAND the BCH engine will already
1146 * be operational and obviously does not like being reset here.
1147 * There will be occasional read errors upon boot when this
1150 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1151 readl(&bch_regs->hw_bch_ctrl_reg);
1153 debug("mtd->writesize=%d\n", mtd->writesize);
1154 debug("mtd->oobsize=%d\n", mtd->oobsize);
1155 debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize));
1157 /* Configure layout 0 */
1158 tmp = (mxs_nand_ecc_chunk_cnt(mtd) - 1)
1159 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1160 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1161 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1162 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1163 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1164 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1165 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1167 tmp = (mtd->writesize + mtd->oobsize)
1168 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1169 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1170 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1171 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1172 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1173 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1175 /* Set *all* chip selects to use layout 0 */
1176 writel(0, &bch_regs->hw_bch_layoutselect);
1178 /* Enable BCH complete interrupt */
1179 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1181 /* Hook some operations at the MTD level. */
1182 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1183 nand_info->hooked_read_oob = mtd->_read_oob;
1184 mtd->_read_oob = mxs_nand_hook_read_oob;
1187 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1188 nand_info->hooked_write_oob = mtd->_write_oob;
1189 mtd->_write_oob = mxs_nand_hook_write_oob;
1192 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1193 nand_info->hooked_block_markbad = mtd->_block_markbad;
1194 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1197 /* We use the reference implementation for bad block management. */
1198 return nand_default_bbt(mtd);
1202 * Allocate DMA buffers
1204 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1207 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1209 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1212 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1214 printf("%s: Error allocating DMA buffers\n", __func__);
1218 memset(buf, 0, nand_info->data_buf_size);
1220 nand_info->data_buf = buf;
1221 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1222 /* Command buffers */
1223 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1224 MXS_NAND_COMMAND_BUFFER_SIZE);
1225 if (!nand_info->cmd_buf) {
1227 printf("MXS NAND: Error allocating command buffers\n");
1230 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1231 nand_info->cmd_queue_len = 0;
1237 * Initializes the NFC hardware.
1239 int mxs_nand_init(struct mxs_nand_info *info)
1244 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1245 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1247 printf("MXS NAND: Unable to allocate DMA descriptor table\n");
1254 /* Allocate the DMA descriptors. */
1255 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1256 info->desc[i] = mxs_dma_desc_alloc();
1257 if (!info->desc[i]) {
1258 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1264 /* Init the DMA controller. */
1265 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) {
1266 const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i;
1268 ret = mxs_dma_init_channel(chan);
1270 printf("Failed to initialize DMA channel %d\n", chan);
1275 ret = mxs_nand_gpmi_init();
1282 for (--i; i >= 0; i--)
1283 mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0);
1284 i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1;
1287 for (--i; i >= 0; i--)
1288 mxs_dma_desc_free(info->desc[i]);
1294 * This function is called during the driver binding process.
1296 * @param pdev the device structure used to store device specific
1297 * information that is used by the suspend, resume and
1300 * @return The function always returns 0.
1302 int board_nand_init(struct nand_chip *nand)
1304 struct mxs_nand_info *nand_info;
1307 nand_info = calloc(1, sizeof(struct mxs_nand_info));
1309 printf("MXS NAND: Failed to allocate private data\n");
1313 err = mxs_nand_alloc_buffers(nand_info);
1317 err = mxs_nand_init(nand_info);
1321 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1323 nand->priv = nand_info;
1324 nand->options |= NAND_NO_SUBPAGE_WRITE;
1325 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1326 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1328 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1330 nand->dev_ready = mxs_nand_device_ready;
1331 nand->select_chip = mxs_nand_select_chip;
1332 nand->block_bad = mxs_nand_block_bad;
1333 nand->scan_bbt = mxs_nand_scan_bbt;
1335 nand->read_byte = mxs_nand_read_byte;
1337 nand->read_buf = mxs_nand_read_buf;
1338 nand->write_buf = mxs_nand_write_buf;
1340 nand->ecc.read_page = mxs_nand_ecc_read_page;
1341 nand->ecc.write_page = mxs_nand_ecc_write_page;
1342 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1343 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1345 nand->ecc.layout = &fake_ecc_layout;
1346 nand->ecc.mode = NAND_ECC_HW;
1347 nand->ecc.bytes = 9;
1348 nand->ecc.size = 512;
1349 nand->ecc.strength = 8;
1354 free(nand_info->data_buf);
1355 free(nand_info->cmd_buf);