2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/types.h>
22 #include <asm/errno.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/imx-common/regs-bch.h>
27 #include <asm/imx-common/regs-gpmi.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/imx-common/dma.h>
31 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
33 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
34 #if defined(CONFIG_SOC_MX6)
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
39 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
41 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
43 /* BCH timeout in microseconds */
44 #define MXS_NAND_BCH_TIMEOUT 10000
46 static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS;
47 static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS;
48 struct mxs_nand_info {
51 uint32_t cmd_queue_len;
52 uint32_t data_buf_size;
58 uint8_t marking_block_bad;
61 /* Functions with altered behaviour */
62 int (*hooked_read_oob)(struct mtd_info *mtd,
63 loff_t from, struct mtd_oob_ops *ops);
64 int (*hooked_write_oob)(struct mtd_info *mtd,
65 loff_t to, struct mtd_oob_ops *ops);
66 int (*hooked_block_markbad)(struct mtd_info *mtd,
70 struct mxs_dma_desc **desc;
75 #define dump_reg(b, r) __dump_reg(&b->r, #r)
76 static inline void __dump_reg(void *addr, const char *name)
78 printf("%16s[%p]=%08x\n", name, addr, readl(addr));
81 #define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n)
82 #define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n)
83 static inline void dump_regs(void)
87 dump_bch_reg(status0);
90 dump_bch_reg(dbgkesread);
91 dump_bch_reg(dbgcsferead);
92 dump_bch_reg(dbgsyndegread);
93 dump_bch_reg(dbgahbmread);
94 dump_bch_reg(blockname);
95 dump_bch_reg(version);
99 dump_gpmi_reg(eccctrl);
100 dump_gpmi_reg(ecccount);
101 dump_gpmi_reg(payload);
102 dump_gpmi_reg(auxiliary);
103 dump_gpmi_reg(ctrl1);
106 dump_gpmi_reg(debug);
107 dump_gpmi_reg(version);
108 dump_gpmi_reg(debug2);
109 dump_gpmi_reg(debug3);
112 static inline int dbg_addr(void *addr)
114 if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS)
119 static inline u32 mxs_readl(void *addr,
120 const char *fn, int ln)
122 u32 val = readl(addr);
123 static void *last_addr;
129 if (addr != last_addr || last_val != val) {
130 printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
137 static inline void mxs_writel(u32 val, void *addr,
138 const char *fn, int ln)
141 printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
144 printf(" result: %08x\n", readl(addr));
148 #define readl(a) mxs_readl(a, __func__, __LINE__)
151 #define writel(v, a) mxs_writel(v, a, __func__, __LINE__)
152 static inline void memdump(const void *addr, size_t len)
154 const char *buf = addr;
157 for (i = 0; i < len; i++) {
161 printf("%p:", &buf[i]);
163 printf(" %02x", buf[i]);
168 static inline void memdump(void *addr, size_t len)
172 static inline void dump_regs(void)
177 struct nand_ecclayout fake_ecc_layout;
180 * Cache management functions
182 #ifndef CONFIG_SYS_DCACHE_OFF
183 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
185 uint32_t addr = (uint32_t)info->data_buf;
187 flush_dcache_range(addr, addr + info->data_buf_size);
190 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
192 uint32_t addr = (uint32_t)info->data_buf;
194 invalidate_dcache_range(addr, addr + info->data_buf_size);
197 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
199 uint32_t addr = (uint32_t)info->cmd_buf;
201 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
204 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
205 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
206 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
209 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
211 struct mxs_dma_desc *desc;
213 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
214 printf("MXS NAND: Too many DMA descriptors requested\n");
218 desc = info->desc[info->desc_index];
224 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
227 struct mxs_dma_desc *desc;
229 for (i = 0; i < info->desc_index; i++) {
230 desc = info->desc[i];
231 memset(desc, 0, sizeof(struct mxs_dma_desc));
232 desc->address = (dma_addr_t)desc;
235 info->desc_index = 0;
238 static uint32_t mxs_nand_ecc_chunk_cnt(struct mtd_info *mtd)
240 struct nand_chip *nand = mtd->priv;
241 return mtd->writesize / nand->ecc.size;
244 static inline uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
246 return ecc_strength * MXS_NAND_BITS_PER_ECC_LEVEL;
249 static uint32_t mxs_nand_aux_status_offset(void)
251 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
254 static int mxs_nand_gpmi_init(void)
258 /* Reset the GPMI block. */
259 ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
264 * Choose NAND mode, set IRQ polarity, disable write protection and
267 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
268 GPMI_CTRL1_GPMI_MODE,
269 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
270 GPMI_CTRL1_BCH_MODE);
271 writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1);
275 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
276 uint32_t page_oob_size)
281 * Determine the ECC layout with the formula:
282 * ECC bits per chunk = (total page spare data bits) /
283 * (bits per ECC level) / (chunks per page)
285 * total page spare data bits =
286 * (page oob size - meta data size) * (bits per byte)
288 ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
289 / (MXS_NAND_BITS_PER_ECC_LEVEL *
290 mxs_nand_ecc_chunk_cnt(page_data_size));
292 return round_down(ecc_strength, 2);
295 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
296 uint32_t ecc_strength)
298 uint32_t chunk_data_size_in_bits;
299 uint32_t chunk_ecc_size_in_bits;
300 uint32_t chunk_total_size_in_bits;
301 uint32_t block_mark_chunk_number;
302 uint32_t block_mark_chunk_bit_offset;
303 uint32_t block_mark_bit_offset;
305 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
306 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
308 chunk_total_size_in_bits =
309 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
311 /* Compute the bit offset of the block mark within the physical page. */
312 block_mark_bit_offset = page_data_size * 8;
314 /* Subtract the metadata bits. */
315 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
318 * Compute the chunk number (starting at zero) in which the block mark
321 block_mark_chunk_number =
322 block_mark_bit_offset / chunk_total_size_in_bits;
325 * Compute the bit offset of the block mark within its chunk, and
328 block_mark_chunk_bit_offset = block_mark_bit_offset -
329 (block_mark_chunk_number * chunk_total_size_in_bits);
331 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
335 * Now that we know the chunk number in which the block mark appears,
336 * we can subtract all the ECC bits that appear before it.
338 block_mark_bit_offset -=
339 block_mark_chunk_number * chunk_ecc_size_in_bits;
341 return block_mark_bit_offset;
344 static inline uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
346 uint32_t ecc_strength;
347 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
348 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
351 static inline uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
353 uint32_t ecc_strength;
354 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
355 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
359 * Wait for BCH complete IRQ and clear the IRQ
361 static int mxs_nand_wait_for_bch_complete(void)
363 int timeout = MXS_NAND_BCH_TIMEOUT;
366 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
367 BCH_CTRL_COMPLETE_IRQ, timeout);
369 debug("%s@%d: %d\n", __func__, __LINE__, ret);
370 mxs_nand_gpmi_init();
373 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
379 * This is the function that we install in the cmd_ctrl function pointer of the
380 * owning struct nand_chip. The only functions in the reference implementation
381 * that use these functions pointers are cmdfunc and select_chip.
383 * In this driver, we implement our own select_chip, so this function will only
384 * be called by the reference implementation's cmdfunc. For this reason, we can
385 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
388 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
390 struct nand_chip *nand = mtd->priv;
391 struct mxs_nand_info *nand_info = nand->priv;
392 struct mxs_dma_desc *d;
393 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
397 * If this condition is true, something is _VERY_ wrong in MTD
400 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
401 printf("MXS NAND: Command queue too long\n");
406 * Every operation begins with a command byte and a series of zero or
407 * more address bytes. These are distinguished by either the Address
408 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
409 * asserted. When MTD is ready to execute the command, it will
410 * deasert both latch enables.
412 * Rather than run a separate DMA operation for every single byte, we
413 * queue them up and run a single DMA operation for the entire series
414 * of command and data bytes.
416 if (ctrl & (NAND_ALE | NAND_CLE)) {
417 if (data != NAND_CMD_NONE)
418 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
423 * If control arrives here, MTD has deasserted both the ALE and CLE,
424 * which means it's ready to run an operation. Check if we have any
427 if (nand_info->cmd_queue_len == 0)
430 /* Compile the DMA descriptor -- a descriptor that sends command. */
431 d = mxs_nand_get_dma_desc(nand_info);
433 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
434 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
435 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
436 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
438 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
440 d->cmd.pio_words[0] =
441 GPMI_CTRL0_COMMAND_MODE_WRITE |
442 GPMI_CTRL0_WORD_LENGTH |
443 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
444 GPMI_CTRL0_ADDRESS_NAND_CLE |
445 GPMI_CTRL0_ADDRESS_INCREMENT |
446 nand_info->cmd_queue_len;
448 mxs_dma_desc_append(channel, d);
451 mxs_nand_flush_cmd_buf(nand_info);
453 /* Execute the DMA chain. */
454 ret = mxs_dma_go(channel);
458 printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]);
459 for (i = 0; i < nand_info->cmd_queue_len; i++) {
460 printf("%02x ", nand_info->cmd_buf[i]);
465 mxs_nand_return_dma_descs(nand_info);
467 /* Reset the command queue. */
468 nand_info->cmd_queue_len = 0;
472 * Test if the NAND flash is ready.
474 static int mxs_nand_device_ready(struct mtd_info *mtd)
476 struct nand_chip *chip = mtd->priv;
477 struct mxs_nand_info *nand_info = chip->priv;
480 tmp = readl(&gpmi_regs->hw_gpmi_stat);
481 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
487 * Select the NAND chip.
489 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
491 struct nand_chip *nand = mtd->priv;
492 struct mxs_nand_info *nand_info = nand->priv;
494 nand_info->cur_chip = chip;
498 * Handle block mark swapping.
500 * Note that, when this function is called, it doesn't know whether it's
501 * swapping the block mark, or swapping it *back* -- but it doesn't matter
502 * because the the operation is the same.
504 #ifndef CONFIG_NAND_MXS_NO_BBM_SWAP
505 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
506 uint8_t *data_buf, uint8_t *oob_buf)
514 bit_offset = mxs_nand_mark_bit_offset(mtd);
515 buf_offset = mxs_nand_mark_byte_offset(mtd);
518 * Get the byte from the data area that overlays the block mark. Since
519 * the ECC engine applies its own view to the bits in the page, the
520 * physical block mark won't (in general) appear on a byte boundary in
523 src = data_buf[buf_offset] >> bit_offset;
524 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
528 debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n",
529 src & 0xff, buf_offset, bit_offset, dst & 0xff, 0);
533 data_buf[buf_offset] &= ~(0xff << bit_offset);
534 data_buf[buf_offset + 1] &= 0xff << bit_offset;
536 data_buf[buf_offset] |= dst << bit_offset;
537 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
540 static inline void mxs_nand_swap_block_mark(struct mtd_info *mtd,
541 uint8_t *data_buf, uint8_t *oob_buf)
547 * Read data from NAND.
549 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
551 struct nand_chip *nand = mtd->priv;
552 struct mxs_nand_info *nand_info = nand->priv;
553 struct mxs_dma_desc *d;
554 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
557 if (length > NAND_MAX_PAGESIZE) {
558 printf("MXS NAND: DMA buffer too big\n");
563 printf("MXS NAND: DMA buffer is NULL\n");
567 memset(buf, 0xee, length);
569 /* Compile the DMA descriptor - a descriptor that reads data. */
570 d = mxs_nand_get_dma_desc(nand_info);
572 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
573 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
574 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
575 (length << MXS_DMA_DESC_BYTES_OFFSET);
577 d->cmd.address = (dma_addr_t)nand_info->data_buf;
579 d->cmd.pio_words[0] =
580 GPMI_CTRL0_COMMAND_MODE_READ |
581 GPMI_CTRL0_WORD_LENGTH |
582 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
583 GPMI_CTRL0_ADDRESS_NAND_DATA |
586 mxs_dma_desc_append(channel, d);
587 #ifndef CONFIG_SOC_MX6Q
589 * A DMA descriptor that waits for the command to end and the chip to
592 * I think we actually should *not* be waiting for the chip to become
593 * ready because, after all, we don't care. I think the original code
594 * did that and no one has re-thought it yet.
596 d = mxs_nand_get_dma_desc(nand_info);
598 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
599 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
600 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
604 d->cmd.pio_words[0] =
605 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
606 GPMI_CTRL0_WORD_LENGTH |
607 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
608 GPMI_CTRL0_ADDRESS_NAND_DATA;
610 mxs_dma_desc_append(channel, d);
612 /* Execute the DMA chain. */
613 ret = mxs_dma_go(channel);
615 printf("%s: DMA read error\n", __func__);
619 /* Invalidate caches */
620 mxs_nand_inval_data_buf(nand_info);
622 memcpy(buf, nand_info->data_buf, length);
625 mxs_nand_return_dma_descs(nand_info);
629 * Write data to NAND.
631 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
634 struct nand_chip *nand = mtd->priv;
635 struct mxs_nand_info *nand_info = nand->priv;
636 struct mxs_dma_desc *d;
637 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
640 if (length > NAND_MAX_PAGESIZE) {
641 printf("MXS NAND: DMA buffer too big\n");
646 printf("MXS NAND: DMA buffer is NULL\n");
650 memcpy(nand_info->data_buf, buf, length);
652 /* Compile the DMA descriptor - a descriptor that writes data. */
653 d = mxs_nand_get_dma_desc(nand_info);
655 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
656 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
657 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
658 (length << MXS_DMA_DESC_BYTES_OFFSET);
660 d->cmd.address = (dma_addr_t)nand_info->data_buf;
662 d->cmd.pio_words[0] =
663 GPMI_CTRL0_COMMAND_MODE_WRITE |
664 GPMI_CTRL0_WORD_LENGTH |
665 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
666 GPMI_CTRL0_ADDRESS_NAND_DATA |
669 mxs_dma_desc_append(channel, d);
672 mxs_nand_flush_data_buf(nand_info);
674 /* Execute the DMA chain. */
675 ret = mxs_dma_go(channel);
677 printf("%s: DMA write error\n", __func__);
679 mxs_nand_return_dma_descs(nand_info);
683 * Read a single byte from NAND.
685 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
688 mxs_nand_read_buf(mtd, &buf, 1);
692 static void flush_buffers(struct mtd_info *mtd, struct mxs_nand_info *nand_info)
694 flush_dcache_range((unsigned long)nand_info->data_buf,
695 (unsigned long)nand_info->data_buf +
697 flush_dcache_range((unsigned long)nand_info->oob_buf,
698 (unsigned long)nand_info->oob_buf +
703 * Read a page from NAND.
705 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
706 uint8_t *buf, int oob_required,
709 struct mxs_nand_info *nand_info = nand->priv;
710 struct mxs_dma_desc *d;
711 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
712 uint32_t corrected = 0, failed = 0;
716 /* Compile the DMA descriptor - wait for ready. */
717 d = mxs_nand_get_dma_desc(nand_info);
719 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
720 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
721 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
725 d->cmd.pio_words[0] =
726 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
727 GPMI_CTRL0_WORD_LENGTH |
728 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
729 GPMI_CTRL0_ADDRESS_NAND_DATA;
731 mxs_dma_desc_append(channel, d);
733 /* Compile the DMA descriptor - enable the BCH block and read. */
734 d = mxs_nand_get_dma_desc(nand_info);
736 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
737 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
741 d->cmd.pio_words[0] =
742 GPMI_CTRL0_COMMAND_MODE_READ |
743 GPMI_CTRL0_WORD_LENGTH |
744 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
745 GPMI_CTRL0_ADDRESS_NAND_DATA |
746 (mtd->writesize + mtd->oobsize);
747 d->cmd.pio_words[1] = 0;
748 d->cmd.pio_words[2] =
749 GPMI_ECCCTRL_ENABLE_ECC |
750 GPMI_ECCCTRL_ECC_CMD_DECODE |
751 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
752 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
753 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
754 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
756 flush_buffers(mtd, nand_info);
758 mxs_dma_desc_append(channel, d);
760 /* Compile the DMA descriptor - disable the BCH block. */
761 d = mxs_nand_get_dma_desc(nand_info);
763 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
764 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
765 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
769 d->cmd.pio_words[0] =
770 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
771 GPMI_CTRL0_WORD_LENGTH |
772 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
773 GPMI_CTRL0_ADDRESS_NAND_DATA |
774 (mtd->writesize + mtd->oobsize);
775 d->cmd.pio_words[1] = 0;
776 d->cmd.pio_words[2] = 0;
778 mxs_dma_desc_append(channel, d);
780 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
781 d = mxs_nand_get_dma_desc(nand_info);
783 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
784 MXS_DMA_DESC_DEC_SEM;
788 mxs_dma_desc_append(channel, d);
790 /* Execute the DMA chain. */
791 ret = mxs_dma_go(channel);
793 printf("%s: DMA read error\n", __func__);
797 ret = mxs_nand_wait_for_bch_complete();
799 printf("MXS NAND: BCH read timeout\n");
803 /* Invalidate caches */
804 mxs_nand_inval_data_buf(nand_info);
806 /* Read DMA completed, now do the mark swapping. */
807 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
809 /* Loop over status bytes, accumulating ECC status. */
810 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
811 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd); i++) {
812 if (status[i] == 0x00)
815 if (status[i] == 0xff)
818 if (status[i] == 0xfe) {
823 corrected += status[i];
826 /* Propagate ECC status to the owning MTD. */
827 mtd->ecc_stats.failed += failed;
828 mtd->ecc_stats.corrected += corrected;
831 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
832 * details about our policy for delivering the OOB.
834 * We fill the caller's buffer with set bits, and then copy the block
835 * mark to the caller's buffer. Note that, if block mark swapping was
836 * necessary, it has already been done, so we can rely on the first
837 * byte of the auxiliary buffer to contain the block mark.
839 memset(nand->oob_poi, 0xff, mtd->oobsize);
841 nand->oob_poi[0] = nand_info->oob_buf[0];
843 memcpy(buf, nand_info->data_buf, mtd->writesize);
846 mxs_nand_return_dma_descs(nand_info);
852 * Write a page to NAND.
854 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
855 struct nand_chip *nand, const uint8_t *buf,
858 struct mxs_nand_info *nand_info = nand->priv;
859 struct mxs_dma_desc *d;
860 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
863 memcpy(nand_info->data_buf, buf, mtd->writesize);
864 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
866 /* Handle block mark swapping. */
867 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
869 /* Compile the DMA descriptor - write data. */
870 d = mxs_nand_get_dma_desc(nand_info);
872 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
873 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
874 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
878 d->cmd.pio_words[0] =
879 GPMI_CTRL0_COMMAND_MODE_WRITE |
880 GPMI_CTRL0_WORD_LENGTH |
881 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
882 GPMI_CTRL0_ADDRESS_NAND_DATA;
883 d->cmd.pio_words[1] = 0;
884 d->cmd.pio_words[2] =
885 GPMI_ECCCTRL_ENABLE_ECC |
886 GPMI_ECCCTRL_ECC_CMD_ENCODE |
887 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
888 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
889 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
890 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
892 flush_buffers(mtd, nand_info);
894 mxs_dma_desc_append(channel, d);
897 mxs_nand_flush_data_buf(nand_info);
899 /* Execute the DMA chain. */
900 ret = mxs_dma_go(channel);
902 printf("%s: DMA write error\n", __func__);
906 ret = mxs_nand_wait_for_bch_complete();
908 printf("%s: BCH write timeout\n", __func__);
913 mxs_nand_return_dma_descs(nand_info);
918 * Read OOB from NAND.
920 * This function is a veneer that replaces the function originally installed by
921 * the NAND Flash MTD code.
923 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
924 struct mtd_oob_ops *ops)
926 struct nand_chip *chip = mtd->priv;
927 struct mxs_nand_info *nand_info = chip->priv;
930 if (ops->mode == MTD_OPS_RAW)
931 nand_info->raw_oob_mode = 1;
933 nand_info->raw_oob_mode = 0;
935 ret = nand_info->hooked_read_oob(mtd, from, ops);
937 nand_info->raw_oob_mode = 0;
945 * This function is a veneer that replaces the function originally installed by
946 * the NAND Flash MTD code.
948 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
949 struct mtd_oob_ops *ops)
951 struct nand_chip *chip = mtd->priv;
952 struct mxs_nand_info *nand_info = chip->priv;
955 if (ops->mode == MTD_OPS_RAW)
956 nand_info->raw_oob_mode = 1;
958 nand_info->raw_oob_mode = 0;
960 ret = nand_info->hooked_write_oob(mtd, to, ops);
962 nand_info->raw_oob_mode = 0;
968 * Mark a block bad in NAND.
970 * This function is a veneer that replaces the function originally installed by
971 * the NAND Flash MTD code.
973 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
975 struct nand_chip *chip = mtd->priv;
976 struct mxs_nand_info *nand_info = chip->priv;
979 nand_info->marking_block_bad = 1;
981 ret = nand_info->hooked_block_markbad(mtd, ofs);
983 nand_info->marking_block_bad = 0;
989 * There are several places in this driver where we have to handle the OOB and
990 * block marks. This is the function where things are the most complicated, so
991 * this is where we try to explain it all. All the other places refer back to
994 * These are the rules, in order of decreasing importance:
996 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
997 * write operations take measures to protect it.
999 * 2) In read operations, the first byte of the OOB we return must reflect the
1000 * true state of the block mark, no matter where that block mark appears in
1001 * the physical page.
1003 * 3) ECC-based read operations return an OOB full of set bits (since we never
1004 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1007 * 4) "Raw" read operations return a direct view of the physical bytes in the
1008 * page, using the conventional definition of which bytes are data and which
1009 * are OOB. This gives the caller a way to see the actual, physical bytes
1010 * in the page, without the distortions applied by our ECC engine.
1012 * What we do for this specific read operation depends on whether we're doing
1013 * "raw" read, or an ECC-based read.
1015 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1016 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1017 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1018 * ECC-based or raw view of the page is implicit in which function it calls
1019 * (there is a similar pair of ECC-based/raw functions for writing).
1021 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
1022 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
1023 * caller wants an ECC-based or raw view of the page is not propagated down to
1026 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
1027 * ecc.read_oob and ecc.write_oob function pointers in the owning
1028 * struct mtd_info with our own functions. These hook functions set the
1029 * raw_oob_mode field so that, when control finally arrives here, we'll know
1032 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
1035 struct mxs_nand_info *nand_info = nand->priv;
1038 * First, fill in the OOB buffer. If we're doing a raw read, we need to
1039 * get the bytes from the physical page. If we're not doing a raw read,
1040 * we need to fill the buffer with set bits.
1042 if (nand_info->raw_oob_mode) {
1044 * If control arrives here, we're doing a "raw" read. Send the
1045 * command to read the conventional OOB and read it.
1047 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1048 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
1051 * If control arrives here, we're not doing a "raw" read. Fill
1052 * the OOB buffer with set bits and correct the block mark.
1054 memset(nand->oob_poi, 0xff, mtd->oobsize);
1056 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1057 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
1065 * Write OOB data to NAND.
1067 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1070 struct mxs_nand_info *nand_info = nand->priv;
1071 uint8_t block_mark = 0;
1074 * There are fundamental incompatibilities between the i.MX GPMI NFC and
1075 * the NAND Flash MTD model that make it essentially impossible to write
1076 * the out-of-band bytes.
1078 * We permit *ONE* exception. If the *intent* of writing the OOB is to
1079 * mark a block bad, we can do that.
1082 if (!nand_info->marking_block_bad) {
1083 printf("NXS NAND: Writing OOB isn't supported\n");
1087 /* Write the block mark. */
1088 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1089 nand->write_buf(mtd, &block_mark, 1);
1090 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1092 /* Check if it worked. */
1093 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1100 * Claims all blocks are good.
1102 * In principle, this function is *only* called when the NAND Flash MTD system
1103 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1104 * the driver for bad block information.
1106 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1107 * this function is *only* called when we take it away.
1109 * Thus, this function is only called when we want *all* blocks to look good,
1110 * so it *always* return success.
1112 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
1118 * Nominally, the purpose of this function is to look for or create the bad
1119 * block table. In fact, since the we call this function at the very end of
1120 * the initialization process started by nand_scan(), and we don't have a
1121 * more formal mechanism, we "hook" this function to continue init process.
1123 * At this point, the physical NAND Flash chips have been identified and
1124 * counted, so we know the physical geometry. This enables us to make some
1125 * important configuration decisions.
1127 * The return value of this function propogates directly back to this driver's
1128 * call to nand_scan(). Anything other than zero will cause this driver to
1129 * tear everything down and declare failure.
1131 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
1133 struct nand_chip *nand = mtd->priv;
1134 struct mxs_nand_info *nand_info = nand->priv;
1137 /* Configure BCH and set NFC geometry */
1138 if (readl(&bch_regs->hw_bch_ctrl_reg) &
1139 (BCH_CTRL_SFTRST | BCH_CTRL_CLKGATE))
1140 /* When booting from NAND the BCH engine will already
1141 * be operational and obviously does not like being reset here.
1142 * There will be occasional read errors upon boot when this
1145 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1146 readl(&bch_regs->hw_bch_ctrl_reg);
1148 debug("mtd->writesize=%d\n", mtd->writesize);
1149 debug("mtd->oobsize=%d\n", mtd->oobsize);
1150 debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize));
1152 /* Configure layout 0 */
1153 tmp = (mxs_nand_ecc_chunk_cnt(mtd) - 1)
1154 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1155 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1156 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1157 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1158 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1159 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1160 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1162 tmp = (mtd->writesize + mtd->oobsize)
1163 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1164 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1165 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1166 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1167 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1168 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1170 /* Set *all* chip selects to use layout 0 */
1171 writel(0, &bch_regs->hw_bch_layoutselect);
1173 /* Enable BCH complete interrupt */
1174 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1176 /* Hook some operations at the MTD level. */
1177 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1178 nand_info->hooked_read_oob = mtd->_read_oob;
1179 mtd->_read_oob = mxs_nand_hook_read_oob;
1182 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1183 nand_info->hooked_write_oob = mtd->_write_oob;
1184 mtd->_write_oob = mxs_nand_hook_write_oob;
1187 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1188 nand_info->hooked_block_markbad = mtd->_block_markbad;
1189 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1192 /* We use the reference implementation for bad block management. */
1193 return nand_default_bbt(mtd);
1197 * Allocate DMA buffers
1199 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1202 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1204 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1207 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1209 printf("%s: Error allocating DMA buffers\n", __func__);
1213 memset(buf, 0, nand_info->data_buf_size);
1215 nand_info->data_buf = buf;
1216 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1217 /* Command buffers */
1218 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1219 MXS_NAND_COMMAND_BUFFER_SIZE);
1220 if (!nand_info->cmd_buf) {
1222 printf("MXS NAND: Error allocating command buffers\n");
1225 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1226 nand_info->cmd_queue_len = 0;
1232 * Initializes the NFC hardware.
1234 int mxs_nand_init(struct mxs_nand_info *info)
1239 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1240 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1242 printf("MXS NAND: Unable to allocate DMA descriptor table\n");
1249 /* Allocate the DMA descriptors. */
1250 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1251 info->desc[i] = mxs_dma_desc_alloc();
1252 if (!info->desc[i]) {
1253 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1259 /* Init the DMA controller. */
1260 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) {
1261 const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i;
1263 ret = mxs_dma_init_channel(chan);
1265 printf("Failed to initialize DMA channel %d\n", chan);
1270 ret = mxs_nand_gpmi_init();
1277 for (--i; i >= 0; i--)
1278 mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0);
1279 i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1;
1282 for (--i; i >= 0; i--)
1283 mxs_dma_desc_free(info->desc[i]);
1289 * This function is called during the driver binding process.
1291 * @param pdev the device structure used to store device specific
1292 * information that is used by the suspend, resume and
1295 * @return The function always returns 0.
1297 int board_nand_init(struct nand_chip *nand)
1299 struct mxs_nand_info *nand_info;
1302 nand_info = calloc(1, sizeof(struct mxs_nand_info));
1304 printf("MXS NAND: Failed to allocate private data\n");
1308 err = mxs_nand_alloc_buffers(nand_info);
1312 err = mxs_nand_init(nand_info);
1316 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1318 nand->priv = nand_info;
1319 nand->options |= NAND_NO_SUBPAGE_WRITE;
1320 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1321 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1323 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1325 nand->dev_ready = mxs_nand_device_ready;
1326 nand->select_chip = mxs_nand_select_chip;
1327 nand->block_bad = mxs_nand_block_bad;
1328 nand->scan_bbt = mxs_nand_scan_bbt;
1330 nand->read_byte = mxs_nand_read_byte;
1332 nand->read_buf = mxs_nand_read_buf;
1333 nand->write_buf = mxs_nand_write_buf;
1335 nand->ecc.read_page = mxs_nand_ecc_read_page;
1336 nand->ecc.write_page = mxs_nand_ecc_write_page;
1337 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1338 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1340 nand->ecc.layout = &fake_ecc_layout;
1341 nand->ecc.mode = NAND_ECC_HW;
1342 nand->ecc.bytes = 9;
1343 nand->ecc.size = 512;
1344 nand->ecc.strength = 8;
1349 free(nand_info->data_buf);
1350 free(nand_info->cmd_buf);