5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/err.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/nand_bch.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
49 #include <linux/mtd/partitions.h>
51 /* Define default oob placement schemes for large and small page devices */
52 static struct nand_ecclayout nand_oob_8 = {
62 static struct nand_ecclayout nand_oob_16 = {
64 .eccpos = {0, 1, 2, 3, 6, 7},
70 static struct nand_ecclayout nand_oob_64 = {
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
81 static struct nand_ecclayout nand_oob_128 = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
95 static int nand_get_device(struct mtd_info *mtd, int new_state);
97 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
101 * For devices which display every fart in the system on a separate LED. Is
102 * compiled away when LED support is disabled.
104 DEFINE_LED_TRIGGER(nand_led_trigger);
106 static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
109 struct nand_chip *chip = mtd->priv;
112 /* Start address must align on block boundary */
113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
114 pr_debug("%s: unaligned address\n", __func__);
118 /* Length must align on block boundary */
119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
120 pr_debug("%s: length not block aligned\n", __func__);
128 * nand_release_device - [GENERIC] release chip
129 * @mtd: MTD device structure
131 * Release chip lock and wake up anyone waiting on the device.
133 static void nand_release_device(struct mtd_info *mtd)
135 struct nand_chip *chip = mtd->priv;
137 /* Release the controller and the chip */
138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
146 * nand_read_byte - [DEFAULT] read one byte from the chip
147 * @mtd: MTD device structure
149 * Default read function for 8bit buswidth
151 static uint8_t nand_read_byte(struct mtd_info *mtd)
153 struct nand_chip *chip = mtd->priv;
154 return readb(chip->IO_ADDR_R);
158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
160 * @mtd: MTD device structure
162 * Default read function for 16bit buswidth with endianness conversion.
165 static uint8_t nand_read_byte16(struct mtd_info *mtd)
167 struct nand_chip *chip = mtd->priv;
168 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
172 * nand_read_word - [DEFAULT] read one word from the chip
173 * @mtd: MTD device structure
175 * Default read function for 16bit buswidth without endianness conversion.
177 static u16 nand_read_word(struct mtd_info *mtd)
179 struct nand_chip *chip = mtd->priv;
180 return readw(chip->IO_ADDR_R);
184 * nand_select_chip - [DEFAULT] control CE line
185 * @mtd: MTD device structure
186 * @chipnr: chipnumber to select, -1 for deselect
188 * Default select function for 1 chip devices.
190 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
192 struct nand_chip *chip = mtd->priv;
196 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
207 * nand_write_byte - [DEFAULT] write single byte to chip
208 * @mtd: MTD device structure
209 * @byte: value to write
211 * Default function to write a byte to I/O[7:0]
213 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
215 struct nand_chip *chip = mtd->priv;
217 chip->write_buf(mtd, &byte, 1);
221 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
222 * @mtd: MTD device structure
223 * @byte: value to write
225 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
227 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
229 struct nand_chip *chip = mtd->priv;
230 uint16_t word = byte;
233 * It's not entirely clear what should happen to I/O[15:8] when writing
234 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
236 * When the host supports a 16-bit bus width, only data is
237 * transferred at the 16-bit width. All address and command line
238 * transfers shall use only the lower 8-bits of the data bus. During
239 * command transfers, the host may place any value on the upper
240 * 8-bits of the data bus. During address transfers, the host shall
241 * set the upper 8-bits of the data bus to 00h.
243 * One user of the write_byte callback is nand_onfi_set_features. The
244 * four parameters are specified to be written to I/O[7:0], but this is
245 * neither an address nor a command transfer. Let's assume a 0 on the
246 * upper I/O lines is OK.
248 chip->write_buf(mtd, (uint8_t *)&word, 2);
252 * nand_write_buf - [DEFAULT] write buffer to chip
253 * @mtd: MTD device structure
255 * @len: number of bytes to write
257 * Default write function for 8bit buswidth.
259 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
261 struct nand_chip *chip = mtd->priv;
263 iowrite8_rep(chip->IO_ADDR_W, buf, len);
267 * nand_read_buf - [DEFAULT] read chip data into buffer
268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
272 * Default read function for 8bit buswidth.
274 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
276 struct nand_chip *chip = mtd->priv;
278 ioread8_rep(chip->IO_ADDR_R, buf, len);
282 * nand_write_buf16 - [DEFAULT] write buffer to chip
283 * @mtd: MTD device structure
285 * @len: number of bytes to write
287 * Default write function for 16bit buswidth.
289 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
291 struct nand_chip *chip = mtd->priv;
292 u16 *p = (u16 *) buf;
294 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
298 * nand_read_buf16 - [DEFAULT] read chip data into buffer
299 * @mtd: MTD device structure
300 * @buf: buffer to store date
301 * @len: number of bytes to read
303 * Default read function for 16bit buswidth.
305 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
307 struct nand_chip *chip = mtd->priv;
308 u16 *p = (u16 *) buf;
310 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
314 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
315 * @mtd: MTD device structure
316 * @ofs: offset from device start
317 * @getchip: 0, if the chip is already selected
319 * Check, if the block is bad.
321 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
323 int page, chipnr, res = 0, i = 0;
324 struct nand_chip *chip = mtd->priv;
327 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
328 ofs += mtd->erasesize - mtd->writesize;
330 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
333 chipnr = (int)(ofs >> chip->chip_shift);
335 nand_get_device(mtd, FL_READING);
337 /* Select the NAND device */
338 chip->select_chip(mtd, chipnr);
342 if (chip->options & NAND_BUSWIDTH_16) {
343 chip->cmdfunc(mtd, NAND_CMD_READOOB,
344 chip->badblockpos & 0xFE, page);
345 bad = cpu_to_le16(chip->read_word(mtd));
346 if (chip->badblockpos & 0x1)
351 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
353 bad = chip->read_byte(mtd);
356 if (likely(chip->badblockbits == 8))
359 res = hweight8(bad) < chip->badblockbits;
360 ofs += mtd->writesize;
361 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
363 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
366 chip->select_chip(mtd, -1);
367 nand_release_device(mtd);
374 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
375 * @mtd: MTD device structure
376 * @ofs: offset from device start
378 * This is the default implementation, which can be overridden by a hardware
379 * specific driver. It provides the details for writing a bad block marker to a
382 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
384 struct nand_chip *chip = mtd->priv;
385 struct mtd_oob_ops ops;
386 uint8_t buf[2] = { 0, 0 };
387 int ret = 0, res, i = 0;
391 ops.ooboffs = chip->badblockpos;
392 if (chip->options & NAND_BUSWIDTH_16) {
393 ops.ooboffs &= ~0x01;
394 ops.len = ops.ooblen = 2;
396 ops.len = ops.ooblen = 1;
398 ops.mode = MTD_OPS_PLACE_OOB;
400 /* Write to first/last page(s) if necessary */
401 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
402 ofs += mtd->erasesize - mtd->writesize;
404 res = nand_do_write_oob(mtd, ofs, &ops);
409 ofs += mtd->writesize;
410 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
416 * nand_block_markbad_lowlevel - mark a block bad
417 * @mtd: MTD device structure
418 * @ofs: offset from device start
420 * This function performs the generic NAND bad block marking steps (i.e., bad
421 * block table(s) and/or marker(s)). We only allow the hardware driver to
422 * specify how to write bad block markers to OOB (chip->block_markbad).
424 * We try operations in the following order:
425 * (1) erase the affected block, to allow OOB marker to be written cleanly
426 * (2) write bad block marker to OOB area of affected block (unless flag
427 * NAND_BBT_NO_OOB_BBM is present)
429 * Note that we retain the first error encountered in (2) or (3), finish the
430 * procedures, and dump the error in the end.
432 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
434 struct nand_chip *chip = mtd->priv;
437 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
438 struct erase_info einfo;
440 /* Attempt erase before marking OOB */
441 memset(&einfo, 0, sizeof(einfo));
444 einfo.len = 1ULL << chip->phys_erase_shift;
445 nand_erase_nand(mtd, &einfo, 0);
447 /* Write bad block marker to OOB */
448 nand_get_device(mtd, FL_WRITING);
449 ret = chip->block_markbad(mtd, ofs);
450 nand_release_device(mtd);
453 /* Mark block bad in BBT */
455 res = nand_markbad_bbt(mtd, ofs);
461 mtd->ecc_stats.badblocks++;
467 * nand_check_wp - [GENERIC] check if the chip is write protected
468 * @mtd: MTD device structure
470 * Check, if the device is write protected. The function expects, that the
471 * device is already selected.
473 static int nand_check_wp(struct mtd_info *mtd)
475 struct nand_chip *chip = mtd->priv;
477 /* Broken xD cards report WP despite being writable */
478 if (chip->options & NAND_BROKEN_XD)
481 /* Check the WP bit */
482 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
483 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
487 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
488 * @mtd: MTD device structure
489 * @ofs: offset from device start
490 * @getchip: 0, if the chip is already selected
491 * @allowbbt: 1, if its allowed to access the bbt area
493 * Check, if the block is bad. Either by reading the bad block table or
494 * calling of the scan function.
496 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 struct nand_chip *chip = mtd->priv;
502 return chip->block_bad(mtd, ofs, getchip);
504 /* Return info from the table */
505 return nand_isbad_bbt(mtd, ofs, allowbbt);
509 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
510 * @mtd: MTD device structure
513 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
518 struct nand_chip *chip = mtd->priv;
521 /* Wait for the device to get ready */
522 for (i = 0; i < timeo; i++) {
523 if (chip->dev_ready(mtd))
525 touch_softlockup_watchdog();
530 /* Wait for the ready pin, after a command. The timeout is caught later. */
531 void nand_wait_ready(struct mtd_info *mtd)
533 struct nand_chip *chip = mtd->priv;
534 unsigned long timeo = jiffies + msecs_to_jiffies(20);
537 if (in_interrupt() || oops_in_progress)
538 return panic_nand_wait_ready(mtd, 400);
540 led_trigger_event(nand_led_trigger, LED_FULL);
541 /* Wait until command is processed or timeout occurs */
543 if (chip->dev_ready(mtd))
545 touch_softlockup_watchdog();
546 } while (time_before(jiffies, timeo));
547 led_trigger_event(nand_led_trigger, LED_OFF);
549 EXPORT_SYMBOL_GPL(nand_wait_ready);
552 * nand_command - [DEFAULT] Send command to NAND device
553 * @mtd: MTD device structure
554 * @command: the command to be sent
555 * @column: the column address for this command, -1 if none
556 * @page_addr: the page address for this command, -1 if none
558 * Send command to NAND device. This function is used for small page devices
559 * (512 Bytes per page).
561 static void nand_command(struct mtd_info *mtd, unsigned int command,
562 int column, int page_addr)
564 register struct nand_chip *chip = mtd->priv;
565 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
567 /* Write out the command to the device */
568 if (command == NAND_CMD_SEQIN) {
571 if (column >= mtd->writesize) {
573 column -= mtd->writesize;
574 readcmd = NAND_CMD_READOOB;
575 } else if (column < 256) {
576 /* First 256 bytes --> READ0 */
577 readcmd = NAND_CMD_READ0;
580 readcmd = NAND_CMD_READ1;
582 chip->cmd_ctrl(mtd, readcmd, ctrl);
583 ctrl &= ~NAND_CTRL_CHANGE;
585 chip->cmd_ctrl(mtd, command, ctrl);
587 /* Address cycle, when necessary */
588 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
589 /* Serially input address */
591 /* Adjust columns for 16 bit buswidth */
592 if (chip->options & NAND_BUSWIDTH_16 &&
593 !nand_opcode_8bits(command))
595 chip->cmd_ctrl(mtd, column, ctrl);
596 ctrl &= ~NAND_CTRL_CHANGE;
598 if (page_addr != -1) {
599 chip->cmd_ctrl(mtd, page_addr, ctrl);
600 ctrl &= ~NAND_CTRL_CHANGE;
601 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
602 /* One more address cycle for devices > 32MiB */
603 if (chip->chipsize > (32 << 20))
604 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
606 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
609 * Program and erase have their own busy handlers status and sequential
614 case NAND_CMD_PAGEPROG:
615 case NAND_CMD_ERASE1:
616 case NAND_CMD_ERASE2:
618 case NAND_CMD_STATUS:
624 udelay(chip->chip_delay);
625 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
626 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
628 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
629 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
633 /* This applies to read commands */
636 * If we don't have access to the busy pin, we apply the given
639 if (!chip->dev_ready) {
640 udelay(chip->chip_delay);
645 * Apply this short delay always to ensure that we do wait tWB in
646 * any case on any machine.
650 nand_wait_ready(mtd);
654 * nand_command_lp - [DEFAULT] Send command to NAND large page device
655 * @mtd: MTD device structure
656 * @command: the command to be sent
657 * @column: the column address for this command, -1 if none
658 * @page_addr: the page address for this command, -1 if none
660 * Send command to NAND device. This is the version for the new large page
661 * devices. We don't have the separate regions as we have in the small page
662 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
664 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
665 int column, int page_addr)
667 register struct nand_chip *chip = mtd->priv;
669 /* Emulate NAND_CMD_READOOB */
670 if (command == NAND_CMD_READOOB) {
671 column += mtd->writesize;
672 command = NAND_CMD_READ0;
675 /* Command latch cycle */
676 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
678 if (column != -1 || page_addr != -1) {
679 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
681 /* Serially input address */
683 /* Adjust columns for 16 bit buswidth */
684 if (chip->options & NAND_BUSWIDTH_16 &&
685 !nand_opcode_8bits(command))
687 chip->cmd_ctrl(mtd, column, ctrl);
688 ctrl &= ~NAND_CTRL_CHANGE;
689 chip->cmd_ctrl(mtd, column >> 8, ctrl);
691 if (page_addr != -1) {
692 chip->cmd_ctrl(mtd, page_addr, ctrl);
693 chip->cmd_ctrl(mtd, page_addr >> 8,
694 NAND_NCE | NAND_ALE);
695 /* One more address cycle for devices > 128MiB */
696 if (chip->chipsize > (128 << 20))
697 chip->cmd_ctrl(mtd, page_addr >> 16,
698 NAND_NCE | NAND_ALE);
701 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
704 * Program and erase have their own busy handlers status, sequential
705 * in, and deplete1 need no delay.
709 case NAND_CMD_CACHEDPROG:
710 case NAND_CMD_PAGEPROG:
711 case NAND_CMD_ERASE1:
712 case NAND_CMD_ERASE2:
715 case NAND_CMD_STATUS:
721 udelay(chip->chip_delay);
722 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
723 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
724 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
725 NAND_NCE | NAND_CTRL_CHANGE);
726 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
730 case NAND_CMD_RNDOUT:
731 /* No ready / busy check necessary */
732 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
733 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
734 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
735 NAND_NCE | NAND_CTRL_CHANGE);
739 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
740 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
741 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
742 NAND_NCE | NAND_CTRL_CHANGE);
744 /* This applies to read commands */
747 * If we don't have access to the busy pin, we apply the given
750 if (!chip->dev_ready) {
751 udelay(chip->chip_delay);
757 * Apply this short delay always to ensure that we do wait tWB in
758 * any case on any machine.
762 nand_wait_ready(mtd);
766 * panic_nand_get_device - [GENERIC] Get chip for selected access
767 * @chip: the nand chip descriptor
768 * @mtd: MTD device structure
769 * @new_state: the state which is requested
771 * Used when in panic, no locks are taken.
773 static void panic_nand_get_device(struct nand_chip *chip,
774 struct mtd_info *mtd, int new_state)
776 /* Hardware controller shared among independent devices */
777 chip->controller->active = chip;
778 chip->state = new_state;
782 * nand_get_device - [GENERIC] Get chip for selected access
783 * @mtd: MTD device structure
784 * @new_state: the state which is requested
786 * Get the device and lock it for exclusive access
789 nand_get_device(struct mtd_info *mtd, int new_state)
791 struct nand_chip *chip = mtd->priv;
792 spinlock_t *lock = &chip->controller->lock;
793 wait_queue_head_t *wq = &chip->controller->wq;
794 DECLARE_WAITQUEUE(wait, current);
798 /* Hardware controller shared among independent devices */
799 if (!chip->controller->active)
800 chip->controller->active = chip;
802 if (chip->controller->active == chip && chip->state == FL_READY) {
803 chip->state = new_state;
807 if (new_state == FL_PM_SUSPENDED) {
808 if (chip->controller->active->state == FL_PM_SUSPENDED) {
809 chip->state = FL_PM_SUSPENDED;
814 set_current_state(TASK_UNINTERRUPTIBLE);
815 add_wait_queue(wq, &wait);
818 remove_wait_queue(wq, &wait);
823 * panic_nand_wait - [GENERIC] wait until the command is done
824 * @mtd: MTD device structure
825 * @chip: NAND chip structure
828 * Wait for command done. This is a helper function for nand_wait used when
829 * we are in interrupt context. May happen when in panic and trying to write
830 * an oops through mtdoops.
832 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
836 for (i = 0; i < timeo; i++) {
837 if (chip->dev_ready) {
838 if (chip->dev_ready(mtd))
841 if (chip->read_byte(mtd) & NAND_STATUS_READY)
849 * nand_wait - [DEFAULT] wait until the command is done
850 * @mtd: MTD device structure
851 * @chip: NAND chip structure
853 * Wait for command done. This applies to erase and program only. Erase can
854 * take up to 400ms and program up to 20ms according to general NAND and
857 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
860 int status, state = chip->state;
861 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
863 led_trigger_event(nand_led_trigger, LED_FULL);
866 * Apply this short delay always to ensure that we do wait tWB in any
867 * case on any machine.
871 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
873 if (in_interrupt() || oops_in_progress)
874 panic_nand_wait(mtd, chip, timeo);
876 timeo = jiffies + msecs_to_jiffies(timeo);
877 while (time_before(jiffies, timeo)) {
878 if (chip->dev_ready) {
879 if (chip->dev_ready(mtd))
882 if (chip->read_byte(mtd) & NAND_STATUS_READY)
888 led_trigger_event(nand_led_trigger, LED_OFF);
890 status = (int)chip->read_byte(mtd);
891 /* This can happen if in case of timeout or buggy dev_ready */
892 WARN_ON(!(status & NAND_STATUS_READY));
897 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
899 * @ofs: offset to start unlock from
900 * @len: length to unlock
901 * @invert: when = 0, unlock the range of blocks within the lower and
902 * upper boundary address
903 * when = 1, unlock the range of blocks outside the boundaries
904 * of the lower and upper boundary address
906 * Returs unlock status.
908 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
909 uint64_t len, int invert)
913 struct nand_chip *chip = mtd->priv;
915 /* Submit address of first page to unlock */
916 page = ofs >> chip->page_shift;
917 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
919 /* Submit address of last page to unlock */
920 page = (ofs + len) >> chip->page_shift;
921 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
922 (page | invert) & chip->pagemask);
924 /* Call wait ready function */
925 status = chip->waitfunc(mtd, chip);
926 /* See if device thinks it succeeded */
927 if (status & NAND_STATUS_FAIL) {
928 pr_debug("%s: error status = 0x%08x\n",
937 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
942 * Returns unlock status.
944 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
948 struct nand_chip *chip = mtd->priv;
950 pr_debug("%s: start = 0x%012llx, len = %llu\n",
951 __func__, (unsigned long long)ofs, len);
953 if (check_offs_len(mtd, ofs, len))
956 /* Align to last block address if size addresses end of the device */
957 if (ofs + len == mtd->size)
958 len -= mtd->erasesize;
960 nand_get_device(mtd, FL_UNLOCKING);
962 /* Shift to get chip number */
963 chipnr = ofs >> chip->chip_shift;
965 chip->select_chip(mtd, chipnr);
967 /* Check, if it is write protected */
968 if (nand_check_wp(mtd)) {
969 pr_debug("%s: device is write protected!\n",
975 ret = __nand_unlock(mtd, ofs, len, 0);
978 chip->select_chip(mtd, -1);
979 nand_release_device(mtd);
983 EXPORT_SYMBOL(nand_unlock);
986 * nand_lock - [REPLACEABLE] locks all blocks present in the device
988 * @ofs: offset to start unlock from
989 * @len: length to unlock
991 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
992 * have this feature, but it allows only to lock all blocks, not for specified
993 * range for block. Implementing 'lock' feature by making use of 'unlock', for
996 * Returns lock status.
998 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1001 int chipnr, status, page;
1002 struct nand_chip *chip = mtd->priv;
1004 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1005 __func__, (unsigned long long)ofs, len);
1007 if (check_offs_len(mtd, ofs, len))
1010 nand_get_device(mtd, FL_LOCKING);
1012 /* Shift to get chip number */
1013 chipnr = ofs >> chip->chip_shift;
1015 chip->select_chip(mtd, chipnr);
1017 /* Check, if it is write protected */
1018 if (nand_check_wp(mtd)) {
1019 pr_debug("%s: device is write protected!\n",
1021 status = MTD_ERASE_FAILED;
1026 /* Submit address of first page to lock */
1027 page = ofs >> chip->page_shift;
1028 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1030 /* Call wait ready function */
1031 status = chip->waitfunc(mtd, chip);
1032 /* See if device thinks it succeeded */
1033 if (status & NAND_STATUS_FAIL) {
1034 pr_debug("%s: error status = 0x%08x\n",
1040 ret = __nand_unlock(mtd, ofs, len, 0x1);
1043 chip->select_chip(mtd, -1);
1044 nand_release_device(mtd);
1048 EXPORT_SYMBOL(nand_lock);
1051 * nand_read_page_raw - [INTERN] read raw page data without ecc
1052 * @mtd: mtd info structure
1053 * @chip: nand chip info structure
1054 * @buf: buffer to store read data
1055 * @oob_required: caller requires OOB data read to chip->oob_poi
1056 * @page: page number to read
1058 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1060 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1061 uint8_t *buf, int oob_required, int page)
1063 chip->read_buf(mtd, buf, mtd->writesize);
1065 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1070 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1071 * @mtd: mtd info structure
1072 * @chip: nand chip info structure
1073 * @buf: buffer to store read data
1074 * @oob_required: caller requires OOB data read to chip->oob_poi
1075 * @page: page number to read
1077 * We need a special oob layout and handling even when OOB isn't used.
1079 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1080 struct nand_chip *chip, uint8_t *buf,
1081 int oob_required, int page)
1083 int eccsize = chip->ecc.size;
1084 int eccbytes = chip->ecc.bytes;
1085 uint8_t *oob = chip->oob_poi;
1088 for (steps = chip->ecc.steps; steps > 0; steps--) {
1089 chip->read_buf(mtd, buf, eccsize);
1092 if (chip->ecc.prepad) {
1093 chip->read_buf(mtd, oob, chip->ecc.prepad);
1094 oob += chip->ecc.prepad;
1097 chip->read_buf(mtd, oob, eccbytes);
1100 if (chip->ecc.postpad) {
1101 chip->read_buf(mtd, oob, chip->ecc.postpad);
1102 oob += chip->ecc.postpad;
1106 size = mtd->oobsize - (oob - chip->oob_poi);
1108 chip->read_buf(mtd, oob, size);
1114 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1115 * @mtd: mtd info structure
1116 * @chip: nand chip info structure
1117 * @buf: buffer to store read data
1118 * @oob_required: caller requires OOB data read to chip->oob_poi
1119 * @page: page number to read
1121 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1122 uint8_t *buf, int oob_required, int page)
1124 int i, eccsize = chip->ecc.size;
1125 int eccbytes = chip->ecc.bytes;
1126 int eccsteps = chip->ecc.steps;
1128 uint8_t *ecc_calc = chip->buffers->ecccalc;
1129 uint8_t *ecc_code = chip->buffers->ecccode;
1130 uint32_t *eccpos = chip->ecc.layout->eccpos;
1131 unsigned int max_bitflips = 0;
1133 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1135 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1136 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1138 for (i = 0; i < chip->ecc.total; i++)
1139 ecc_code[i] = chip->oob_poi[eccpos[i]];
1141 eccsteps = chip->ecc.steps;
1144 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1147 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1149 mtd->ecc_stats.failed++;
1151 mtd->ecc_stats.corrected += stat;
1152 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1155 return max_bitflips;
1159 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1160 * @mtd: mtd info structure
1161 * @chip: nand chip info structure
1162 * @data_offs: offset of requested data within the page
1163 * @readlen: data length
1164 * @bufpoi: buffer to store read data
1166 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1167 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1169 int start_step, end_step, num_steps;
1170 uint32_t *eccpos = chip->ecc.layout->eccpos;
1172 int data_col_addr, i, gaps = 0;
1173 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1174 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1176 unsigned int max_bitflips = 0;
1178 /* Column address within the page aligned to ECC size (256bytes) */
1179 start_step = data_offs / chip->ecc.size;
1180 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1181 num_steps = end_step - start_step + 1;
1183 /* Data size aligned to ECC ecc.size */
1184 datafrag_len = num_steps * chip->ecc.size;
1185 eccfrag_len = num_steps * chip->ecc.bytes;
1187 data_col_addr = start_step * chip->ecc.size;
1188 /* If we read not a page aligned data */
1189 if (data_col_addr != 0)
1190 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1192 p = bufpoi + data_col_addr;
1193 chip->read_buf(mtd, p, datafrag_len);
1196 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1197 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1200 * The performance is faster if we position offsets according to
1201 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1203 for (i = 0; i < eccfrag_len - 1; i++) {
1204 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1205 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1211 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1212 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1215 * Send the command to read the particular ECC bytes take care
1216 * about buswidth alignment in read_buf.
1218 index = start_step * chip->ecc.bytes;
1220 aligned_pos = eccpos[index] & ~(busw - 1);
1221 aligned_len = eccfrag_len;
1222 if (eccpos[index] & (busw - 1))
1224 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1227 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1228 mtd->writesize + aligned_pos, -1);
1229 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1232 for (i = 0; i < eccfrag_len; i++)
1233 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1235 p = bufpoi + data_col_addr;
1236 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1239 stat = chip->ecc.correct(mtd, p,
1240 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1242 mtd->ecc_stats.failed++;
1244 mtd->ecc_stats.corrected += stat;
1245 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1248 return max_bitflips;
1252 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1253 * @mtd: mtd info structure
1254 * @chip: nand chip info structure
1255 * @buf: buffer to store read data
1256 * @oob_required: caller requires OOB data read to chip->oob_poi
1257 * @page: page number to read
1259 * Not for syndrome calculating ECC controllers which need a special oob layout.
1261 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1262 uint8_t *buf, int oob_required, int page)
1264 int i, eccsize = chip->ecc.size;
1265 int eccbytes = chip->ecc.bytes;
1266 int eccsteps = chip->ecc.steps;
1268 uint8_t *ecc_calc = chip->buffers->ecccalc;
1269 uint8_t *ecc_code = chip->buffers->ecccode;
1270 uint32_t *eccpos = chip->ecc.layout->eccpos;
1271 unsigned int max_bitflips = 0;
1273 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1274 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1275 chip->read_buf(mtd, p, eccsize);
1276 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1278 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1280 for (i = 0; i < chip->ecc.total; i++)
1281 ecc_code[i] = chip->oob_poi[eccpos[i]];
1283 eccsteps = chip->ecc.steps;
1286 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1289 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1291 mtd->ecc_stats.failed++;
1293 mtd->ecc_stats.corrected += stat;
1294 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1297 return max_bitflips;
1301 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1302 * @mtd: mtd info structure
1303 * @chip: nand chip info structure
1304 * @buf: buffer to store read data
1305 * @oob_required: caller requires OOB data read to chip->oob_poi
1306 * @page: page number to read
1308 * Hardware ECC for large page chips, require OOB to be read first. For this
1309 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1310 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1311 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1312 * the data area, by overwriting the NAND manufacturer bad block markings.
1314 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1315 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1321 uint8_t *ecc_code = chip->buffers->ecccode;
1322 uint32_t *eccpos = chip->ecc.layout->eccpos;
1323 uint8_t *ecc_calc = chip->buffers->ecccalc;
1324 unsigned int max_bitflips = 0;
1326 /* Read the OOB area first */
1327 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1328 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1329 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1331 for (i = 0; i < chip->ecc.total; i++)
1332 ecc_code[i] = chip->oob_poi[eccpos[i]];
1334 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1337 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1338 chip->read_buf(mtd, p, eccsize);
1339 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1341 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1343 mtd->ecc_stats.failed++;
1345 mtd->ecc_stats.corrected += stat;
1346 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1349 return max_bitflips;
1353 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1354 * @mtd: mtd info structure
1355 * @chip: nand chip info structure
1356 * @buf: buffer to store read data
1357 * @oob_required: caller requires OOB data read to chip->oob_poi
1358 * @page: page number to read
1360 * The hw generator calculates the error syndrome automatically. Therefore we
1361 * need a special oob layout and handling.
1363 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1364 uint8_t *buf, int oob_required, int page)
1366 int i, eccsize = chip->ecc.size;
1367 int eccbytes = chip->ecc.bytes;
1368 int eccsteps = chip->ecc.steps;
1370 uint8_t *oob = chip->oob_poi;
1371 unsigned int max_bitflips = 0;
1373 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1376 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1377 chip->read_buf(mtd, p, eccsize);
1379 if (chip->ecc.prepad) {
1380 chip->read_buf(mtd, oob, chip->ecc.prepad);
1381 oob += chip->ecc.prepad;
1384 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1385 chip->read_buf(mtd, oob, eccbytes);
1386 stat = chip->ecc.correct(mtd, p, oob, NULL);
1389 mtd->ecc_stats.failed++;
1391 mtd->ecc_stats.corrected += stat;
1392 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1397 if (chip->ecc.postpad) {
1398 chip->read_buf(mtd, oob, chip->ecc.postpad);
1399 oob += chip->ecc.postpad;
1403 /* Calculate remaining oob bytes */
1404 i = mtd->oobsize - (oob - chip->oob_poi);
1406 chip->read_buf(mtd, oob, i);
1408 return max_bitflips;
1412 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1413 * @chip: nand chip structure
1414 * @oob: oob destination address
1415 * @ops: oob ops structure
1416 * @len: size of oob to transfer
1418 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1419 struct mtd_oob_ops *ops, size_t len)
1421 switch (ops->mode) {
1423 case MTD_OPS_PLACE_OOB:
1425 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1428 case MTD_OPS_AUTO_OOB: {
1429 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1430 uint32_t boffs = 0, roffs = ops->ooboffs;
1433 for (; free->length && len; free++, len -= bytes) {
1434 /* Read request not from offset 0? */
1435 if (unlikely(roffs)) {
1436 if (roffs >= free->length) {
1437 roffs -= free->length;
1440 boffs = free->offset + roffs;
1441 bytes = min_t(size_t, len,
1442 (free->length - roffs));
1445 bytes = min_t(size_t, len, free->length);
1446 boffs = free->offset;
1448 memcpy(oob, chip->oob_poi + boffs, bytes);
1460 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1461 * @mtd: MTD device structure
1462 * @retry_mode: the retry mode to use
1464 * Some vendors supply a special command to shift the Vt threshold, to be used
1465 * when there are too many bitflips in a page (i.e., ECC error). After setting
1466 * a new threshold, the host should retry reading the page.
1468 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1470 struct nand_chip *chip = mtd->priv;
1472 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1474 if (retry_mode >= chip->read_retries)
1477 if (!chip->setup_read_retry)
1480 return chip->setup_read_retry(mtd, retry_mode);
1484 * nand_do_read_ops - [INTERN] Read data with ECC
1485 * @mtd: MTD device structure
1486 * @from: offset to read from
1487 * @ops: oob ops structure
1489 * Internal function. Called with chip held.
1491 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1492 struct mtd_oob_ops *ops)
1494 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1495 struct nand_chip *chip = mtd->priv;
1497 uint32_t readlen = ops->len;
1498 uint32_t oobreadlen = ops->ooblen;
1499 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1500 mtd->oobavail : mtd->oobsize;
1502 uint8_t *bufpoi, *oob, *buf;
1503 unsigned int max_bitflips = 0;
1505 bool ecc_fail = false;
1507 chipnr = (int)(from >> chip->chip_shift);
1508 chip->select_chip(mtd, chipnr);
1510 realpage = (int)(from >> chip->page_shift);
1511 page = realpage & chip->pagemask;
1513 col = (int)(from & (mtd->writesize - 1));
1517 oob_required = oob ? 1 : 0;
1520 unsigned int ecc_failures = mtd->ecc_stats.failed;
1522 bytes = min(mtd->writesize - col, readlen);
1523 aligned = (bytes == mtd->writesize);
1525 /* Is the current page in the buffer? */
1526 if (realpage != chip->pagebuf || oob) {
1527 bufpoi = aligned ? buf : chip->buffers->databuf;
1530 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1533 * Now read the page into the buffer. Absent an error,
1534 * the read methods return max bitflips per ecc step.
1536 if (unlikely(ops->mode == MTD_OPS_RAW))
1537 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1540 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1542 ret = chip->ecc.read_subpage(mtd, chip,
1543 col, bytes, bufpoi);
1545 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1546 oob_required, page);
1549 /* Invalidate page cache */
1554 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1556 /* Transfer not aligned data */
1558 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1559 !(mtd->ecc_stats.failed - ecc_failures) &&
1560 (ops->mode != MTD_OPS_RAW)) {
1561 chip->pagebuf = realpage;
1562 chip->pagebuf_bitflips = ret;
1564 /* Invalidate page cache */
1567 memcpy(buf, chip->buffers->databuf + col, bytes);
1570 if (unlikely(oob)) {
1571 int toread = min(oobreadlen, max_oobsize);
1574 oob = nand_transfer_oob(chip,
1576 oobreadlen -= toread;
1580 if (chip->options & NAND_NEED_READRDY) {
1581 /* Apply delay or wait for ready/busy pin */
1582 if (!chip->dev_ready)
1583 udelay(chip->chip_delay);
1585 nand_wait_ready(mtd);
1588 if (mtd->ecc_stats.failed - ecc_failures) {
1589 if (retry_mode + 1 < chip->read_retries) {
1591 ret = nand_setup_read_retry(mtd,
1596 /* Reset failures; retry */
1597 mtd->ecc_stats.failed = ecc_failures;
1600 /* No more retry modes; real failure */
1607 memcpy(buf, chip->buffers->databuf + col, bytes);
1609 max_bitflips = max_t(unsigned int, max_bitflips,
1610 chip->pagebuf_bitflips);
1615 /* Reset to retry mode 0 */
1617 ret = nand_setup_read_retry(mtd, 0);
1626 /* For subsequent reads align to page boundary */
1628 /* Increment page address */
1631 page = realpage & chip->pagemask;
1632 /* Check, if we cross a chip boundary */
1635 chip->select_chip(mtd, -1);
1636 chip->select_chip(mtd, chipnr);
1639 chip->select_chip(mtd, -1);
1641 ops->retlen = ops->len - (size_t) readlen;
1643 ops->oobretlen = ops->ooblen - oobreadlen;
1651 return max_bitflips;
1655 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1656 * @mtd: MTD device structure
1657 * @from: offset to read from
1658 * @len: number of bytes to read
1659 * @retlen: pointer to variable to store the number of read bytes
1660 * @buf: the databuffer to put data
1662 * Get hold of the chip and call nand_do_read.
1664 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1665 size_t *retlen, uint8_t *buf)
1667 struct mtd_oob_ops ops;
1670 nand_get_device(mtd, FL_READING);
1674 ops.mode = MTD_OPS_PLACE_OOB;
1675 ret = nand_do_read_ops(mtd, from, &ops);
1676 *retlen = ops.retlen;
1677 nand_release_device(mtd);
1682 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1683 * @mtd: mtd info structure
1684 * @chip: nand chip info structure
1685 * @page: page number to read
1687 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1690 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1691 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1696 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1698 * @mtd: mtd info structure
1699 * @chip: nand chip info structure
1700 * @page: page number to read
1702 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1705 uint8_t *buf = chip->oob_poi;
1706 int length = mtd->oobsize;
1707 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1708 int eccsize = chip->ecc.size;
1709 uint8_t *bufpoi = buf;
1710 int i, toread, sndrnd = 0, pos;
1712 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1713 for (i = 0; i < chip->ecc.steps; i++) {
1715 pos = eccsize + i * (eccsize + chunk);
1716 if (mtd->writesize > 512)
1717 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1719 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1722 toread = min_t(int, length, chunk);
1723 chip->read_buf(mtd, bufpoi, toread);
1728 chip->read_buf(mtd, bufpoi, length);
1734 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1735 * @mtd: mtd info structure
1736 * @chip: nand chip info structure
1737 * @page: page number to write
1739 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1743 const uint8_t *buf = chip->oob_poi;
1744 int length = mtd->oobsize;
1746 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1747 chip->write_buf(mtd, buf, length);
1748 /* Send command to program the OOB data */
1749 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1751 status = chip->waitfunc(mtd, chip);
1753 return status & NAND_STATUS_FAIL ? -EIO : 0;
1757 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1758 * with syndrome - only for large page flash
1759 * @mtd: mtd info structure
1760 * @chip: nand chip info structure
1761 * @page: page number to write
1763 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1764 struct nand_chip *chip, int page)
1766 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1767 int eccsize = chip->ecc.size, length = mtd->oobsize;
1768 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1769 const uint8_t *bufpoi = chip->oob_poi;
1772 * data-ecc-data-ecc ... ecc-oob
1774 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1776 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1777 pos = steps * (eccsize + chunk);
1782 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1783 for (i = 0; i < steps; i++) {
1785 if (mtd->writesize <= 512) {
1786 uint32_t fill = 0xFFFFFFFF;
1790 int num = min_t(int, len, 4);
1791 chip->write_buf(mtd, (uint8_t *)&fill,
1796 pos = eccsize + i * (eccsize + chunk);
1797 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1801 len = min_t(int, length, chunk);
1802 chip->write_buf(mtd, bufpoi, len);
1807 chip->write_buf(mtd, bufpoi, length);
1809 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1810 status = chip->waitfunc(mtd, chip);
1812 return status & NAND_STATUS_FAIL ? -EIO : 0;
1816 * nand_do_read_oob - [INTERN] NAND read out-of-band
1817 * @mtd: MTD device structure
1818 * @from: offset to read from
1819 * @ops: oob operations description structure
1821 * NAND read out-of-band data from the spare area.
1823 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1824 struct mtd_oob_ops *ops)
1826 int page, realpage, chipnr;
1827 struct nand_chip *chip = mtd->priv;
1828 struct mtd_ecc_stats stats;
1829 int readlen = ops->ooblen;
1831 uint8_t *buf = ops->oobbuf;
1834 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1835 __func__, (unsigned long long)from, readlen);
1837 stats = mtd->ecc_stats;
1839 if (ops->mode == MTD_OPS_AUTO_OOB)
1840 len = chip->ecc.layout->oobavail;
1844 if (unlikely(ops->ooboffs >= len)) {
1845 pr_debug("%s: attempt to start read outside oob\n",
1850 /* Do not allow reads past end of device */
1851 if (unlikely(from >= mtd->size ||
1852 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1853 (from >> chip->page_shift)) * len)) {
1854 pr_debug("%s: attempt to read beyond end of device\n",
1859 chipnr = (int)(from >> chip->chip_shift);
1860 chip->select_chip(mtd, chipnr);
1862 /* Shift to get page */
1863 realpage = (int)(from >> chip->page_shift);
1864 page = realpage & chip->pagemask;
1867 if (ops->mode == MTD_OPS_RAW)
1868 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1870 ret = chip->ecc.read_oob(mtd, chip, page);
1875 len = min(len, readlen);
1876 buf = nand_transfer_oob(chip, buf, ops, len);
1878 if (chip->options & NAND_NEED_READRDY) {
1879 /* Apply delay or wait for ready/busy pin */
1880 if (!chip->dev_ready)
1881 udelay(chip->chip_delay);
1883 nand_wait_ready(mtd);
1890 /* Increment page address */
1893 page = realpage & chip->pagemask;
1894 /* Check, if we cross a chip boundary */
1897 chip->select_chip(mtd, -1);
1898 chip->select_chip(mtd, chipnr);
1901 chip->select_chip(mtd, -1);
1903 ops->oobretlen = ops->ooblen - readlen;
1908 if (mtd->ecc_stats.failed - stats.failed)
1911 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1915 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1916 * @mtd: MTD device structure
1917 * @from: offset to read from
1918 * @ops: oob operation description structure
1920 * NAND read data and/or out-of-band data.
1922 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1923 struct mtd_oob_ops *ops)
1925 int ret = -ENOTSUPP;
1929 /* Do not allow reads past end of device */
1930 if (ops->datbuf && (from + ops->len) > mtd->size) {
1931 pr_debug("%s: attempt to read beyond end of device\n",
1936 nand_get_device(mtd, FL_READING);
1938 switch (ops->mode) {
1939 case MTD_OPS_PLACE_OOB:
1940 case MTD_OPS_AUTO_OOB:
1949 ret = nand_do_read_oob(mtd, from, ops);
1951 ret = nand_do_read_ops(mtd, from, ops);
1954 nand_release_device(mtd);
1960 * nand_write_page_raw - [INTERN] raw page write function
1961 * @mtd: mtd info structure
1962 * @chip: nand chip info structure
1964 * @oob_required: must write chip->oob_poi to OOB
1966 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1968 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1969 const uint8_t *buf, int oob_required)
1971 chip->write_buf(mtd, buf, mtd->writesize);
1973 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1979 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1980 * @mtd: mtd info structure
1981 * @chip: nand chip info structure
1983 * @oob_required: must write chip->oob_poi to OOB
1985 * We need a special oob layout and handling even when ECC isn't checked.
1987 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1988 struct nand_chip *chip,
1989 const uint8_t *buf, int oob_required)
1991 int eccsize = chip->ecc.size;
1992 int eccbytes = chip->ecc.bytes;
1993 uint8_t *oob = chip->oob_poi;
1996 for (steps = chip->ecc.steps; steps > 0; steps--) {
1997 chip->write_buf(mtd, buf, eccsize);
2000 if (chip->ecc.prepad) {
2001 chip->write_buf(mtd, oob, chip->ecc.prepad);
2002 oob += chip->ecc.prepad;
2005 chip->write_buf(mtd, oob, eccbytes);
2008 if (chip->ecc.postpad) {
2009 chip->write_buf(mtd, oob, chip->ecc.postpad);
2010 oob += chip->ecc.postpad;
2014 size = mtd->oobsize - (oob - chip->oob_poi);
2016 chip->write_buf(mtd, oob, size);
2021 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2022 * @mtd: mtd info structure
2023 * @chip: nand chip info structure
2025 * @oob_required: must write chip->oob_poi to OOB
2027 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2028 const uint8_t *buf, int oob_required)
2030 int i, eccsize = chip->ecc.size;
2031 int eccbytes = chip->ecc.bytes;
2032 int eccsteps = chip->ecc.steps;
2033 uint8_t *ecc_calc = chip->buffers->ecccalc;
2034 const uint8_t *p = buf;
2035 uint32_t *eccpos = chip->ecc.layout->eccpos;
2037 /* Software ECC calculation */
2038 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2039 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2041 for (i = 0; i < chip->ecc.total; i++)
2042 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2044 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2048 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2049 * @mtd: mtd info structure
2050 * @chip: nand chip info structure
2052 * @oob_required: must write chip->oob_poi to OOB
2054 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2055 const uint8_t *buf, int oob_required)
2057 int i, eccsize = chip->ecc.size;
2058 int eccbytes = chip->ecc.bytes;
2059 int eccsteps = chip->ecc.steps;
2060 uint8_t *ecc_calc = chip->buffers->ecccalc;
2061 const uint8_t *p = buf;
2062 uint32_t *eccpos = chip->ecc.layout->eccpos;
2064 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2065 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2066 chip->write_buf(mtd, p, eccsize);
2067 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2070 for (i = 0; i < chip->ecc.total; i++)
2071 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2073 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2080 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2081 * @mtd: mtd info structure
2082 * @chip: nand chip info structure
2083 * @offset: column address of subpage within the page
2084 * @data_len: data length
2086 * @oob_required: must write chip->oob_poi to OOB
2088 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2089 struct nand_chip *chip, uint32_t offset,
2090 uint32_t data_len, const uint8_t *buf,
2093 uint8_t *oob_buf = chip->oob_poi;
2094 uint8_t *ecc_calc = chip->buffers->ecccalc;
2095 int ecc_size = chip->ecc.size;
2096 int ecc_bytes = chip->ecc.bytes;
2097 int ecc_steps = chip->ecc.steps;
2098 uint32_t *eccpos = chip->ecc.layout->eccpos;
2099 uint32_t start_step = offset / ecc_size;
2100 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2101 int oob_bytes = mtd->oobsize / ecc_steps;
2104 for (step = 0; step < ecc_steps; step++) {
2105 /* configure controller for WRITE access */
2106 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2108 /* write data (untouched subpages already masked by 0xFF) */
2109 chip->write_buf(mtd, buf, ecc_size);
2111 /* mask ECC of un-touched subpages by padding 0xFF */
2112 if ((step < start_step) || (step > end_step))
2113 memset(ecc_calc, 0xff, ecc_bytes);
2115 chip->ecc.calculate(mtd, buf, ecc_calc);
2117 /* mask OOB of un-touched subpages by padding 0xFF */
2118 /* if oob_required, preserve OOB metadata of written subpage */
2119 if (!oob_required || (step < start_step) || (step > end_step))
2120 memset(oob_buf, 0xff, oob_bytes);
2123 ecc_calc += ecc_bytes;
2124 oob_buf += oob_bytes;
2127 /* copy calculated ECC for whole page to chip->buffer->oob */
2128 /* this include masked-value(0xFF) for unwritten subpages */
2129 ecc_calc = chip->buffers->ecccalc;
2130 for (i = 0; i < chip->ecc.total; i++)
2131 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2133 /* write OOB buffer to NAND device */
2134 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2141 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2142 * @mtd: mtd info structure
2143 * @chip: nand chip info structure
2145 * @oob_required: must write chip->oob_poi to OOB
2147 * The hw generator calculates the error syndrome automatically. Therefore we
2148 * need a special oob layout and handling.
2150 static int nand_write_page_syndrome(struct mtd_info *mtd,
2151 struct nand_chip *chip,
2152 const uint8_t *buf, int oob_required)
2154 int i, eccsize = chip->ecc.size;
2155 int eccbytes = chip->ecc.bytes;
2156 int eccsteps = chip->ecc.steps;
2157 const uint8_t *p = buf;
2158 uint8_t *oob = chip->oob_poi;
2160 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2162 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2163 chip->write_buf(mtd, p, eccsize);
2165 if (chip->ecc.prepad) {
2166 chip->write_buf(mtd, oob, chip->ecc.prepad);
2167 oob += chip->ecc.prepad;
2170 chip->ecc.calculate(mtd, p, oob);
2171 chip->write_buf(mtd, oob, eccbytes);
2174 if (chip->ecc.postpad) {
2175 chip->write_buf(mtd, oob, chip->ecc.postpad);
2176 oob += chip->ecc.postpad;
2180 /* Calculate remaining oob bytes */
2181 i = mtd->oobsize - (oob - chip->oob_poi);
2183 chip->write_buf(mtd, oob, i);
2189 * nand_write_page - [REPLACEABLE] write one page
2190 * @mtd: MTD device structure
2191 * @chip: NAND chip descriptor
2192 * @offset: address offset within the page
2193 * @data_len: length of actual data to be written
2194 * @buf: the data to write
2195 * @oob_required: must write chip->oob_poi to OOB
2196 * @page: page number to write
2197 * @cached: cached programming
2198 * @raw: use _raw version of write_page
2200 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2201 uint32_t offset, int data_len, const uint8_t *buf,
2202 int oob_required, int page, int cached, int raw)
2204 int status, subpage;
2206 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2207 chip->ecc.write_subpage)
2208 subpage = offset || (data_len < mtd->writesize);
2212 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2215 status = chip->ecc.write_page_raw(mtd, chip, buf,
2218 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2221 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2227 * Cached progamming disabled for now. Not sure if it's worth the
2228 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2232 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2234 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2235 status = chip->waitfunc(mtd, chip);
2237 * See if operation failed and additional status checks are
2240 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2241 status = chip->errstat(mtd, chip, FL_WRITING, status,
2244 if (status & NAND_STATUS_FAIL)
2247 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2248 status = chip->waitfunc(mtd, chip);
2255 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2256 * @mtd: MTD device structure
2257 * @oob: oob data buffer
2258 * @len: oob data write length
2259 * @ops: oob ops structure
2261 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2262 struct mtd_oob_ops *ops)
2264 struct nand_chip *chip = mtd->priv;
2267 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2268 * data from a previous OOB read.
2270 memset(chip->oob_poi, 0xff, mtd->oobsize);
2272 switch (ops->mode) {
2274 case MTD_OPS_PLACE_OOB:
2276 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2279 case MTD_OPS_AUTO_OOB: {
2280 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2281 uint32_t boffs = 0, woffs = ops->ooboffs;
2284 for (; free->length && len; free++, len -= bytes) {
2285 /* Write request not from offset 0? */
2286 if (unlikely(woffs)) {
2287 if (woffs >= free->length) {
2288 woffs -= free->length;
2291 boffs = free->offset + woffs;
2292 bytes = min_t(size_t, len,
2293 (free->length - woffs));
2296 bytes = min_t(size_t, len, free->length);
2297 boffs = free->offset;
2299 memcpy(chip->oob_poi + boffs, oob, bytes);
2310 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2313 * nand_do_write_ops - [INTERN] NAND write with ECC
2314 * @mtd: MTD device structure
2315 * @to: offset to write to
2316 * @ops: oob operations description structure
2318 * NAND write with ECC.
2320 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2321 struct mtd_oob_ops *ops)
2323 int chipnr, realpage, page, blockmask, column;
2324 struct nand_chip *chip = mtd->priv;
2325 uint32_t writelen = ops->len;
2327 uint32_t oobwritelen = ops->ooblen;
2328 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2329 mtd->oobavail : mtd->oobsize;
2331 uint8_t *oob = ops->oobbuf;
2332 uint8_t *buf = ops->datbuf;
2334 int oob_required = oob ? 1 : 0;
2340 /* Reject writes, which are not page aligned */
2341 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2342 pr_notice("%s: attempt to write non page aligned data\n",
2347 column = to & (mtd->writesize - 1);
2349 chipnr = (int)(to >> chip->chip_shift);
2350 chip->select_chip(mtd, chipnr);
2352 /* Check, if it is write protected */
2353 if (nand_check_wp(mtd)) {
2358 realpage = (int)(to >> chip->page_shift);
2359 page = realpage & chip->pagemask;
2360 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2362 /* Invalidate the page cache, when we write to the cached page */
2363 if (to <= (chip->pagebuf << chip->page_shift) &&
2364 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2367 /* Don't allow multipage oob writes with offset */
2368 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2374 int bytes = mtd->writesize;
2375 int cached = writelen > bytes && page != blockmask;
2376 uint8_t *wbuf = buf;
2378 /* Partial page write? */
2379 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2381 bytes = min_t(int, bytes - column, (int) writelen);
2383 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2384 memcpy(&chip->buffers->databuf[column], buf, bytes);
2385 wbuf = chip->buffers->databuf;
2388 if (unlikely(oob)) {
2389 size_t len = min(oobwritelen, oobmaxlen);
2390 oob = nand_fill_oob(mtd, oob, len, ops);
2393 /* We still need to erase leftover OOB data */
2394 memset(chip->oob_poi, 0xff, mtd->oobsize);
2396 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2397 oob_required, page, cached,
2398 (ops->mode == MTD_OPS_RAW));
2410 page = realpage & chip->pagemask;
2411 /* Check, if we cross a chip boundary */
2414 chip->select_chip(mtd, -1);
2415 chip->select_chip(mtd, chipnr);
2419 ops->retlen = ops->len - writelen;
2421 ops->oobretlen = ops->ooblen;
2424 chip->select_chip(mtd, -1);
2429 * panic_nand_write - [MTD Interface] NAND write with ECC
2430 * @mtd: MTD device structure
2431 * @to: offset to write to
2432 * @len: number of bytes to write
2433 * @retlen: pointer to variable to store the number of written bytes
2434 * @buf: the data to write
2436 * NAND write with ECC. Used when performing writes in interrupt context, this
2437 * may for example be called by mtdoops when writing an oops while in panic.
2439 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2440 size_t *retlen, const uint8_t *buf)
2442 struct nand_chip *chip = mtd->priv;
2443 struct mtd_oob_ops ops;
2446 /* Wait for the device to get ready */
2447 panic_nand_wait(mtd, chip, 400);
2449 /* Grab the device */
2450 panic_nand_get_device(chip, mtd, FL_WRITING);
2453 ops.datbuf = (uint8_t *)buf;
2455 ops.mode = MTD_OPS_PLACE_OOB;
2457 ret = nand_do_write_ops(mtd, to, &ops);
2459 *retlen = ops.retlen;
2464 * nand_write - [MTD Interface] NAND write with ECC
2465 * @mtd: MTD device structure
2466 * @to: offset to write to
2467 * @len: number of bytes to write
2468 * @retlen: pointer to variable to store the number of written bytes
2469 * @buf: the data to write
2471 * NAND write with ECC.
2473 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2474 size_t *retlen, const uint8_t *buf)
2476 struct mtd_oob_ops ops;
2479 nand_get_device(mtd, FL_WRITING);
2481 ops.datbuf = (uint8_t *)buf;
2483 ops.mode = MTD_OPS_PLACE_OOB;
2484 ret = nand_do_write_ops(mtd, to, &ops);
2485 *retlen = ops.retlen;
2486 nand_release_device(mtd);
2491 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2492 * @mtd: MTD device structure
2493 * @to: offset to write to
2494 * @ops: oob operation description structure
2496 * NAND write out-of-band.
2498 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2499 struct mtd_oob_ops *ops)
2501 int chipnr, page, status, len;
2502 struct nand_chip *chip = mtd->priv;
2504 pr_debug("%s: to = 0x%08x, len = %i\n",
2505 __func__, (unsigned int)to, (int)ops->ooblen);
2507 if (ops->mode == MTD_OPS_AUTO_OOB)
2508 len = chip->ecc.layout->oobavail;
2512 /* Do not allow write past end of page */
2513 if ((ops->ooboffs + ops->ooblen) > len) {
2514 pr_debug("%s: attempt to write past end of page\n",
2519 if (unlikely(ops->ooboffs >= len)) {
2520 pr_debug("%s: attempt to start write outside oob\n",
2525 /* Do not allow write past end of device */
2526 if (unlikely(to >= mtd->size ||
2527 ops->ooboffs + ops->ooblen >
2528 ((mtd->size >> chip->page_shift) -
2529 (to >> chip->page_shift)) * len)) {
2530 pr_debug("%s: attempt to write beyond end of device\n",
2535 chipnr = (int)(to >> chip->chip_shift);
2536 chip->select_chip(mtd, chipnr);
2538 /* Shift to get page */
2539 page = (int)(to >> chip->page_shift);
2542 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2543 * of my DiskOnChip 2000 test units) will clear the whole data page too
2544 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2545 * it in the doc2000 driver in August 1999. dwmw2.
2547 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2549 /* Check, if it is write protected */
2550 if (nand_check_wp(mtd)) {
2551 chip->select_chip(mtd, -1);
2555 /* Invalidate the page cache, if we write to the cached page */
2556 if (page == chip->pagebuf)
2559 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2561 if (ops->mode == MTD_OPS_RAW)
2562 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2564 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2566 chip->select_chip(mtd, -1);
2571 ops->oobretlen = ops->ooblen;
2577 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2578 * @mtd: MTD device structure
2579 * @to: offset to write to
2580 * @ops: oob operation description structure
2582 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2583 struct mtd_oob_ops *ops)
2585 int ret = -ENOTSUPP;
2589 /* Do not allow writes past end of device */
2590 if (ops->datbuf && (to + ops->len) > mtd->size) {
2591 pr_debug("%s: attempt to write beyond end of device\n",
2596 nand_get_device(mtd, FL_WRITING);
2598 switch (ops->mode) {
2599 case MTD_OPS_PLACE_OOB:
2600 case MTD_OPS_AUTO_OOB:
2609 ret = nand_do_write_oob(mtd, to, ops);
2611 ret = nand_do_write_ops(mtd, to, ops);
2614 nand_release_device(mtd);
2619 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2620 * @mtd: MTD device structure
2621 * @page: the page address of the block which will be erased
2623 * Standard erase command for NAND chips.
2625 static void single_erase_cmd(struct mtd_info *mtd, int page)
2627 struct nand_chip *chip = mtd->priv;
2628 /* Send commands to erase a block */
2629 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2630 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2634 * nand_erase - [MTD Interface] erase block(s)
2635 * @mtd: MTD device structure
2636 * @instr: erase instruction
2638 * Erase one ore more blocks.
2640 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2642 return nand_erase_nand(mtd, instr, 0);
2646 * nand_erase_nand - [INTERN] erase block(s)
2647 * @mtd: MTD device structure
2648 * @instr: erase instruction
2649 * @allowbbt: allow erasing the bbt area
2651 * Erase one ore more blocks.
2653 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2656 int page, status, pages_per_block, ret, chipnr;
2657 struct nand_chip *chip = mtd->priv;
2660 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2661 __func__, (unsigned long long)instr->addr,
2662 (unsigned long long)instr->len);
2664 if (check_offs_len(mtd, instr->addr, instr->len))
2667 /* Grab the lock and see if the device is available */
2668 nand_get_device(mtd, FL_ERASING);
2670 /* Shift to get first page */
2671 page = (int)(instr->addr >> chip->page_shift);
2672 chipnr = (int)(instr->addr >> chip->chip_shift);
2674 /* Calculate pages in each block */
2675 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2677 /* Select the NAND device */
2678 chip->select_chip(mtd, chipnr);
2680 /* Check, if it is write protected */
2681 if (nand_check_wp(mtd)) {
2682 pr_debug("%s: device is write protected!\n",
2684 instr->state = MTD_ERASE_FAILED;
2688 /* Loop through the pages */
2691 instr->state = MTD_ERASING;
2694 /* Check if we have a bad block, we do not erase bad blocks! */
2695 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2696 chip->page_shift, 0, allowbbt)) {
2697 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2699 instr->state = MTD_ERASE_FAILED;
2704 * Invalidate the page cache, if we erase the block which
2705 * contains the current cached page.
2707 if (page <= chip->pagebuf && chip->pagebuf <
2708 (page + pages_per_block))
2711 chip->erase_cmd(mtd, page & chip->pagemask);
2713 status = chip->waitfunc(mtd, chip);
2716 * See if operation failed and additional status checks are
2719 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2720 status = chip->errstat(mtd, chip, FL_ERASING,
2723 /* See if block erase succeeded */
2724 if (status & NAND_STATUS_FAIL) {
2725 pr_debug("%s: failed erase, page 0x%08x\n",
2727 instr->state = MTD_ERASE_FAILED;
2729 ((loff_t)page << chip->page_shift);
2733 /* Increment page address and decrement length */
2734 len -= (1ULL << chip->phys_erase_shift);
2735 page += pages_per_block;
2737 /* Check, if we cross a chip boundary */
2738 if (len && !(page & chip->pagemask)) {
2740 chip->select_chip(mtd, -1);
2741 chip->select_chip(mtd, chipnr);
2744 instr->state = MTD_ERASE_DONE;
2748 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2750 /* Deselect and wake up anyone waiting on the device */
2751 chip->select_chip(mtd, -1);
2752 nand_release_device(mtd);
2754 /* Do call back function */
2756 mtd_erase_callback(instr);
2758 /* Return more or less happy */
2763 * nand_sync - [MTD Interface] sync
2764 * @mtd: MTD device structure
2766 * Sync is actually a wait for chip ready function.
2768 static void nand_sync(struct mtd_info *mtd)
2770 pr_debug("%s: called\n", __func__);
2772 /* Grab the lock and see if the device is available */
2773 nand_get_device(mtd, FL_SYNCING);
2774 /* Release it and go back */
2775 nand_release_device(mtd);
2779 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2780 * @mtd: MTD device structure
2781 * @offs: offset relative to mtd start
2783 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2785 return nand_block_checkbad(mtd, offs, 1, 0);
2789 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2790 * @mtd: MTD device structure
2791 * @ofs: offset relative to mtd start
2793 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2797 ret = nand_block_isbad(mtd, ofs);
2799 /* If it was bad already, return success and do nothing */
2805 return nand_block_markbad_lowlevel(mtd, ofs);
2809 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2810 * @mtd: MTD device structure
2811 * @chip: nand chip info structure
2812 * @addr: feature address.
2813 * @subfeature_param: the subfeature parameters, a four bytes array.
2815 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2816 int addr, uint8_t *subfeature_param)
2821 if (!chip->onfi_version ||
2822 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2823 & ONFI_OPT_CMD_SET_GET_FEATURES))
2826 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2827 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2828 chip->write_byte(mtd, subfeature_param[i]);
2830 status = chip->waitfunc(mtd, chip);
2831 if (status & NAND_STATUS_FAIL)
2837 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2838 * @mtd: MTD device structure
2839 * @chip: nand chip info structure
2840 * @addr: feature address.
2841 * @subfeature_param: the subfeature parameters, a four bytes array.
2843 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2844 int addr, uint8_t *subfeature_param)
2848 if (!chip->onfi_version ||
2849 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2850 & ONFI_OPT_CMD_SET_GET_FEATURES))
2853 /* clear the sub feature parameters */
2854 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2856 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2857 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2858 *subfeature_param++ = chip->read_byte(mtd);
2863 * nand_suspend - [MTD Interface] Suspend the NAND flash
2864 * @mtd: MTD device structure
2866 static int nand_suspend(struct mtd_info *mtd)
2868 return nand_get_device(mtd, FL_PM_SUSPENDED);
2872 * nand_resume - [MTD Interface] Resume the NAND flash
2873 * @mtd: MTD device structure
2875 static void nand_resume(struct mtd_info *mtd)
2877 struct nand_chip *chip = mtd->priv;
2879 if (chip->state == FL_PM_SUSPENDED)
2880 nand_release_device(mtd);
2882 pr_err("%s called for a chip which is not in suspended state\n",
2886 /* Set default functions */
2887 static void nand_set_defaults(struct nand_chip *chip, int busw)
2889 /* check for proper chip_delay setup, set 20us if not */
2890 if (!chip->chip_delay)
2891 chip->chip_delay = 20;
2893 /* check, if a user supplied command function given */
2894 if (chip->cmdfunc == NULL)
2895 chip->cmdfunc = nand_command;
2897 /* check, if a user supplied wait function given */
2898 if (chip->waitfunc == NULL)
2899 chip->waitfunc = nand_wait;
2901 if (!chip->select_chip)
2902 chip->select_chip = nand_select_chip;
2904 /* set for ONFI nand */
2905 if (!chip->onfi_set_features)
2906 chip->onfi_set_features = nand_onfi_set_features;
2907 if (!chip->onfi_get_features)
2908 chip->onfi_get_features = nand_onfi_get_features;
2910 /* If called twice, pointers that depend on busw may need to be reset */
2911 if (!chip->read_byte || chip->read_byte == nand_read_byte)
2912 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2913 if (!chip->read_word)
2914 chip->read_word = nand_read_word;
2915 if (!chip->block_bad)
2916 chip->block_bad = nand_block_bad;
2917 if (!chip->block_markbad)
2918 chip->block_markbad = nand_default_block_markbad;
2919 if (!chip->write_buf || chip->write_buf == nand_write_buf)
2920 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2921 if (!chip->write_byte || chip->write_byte == nand_write_byte)
2922 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
2923 if (!chip->read_buf || chip->read_buf == nand_read_buf)
2924 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2925 if (!chip->scan_bbt)
2926 chip->scan_bbt = nand_default_bbt;
2928 if (!chip->controller) {
2929 chip->controller = &chip->hwcontrol;
2930 spin_lock_init(&chip->controller->lock);
2931 init_waitqueue_head(&chip->controller->wq);
2936 /* Sanitize ONFI strings so we can safely print them */
2937 static void sanitize_string(uint8_t *s, size_t len)
2941 /* Null terminate */
2944 /* Remove non printable chars */
2945 for (i = 0; i < len - 1; i++) {
2946 if (s[i] < ' ' || s[i] > 127)
2950 /* Remove trailing spaces */
2954 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2959 for (i = 0; i < 8; i++)
2960 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2966 /* Parse the Extended Parameter Page. */
2967 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2968 struct nand_chip *chip, struct nand_onfi_params *p)
2970 struct onfi_ext_param_page *ep;
2971 struct onfi_ext_section *s;
2972 struct onfi_ext_ecc_info *ecc;
2978 len = le16_to_cpu(p->ext_param_page_length) * 16;
2979 ep = kmalloc(len, GFP_KERNEL);
2983 /* Send our own NAND_CMD_PARAM. */
2984 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2986 /* Use the Change Read Column command to skip the ONFI param pages. */
2987 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2988 sizeof(*p) * p->num_of_param_pages , -1);
2990 /* Read out the Extended Parameter Page. */
2991 chip->read_buf(mtd, (uint8_t *)ep, len);
2992 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2993 != le16_to_cpu(ep->crc))) {
2994 pr_debug("fail in the CRC.\n");
2999 * Check the signature.
3000 * Do not strictly follow the ONFI spec, maybe changed in future.
3002 if (strncmp(ep->sig, "EPPS", 4)) {
3003 pr_debug("The signature is invalid.\n");
3007 /* find the ECC section. */
3008 cursor = (uint8_t *)(ep + 1);
3009 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3010 s = ep->sections + i;
3011 if (s->type == ONFI_SECTION_TYPE_2)
3013 cursor += s->length * 16;
3015 if (i == ONFI_EXT_SECTION_MAX) {
3016 pr_debug("We can not find the ECC section.\n");
3020 /* get the info we want. */
3021 ecc = (struct onfi_ext_ecc_info *)cursor;
3023 if (!ecc->codeword_size) {
3024 pr_debug("Invalid codeword size\n");
3028 chip->ecc_strength_ds = ecc->ecc_bits;
3029 chip->ecc_step_ds = 1 << ecc->codeword_size;
3037 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3039 struct nand_chip *chip = mtd->priv;
3040 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3042 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3047 * Configure chip properties from Micron vendor-specific ONFI table
3049 static void nand_onfi_detect_micron(struct nand_chip *chip,
3050 struct nand_onfi_params *p)
3052 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3054 if (le16_to_cpu(p->vendor_revision) < 1)
3057 chip->read_retries = micron->read_retry_options;
3058 chip->setup_read_retry = nand_setup_read_retry_micron;
3062 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3064 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3067 struct nand_onfi_params *p = &chip->onfi_params;
3071 /* Try ONFI for unknown chip or LP */
3072 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3073 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3074 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3077 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3078 for (i = 0; i < 3; i++) {
3079 for (j = 0; j < sizeof(*p); j++)
3080 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3081 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3082 le16_to_cpu(p->crc)) {
3088 pr_err("Could not find valid ONFI parameter page; aborting\n");
3093 val = le16_to_cpu(p->revision);
3095 chip->onfi_version = 23;
3096 else if (val & (1 << 4))
3097 chip->onfi_version = 22;
3098 else if (val & (1 << 3))
3099 chip->onfi_version = 21;
3100 else if (val & (1 << 2))
3101 chip->onfi_version = 20;
3102 else if (val & (1 << 1))
3103 chip->onfi_version = 10;
3105 if (!chip->onfi_version) {
3106 pr_info("unsupported ONFI version: %d\n", val);
3110 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3111 sanitize_string(p->model, sizeof(p->model));
3113 mtd->name = p->model;
3115 mtd->writesize = le32_to_cpu(p->byte_per_page);
3118 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3119 * (don't ask me who thought of this...). MTD assumes that these
3120 * dimensions will be power-of-2, so just truncate the remaining area.
3122 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3123 mtd->erasesize *= mtd->writesize;
3125 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3127 /* See erasesize comment */
3128 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3129 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3130 chip->bits_per_cell = p->bits_per_cell;
3132 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3133 *busw = NAND_BUSWIDTH_16;
3137 if (p->ecc_bits != 0xff) {
3138 chip->ecc_strength_ds = p->ecc_bits;
3139 chip->ecc_step_ds = 512;
3140 } else if (chip->onfi_version >= 21 &&
3141 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3144 * The nand_flash_detect_ext_param_page() uses the
3145 * Change Read Column command which maybe not supported
3146 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3147 * now. We do not replace user supplied command function.
3149 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3150 chip->cmdfunc = nand_command_lp;
3152 /* The Extended Parameter Page is supported since ONFI 2.1. */
3153 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3154 pr_warn("Failed to detect ONFI extended param page\n");
3156 pr_warn("Could not retrieve ONFI ECC requirements\n");
3159 if (p->jedec_id == NAND_MFR_MICRON)
3160 nand_onfi_detect_micron(chip, p);
3166 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3168 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3171 struct nand_jedec_params *p = &chip->jedec_params;
3172 struct jedec_ecc_info *ecc;
3176 /* Try JEDEC for unknown chip or LP */
3177 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3178 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3179 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3180 chip->read_byte(mtd) != 'C')
3183 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3184 for (i = 0; i < 3; i++) {
3185 for (j = 0; j < sizeof(*p); j++)
3186 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3188 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3189 le16_to_cpu(p->crc))
3194 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3199 val = le16_to_cpu(p->revision);
3201 chip->jedec_version = 10;
3202 else if (val & (1 << 1))
3203 chip->jedec_version = 1; /* vendor specific version */
3205 if (!chip->jedec_version) {
3206 pr_info("unsupported JEDEC version: %d\n", val);
3210 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3211 sanitize_string(p->model, sizeof(p->model));
3213 mtd->name = p->model;
3215 mtd->writesize = le32_to_cpu(p->byte_per_page);
3217 /* Please reference to the comment for nand_flash_detect_onfi. */
3218 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3219 mtd->erasesize *= mtd->writesize;
3221 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3223 /* Please reference to the comment for nand_flash_detect_onfi. */
3224 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3225 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3226 chip->bits_per_cell = p->bits_per_cell;
3228 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3229 *busw = NAND_BUSWIDTH_16;
3234 ecc = &p->ecc_info[0];
3236 if (ecc->codeword_size >= 9) {
3237 chip->ecc_strength_ds = ecc->ecc_bits;
3238 chip->ecc_step_ds = 1 << ecc->codeword_size;
3240 pr_warn("Invalid codeword size\n");
3247 * nand_id_has_period - Check if an ID string has a given wraparound period
3248 * @id_data: the ID string
3249 * @arrlen: the length of the @id_data array
3250 * @period: the period of repitition
3252 * Check if an ID string is repeated within a given sequence of bytes at
3253 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3254 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3255 * if the repetition has a period of @period; otherwise, returns zero.
3257 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3260 for (i = 0; i < period; i++)
3261 for (j = i + period; j < arrlen; j += period)
3262 if (id_data[i] != id_data[j])
3268 * nand_id_len - Get the length of an ID string returned by CMD_READID
3269 * @id_data: the ID string
3270 * @arrlen: the length of the @id_data array
3272 * Returns the length of the ID string, according to known wraparound/trailing
3273 * zero patterns. If no pattern exists, returns the length of the array.
3275 static int nand_id_len(u8 *id_data, int arrlen)
3277 int last_nonzero, period;
3279 /* Find last non-zero byte */
3280 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3281 if (id_data[last_nonzero])
3285 if (last_nonzero < 0)
3288 /* Calculate wraparound period */
3289 for (period = 1; period < arrlen; period++)
3290 if (nand_id_has_period(id_data, arrlen, period))
3293 /* There's a repeated pattern */
3294 if (period < arrlen)
3297 /* There are trailing zeros */
3298 if (last_nonzero < arrlen - 1)
3299 return last_nonzero + 1;
3301 /* No pattern detected */
3305 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3306 static int nand_get_bits_per_cell(u8 cellinfo)
3310 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3311 bits >>= NAND_CI_CELLTYPE_SHIFT;
3316 * Many new NAND share similar device ID codes, which represent the size of the
3317 * chip. The rest of the parameters must be decoded according to generic or
3318 * manufacturer-specific "extended ID" decoding patterns.
3320 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3321 u8 id_data[8], int *busw)
3324 /* The 3rd id byte holds MLC / multichip data */
3325 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3326 /* The 4th id byte is the important one */
3329 id_len = nand_id_len(id_data, 8);
3332 * Field definitions are in the following datasheets:
3333 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3334 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3335 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3337 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3338 * ID to decide what to do.
3340 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3341 !nand_is_slc(chip) && id_data[5] != 0x00) {
3343 mtd->writesize = 2048 << (extid & 0x03);
3346 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3366 default: /* Other cases are "reserved" (unknown) */
3367 mtd->oobsize = 1024;
3371 /* Calc blocksize */
3372 mtd->erasesize = (128 * 1024) <<
3373 (((extid >> 1) & 0x04) | (extid & 0x03));
3375 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3376 !nand_is_slc(chip)) {
3380 mtd->writesize = 2048 << (extid & 0x03);
3383 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3407 /* Calc blocksize */
3408 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3410 mtd->erasesize = (128 * 1024) << tmp;
3411 else if (tmp == 0x03)
3412 mtd->erasesize = 768 * 1024;
3414 mtd->erasesize = (64 * 1024) << tmp;
3418 mtd->writesize = 1024 << (extid & 0x03);
3421 mtd->oobsize = (8 << (extid & 0x01)) *
3422 (mtd->writesize >> 9);
3424 /* Calc blocksize. Blocksize is multiples of 64KiB */
3425 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3427 /* Get buswidth information */
3428 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3431 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3432 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3434 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3436 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3438 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3439 nand_is_slc(chip) &&
3440 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3441 !(id_data[4] & 0x80) /* !BENAND */) {
3442 mtd->oobsize = 32 * mtd->writesize >> 9;
3449 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3450 * decodes a matching ID table entry and assigns the MTD size parameters for
3453 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3454 struct nand_flash_dev *type, u8 id_data[8],
3457 int maf_id = id_data[0];
3459 mtd->erasesize = type->erasesize;
3460 mtd->writesize = type->pagesize;
3461 mtd->oobsize = mtd->writesize / 32;
3462 *busw = type->options & NAND_BUSWIDTH_16;
3464 /* All legacy ID NAND are small-page, SLC */
3465 chip->bits_per_cell = 1;
3468 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3469 * some Spansion chips have erasesize that conflicts with size
3470 * listed in nand_ids table.
3471 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3473 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3474 && id_data[6] == 0x00 && id_data[7] == 0x00
3475 && mtd->writesize == 512) {
3476 mtd->erasesize = 128 * 1024;
3477 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3482 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3483 * heuristic patterns using various detected parameters (e.g., manufacturer,
3484 * page size, cell-type information).
3486 static void nand_decode_bbm_options(struct mtd_info *mtd,
3487 struct nand_chip *chip, u8 id_data[8])
3489 int maf_id = id_data[0];
3491 /* Set the bad block position */
3492 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3493 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3495 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3498 * Bad block marker is stored in the last page of each block on Samsung
3499 * and Hynix MLC devices; stored in first two pages of each block on
3500 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3501 * AMD/Spansion, and Macronix. All others scan only the first page.
3503 if (!nand_is_slc(chip) &&
3504 (maf_id == NAND_MFR_SAMSUNG ||
3505 maf_id == NAND_MFR_HYNIX))
3506 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3507 else if ((nand_is_slc(chip) &&
3508 (maf_id == NAND_MFR_SAMSUNG ||
3509 maf_id == NAND_MFR_HYNIX ||
3510 maf_id == NAND_MFR_TOSHIBA ||
3511 maf_id == NAND_MFR_AMD ||
3512 maf_id == NAND_MFR_MACRONIX)) ||
3513 (mtd->writesize == 2048 &&
3514 maf_id == NAND_MFR_MICRON))
3515 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3518 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3520 return type->id_len;
3523 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3524 struct nand_flash_dev *type, u8 *id_data, int *busw)
3526 if (!strncmp(type->id, id_data, type->id_len)) {
3527 mtd->writesize = type->pagesize;
3528 mtd->erasesize = type->erasesize;
3529 mtd->oobsize = type->oobsize;
3531 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3532 chip->chipsize = (uint64_t)type->chipsize << 20;
3533 chip->options |= type->options;
3534 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3535 chip->ecc_step_ds = NAND_ECC_STEP(type);
3537 *busw = type->options & NAND_BUSWIDTH_16;
3540 mtd->name = type->name;
3548 * Get the flash and manufacturer id and lookup if the type is supported.
3550 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3551 struct nand_chip *chip,
3553 int *maf_id, int *dev_id,
3554 struct nand_flash_dev *type)
3559 /* Select the device */
3560 chip->select_chip(mtd, 0);
3563 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3566 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3568 /* Send the command for reading device ID */
3569 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3571 /* Read manufacturer and device IDs */
3572 *maf_id = chip->read_byte(mtd);
3573 *dev_id = chip->read_byte(mtd);
3576 * Try again to make sure, as some systems the bus-hold or other
3577 * interface concerns can cause random data which looks like a
3578 * possibly credible NAND flash to appear. If the two results do
3579 * not match, ignore the device completely.
3582 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3584 /* Read entire ID string */
3585 for (i = 0; i < 8; i++)
3586 id_data[i] = chip->read_byte(mtd);
3588 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3589 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3590 *maf_id, *dev_id, id_data[0], id_data[1]);
3591 return ERR_PTR(-ENODEV);
3595 type = nand_flash_ids;
3597 for (; type->name != NULL; type++) {
3598 if (is_full_id_nand(type)) {
3599 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3601 } else if (*dev_id == type->dev_id) {
3606 chip->onfi_version = 0;
3607 if (!type->name || !type->pagesize) {
3608 /* Check is chip is ONFI compliant */
3609 if (nand_flash_detect_onfi(mtd, chip, &busw))
3612 /* Check if the chip is JEDEC compliant */
3613 if (nand_flash_detect_jedec(mtd, chip, &busw))
3618 return ERR_PTR(-ENODEV);
3621 mtd->name = type->name;
3623 chip->chipsize = (uint64_t)type->chipsize << 20;
3625 if (!type->pagesize && chip->init_size) {
3626 /* Set the pagesize, oobsize, erasesize by the driver */
3627 busw = chip->init_size(mtd, chip, id_data);
3628 } else if (!type->pagesize) {
3629 /* Decode parameters from extended ID */
3630 nand_decode_ext_id(mtd, chip, id_data, &busw);
3632 nand_decode_id(mtd, chip, type, id_data, &busw);
3634 /* Get chip options */
3635 chip->options |= type->options;
3638 * Check if chip is not a Samsung device. Do not clear the
3639 * options for chips which do not have an extended id.
3641 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3642 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3645 /* Try to identify manufacturer */
3646 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3647 if (nand_manuf_ids[maf_idx].id == *maf_id)
3651 if (chip->options & NAND_BUSWIDTH_AUTO) {
3652 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3653 chip->options |= busw;
3654 nand_set_defaults(chip, busw);
3655 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3657 * Check, if buswidth is correct. Hardware drivers should set
3660 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3662 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3663 pr_warn("bus width %d instead %d bit\n",
3664 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3666 return ERR_PTR(-EINVAL);
3669 nand_decode_bbm_options(mtd, chip, id_data);
3671 /* Calculate the address shift from the page size */
3672 chip->page_shift = ffs(mtd->writesize) - 1;
3673 /* Convert chipsize to number of pages per chip -1 */
3674 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3676 chip->bbt_erase_shift = chip->phys_erase_shift =
3677 ffs(mtd->erasesize) - 1;
3678 if (chip->chipsize & 0xffffffff)
3679 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3681 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3682 chip->chip_shift += 32 - 1;
3685 chip->badblockbits = 8;
3686 chip->erase_cmd = single_erase_cmd;
3688 /* Do not replace user supplied command function! */
3689 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3690 chip->cmdfunc = nand_command_lp;
3692 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3695 if (chip->onfi_version)
3696 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3697 chip->onfi_params.model);
3698 else if (chip->jedec_version)
3699 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3700 chip->jedec_params.model);
3702 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3705 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3706 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3707 mtd->writesize, mtd->oobsize);
3712 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3713 * @mtd: MTD device structure
3714 * @maxchips: number of chips to scan for
3715 * @table: alternative NAND ID table
3717 * This is the first phase of the normal nand_scan() function. It reads the
3718 * flash ID and sets up MTD fields accordingly.
3720 * The mtd->owner field must be set to the module of the caller.
3722 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3723 struct nand_flash_dev *table)
3725 int i, busw, nand_maf_id, nand_dev_id;
3726 struct nand_chip *chip = mtd->priv;
3727 struct nand_flash_dev *type;
3729 /* Get buswidth to select the correct functions */
3730 busw = chip->options & NAND_BUSWIDTH_16;
3731 /* Set the default functions */
3732 nand_set_defaults(chip, busw);
3734 /* Read the flash type */
3735 type = nand_get_flash_type(mtd, chip, busw,
3736 &nand_maf_id, &nand_dev_id, table);
3739 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3740 pr_warn("No NAND device found\n");
3741 chip->select_chip(mtd, -1);
3742 return PTR_ERR(type);
3745 chip->select_chip(mtd, -1);
3747 /* Check for a chip array */
3748 for (i = 1; i < maxchips; i++) {
3749 chip->select_chip(mtd, i);
3750 /* See comment in nand_get_flash_type for reset */
3751 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3752 /* Send the command for reading device ID */
3753 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3754 /* Read manufacturer and device IDs */
3755 if (nand_maf_id != chip->read_byte(mtd) ||
3756 nand_dev_id != chip->read_byte(mtd)) {
3757 chip->select_chip(mtd, -1);
3760 chip->select_chip(mtd, -1);
3763 pr_info("%d chips detected\n", i);
3765 /* Store the number of chips and calc total size for mtd */
3767 mtd->size = i * chip->chipsize;
3771 EXPORT_SYMBOL(nand_scan_ident);
3775 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3776 * @mtd: MTD device structure
3778 * This is the second phase of the normal nand_scan() function. It fills out
3779 * all the uninitialized function pointers with the defaults and scans for a
3780 * bad block table if appropriate.
3782 int nand_scan_tail(struct mtd_info *mtd)
3785 struct nand_chip *chip = mtd->priv;
3786 struct nand_ecc_ctrl *ecc = &chip->ecc;
3787 struct nand_buffers *nbuf;
3789 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3790 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3791 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3793 if (!(chip->options & NAND_OWN_BUFFERS)) {
3794 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3795 + mtd->oobsize * 3, GFP_KERNEL);
3798 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3799 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3800 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3802 chip->buffers = nbuf;
3808 /* Set the internal oob buffer location, just after the page data */
3809 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3812 * If no default placement scheme is given, select an appropriate one.
3814 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
3815 switch (mtd->oobsize) {
3817 ecc->layout = &nand_oob_8;
3820 ecc->layout = &nand_oob_16;
3823 ecc->layout = &nand_oob_64;
3826 ecc->layout = &nand_oob_128;
3829 pr_warn("No oob scheme defined for oobsize %d\n",
3835 if (!chip->write_page)
3836 chip->write_page = nand_write_page;
3839 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3840 * selected and we have 256 byte pagesize fallback to software ECC
3843 switch (ecc->mode) {
3844 case NAND_ECC_HW_OOB_FIRST:
3845 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3846 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
3847 pr_warn("No ECC functions supplied; "
3848 "hardware ECC not possible\n");
3851 if (!ecc->read_page)
3852 ecc->read_page = nand_read_page_hwecc_oob_first;
3855 /* Use standard hwecc read page function? */
3856 if (!ecc->read_page)
3857 ecc->read_page = nand_read_page_hwecc;
3858 if (!ecc->write_page)
3859 ecc->write_page = nand_write_page_hwecc;
3860 if (!ecc->read_page_raw)
3861 ecc->read_page_raw = nand_read_page_raw;
3862 if (!ecc->write_page_raw)
3863 ecc->write_page_raw = nand_write_page_raw;
3865 ecc->read_oob = nand_read_oob_std;
3866 if (!ecc->write_oob)
3867 ecc->write_oob = nand_write_oob_std;
3868 if (!ecc->read_subpage)
3869 ecc->read_subpage = nand_read_subpage;
3870 if (!ecc->write_subpage)
3871 ecc->write_subpage = nand_write_subpage_hwecc;
3873 case NAND_ECC_HW_SYNDROME:
3874 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3876 ecc->read_page == nand_read_page_hwecc ||
3878 ecc->write_page == nand_write_page_hwecc)) {
3879 pr_warn("No ECC functions supplied; "
3880 "hardware ECC not possible\n");
3883 /* Use standard syndrome read/write page function? */
3884 if (!ecc->read_page)
3885 ecc->read_page = nand_read_page_syndrome;
3886 if (!ecc->write_page)
3887 ecc->write_page = nand_write_page_syndrome;
3888 if (!ecc->read_page_raw)
3889 ecc->read_page_raw = nand_read_page_raw_syndrome;
3890 if (!ecc->write_page_raw)
3891 ecc->write_page_raw = nand_write_page_raw_syndrome;
3893 ecc->read_oob = nand_read_oob_syndrome;
3894 if (!ecc->write_oob)
3895 ecc->write_oob = nand_write_oob_syndrome;
3897 if (mtd->writesize >= ecc->size) {
3898 if (!ecc->strength) {
3899 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3904 pr_warn("%d byte HW ECC not possible on "
3905 "%d byte page size, fallback to SW ECC\n",
3906 ecc->size, mtd->writesize);
3907 ecc->mode = NAND_ECC_SOFT;
3910 ecc->calculate = nand_calculate_ecc;
3911 ecc->correct = nand_correct_data;
3912 ecc->read_page = nand_read_page_swecc;
3913 ecc->read_subpage = nand_read_subpage;
3914 ecc->write_page = nand_write_page_swecc;
3915 ecc->read_page_raw = nand_read_page_raw;
3916 ecc->write_page_raw = nand_write_page_raw;
3917 ecc->read_oob = nand_read_oob_std;
3918 ecc->write_oob = nand_write_oob_std;
3925 case NAND_ECC_SOFT_BCH:
3926 if (!mtd_nand_has_bch()) {
3927 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3930 ecc->calculate = nand_bch_calculate_ecc;
3931 ecc->correct = nand_bch_correct_data;
3932 ecc->read_page = nand_read_page_swecc;
3933 ecc->read_subpage = nand_read_subpage;
3934 ecc->write_page = nand_write_page_swecc;
3935 ecc->read_page_raw = nand_read_page_raw;
3936 ecc->write_page_raw = nand_write_page_raw;
3937 ecc->read_oob = nand_read_oob_std;
3938 ecc->write_oob = nand_write_oob_std;
3940 * Board driver should supply ecc.size and ecc.bytes values to
3941 * select how many bits are correctable; see nand_bch_init()
3942 * for details. Otherwise, default to 4 bits for large page
3945 if (!ecc->size && (mtd->oobsize >= 64)) {
3949 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
3952 pr_warn("BCH ECC initialization failed!\n");
3955 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
3959 pr_warn("NAND_ECC_NONE selected by board driver. "
3960 "This is not recommended!\n");
3961 ecc->read_page = nand_read_page_raw;
3962 ecc->write_page = nand_write_page_raw;
3963 ecc->read_oob = nand_read_oob_std;
3964 ecc->read_page_raw = nand_read_page_raw;
3965 ecc->write_page_raw = nand_write_page_raw;
3966 ecc->write_oob = nand_write_oob_std;
3967 ecc->size = mtd->writesize;
3973 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
3977 /* For many systems, the standard OOB write also works for raw */
3978 if (!ecc->read_oob_raw)
3979 ecc->read_oob_raw = ecc->read_oob;
3980 if (!ecc->write_oob_raw)
3981 ecc->write_oob_raw = ecc->write_oob;
3984 * The number of bytes available for a client to place data into
3985 * the out of band area.
3987 ecc->layout->oobavail = 0;
3988 for (i = 0; ecc->layout->oobfree[i].length
3989 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
3990 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
3991 mtd->oobavail = ecc->layout->oobavail;
3994 * Set the number of read / write steps for one page depending on ECC
3997 ecc->steps = mtd->writesize / ecc->size;
3998 if (ecc->steps * ecc->size != mtd->writesize) {
3999 pr_warn("Invalid ECC parameters\n");
4002 ecc->total = ecc->steps * ecc->bytes;
4004 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4005 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4006 switch (ecc->steps) {
4008 mtd->subpage_sft = 1;
4013 mtd->subpage_sft = 2;
4017 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4019 /* Initialize state */
4020 chip->state = FL_READY;
4022 /* Invalidate the pagebuffer reference */
4025 /* Large page NAND with SOFT_ECC should support subpage reads */
4026 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4027 chip->options |= NAND_SUBPAGE_READ;
4029 /* Fill in remaining MTD driver data */
4030 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4031 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4033 mtd->_erase = nand_erase;
4035 mtd->_unpoint = NULL;
4036 mtd->_read = nand_read;
4037 mtd->_write = nand_write;
4038 mtd->_panic_write = panic_nand_write;
4039 mtd->_read_oob = nand_read_oob;
4040 mtd->_write_oob = nand_write_oob;
4041 mtd->_sync = nand_sync;
4043 mtd->_unlock = NULL;
4044 mtd->_suspend = nand_suspend;
4045 mtd->_resume = nand_resume;
4046 mtd->_block_isbad = nand_block_isbad;
4047 mtd->_block_markbad = nand_block_markbad;
4048 mtd->writebufsize = mtd->writesize;
4050 /* propagate ecc info to mtd_info */
4051 mtd->ecclayout = ecc->layout;
4052 mtd->ecc_strength = ecc->strength;
4053 mtd->ecc_step_size = ecc->size;
4055 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4056 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4059 if (!mtd->bitflip_threshold)
4060 mtd->bitflip_threshold = mtd->ecc_strength;
4062 /* Check, if we should skip the bad block table scan */
4063 if (chip->options & NAND_SKIP_BBTSCAN)
4066 /* Build bad block table */
4067 return chip->scan_bbt(mtd);
4069 EXPORT_SYMBOL(nand_scan_tail);
4072 * is_module_text_address() isn't exported, and it's mostly a pointless
4073 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4074 * to call us from in-kernel code if the core NAND support is modular.
4077 #define caller_is_module() (1)
4079 #define caller_is_module() \
4080 is_module_text_address((unsigned long)__builtin_return_address(0))
4084 * nand_scan - [NAND Interface] Scan for the NAND device
4085 * @mtd: MTD device structure
4086 * @maxchips: number of chips to scan for
4088 * This fills out all the uninitialized function pointers with the defaults.
4089 * The flash ID is read and the mtd/chip structures are filled with the
4090 * appropriate values. The mtd->owner field must be set to the module of the
4093 int nand_scan(struct mtd_info *mtd, int maxchips)
4097 /* Many callers got this wrong, so check for it for a while... */
4098 if (!mtd->owner && caller_is_module()) {
4099 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4103 ret = nand_scan_ident(mtd, maxchips, NULL);
4105 ret = nand_scan_tail(mtd);
4108 EXPORT_SYMBOL(nand_scan);
4111 * nand_release - [NAND Interface] Free resources held by the NAND device
4112 * @mtd: MTD device structure
4114 void nand_release(struct mtd_info *mtd)
4116 struct nand_chip *chip = mtd->priv;
4118 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4119 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4121 mtd_device_unregister(mtd);
4123 /* Free bad block table memory */
4125 if (!(chip->options & NAND_OWN_BUFFERS))
4126 kfree(chip->buffers);
4128 /* Free bad block descriptor memory */
4129 if (chip->badblock_pattern && chip->badblock_pattern->options
4130 & NAND_BBT_DYNAMICSTRUCT)
4131 kfree(chip->badblock_pattern);
4133 EXPORT_SYMBOL_GPL(nand_release);
4135 static int __init nand_base_init(void)
4137 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4141 static void __exit nand_base_exit(void)
4143 led_trigger_unregister_simple(nand_led_trigger);
4146 module_init(nand_base_init);
4147 module_exit(nand_base_exit);
4149 MODULE_LICENSE("GPL");
4150 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4151 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4152 MODULE_DESCRIPTION("Generic NAND flash driver code");