5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #include <linux/interrupt.h>
44 #include <linux/bitops.h>
45 #include <linux/leds.h>
47 #include <linux/mtd/partitions.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8 = {
60 static struct nand_ecclayout nand_oob_16 = {
62 .eccpos = {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64 = {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128 = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info *mtd, int new_state);
95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger);
104 static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
107 struct nand_chip *chip = mtd->priv;
110 /* Start address must align on block boundary */
111 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__);
116 /* Length must align on block boundary */
117 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info *mtd)
133 struct nand_chip *chip = mtd->priv;
135 /* Release the controller and the chip */
136 spin_lock(&chip->controller->lock);
137 chip->controller->active = NULL;
138 chip->state = FL_READY;
139 wake_up(&chip->controller->wq);
140 spin_unlock(&chip->controller->lock);
144 * nand_read_byte - [DEFAULT] read one byte from the chip
145 * @mtd: MTD device structure
147 * Default read function for 8bit buswidth
149 static uint8_t nand_read_byte(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return readb(chip->IO_ADDR_R);
156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
157 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
158 * @mtd: MTD device structure
160 * Default read function for 16bit buswidth with endianness conversion.
163 static uint8_t nand_read_byte16(struct mtd_info *mtd)
165 struct nand_chip *chip = mtd->priv;
166 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
170 * nand_read_word - [DEFAULT] read one word from the chip
171 * @mtd: MTD device structure
173 * Default read function for 16bit buswidth without endianness conversion.
175 static u16 nand_read_word(struct mtd_info *mtd)
177 struct nand_chip *chip = mtd->priv;
178 return readw(chip->IO_ADDR_R);
182 * nand_select_chip - [DEFAULT] control CE line
183 * @mtd: MTD device structure
184 * @chipnr: chipnumber to select, -1 for deselect
186 * Default select function for 1 chip devices.
188 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
190 struct nand_chip *chip = mtd->priv;
194 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
205 * nand_write_buf - [DEFAULT] write buffer to chip
206 * @mtd: MTD device structure
208 * @len: number of bytes to write
210 * Default write function for 8bit buswidth.
212 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
214 struct nand_chip *chip = mtd->priv;
216 iowrite8_rep(chip->IO_ADDR_W, buf, len);
220 * nand_read_buf - [DEFAULT] read chip data into buffer
221 * @mtd: MTD device structure
222 * @buf: buffer to store date
223 * @len: number of bytes to read
225 * Default read function for 8bit buswidth.
227 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
229 struct nand_chip *chip = mtd->priv;
231 ioread8_rep(chip->IO_ADDR_R, buf, len);
235 * nand_write_buf16 - [DEFAULT] write buffer to chip
236 * @mtd: MTD device structure
238 * @len: number of bytes to write
240 * Default write function for 16bit buswidth.
242 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
244 struct nand_chip *chip = mtd->priv;
245 u16 *p = (u16 *) buf;
247 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
251 * nand_read_buf16 - [DEFAULT] read chip data into buffer
252 * @mtd: MTD device structure
253 * @buf: buffer to store date
254 * @len: number of bytes to read
256 * Default read function for 16bit buswidth.
258 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
261 u16 *p = (u16 *) buf;
263 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
267 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
268 * @mtd: MTD device structure
269 * @ofs: offset from device start
270 * @getchip: 0, if the chip is already selected
272 * Check, if the block is bad.
274 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
276 int page, chipnr, res = 0, i = 0;
277 struct nand_chip *chip = mtd->priv;
280 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
281 ofs += mtd->erasesize - mtd->writesize;
283 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
286 chipnr = (int)(ofs >> chip->chip_shift);
288 nand_get_device(mtd, FL_READING);
290 /* Select the NAND device */
291 chip->select_chip(mtd, chipnr);
295 if (chip->options & NAND_BUSWIDTH_16) {
296 chip->cmdfunc(mtd, NAND_CMD_READOOB,
297 chip->badblockpos & 0xFE, page);
298 bad = cpu_to_le16(chip->read_word(mtd));
299 if (chip->badblockpos & 0x1)
304 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
306 bad = chip->read_byte(mtd);
309 if (likely(chip->badblockbits == 8))
312 res = hweight8(bad) < chip->badblockbits;
313 ofs += mtd->writesize;
314 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
316 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
319 chip->select_chip(mtd, -1);
320 nand_release_device(mtd);
327 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
328 * @mtd: MTD device structure
329 * @ofs: offset from device start
331 * This is the default implementation, which can be overridden by a hardware
332 * specific driver. It provides the details for writing a bad block marker to a
335 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
337 struct nand_chip *chip = mtd->priv;
338 struct mtd_oob_ops ops;
339 uint8_t buf[2] = { 0, 0 };
340 int ret = 0, res, i = 0;
344 ops.ooboffs = chip->badblockpos;
345 if (chip->options & NAND_BUSWIDTH_16) {
346 ops.ooboffs &= ~0x01;
347 ops.len = ops.ooblen = 2;
349 ops.len = ops.ooblen = 1;
351 ops.mode = MTD_OPS_PLACE_OOB;
353 /* Write to first/last page(s) if necessary */
354 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
355 ofs += mtd->erasesize - mtd->writesize;
357 res = nand_do_write_oob(mtd, ofs, &ops);
362 ofs += mtd->writesize;
363 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
369 * nand_block_markbad_lowlevel - mark a block bad
370 * @mtd: MTD device structure
371 * @ofs: offset from device start
373 * This function performs the generic NAND bad block marking steps (i.e., bad
374 * block table(s) and/or marker(s)). We only allow the hardware driver to
375 * specify how to write bad block markers to OOB (chip->block_markbad).
377 * We try operations in the following order:
378 * (1) erase the affected block, to allow OOB marker to be written cleanly
379 * (2) write bad block marker to OOB area of affected block (unless flag
380 * NAND_BBT_NO_OOB_BBM is present)
382 * Note that we retain the first error encountered in (2) or (3), finish the
383 * procedures, and dump the error in the end.
385 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
387 struct nand_chip *chip = mtd->priv;
390 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
391 struct erase_info einfo;
393 /* Attempt erase before marking OOB */
394 memset(&einfo, 0, sizeof(einfo));
397 einfo.len = 1ULL << chip->phys_erase_shift;
398 nand_erase_nand(mtd, &einfo, 0);
400 /* Write bad block marker to OOB */
401 nand_get_device(mtd, FL_WRITING);
402 ret = chip->block_markbad(mtd, ofs);
403 nand_release_device(mtd);
406 /* Mark block bad in BBT */
408 res = nand_markbad_bbt(mtd, ofs);
414 mtd->ecc_stats.badblocks++;
420 * nand_check_wp - [GENERIC] check if the chip is write protected
421 * @mtd: MTD device structure
423 * Check, if the device is write protected. The function expects, that the
424 * device is already selected.
426 static int nand_check_wp(struct mtd_info *mtd)
428 struct nand_chip *chip = mtd->priv;
430 /* Broken xD cards report WP despite being writable */
431 if (chip->options & NAND_BROKEN_XD)
434 /* Check the WP bit */
435 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
436 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
440 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
441 * @mtd: MTD device structure
442 * @ofs: offset from device start
443 * @getchip: 0, if the chip is already selected
444 * @allowbbt: 1, if its allowed to access the bbt area
446 * Check, if the block is bad. Either by reading the bad block table or
447 * calling of the scan function.
449 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
452 struct nand_chip *chip = mtd->priv;
455 return chip->block_bad(mtd, ofs, getchip);
457 /* Return info from the table */
458 return nand_isbad_bbt(mtd, ofs, allowbbt);
462 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
463 * @mtd: MTD device structure
466 * Helper function for nand_wait_ready used when needing to wait in interrupt
469 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
471 struct nand_chip *chip = mtd->priv;
474 /* Wait for the device to get ready */
475 for (i = 0; i < timeo; i++) {
476 if (chip->dev_ready(mtd))
478 touch_softlockup_watchdog();
483 /* Wait for the ready pin, after a command. The timeout is caught later. */
484 void nand_wait_ready(struct mtd_info *mtd)
486 struct nand_chip *chip = mtd->priv;
487 unsigned long timeo = jiffies + msecs_to_jiffies(20);
490 if (in_interrupt() || oops_in_progress)
491 return panic_nand_wait_ready(mtd, 400);
493 led_trigger_event(nand_led_trigger, LED_FULL);
494 /* Wait until command is processed or timeout occurs */
496 if (chip->dev_ready(mtd))
498 touch_softlockup_watchdog();
499 } while (time_before(jiffies, timeo));
500 led_trigger_event(nand_led_trigger, LED_OFF);
502 EXPORT_SYMBOL_GPL(nand_wait_ready);
505 * nand_command - [DEFAULT] Send command to NAND device
506 * @mtd: MTD device structure
507 * @command: the command to be sent
508 * @column: the column address for this command, -1 if none
509 * @page_addr: the page address for this command, -1 if none
511 * Send command to NAND device. This function is used for small page devices
512 * (512 Bytes per page).
514 static void nand_command(struct mtd_info *mtd, unsigned int command,
515 int column, int page_addr)
517 register struct nand_chip *chip = mtd->priv;
518 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
520 /* Write out the command to the device */
521 if (command == NAND_CMD_SEQIN) {
524 if (column >= mtd->writesize) {
526 column -= mtd->writesize;
527 readcmd = NAND_CMD_READOOB;
528 } else if (column < 256) {
529 /* First 256 bytes --> READ0 */
530 readcmd = NAND_CMD_READ0;
533 readcmd = NAND_CMD_READ1;
535 chip->cmd_ctrl(mtd, readcmd, ctrl);
536 ctrl &= ~NAND_CTRL_CHANGE;
538 chip->cmd_ctrl(mtd, command, ctrl);
540 /* Address cycle, when necessary */
541 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
542 /* Serially input address */
544 /* Adjust columns for 16 bit buswidth */
545 if (chip->options & NAND_BUSWIDTH_16)
547 chip->cmd_ctrl(mtd, column, ctrl);
548 ctrl &= ~NAND_CTRL_CHANGE;
550 if (page_addr != -1) {
551 chip->cmd_ctrl(mtd, page_addr, ctrl);
552 ctrl &= ~NAND_CTRL_CHANGE;
553 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
554 /* One more address cycle for devices > 32MiB */
555 if (chip->chipsize > (32 << 20))
556 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
558 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
561 * Program and erase have their own busy handlers status and sequential
566 case NAND_CMD_PAGEPROG:
567 case NAND_CMD_ERASE1:
568 case NAND_CMD_ERASE2:
570 case NAND_CMD_STATUS:
576 udelay(chip->chip_delay);
577 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
578 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
580 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
581 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
585 /* This applies to read commands */
588 * If we don't have access to the busy pin, we apply the given
591 if (!chip->dev_ready) {
592 udelay(chip->chip_delay);
597 * Apply this short delay always to ensure that we do wait tWB in
598 * any case on any machine.
602 nand_wait_ready(mtd);
606 * nand_command_lp - [DEFAULT] Send command to NAND large page device
607 * @mtd: MTD device structure
608 * @command: the command to be sent
609 * @column: the column address for this command, -1 if none
610 * @page_addr: the page address for this command, -1 if none
612 * Send command to NAND device. This is the version for the new large page
613 * devices. We don't have the separate regions as we have in the small page
614 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
616 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
617 int column, int page_addr)
619 register struct nand_chip *chip = mtd->priv;
621 /* Emulate NAND_CMD_READOOB */
622 if (command == NAND_CMD_READOOB) {
623 column += mtd->writesize;
624 command = NAND_CMD_READ0;
627 /* Command latch cycle */
628 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
630 if (column != -1 || page_addr != -1) {
631 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
633 /* Serially input address */
635 /* Adjust columns for 16 bit buswidth */
636 if (chip->options & NAND_BUSWIDTH_16)
638 chip->cmd_ctrl(mtd, column, ctrl);
639 ctrl &= ~NAND_CTRL_CHANGE;
640 chip->cmd_ctrl(mtd, column >> 8, ctrl);
642 if (page_addr != -1) {
643 chip->cmd_ctrl(mtd, page_addr, ctrl);
644 chip->cmd_ctrl(mtd, page_addr >> 8,
645 NAND_NCE | NAND_ALE);
646 /* One more address cycle for devices > 128MiB */
647 if (chip->chipsize > (128 << 20))
648 chip->cmd_ctrl(mtd, page_addr >> 16,
649 NAND_NCE | NAND_ALE);
652 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
655 * Program and erase have their own busy handlers status, sequential
656 * in, and deplete1 need no delay.
660 case NAND_CMD_CACHEDPROG:
661 case NAND_CMD_PAGEPROG:
662 case NAND_CMD_ERASE1:
663 case NAND_CMD_ERASE2:
666 case NAND_CMD_STATUS:
672 udelay(chip->chip_delay);
673 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
674 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
675 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
676 NAND_NCE | NAND_CTRL_CHANGE);
677 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
681 case NAND_CMD_RNDOUT:
682 /* No ready / busy check necessary */
683 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
684 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
685 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
686 NAND_NCE | NAND_CTRL_CHANGE);
690 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
691 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
692 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
693 NAND_NCE | NAND_CTRL_CHANGE);
695 /* This applies to read commands */
698 * If we don't have access to the busy pin, we apply the given
701 if (!chip->dev_ready) {
702 udelay(chip->chip_delay);
708 * Apply this short delay always to ensure that we do wait tWB in
709 * any case on any machine.
713 nand_wait_ready(mtd);
717 * panic_nand_get_device - [GENERIC] Get chip for selected access
718 * @chip: the nand chip descriptor
719 * @mtd: MTD device structure
720 * @new_state: the state which is requested
722 * Used when in panic, no locks are taken.
724 static void panic_nand_get_device(struct nand_chip *chip,
725 struct mtd_info *mtd, int new_state)
727 /* Hardware controller shared among independent devices */
728 chip->controller->active = chip;
729 chip->state = new_state;
733 * nand_get_device - [GENERIC] Get chip for selected access
734 * @mtd: MTD device structure
735 * @new_state: the state which is requested
737 * Get the device and lock it for exclusive access
740 nand_get_device(struct mtd_info *mtd, int new_state)
742 struct nand_chip *chip = mtd->priv;
743 spinlock_t *lock = &chip->controller->lock;
744 wait_queue_head_t *wq = &chip->controller->wq;
745 DECLARE_WAITQUEUE(wait, current);
749 /* Hardware controller shared among independent devices */
750 if (!chip->controller->active)
751 chip->controller->active = chip;
753 if (chip->controller->active == chip && chip->state == FL_READY) {
754 chip->state = new_state;
758 if (new_state == FL_PM_SUSPENDED) {
759 if (chip->controller->active->state == FL_PM_SUSPENDED) {
760 chip->state = FL_PM_SUSPENDED;
765 set_current_state(TASK_UNINTERRUPTIBLE);
766 add_wait_queue(wq, &wait);
769 remove_wait_queue(wq, &wait);
774 * panic_nand_wait - [GENERIC] wait until the command is done
775 * @mtd: MTD device structure
776 * @chip: NAND chip structure
779 * Wait for command done. This is a helper function for nand_wait used when
780 * we are in interrupt context. May happen when in panic and trying to write
781 * an oops through mtdoops.
783 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
787 for (i = 0; i < timeo; i++) {
788 if (chip->dev_ready) {
789 if (chip->dev_ready(mtd))
792 if (chip->read_byte(mtd) & NAND_STATUS_READY)
800 * nand_wait - [DEFAULT] wait until the command is done
801 * @mtd: MTD device structure
802 * @chip: NAND chip structure
804 * Wait for command done. This applies to erase and program only. Erase can
805 * take up to 400ms and program up to 20ms according to general NAND and
808 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
811 int status, state = chip->state;
812 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
814 led_trigger_event(nand_led_trigger, LED_FULL);
817 * Apply this short delay always to ensure that we do wait tWB in any
818 * case on any machine.
822 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
824 if (in_interrupt() || oops_in_progress)
825 panic_nand_wait(mtd, chip, timeo);
827 timeo = jiffies + msecs_to_jiffies(timeo);
828 while (time_before(jiffies, timeo)) {
829 if (chip->dev_ready) {
830 if (chip->dev_ready(mtd))
833 if (chip->read_byte(mtd) & NAND_STATUS_READY)
839 led_trigger_event(nand_led_trigger, LED_OFF);
841 status = (int)chip->read_byte(mtd);
842 /* This can happen if in case of timeout or buggy dev_ready */
843 WARN_ON(!(status & NAND_STATUS_READY));
848 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
850 * @ofs: offset to start unlock from
851 * @len: length to unlock
852 * @invert: when = 0, unlock the range of blocks within the lower and
853 * upper boundary address
854 * when = 1, unlock the range of blocks outside the boundaries
855 * of the lower and upper boundary address
857 * Returs unlock status.
859 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
860 uint64_t len, int invert)
864 struct nand_chip *chip = mtd->priv;
866 /* Submit address of first page to unlock */
867 page = ofs >> chip->page_shift;
868 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
870 /* Submit address of last page to unlock */
871 page = (ofs + len) >> chip->page_shift;
872 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
873 (page | invert) & chip->pagemask);
875 /* Call wait ready function */
876 status = chip->waitfunc(mtd, chip);
877 /* See if device thinks it succeeded */
878 if (status & NAND_STATUS_FAIL) {
879 pr_debug("%s: error status = 0x%08x\n",
888 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
890 * @ofs: offset to start unlock from
891 * @len: length to unlock
893 * Returns unlock status.
895 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
899 struct nand_chip *chip = mtd->priv;
901 pr_debug("%s: start = 0x%012llx, len = %llu\n",
902 __func__, (unsigned long long)ofs, len);
904 if (check_offs_len(mtd, ofs, len))
907 /* Align to last block address if size addresses end of the device */
908 if (ofs + len == mtd->size)
909 len -= mtd->erasesize;
911 nand_get_device(mtd, FL_UNLOCKING);
913 /* Shift to get chip number */
914 chipnr = ofs >> chip->chip_shift;
916 chip->select_chip(mtd, chipnr);
918 /* Check, if it is write protected */
919 if (nand_check_wp(mtd)) {
920 pr_debug("%s: device is write protected!\n",
926 ret = __nand_unlock(mtd, ofs, len, 0);
929 chip->select_chip(mtd, -1);
930 nand_release_device(mtd);
934 EXPORT_SYMBOL(nand_unlock);
937 * nand_lock - [REPLACEABLE] locks all blocks present in the device
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
942 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
943 * have this feature, but it allows only to lock all blocks, not for specified
944 * range for block. Implementing 'lock' feature by making use of 'unlock', for
947 * Returns lock status.
949 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
952 int chipnr, status, page;
953 struct nand_chip *chip = mtd->priv;
955 pr_debug("%s: start = 0x%012llx, len = %llu\n",
956 __func__, (unsigned long long)ofs, len);
958 if (check_offs_len(mtd, ofs, len))
961 nand_get_device(mtd, FL_LOCKING);
963 /* Shift to get chip number */
964 chipnr = ofs >> chip->chip_shift;
966 chip->select_chip(mtd, chipnr);
968 /* Check, if it is write protected */
969 if (nand_check_wp(mtd)) {
970 pr_debug("%s: device is write protected!\n",
972 status = MTD_ERASE_FAILED;
977 /* Submit address of first page to lock */
978 page = ofs >> chip->page_shift;
979 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
981 /* Call wait ready function */
982 status = chip->waitfunc(mtd, chip);
983 /* See if device thinks it succeeded */
984 if (status & NAND_STATUS_FAIL) {
985 pr_debug("%s: error status = 0x%08x\n",
991 ret = __nand_unlock(mtd, ofs, len, 0x1);
994 chip->select_chip(mtd, -1);
995 nand_release_device(mtd);
999 EXPORT_SYMBOL(nand_lock);
1002 * nand_read_page_raw - [INTERN] read raw page data without ecc
1003 * @mtd: mtd info structure
1004 * @chip: nand chip info structure
1005 * @buf: buffer to store read data
1006 * @oob_required: caller requires OOB data read to chip->oob_poi
1007 * @page: page number to read
1009 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1011 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1012 uint8_t *buf, int oob_required, int page)
1014 chip->read_buf(mtd, buf, mtd->writesize);
1016 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1021 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1022 * @mtd: mtd info structure
1023 * @chip: nand chip info structure
1024 * @buf: buffer to store read data
1025 * @oob_required: caller requires OOB data read to chip->oob_poi
1026 * @page: page number to read
1028 * We need a special oob layout and handling even when OOB isn't used.
1030 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1031 struct nand_chip *chip, uint8_t *buf,
1032 int oob_required, int page)
1034 int eccsize = chip->ecc.size;
1035 int eccbytes = chip->ecc.bytes;
1036 uint8_t *oob = chip->oob_poi;
1039 for (steps = chip->ecc.steps; steps > 0; steps--) {
1040 chip->read_buf(mtd, buf, eccsize);
1043 if (chip->ecc.prepad) {
1044 chip->read_buf(mtd, oob, chip->ecc.prepad);
1045 oob += chip->ecc.prepad;
1048 chip->read_buf(mtd, oob, eccbytes);
1051 if (chip->ecc.postpad) {
1052 chip->read_buf(mtd, oob, chip->ecc.postpad);
1053 oob += chip->ecc.postpad;
1057 size = mtd->oobsize - (oob - chip->oob_poi);
1059 chip->read_buf(mtd, oob, size);
1065 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1069 * @oob_required: caller requires OOB data read to chip->oob_poi
1070 * @page: page number to read
1072 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1073 uint8_t *buf, int oob_required, int page)
1075 int i, eccsize = chip->ecc.size;
1076 int eccbytes = chip->ecc.bytes;
1077 int eccsteps = chip->ecc.steps;
1079 uint8_t *ecc_calc = chip->buffers->ecccalc;
1080 uint8_t *ecc_code = chip->buffers->ecccode;
1081 uint32_t *eccpos = chip->ecc.layout->eccpos;
1082 unsigned int max_bitflips = 0;
1084 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1086 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1087 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1089 for (i = 0; i < chip->ecc.total; i++)
1090 ecc_code[i] = chip->oob_poi[eccpos[i]];
1092 eccsteps = chip->ecc.steps;
1095 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1098 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1100 mtd->ecc_stats.failed++;
1102 mtd->ecc_stats.corrected += stat;
1103 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1106 return max_bitflips;
1110 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1111 * @mtd: mtd info structure
1112 * @chip: nand chip info structure
1113 * @data_offs: offset of requested data within the page
1114 * @readlen: data length
1115 * @bufpoi: buffer to store read data
1117 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1118 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1120 int start_step, end_step, num_steps;
1121 uint32_t *eccpos = chip->ecc.layout->eccpos;
1123 int data_col_addr, i, gaps = 0;
1124 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1125 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1127 unsigned int max_bitflips = 0;
1129 /* Column address within the page aligned to ECC size (256bytes) */
1130 start_step = data_offs / chip->ecc.size;
1131 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1132 num_steps = end_step - start_step + 1;
1134 /* Data size aligned to ECC ecc.size */
1135 datafrag_len = num_steps * chip->ecc.size;
1136 eccfrag_len = num_steps * chip->ecc.bytes;
1138 data_col_addr = start_step * chip->ecc.size;
1139 /* If we read not a page aligned data */
1140 if (data_col_addr != 0)
1141 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1143 p = bufpoi + data_col_addr;
1144 chip->read_buf(mtd, p, datafrag_len);
1147 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1148 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1151 * The performance is faster if we position offsets according to
1152 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1154 for (i = 0; i < eccfrag_len - 1; i++) {
1155 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1156 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1162 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1163 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1166 * Send the command to read the particular ECC bytes take care
1167 * about buswidth alignment in read_buf.
1169 index = start_step * chip->ecc.bytes;
1171 aligned_pos = eccpos[index] & ~(busw - 1);
1172 aligned_len = eccfrag_len;
1173 if (eccpos[index] & (busw - 1))
1175 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1178 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1179 mtd->writesize + aligned_pos, -1);
1180 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1183 for (i = 0; i < eccfrag_len; i++)
1184 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1186 p = bufpoi + data_col_addr;
1187 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1190 stat = chip->ecc.correct(mtd, p,
1191 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1193 mtd->ecc_stats.failed++;
1195 mtd->ecc_stats.corrected += stat;
1196 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1199 return max_bitflips;
1203 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1204 * @mtd: mtd info structure
1205 * @chip: nand chip info structure
1206 * @buf: buffer to store read data
1207 * @oob_required: caller requires OOB data read to chip->oob_poi
1208 * @page: page number to read
1210 * Not for syndrome calculating ECC controllers which need a special oob layout.
1212 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1213 uint8_t *buf, int oob_required, int page)
1215 int i, eccsize = chip->ecc.size;
1216 int eccbytes = chip->ecc.bytes;
1217 int eccsteps = chip->ecc.steps;
1219 uint8_t *ecc_calc = chip->buffers->ecccalc;
1220 uint8_t *ecc_code = chip->buffers->ecccode;
1221 uint32_t *eccpos = chip->ecc.layout->eccpos;
1222 unsigned int max_bitflips = 0;
1224 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1225 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1226 chip->read_buf(mtd, p, eccsize);
1227 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1229 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1231 for (i = 0; i < chip->ecc.total; i++)
1232 ecc_code[i] = chip->oob_poi[eccpos[i]];
1234 eccsteps = chip->ecc.steps;
1237 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1240 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1242 mtd->ecc_stats.failed++;
1244 mtd->ecc_stats.corrected += stat;
1245 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1248 return max_bitflips;
1252 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1253 * @mtd: mtd info structure
1254 * @chip: nand chip info structure
1255 * @buf: buffer to store read data
1256 * @oob_required: caller requires OOB data read to chip->oob_poi
1257 * @page: page number to read
1259 * Hardware ECC for large page chips, require OOB to be read first. For this
1260 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1261 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1262 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1263 * the data area, by overwriting the NAND manufacturer bad block markings.
1265 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1266 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1268 int i, eccsize = chip->ecc.size;
1269 int eccbytes = chip->ecc.bytes;
1270 int eccsteps = chip->ecc.steps;
1272 uint8_t *ecc_code = chip->buffers->ecccode;
1273 uint32_t *eccpos = chip->ecc.layout->eccpos;
1274 uint8_t *ecc_calc = chip->buffers->ecccalc;
1275 unsigned int max_bitflips = 0;
1277 /* Read the OOB area first */
1278 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1279 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1280 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1282 for (i = 0; i < chip->ecc.total; i++)
1283 ecc_code[i] = chip->oob_poi[eccpos[i]];
1285 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1288 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1289 chip->read_buf(mtd, p, eccsize);
1290 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1292 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1294 mtd->ecc_stats.failed++;
1296 mtd->ecc_stats.corrected += stat;
1297 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1300 return max_bitflips;
1304 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1305 * @mtd: mtd info structure
1306 * @chip: nand chip info structure
1307 * @buf: buffer to store read data
1308 * @oob_required: caller requires OOB data read to chip->oob_poi
1309 * @page: page number to read
1311 * The hw generator calculates the error syndrome automatically. Therefore we
1312 * need a special oob layout and handling.
1314 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1315 uint8_t *buf, int oob_required, int page)
1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1321 uint8_t *oob = chip->oob_poi;
1322 unsigned int max_bitflips = 0;
1324 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1327 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1328 chip->read_buf(mtd, p, eccsize);
1330 if (chip->ecc.prepad) {
1331 chip->read_buf(mtd, oob, chip->ecc.prepad);
1332 oob += chip->ecc.prepad;
1335 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1336 chip->read_buf(mtd, oob, eccbytes);
1337 stat = chip->ecc.correct(mtd, p, oob, NULL);
1340 mtd->ecc_stats.failed++;
1342 mtd->ecc_stats.corrected += stat;
1343 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1348 if (chip->ecc.postpad) {
1349 chip->read_buf(mtd, oob, chip->ecc.postpad);
1350 oob += chip->ecc.postpad;
1354 /* Calculate remaining oob bytes */
1355 i = mtd->oobsize - (oob - chip->oob_poi);
1357 chip->read_buf(mtd, oob, i);
1359 return max_bitflips;
1363 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1364 * @chip: nand chip structure
1365 * @oob: oob destination address
1366 * @ops: oob ops structure
1367 * @len: size of oob to transfer
1369 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1370 struct mtd_oob_ops *ops, size_t len)
1372 switch (ops->mode) {
1374 case MTD_OPS_PLACE_OOB:
1376 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1379 case MTD_OPS_AUTO_OOB: {
1380 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1381 uint32_t boffs = 0, roffs = ops->ooboffs;
1384 for (; free->length && len; free++, len -= bytes) {
1385 /* Read request not from offset 0? */
1386 if (unlikely(roffs)) {
1387 if (roffs >= free->length) {
1388 roffs -= free->length;
1391 boffs = free->offset + roffs;
1392 bytes = min_t(size_t, len,
1393 (free->length - roffs));
1396 bytes = min_t(size_t, len, free->length);
1397 boffs = free->offset;
1399 memcpy(oob, chip->oob_poi + boffs, bytes);
1411 * nand_do_read_ops - [INTERN] Read data with ECC
1412 * @mtd: MTD device structure
1413 * @from: offset to read from
1414 * @ops: oob ops structure
1416 * Internal function. Called with chip held.
1418 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1419 struct mtd_oob_ops *ops)
1421 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1422 struct nand_chip *chip = mtd->priv;
1423 struct mtd_ecc_stats stats;
1425 uint32_t readlen = ops->len;
1426 uint32_t oobreadlen = ops->ooblen;
1427 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1428 mtd->oobavail : mtd->oobsize;
1430 uint8_t *bufpoi, *oob, *buf;
1431 unsigned int max_bitflips = 0;
1433 stats = mtd->ecc_stats;
1435 chipnr = (int)(from >> chip->chip_shift);
1436 chip->select_chip(mtd, chipnr);
1438 realpage = (int)(from >> chip->page_shift);
1439 page = realpage & chip->pagemask;
1441 col = (int)(from & (mtd->writesize - 1));
1445 oob_required = oob ? 1 : 0;
1448 bytes = min(mtd->writesize - col, readlen);
1449 aligned = (bytes == mtd->writesize);
1451 /* Is the current page in the buffer? */
1452 if (realpage != chip->pagebuf || oob) {
1453 bufpoi = aligned ? buf : chip->buffers->databuf;
1455 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1458 * Now read the page into the buffer. Absent an error,
1459 * the read methods return max bitflips per ecc step.
1461 if (unlikely(ops->mode == MTD_OPS_RAW))
1462 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1465 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1467 ret = chip->ecc.read_subpage(mtd, chip,
1468 col, bytes, bufpoi);
1470 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1471 oob_required, page);
1474 /* Invalidate page cache */
1479 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1481 /* Transfer not aligned data */
1483 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1484 !(mtd->ecc_stats.failed - stats.failed) &&
1485 (ops->mode != MTD_OPS_RAW)) {
1486 chip->pagebuf = realpage;
1487 chip->pagebuf_bitflips = ret;
1489 /* Invalidate page cache */
1492 memcpy(buf, chip->buffers->databuf + col, bytes);
1497 if (unlikely(oob)) {
1498 int toread = min(oobreadlen, max_oobsize);
1501 oob = nand_transfer_oob(chip,
1503 oobreadlen -= toread;
1507 if (chip->options & NAND_NEED_READRDY) {
1508 /* Apply delay or wait for ready/busy pin */
1509 if (!chip->dev_ready)
1510 udelay(chip->chip_delay);
1512 nand_wait_ready(mtd);
1515 memcpy(buf, chip->buffers->databuf + col, bytes);
1517 max_bitflips = max_t(unsigned int, max_bitflips,
1518 chip->pagebuf_bitflips);
1526 /* For subsequent reads align to page boundary */
1528 /* Increment page address */
1531 page = realpage & chip->pagemask;
1532 /* Check, if we cross a chip boundary */
1535 chip->select_chip(mtd, -1);
1536 chip->select_chip(mtd, chipnr);
1539 chip->select_chip(mtd, -1);
1541 ops->retlen = ops->len - (size_t) readlen;
1543 ops->oobretlen = ops->ooblen - oobreadlen;
1548 if (mtd->ecc_stats.failed - stats.failed)
1551 return max_bitflips;
1555 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1556 * @mtd: MTD device structure
1557 * @from: offset to read from
1558 * @len: number of bytes to read
1559 * @retlen: pointer to variable to store the number of read bytes
1560 * @buf: the databuffer to put data
1562 * Get hold of the chip and call nand_do_read.
1564 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1565 size_t *retlen, uint8_t *buf)
1567 struct mtd_oob_ops ops;
1570 nand_get_device(mtd, FL_READING);
1574 ops.mode = MTD_OPS_PLACE_OOB;
1575 ret = nand_do_read_ops(mtd, from, &ops);
1576 *retlen = ops.retlen;
1577 nand_release_device(mtd);
1582 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1583 * @mtd: mtd info structure
1584 * @chip: nand chip info structure
1585 * @page: page number to read
1587 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1590 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1591 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1596 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1598 * @mtd: mtd info structure
1599 * @chip: nand chip info structure
1600 * @page: page number to read
1602 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1605 uint8_t *buf = chip->oob_poi;
1606 int length = mtd->oobsize;
1607 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1608 int eccsize = chip->ecc.size;
1609 uint8_t *bufpoi = buf;
1610 int i, toread, sndrnd = 0, pos;
1612 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1613 for (i = 0; i < chip->ecc.steps; i++) {
1615 pos = eccsize + i * (eccsize + chunk);
1616 if (mtd->writesize > 512)
1617 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1619 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1622 toread = min_t(int, length, chunk);
1623 chip->read_buf(mtd, bufpoi, toread);
1628 chip->read_buf(mtd, bufpoi, length);
1634 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1635 * @mtd: mtd info structure
1636 * @chip: nand chip info structure
1637 * @page: page number to write
1639 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1643 const uint8_t *buf = chip->oob_poi;
1644 int length = mtd->oobsize;
1646 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1647 chip->write_buf(mtd, buf, length);
1648 /* Send command to program the OOB data */
1649 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1651 status = chip->waitfunc(mtd, chip);
1653 return status & NAND_STATUS_FAIL ? -EIO : 0;
1657 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1658 * with syndrome - only for large page flash
1659 * @mtd: mtd info structure
1660 * @chip: nand chip info structure
1661 * @page: page number to write
1663 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1664 struct nand_chip *chip, int page)
1666 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1667 int eccsize = chip->ecc.size, length = mtd->oobsize;
1668 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1669 const uint8_t *bufpoi = chip->oob_poi;
1672 * data-ecc-data-ecc ... ecc-oob
1674 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1676 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1677 pos = steps * (eccsize + chunk);
1682 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1683 for (i = 0; i < steps; i++) {
1685 if (mtd->writesize <= 512) {
1686 uint32_t fill = 0xFFFFFFFF;
1690 int num = min_t(int, len, 4);
1691 chip->write_buf(mtd, (uint8_t *)&fill,
1696 pos = eccsize + i * (eccsize + chunk);
1697 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1701 len = min_t(int, length, chunk);
1702 chip->write_buf(mtd, bufpoi, len);
1707 chip->write_buf(mtd, bufpoi, length);
1709 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1710 status = chip->waitfunc(mtd, chip);
1712 return status & NAND_STATUS_FAIL ? -EIO : 0;
1716 * nand_do_read_oob - [INTERN] NAND read out-of-band
1717 * @mtd: MTD device structure
1718 * @from: offset to read from
1719 * @ops: oob operations description structure
1721 * NAND read out-of-band data from the spare area.
1723 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1724 struct mtd_oob_ops *ops)
1726 int page, realpage, chipnr;
1727 struct nand_chip *chip = mtd->priv;
1728 struct mtd_ecc_stats stats;
1729 int readlen = ops->ooblen;
1731 uint8_t *buf = ops->oobbuf;
1734 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1735 __func__, (unsigned long long)from, readlen);
1737 stats = mtd->ecc_stats;
1739 if (ops->mode == MTD_OPS_AUTO_OOB)
1740 len = chip->ecc.layout->oobavail;
1744 if (unlikely(ops->ooboffs >= len)) {
1745 pr_debug("%s: attempt to start read outside oob\n",
1750 /* Do not allow reads past end of device */
1751 if (unlikely(from >= mtd->size ||
1752 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1753 (from >> chip->page_shift)) * len)) {
1754 pr_debug("%s: attempt to read beyond end of device\n",
1759 chipnr = (int)(from >> chip->chip_shift);
1760 chip->select_chip(mtd, chipnr);
1762 /* Shift to get page */
1763 realpage = (int)(from >> chip->page_shift);
1764 page = realpage & chip->pagemask;
1767 if (ops->mode == MTD_OPS_RAW)
1768 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1770 ret = chip->ecc.read_oob(mtd, chip, page);
1775 len = min(len, readlen);
1776 buf = nand_transfer_oob(chip, buf, ops, len);
1778 if (chip->options & NAND_NEED_READRDY) {
1779 /* Apply delay or wait for ready/busy pin */
1780 if (!chip->dev_ready)
1781 udelay(chip->chip_delay);
1783 nand_wait_ready(mtd);
1790 /* Increment page address */
1793 page = realpage & chip->pagemask;
1794 /* Check, if we cross a chip boundary */
1797 chip->select_chip(mtd, -1);
1798 chip->select_chip(mtd, chipnr);
1801 chip->select_chip(mtd, -1);
1803 ops->oobretlen = ops->ooblen - readlen;
1808 if (mtd->ecc_stats.failed - stats.failed)
1811 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1815 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1816 * @mtd: MTD device structure
1817 * @from: offset to read from
1818 * @ops: oob operation description structure
1820 * NAND read data and/or out-of-band data.
1822 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1823 struct mtd_oob_ops *ops)
1825 int ret = -ENOTSUPP;
1829 /* Do not allow reads past end of device */
1830 if (ops->datbuf && (from + ops->len) > mtd->size) {
1831 pr_debug("%s: attempt to read beyond end of device\n",
1836 nand_get_device(mtd, FL_READING);
1838 switch (ops->mode) {
1839 case MTD_OPS_PLACE_OOB:
1840 case MTD_OPS_AUTO_OOB:
1849 ret = nand_do_read_oob(mtd, from, ops);
1851 ret = nand_do_read_ops(mtd, from, ops);
1854 nand_release_device(mtd);
1860 * nand_write_page_raw - [INTERN] raw page write function
1861 * @mtd: mtd info structure
1862 * @chip: nand chip info structure
1864 * @oob_required: must write chip->oob_poi to OOB
1866 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1868 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1869 const uint8_t *buf, int oob_required)
1871 chip->write_buf(mtd, buf, mtd->writesize);
1873 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1879 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1880 * @mtd: mtd info structure
1881 * @chip: nand chip info structure
1883 * @oob_required: must write chip->oob_poi to OOB
1885 * We need a special oob layout and handling even when ECC isn't checked.
1887 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1888 struct nand_chip *chip,
1889 const uint8_t *buf, int oob_required)
1891 int eccsize = chip->ecc.size;
1892 int eccbytes = chip->ecc.bytes;
1893 uint8_t *oob = chip->oob_poi;
1896 for (steps = chip->ecc.steps; steps > 0; steps--) {
1897 chip->write_buf(mtd, buf, eccsize);
1900 if (chip->ecc.prepad) {
1901 chip->write_buf(mtd, oob, chip->ecc.prepad);
1902 oob += chip->ecc.prepad;
1905 chip->read_buf(mtd, oob, eccbytes);
1908 if (chip->ecc.postpad) {
1909 chip->write_buf(mtd, oob, chip->ecc.postpad);
1910 oob += chip->ecc.postpad;
1914 size = mtd->oobsize - (oob - chip->oob_poi);
1916 chip->write_buf(mtd, oob, size);
1921 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1922 * @mtd: mtd info structure
1923 * @chip: nand chip info structure
1925 * @oob_required: must write chip->oob_poi to OOB
1927 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1928 const uint8_t *buf, int oob_required)
1930 int i, eccsize = chip->ecc.size;
1931 int eccbytes = chip->ecc.bytes;
1932 int eccsteps = chip->ecc.steps;
1933 uint8_t *ecc_calc = chip->buffers->ecccalc;
1934 const uint8_t *p = buf;
1935 uint32_t *eccpos = chip->ecc.layout->eccpos;
1937 /* Software ECC calculation */
1938 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1939 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1941 for (i = 0; i < chip->ecc.total; i++)
1942 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1944 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1948 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1949 * @mtd: mtd info structure
1950 * @chip: nand chip info structure
1952 * @oob_required: must write chip->oob_poi to OOB
1954 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1955 const uint8_t *buf, int oob_required)
1957 int i, eccsize = chip->ecc.size;
1958 int eccbytes = chip->ecc.bytes;
1959 int eccsteps = chip->ecc.steps;
1960 uint8_t *ecc_calc = chip->buffers->ecccalc;
1961 const uint8_t *p = buf;
1962 uint32_t *eccpos = chip->ecc.layout->eccpos;
1964 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1965 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1966 chip->write_buf(mtd, p, eccsize);
1967 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1970 for (i = 0; i < chip->ecc.total; i++)
1971 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1973 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1980 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1981 * @mtd: mtd info structure
1982 * @chip: nand chip info structure
1983 * @offset: column address of subpage within the page
1984 * @data_len: data length
1986 * @oob_required: must write chip->oob_poi to OOB
1988 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1989 struct nand_chip *chip, uint32_t offset,
1990 uint32_t data_len, const uint8_t *buf,
1993 uint8_t *oob_buf = chip->oob_poi;
1994 uint8_t *ecc_calc = chip->buffers->ecccalc;
1995 int ecc_size = chip->ecc.size;
1996 int ecc_bytes = chip->ecc.bytes;
1997 int ecc_steps = chip->ecc.steps;
1998 uint32_t *eccpos = chip->ecc.layout->eccpos;
1999 uint32_t start_step = offset / ecc_size;
2000 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2001 int oob_bytes = mtd->oobsize / ecc_steps;
2004 for (step = 0; step < ecc_steps; step++) {
2005 /* configure controller for WRITE access */
2006 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2008 /* write data (untouched subpages already masked by 0xFF) */
2009 chip->write_buf(mtd, buf, ecc_size);
2011 /* mask ECC of un-touched subpages by padding 0xFF */
2012 if ((step < start_step) || (step > end_step))
2013 memset(ecc_calc, 0xff, ecc_bytes);
2015 chip->ecc.calculate(mtd, buf, ecc_calc);
2017 /* mask OOB of un-touched subpages by padding 0xFF */
2018 /* if oob_required, preserve OOB metadata of written subpage */
2019 if (!oob_required || (step < start_step) || (step > end_step))
2020 memset(oob_buf, 0xff, oob_bytes);
2023 ecc_calc += ecc_bytes;
2024 oob_buf += oob_bytes;
2027 /* copy calculated ECC for whole page to chip->buffer->oob */
2028 /* this include masked-value(0xFF) for unwritten subpages */
2029 ecc_calc = chip->buffers->ecccalc;
2030 for (i = 0; i < chip->ecc.total; i++)
2031 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2033 /* write OOB buffer to NAND device */
2034 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2041 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2042 * @mtd: mtd info structure
2043 * @chip: nand chip info structure
2045 * @oob_required: must write chip->oob_poi to OOB
2047 * The hw generator calculates the error syndrome automatically. Therefore we
2048 * need a special oob layout and handling.
2050 static int nand_write_page_syndrome(struct mtd_info *mtd,
2051 struct nand_chip *chip,
2052 const uint8_t *buf, int oob_required)
2054 int i, eccsize = chip->ecc.size;
2055 int eccbytes = chip->ecc.bytes;
2056 int eccsteps = chip->ecc.steps;
2057 const uint8_t *p = buf;
2058 uint8_t *oob = chip->oob_poi;
2060 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2062 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2063 chip->write_buf(mtd, p, eccsize);
2065 if (chip->ecc.prepad) {
2066 chip->write_buf(mtd, oob, chip->ecc.prepad);
2067 oob += chip->ecc.prepad;
2070 chip->ecc.calculate(mtd, p, oob);
2071 chip->write_buf(mtd, oob, eccbytes);
2074 if (chip->ecc.postpad) {
2075 chip->write_buf(mtd, oob, chip->ecc.postpad);
2076 oob += chip->ecc.postpad;
2080 /* Calculate remaining oob bytes */
2081 i = mtd->oobsize - (oob - chip->oob_poi);
2083 chip->write_buf(mtd, oob, i);
2089 * nand_write_page - [REPLACEABLE] write one page
2090 * @mtd: MTD device structure
2091 * @chip: NAND chip descriptor
2092 * @offset: address offset within the page
2093 * @data_len: length of actual data to be written
2094 * @buf: the data to write
2095 * @oob_required: must write chip->oob_poi to OOB
2096 * @page: page number to write
2097 * @cached: cached programming
2098 * @raw: use _raw version of write_page
2100 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2101 uint32_t offset, int data_len, const uint8_t *buf,
2102 int oob_required, int page, int cached, int raw)
2104 int status, subpage;
2106 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2107 chip->ecc.write_subpage)
2108 subpage = offset || (data_len < mtd->writesize);
2112 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2115 status = chip->ecc.write_page_raw(mtd, chip, buf,
2118 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2121 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2127 * Cached progamming disabled for now. Not sure if it's worth the
2128 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2132 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2134 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2135 status = chip->waitfunc(mtd, chip);
2137 * See if operation failed and additional status checks are
2140 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2141 status = chip->errstat(mtd, chip, FL_WRITING, status,
2144 if (status & NAND_STATUS_FAIL)
2147 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2148 status = chip->waitfunc(mtd, chip);
2155 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2156 * @mtd: MTD device structure
2157 * @oob: oob data buffer
2158 * @len: oob data write length
2159 * @ops: oob ops structure
2161 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2162 struct mtd_oob_ops *ops)
2164 struct nand_chip *chip = mtd->priv;
2167 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2168 * data from a previous OOB read.
2170 memset(chip->oob_poi, 0xff, mtd->oobsize);
2172 switch (ops->mode) {
2174 case MTD_OPS_PLACE_OOB:
2176 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2179 case MTD_OPS_AUTO_OOB: {
2180 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2181 uint32_t boffs = 0, woffs = ops->ooboffs;
2184 for (; free->length && len; free++, len -= bytes) {
2185 /* Write request not from offset 0? */
2186 if (unlikely(woffs)) {
2187 if (woffs >= free->length) {
2188 woffs -= free->length;
2191 boffs = free->offset + woffs;
2192 bytes = min_t(size_t, len,
2193 (free->length - woffs));
2196 bytes = min_t(size_t, len, free->length);
2197 boffs = free->offset;
2199 memcpy(chip->oob_poi + boffs, oob, bytes);
2210 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2213 * nand_do_write_ops - [INTERN] NAND write with ECC
2214 * @mtd: MTD device structure
2215 * @to: offset to write to
2216 * @ops: oob operations description structure
2218 * NAND write with ECC.
2220 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2221 struct mtd_oob_ops *ops)
2223 int chipnr, realpage, page, blockmask, column;
2224 struct nand_chip *chip = mtd->priv;
2225 uint32_t writelen = ops->len;
2227 uint32_t oobwritelen = ops->ooblen;
2228 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2229 mtd->oobavail : mtd->oobsize;
2231 uint8_t *oob = ops->oobbuf;
2232 uint8_t *buf = ops->datbuf;
2234 int oob_required = oob ? 1 : 0;
2240 /* Reject writes, which are not page aligned */
2241 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2242 pr_notice("%s: attempt to write non page aligned data\n",
2247 column = to & (mtd->writesize - 1);
2249 chipnr = (int)(to >> chip->chip_shift);
2250 chip->select_chip(mtd, chipnr);
2252 /* Check, if it is write protected */
2253 if (nand_check_wp(mtd)) {
2258 realpage = (int)(to >> chip->page_shift);
2259 page = realpage & chip->pagemask;
2260 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2262 /* Invalidate the page cache, when we write to the cached page */
2263 if (to <= (chip->pagebuf << chip->page_shift) &&
2264 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2267 /* Don't allow multipage oob writes with offset */
2268 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2274 int bytes = mtd->writesize;
2275 int cached = writelen > bytes && page != blockmask;
2276 uint8_t *wbuf = buf;
2278 /* Partial page write? */
2279 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2281 bytes = min_t(int, bytes - column, (int) writelen);
2283 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2284 memcpy(&chip->buffers->databuf[column], buf, bytes);
2285 wbuf = chip->buffers->databuf;
2288 if (unlikely(oob)) {
2289 size_t len = min(oobwritelen, oobmaxlen);
2290 oob = nand_fill_oob(mtd, oob, len, ops);
2293 /* We still need to erase leftover OOB data */
2294 memset(chip->oob_poi, 0xff, mtd->oobsize);
2296 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2297 oob_required, page, cached,
2298 (ops->mode == MTD_OPS_RAW));
2310 page = realpage & chip->pagemask;
2311 /* Check, if we cross a chip boundary */
2314 chip->select_chip(mtd, -1);
2315 chip->select_chip(mtd, chipnr);
2319 ops->retlen = ops->len - writelen;
2321 ops->oobretlen = ops->ooblen;
2324 chip->select_chip(mtd, -1);
2329 * panic_nand_write - [MTD Interface] NAND write with ECC
2330 * @mtd: MTD device structure
2331 * @to: offset to write to
2332 * @len: number of bytes to write
2333 * @retlen: pointer to variable to store the number of written bytes
2334 * @buf: the data to write
2336 * NAND write with ECC. Used when performing writes in interrupt context, this
2337 * may for example be called by mtdoops when writing an oops while in panic.
2339 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2340 size_t *retlen, const uint8_t *buf)
2342 struct nand_chip *chip = mtd->priv;
2343 struct mtd_oob_ops ops;
2346 /* Wait for the device to get ready */
2347 panic_nand_wait(mtd, chip, 400);
2349 /* Grab the device */
2350 panic_nand_get_device(chip, mtd, FL_WRITING);
2353 ops.datbuf = (uint8_t *)buf;
2355 ops.mode = MTD_OPS_PLACE_OOB;
2357 ret = nand_do_write_ops(mtd, to, &ops);
2359 *retlen = ops.retlen;
2364 * nand_write - [MTD Interface] NAND write with ECC
2365 * @mtd: MTD device structure
2366 * @to: offset to write to
2367 * @len: number of bytes to write
2368 * @retlen: pointer to variable to store the number of written bytes
2369 * @buf: the data to write
2371 * NAND write with ECC.
2373 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2374 size_t *retlen, const uint8_t *buf)
2376 struct mtd_oob_ops ops;
2379 nand_get_device(mtd, FL_WRITING);
2381 ops.datbuf = (uint8_t *)buf;
2383 ops.mode = MTD_OPS_PLACE_OOB;
2384 ret = nand_do_write_ops(mtd, to, &ops);
2385 *retlen = ops.retlen;
2386 nand_release_device(mtd);
2391 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2392 * @mtd: MTD device structure
2393 * @to: offset to write to
2394 * @ops: oob operation description structure
2396 * NAND write out-of-band.
2398 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2399 struct mtd_oob_ops *ops)
2401 int chipnr, page, status, len;
2402 struct nand_chip *chip = mtd->priv;
2404 pr_debug("%s: to = 0x%08x, len = %i\n",
2405 __func__, (unsigned int)to, (int)ops->ooblen);
2407 if (ops->mode == MTD_OPS_AUTO_OOB)
2408 len = chip->ecc.layout->oobavail;
2412 /* Do not allow write past end of page */
2413 if ((ops->ooboffs + ops->ooblen) > len) {
2414 pr_debug("%s: attempt to write past end of page\n",
2419 if (unlikely(ops->ooboffs >= len)) {
2420 pr_debug("%s: attempt to start write outside oob\n",
2425 /* Do not allow write past end of device */
2426 if (unlikely(to >= mtd->size ||
2427 ops->ooboffs + ops->ooblen >
2428 ((mtd->size >> chip->page_shift) -
2429 (to >> chip->page_shift)) * len)) {
2430 pr_debug("%s: attempt to write beyond end of device\n",
2435 chipnr = (int)(to >> chip->chip_shift);
2436 chip->select_chip(mtd, chipnr);
2438 /* Shift to get page */
2439 page = (int)(to >> chip->page_shift);
2442 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2443 * of my DiskOnChip 2000 test units) will clear the whole data page too
2444 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2445 * it in the doc2000 driver in August 1999. dwmw2.
2447 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2449 /* Check, if it is write protected */
2450 if (nand_check_wp(mtd)) {
2451 chip->select_chip(mtd, -1);
2455 /* Invalidate the page cache, if we write to the cached page */
2456 if (page == chip->pagebuf)
2459 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2461 if (ops->mode == MTD_OPS_RAW)
2462 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2464 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2466 chip->select_chip(mtd, -1);
2471 ops->oobretlen = ops->ooblen;
2477 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2478 * @mtd: MTD device structure
2479 * @to: offset to write to
2480 * @ops: oob operation description structure
2482 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2483 struct mtd_oob_ops *ops)
2485 int ret = -ENOTSUPP;
2489 /* Do not allow writes past end of device */
2490 if (ops->datbuf && (to + ops->len) > mtd->size) {
2491 pr_debug("%s: attempt to write beyond end of device\n",
2496 nand_get_device(mtd, FL_WRITING);
2498 switch (ops->mode) {
2499 case MTD_OPS_PLACE_OOB:
2500 case MTD_OPS_AUTO_OOB:
2509 ret = nand_do_write_oob(mtd, to, ops);
2511 ret = nand_do_write_ops(mtd, to, ops);
2514 nand_release_device(mtd);
2519 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2520 * @mtd: MTD device structure
2521 * @page: the page address of the block which will be erased
2523 * Standard erase command for NAND chips.
2525 static void single_erase_cmd(struct mtd_info *mtd, int page)
2527 struct nand_chip *chip = mtd->priv;
2528 /* Send commands to erase a block */
2529 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2530 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2534 * nand_erase - [MTD Interface] erase block(s)
2535 * @mtd: MTD device structure
2536 * @instr: erase instruction
2538 * Erase one ore more blocks.
2540 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2542 return nand_erase_nand(mtd, instr, 0);
2546 * nand_erase_nand - [INTERN] erase block(s)
2547 * @mtd: MTD device structure
2548 * @instr: erase instruction
2549 * @allowbbt: allow erasing the bbt area
2551 * Erase one ore more blocks.
2553 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2556 int page, status, pages_per_block, ret, chipnr;
2557 struct nand_chip *chip = mtd->priv;
2560 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2561 __func__, (unsigned long long)instr->addr,
2562 (unsigned long long)instr->len);
2564 if (check_offs_len(mtd, instr->addr, instr->len))
2567 /* Grab the lock and see if the device is available */
2568 nand_get_device(mtd, FL_ERASING);
2570 /* Shift to get first page */
2571 page = (int)(instr->addr >> chip->page_shift);
2572 chipnr = (int)(instr->addr >> chip->chip_shift);
2574 /* Calculate pages in each block */
2575 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2577 /* Select the NAND device */
2578 chip->select_chip(mtd, chipnr);
2580 /* Check, if it is write protected */
2581 if (nand_check_wp(mtd)) {
2582 pr_debug("%s: device is write protected!\n",
2584 instr->state = MTD_ERASE_FAILED;
2588 /* Loop through the pages */
2591 instr->state = MTD_ERASING;
2594 /* Check if we have a bad block, we do not erase bad blocks! */
2595 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2596 chip->page_shift, 0, allowbbt)) {
2597 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2599 instr->state = MTD_ERASE_FAILED;
2604 * Invalidate the page cache, if we erase the block which
2605 * contains the current cached page.
2607 if (page <= chip->pagebuf && chip->pagebuf <
2608 (page + pages_per_block))
2611 chip->erase_cmd(mtd, page & chip->pagemask);
2613 status = chip->waitfunc(mtd, chip);
2616 * See if operation failed and additional status checks are
2619 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2620 status = chip->errstat(mtd, chip, FL_ERASING,
2623 /* See if block erase succeeded */
2624 if (status & NAND_STATUS_FAIL) {
2625 pr_debug("%s: failed erase, page 0x%08x\n",
2627 instr->state = MTD_ERASE_FAILED;
2629 ((loff_t)page << chip->page_shift);
2633 /* Increment page address and decrement length */
2634 len -= (1ULL << chip->phys_erase_shift);
2635 page += pages_per_block;
2637 /* Check, if we cross a chip boundary */
2638 if (len && !(page & chip->pagemask)) {
2640 chip->select_chip(mtd, -1);
2641 chip->select_chip(mtd, chipnr);
2644 instr->state = MTD_ERASE_DONE;
2648 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2650 /* Deselect and wake up anyone waiting on the device */
2651 chip->select_chip(mtd, -1);
2652 nand_release_device(mtd);
2654 /* Do call back function */
2656 mtd_erase_callback(instr);
2658 /* Return more or less happy */
2663 * nand_sync - [MTD Interface] sync
2664 * @mtd: MTD device structure
2666 * Sync is actually a wait for chip ready function.
2668 static void nand_sync(struct mtd_info *mtd)
2670 pr_debug("%s: called\n", __func__);
2672 /* Grab the lock and see if the device is available */
2673 nand_get_device(mtd, FL_SYNCING);
2674 /* Release it and go back */
2675 nand_release_device(mtd);
2679 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2680 * @mtd: MTD device structure
2681 * @offs: offset relative to mtd start
2683 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2685 return nand_block_checkbad(mtd, offs, 1, 0);
2689 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2690 * @mtd: MTD device structure
2691 * @ofs: offset relative to mtd start
2693 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2697 ret = nand_block_isbad(mtd, ofs);
2699 /* If it was bad already, return success and do nothing */
2705 return nand_block_markbad_lowlevel(mtd, ofs);
2709 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2710 * @mtd: MTD device structure
2711 * @chip: nand chip info structure
2712 * @addr: feature address.
2713 * @subfeature_param: the subfeature parameters, a four bytes array.
2715 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2716 int addr, uint8_t *subfeature_param)
2720 if (!chip->onfi_version ||
2721 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2722 & ONFI_OPT_CMD_SET_GET_FEATURES))
2725 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2726 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2727 status = chip->waitfunc(mtd, chip);
2728 if (status & NAND_STATUS_FAIL)
2734 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2735 * @mtd: MTD device structure
2736 * @chip: nand chip info structure
2737 * @addr: feature address.
2738 * @subfeature_param: the subfeature parameters, a four bytes array.
2740 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2741 int addr, uint8_t *subfeature_param)
2743 if (!chip->onfi_version ||
2744 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2745 & ONFI_OPT_CMD_SET_GET_FEATURES))
2748 /* clear the sub feature parameters */
2749 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2751 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2752 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2757 * nand_suspend - [MTD Interface] Suspend the NAND flash
2758 * @mtd: MTD device structure
2760 static int nand_suspend(struct mtd_info *mtd)
2762 return nand_get_device(mtd, FL_PM_SUSPENDED);
2766 * nand_resume - [MTD Interface] Resume the NAND flash
2767 * @mtd: MTD device structure
2769 static void nand_resume(struct mtd_info *mtd)
2771 struct nand_chip *chip = mtd->priv;
2773 if (chip->state == FL_PM_SUSPENDED)
2774 nand_release_device(mtd);
2776 pr_err("%s called for a chip which is not in suspended state\n",
2780 /* Set default functions */
2781 static void nand_set_defaults(struct nand_chip *chip, int busw)
2783 /* check for proper chip_delay setup, set 20us if not */
2784 if (!chip->chip_delay)
2785 chip->chip_delay = 20;
2787 /* check, if a user supplied command function given */
2788 if (chip->cmdfunc == NULL)
2789 chip->cmdfunc = nand_command;
2791 /* check, if a user supplied wait function given */
2792 if (chip->waitfunc == NULL)
2793 chip->waitfunc = nand_wait;
2795 if (!chip->select_chip)
2796 chip->select_chip = nand_select_chip;
2798 /* set for ONFI nand */
2799 if (!chip->onfi_set_features)
2800 chip->onfi_set_features = nand_onfi_set_features;
2801 if (!chip->onfi_get_features)
2802 chip->onfi_get_features = nand_onfi_get_features;
2804 /* If called twice, pointers that depend on busw may need to be reset */
2805 if (!chip->read_byte || chip->read_byte == nand_read_byte)
2806 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2807 if (!chip->read_word)
2808 chip->read_word = nand_read_word;
2809 if (!chip->block_bad)
2810 chip->block_bad = nand_block_bad;
2811 if (!chip->block_markbad)
2812 chip->block_markbad = nand_default_block_markbad;
2813 if (!chip->write_buf || chip->write_buf == nand_write_buf)
2814 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2815 if (!chip->read_buf || chip->read_buf == nand_read_buf)
2816 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2817 if (!chip->scan_bbt)
2818 chip->scan_bbt = nand_default_bbt;
2820 if (!chip->controller) {
2821 chip->controller = &chip->hwcontrol;
2822 spin_lock_init(&chip->controller->lock);
2823 init_waitqueue_head(&chip->controller->wq);
2828 /* Sanitize ONFI strings so we can safely print them */
2829 static void sanitize_string(uint8_t *s, size_t len)
2833 /* Null terminate */
2836 /* Remove non printable chars */
2837 for (i = 0; i < len - 1; i++) {
2838 if (s[i] < ' ' || s[i] > 127)
2842 /* Remove trailing spaces */
2846 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2851 for (i = 0; i < 8; i++)
2852 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2858 /* Parse the Extended Parameter Page. */
2859 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2860 struct nand_chip *chip, struct nand_onfi_params *p)
2862 struct onfi_ext_param_page *ep;
2863 struct onfi_ext_section *s;
2864 struct onfi_ext_ecc_info *ecc;
2870 len = le16_to_cpu(p->ext_param_page_length) * 16;
2871 ep = kmalloc(len, GFP_KERNEL);
2875 /* Send our own NAND_CMD_PARAM. */
2876 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2878 /* Use the Change Read Column command to skip the ONFI param pages. */
2879 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2880 sizeof(*p) * p->num_of_param_pages , -1);
2882 /* Read out the Extended Parameter Page. */
2883 chip->read_buf(mtd, (uint8_t *)ep, len);
2884 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2885 != le16_to_cpu(ep->crc))) {
2886 pr_debug("fail in the CRC.\n");
2891 * Check the signature.
2892 * Do not strictly follow the ONFI spec, maybe changed in future.
2894 if (strncmp(ep->sig, "EPPS", 4)) {
2895 pr_debug("The signature is invalid.\n");
2899 /* find the ECC section. */
2900 cursor = (uint8_t *)(ep + 1);
2901 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
2902 s = ep->sections + i;
2903 if (s->type == ONFI_SECTION_TYPE_2)
2905 cursor += s->length * 16;
2907 if (i == ONFI_EXT_SECTION_MAX) {
2908 pr_debug("We can not find the ECC section.\n");
2912 /* get the info we want. */
2913 ecc = (struct onfi_ext_ecc_info *)cursor;
2915 if (ecc->codeword_size) {
2916 chip->ecc_strength_ds = ecc->ecc_bits;
2917 chip->ecc_step_ds = 1 << ecc->codeword_size;
2920 pr_info("ONFI extended param page detected.\n");
2929 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2931 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2934 struct nand_onfi_params *p = &chip->onfi_params;
2938 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2939 if (chip->options & NAND_BUSWIDTH_16) {
2940 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2943 /* Try ONFI for unknown chip or LP */
2944 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2945 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2946 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2949 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2950 for (i = 0; i < 3; i++) {
2951 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2952 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2953 le16_to_cpu(p->crc)) {
2954 pr_info("ONFI param page %d valid\n", i);
2963 val = le16_to_cpu(p->revision);
2965 chip->onfi_version = 23;
2966 else if (val & (1 << 4))
2967 chip->onfi_version = 22;
2968 else if (val & (1 << 3))
2969 chip->onfi_version = 21;
2970 else if (val & (1 << 2))
2971 chip->onfi_version = 20;
2972 else if (val & (1 << 1))
2973 chip->onfi_version = 10;
2975 if (!chip->onfi_version) {
2976 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2980 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2981 sanitize_string(p->model, sizeof(p->model));
2983 mtd->name = p->model;
2984 mtd->writesize = le32_to_cpu(p->byte_per_page);
2985 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2986 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2987 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2988 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2990 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
2991 *busw = NAND_BUSWIDTH_16;
2995 if (p->ecc_bits != 0xff) {
2996 chip->ecc_strength_ds = p->ecc_bits;
2997 chip->ecc_step_ds = 512;
2998 } else if (chip->onfi_version >= 21 &&
2999 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3002 * The nand_flash_detect_ext_param_page() uses the
3003 * Change Read Column command which maybe not supported
3004 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3005 * now. We do not replace user supplied command function.
3007 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3008 chip->cmdfunc = nand_command_lp;
3010 /* The Extended Parameter Page is supported since ONFI 2.1. */
3011 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3012 pr_info("Failed to detect the extended param page.\n");
3015 pr_info("ONFI flash detected\n");
3020 * nand_id_has_period - Check if an ID string has a given wraparound period
3021 * @id_data: the ID string
3022 * @arrlen: the length of the @id_data array
3023 * @period: the period of repitition
3025 * Check if an ID string is repeated within a given sequence of bytes at
3026 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3027 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3028 * if the repetition has a period of @period; otherwise, returns zero.
3030 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3033 for (i = 0; i < period; i++)
3034 for (j = i + period; j < arrlen; j += period)
3035 if (id_data[i] != id_data[j])
3041 * nand_id_len - Get the length of an ID string returned by CMD_READID
3042 * @id_data: the ID string
3043 * @arrlen: the length of the @id_data array
3045 * Returns the length of the ID string, according to known wraparound/trailing
3046 * zero patterns. If no pattern exists, returns the length of the array.
3048 static int nand_id_len(u8 *id_data, int arrlen)
3050 int last_nonzero, period;
3052 /* Find last non-zero byte */
3053 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3054 if (id_data[last_nonzero])
3058 if (last_nonzero < 0)
3061 /* Calculate wraparound period */
3062 for (period = 1; period < arrlen; period++)
3063 if (nand_id_has_period(id_data, arrlen, period))
3066 /* There's a repeated pattern */
3067 if (period < arrlen)
3070 /* There are trailing zeros */
3071 if (last_nonzero < arrlen - 1)
3072 return last_nonzero + 1;
3074 /* No pattern detected */
3079 * Many new NAND share similar device ID codes, which represent the size of the
3080 * chip. The rest of the parameters must be decoded according to generic or
3081 * manufacturer-specific "extended ID" decoding patterns.
3083 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3084 u8 id_data[8], int *busw)
3087 /* The 3rd id byte holds MLC / multichip data */
3088 chip->cellinfo = id_data[2];
3089 /* The 4th id byte is the important one */
3092 id_len = nand_id_len(id_data, 8);
3095 * Field definitions are in the following datasheets:
3096 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3097 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3098 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3100 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3101 * ID to decide what to do.
3103 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3104 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3105 id_data[5] != 0x00) {
3107 mtd->writesize = 2048 << (extid & 0x03);
3110 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3127 default: /* Other cases are "reserved" (unknown) */
3132 /* Calc blocksize */
3133 mtd->erasesize = (128 * 1024) <<
3134 (((extid >> 1) & 0x04) | (extid & 0x03));
3136 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3137 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3141 mtd->writesize = 2048 << (extid & 0x03);
3144 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3168 /* Calc blocksize */
3169 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3171 mtd->erasesize = (128 * 1024) << tmp;
3172 else if (tmp == 0x03)
3173 mtd->erasesize = 768 * 1024;
3175 mtd->erasesize = (64 * 1024) << tmp;
3179 mtd->writesize = 1024 << (extid & 0x03);
3182 mtd->oobsize = (8 << (extid & 0x01)) *
3183 (mtd->writesize >> 9);
3185 /* Calc blocksize. Blocksize is multiples of 64KiB */
3186 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3188 /* Get buswidth information */
3189 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3192 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3193 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3195 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3197 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3199 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3200 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3201 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3202 !(id_data[4] & 0x80) /* !BENAND */) {
3203 mtd->oobsize = 32 * mtd->writesize >> 9;
3210 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3211 * decodes a matching ID table entry and assigns the MTD size parameters for
3214 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3215 struct nand_flash_dev *type, u8 id_data[8],
3218 int maf_id = id_data[0];
3220 mtd->erasesize = type->erasesize;
3221 mtd->writesize = type->pagesize;
3222 mtd->oobsize = mtd->writesize / 32;
3223 *busw = type->options & NAND_BUSWIDTH_16;
3226 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3227 * some Spansion chips have erasesize that conflicts with size
3228 * listed in nand_ids table.
3229 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3231 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3232 && id_data[6] == 0x00 && id_data[7] == 0x00
3233 && mtd->writesize == 512) {
3234 mtd->erasesize = 128 * 1024;
3235 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3240 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3241 * heuristic patterns using various detected parameters (e.g., manufacturer,
3242 * page size, cell-type information).
3244 static void nand_decode_bbm_options(struct mtd_info *mtd,
3245 struct nand_chip *chip, u8 id_data[8])
3247 int maf_id = id_data[0];
3249 /* Set the bad block position */
3250 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3251 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3253 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3256 * Bad block marker is stored in the last page of each block on Samsung
3257 * and Hynix MLC devices; stored in first two pages of each block on
3258 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3259 * AMD/Spansion, and Macronix. All others scan only the first page.
3261 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3262 (maf_id == NAND_MFR_SAMSUNG ||
3263 maf_id == NAND_MFR_HYNIX))
3264 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3265 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3266 (maf_id == NAND_MFR_SAMSUNG ||
3267 maf_id == NAND_MFR_HYNIX ||
3268 maf_id == NAND_MFR_TOSHIBA ||
3269 maf_id == NAND_MFR_AMD ||
3270 maf_id == NAND_MFR_MACRONIX)) ||
3271 (mtd->writesize == 2048 &&
3272 maf_id == NAND_MFR_MICRON))
3273 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3276 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3278 return type->id_len;
3281 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3282 struct nand_flash_dev *type, u8 *id_data, int *busw)
3284 if (!strncmp(type->id, id_data, type->id_len)) {
3285 mtd->writesize = type->pagesize;
3286 mtd->erasesize = type->erasesize;
3287 mtd->oobsize = type->oobsize;
3289 chip->cellinfo = id_data[2];
3290 chip->chipsize = (uint64_t)type->chipsize << 20;
3291 chip->options |= type->options;
3292 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3293 chip->ecc_step_ds = NAND_ECC_STEP(type);
3295 *busw = type->options & NAND_BUSWIDTH_16;
3303 * Get the flash and manufacturer id and lookup if the type is supported.
3305 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3306 struct nand_chip *chip,
3308 int *maf_id, int *dev_id,
3309 struct nand_flash_dev *type)
3314 /* Select the device */
3315 chip->select_chip(mtd, 0);
3318 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3321 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3323 /* Send the command for reading device ID */
3324 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3326 /* Read manufacturer and device IDs */
3327 *maf_id = chip->read_byte(mtd);
3328 *dev_id = chip->read_byte(mtd);
3331 * Try again to make sure, as some systems the bus-hold or other
3332 * interface concerns can cause random data which looks like a
3333 * possibly credible NAND flash to appear. If the two results do
3334 * not match, ignore the device completely.
3337 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3339 /* Read entire ID string */
3340 for (i = 0; i < 8; i++)
3341 id_data[i] = chip->read_byte(mtd);
3343 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3344 pr_info("%s: second ID read did not match "
3345 "%02x,%02x against %02x,%02x\n", __func__,
3346 *maf_id, *dev_id, id_data[0], id_data[1]);
3347 return ERR_PTR(-ENODEV);
3351 type = nand_flash_ids;
3353 for (; type->name != NULL; type++) {
3354 if (is_full_id_nand(type)) {
3355 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3357 } else if (*dev_id == type->dev_id) {
3362 chip->onfi_version = 0;
3363 if (!type->name || !type->pagesize) {
3364 /* Check is chip is ONFI compliant */
3365 if (nand_flash_detect_onfi(mtd, chip, &busw))
3370 return ERR_PTR(-ENODEV);
3373 mtd->name = type->name;
3375 chip->chipsize = (uint64_t)type->chipsize << 20;
3377 if (!type->pagesize && chip->init_size) {
3378 /* Set the pagesize, oobsize, erasesize by the driver */
3379 busw = chip->init_size(mtd, chip, id_data);
3380 } else if (!type->pagesize) {
3381 /* Decode parameters from extended ID */
3382 nand_decode_ext_id(mtd, chip, id_data, &busw);
3384 nand_decode_id(mtd, chip, type, id_data, &busw);
3386 /* Get chip options */
3387 chip->options |= type->options;
3390 * Check if chip is not a Samsung device. Do not clear the
3391 * options for chips which do not have an extended id.
3393 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3394 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3397 /* Try to identify manufacturer */
3398 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3399 if (nand_manuf_ids[maf_idx].id == *maf_id)
3403 if (chip->options & NAND_BUSWIDTH_AUTO) {
3404 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3405 chip->options |= busw;
3406 nand_set_defaults(chip, busw);
3407 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3409 * Check, if buswidth is correct. Hardware drivers should set
3412 pr_info("NAND device: Manufacturer ID:"
3413 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3414 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3415 pr_warn("NAND bus width %d instead %d bit\n",
3416 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3418 return ERR_PTR(-EINVAL);
3421 nand_decode_bbm_options(mtd, chip, id_data);
3423 /* Calculate the address shift from the page size */
3424 chip->page_shift = ffs(mtd->writesize) - 1;
3425 /* Convert chipsize to number of pages per chip -1 */
3426 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3428 chip->bbt_erase_shift = chip->phys_erase_shift =
3429 ffs(mtd->erasesize) - 1;
3430 if (chip->chipsize & 0xffffffff)
3431 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3433 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3434 chip->chip_shift += 32 - 1;
3437 chip->badblockbits = 8;
3438 chip->erase_cmd = single_erase_cmd;
3440 /* Do not replace user supplied command function! */
3441 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3442 chip->cmdfunc = nand_command_lp;
3444 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3445 " %dMiB, page size: %d, OOB size: %d\n",
3446 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3447 chip->onfi_version ? chip->onfi_params.model : type->name,
3448 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
3454 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3455 * @mtd: MTD device structure
3456 * @maxchips: number of chips to scan for
3457 * @table: alternative NAND ID table
3459 * This is the first phase of the normal nand_scan() function. It reads the
3460 * flash ID and sets up MTD fields accordingly.
3462 * The mtd->owner field must be set to the module of the caller.
3464 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3465 struct nand_flash_dev *table)
3467 int i, busw, nand_maf_id, nand_dev_id;
3468 struct nand_chip *chip = mtd->priv;
3469 struct nand_flash_dev *type;
3471 /* Get buswidth to select the correct functions */
3472 busw = chip->options & NAND_BUSWIDTH_16;
3473 /* Set the default functions */
3474 nand_set_defaults(chip, busw);
3476 /* Read the flash type */
3477 type = nand_get_flash_type(mtd, chip, busw,
3478 &nand_maf_id, &nand_dev_id, table);
3481 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3482 pr_warn("No NAND device found\n");
3483 chip->select_chip(mtd, -1);
3484 return PTR_ERR(type);
3487 chip->select_chip(mtd, -1);
3489 /* Check for a chip array */
3490 for (i = 1; i < maxchips; i++) {
3491 chip->select_chip(mtd, i);
3492 /* See comment in nand_get_flash_type for reset */
3493 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3494 /* Send the command for reading device ID */
3495 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3496 /* Read manufacturer and device IDs */
3497 if (nand_maf_id != chip->read_byte(mtd) ||
3498 nand_dev_id != chip->read_byte(mtd)) {
3499 chip->select_chip(mtd, -1);
3502 chip->select_chip(mtd, -1);
3505 pr_info("%d NAND chips detected\n", i);
3507 /* Store the number of chips and calc total size for mtd */
3509 mtd->size = i * chip->chipsize;
3513 EXPORT_SYMBOL(nand_scan_ident);
3517 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3518 * @mtd: MTD device structure
3520 * This is the second phase of the normal nand_scan() function. It fills out
3521 * all the uninitialized function pointers with the defaults and scans for a
3522 * bad block table if appropriate.
3524 int nand_scan_tail(struct mtd_info *mtd)
3527 struct nand_chip *chip = mtd->priv;
3529 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3530 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3531 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3533 if (!(chip->options & NAND_OWN_BUFFERS))
3534 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3538 /* Set the internal oob buffer location, just after the page data */
3539 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3542 * If no default placement scheme is given, select an appropriate one.
3544 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3545 switch (mtd->oobsize) {
3547 chip->ecc.layout = &nand_oob_8;
3550 chip->ecc.layout = &nand_oob_16;
3553 chip->ecc.layout = &nand_oob_64;
3556 chip->ecc.layout = &nand_oob_128;
3559 pr_warn("No oob scheme defined for oobsize %d\n",
3565 if (!chip->write_page)
3566 chip->write_page = nand_write_page;
3569 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3570 * selected and we have 256 byte pagesize fallback to software ECC
3573 switch (chip->ecc.mode) {
3574 case NAND_ECC_HW_OOB_FIRST:
3575 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3576 if (!chip->ecc.calculate || !chip->ecc.correct ||
3578 pr_warn("No ECC functions supplied; "
3579 "hardware ECC not possible\n");
3582 if (!chip->ecc.read_page)
3583 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3586 /* Use standard hwecc read page function? */
3587 if (!chip->ecc.read_page)
3588 chip->ecc.read_page = nand_read_page_hwecc;
3589 if (!chip->ecc.write_page)
3590 chip->ecc.write_page = nand_write_page_hwecc;
3591 if (!chip->ecc.read_page_raw)
3592 chip->ecc.read_page_raw = nand_read_page_raw;
3593 if (!chip->ecc.write_page_raw)
3594 chip->ecc.write_page_raw = nand_write_page_raw;
3595 if (!chip->ecc.read_oob)
3596 chip->ecc.read_oob = nand_read_oob_std;
3597 if (!chip->ecc.write_oob)
3598 chip->ecc.write_oob = nand_write_oob_std;
3599 if (!chip->ecc.read_subpage)
3600 chip->ecc.read_subpage = nand_read_subpage;
3601 if (!chip->ecc.write_subpage)
3602 chip->ecc.write_subpage = nand_write_subpage_hwecc;
3604 case NAND_ECC_HW_SYNDROME:
3605 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3606 !chip->ecc.hwctl) &&
3607 (!chip->ecc.read_page ||
3608 chip->ecc.read_page == nand_read_page_hwecc ||
3609 !chip->ecc.write_page ||
3610 chip->ecc.write_page == nand_write_page_hwecc)) {
3611 pr_warn("No ECC functions supplied; "
3612 "hardware ECC not possible\n");
3615 /* Use standard syndrome read/write page function? */
3616 if (!chip->ecc.read_page)
3617 chip->ecc.read_page = nand_read_page_syndrome;
3618 if (!chip->ecc.write_page)
3619 chip->ecc.write_page = nand_write_page_syndrome;
3620 if (!chip->ecc.read_page_raw)
3621 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3622 if (!chip->ecc.write_page_raw)
3623 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3624 if (!chip->ecc.read_oob)
3625 chip->ecc.read_oob = nand_read_oob_syndrome;
3626 if (!chip->ecc.write_oob)
3627 chip->ecc.write_oob = nand_write_oob_syndrome;
3629 if (mtd->writesize >= chip->ecc.size) {
3630 if (!chip->ecc.strength) {
3631 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3636 pr_warn("%d byte HW ECC not possible on "
3637 "%d byte page size, fallback to SW ECC\n",
3638 chip->ecc.size, mtd->writesize);
3639 chip->ecc.mode = NAND_ECC_SOFT;
3642 chip->ecc.calculate = nand_calculate_ecc;
3643 chip->ecc.correct = nand_correct_data;
3644 chip->ecc.read_page = nand_read_page_swecc;
3645 chip->ecc.read_subpage = nand_read_subpage;
3646 chip->ecc.write_page = nand_write_page_swecc;
3647 chip->ecc.read_page_raw = nand_read_page_raw;
3648 chip->ecc.write_page_raw = nand_write_page_raw;
3649 chip->ecc.read_oob = nand_read_oob_std;
3650 chip->ecc.write_oob = nand_write_oob_std;
3651 if (!chip->ecc.size)
3652 chip->ecc.size = 256;
3653 chip->ecc.bytes = 3;
3654 chip->ecc.strength = 1;
3657 case NAND_ECC_SOFT_BCH:
3658 if (!mtd_nand_has_bch()) {
3659 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3662 chip->ecc.calculate = nand_bch_calculate_ecc;
3663 chip->ecc.correct = nand_bch_correct_data;
3664 chip->ecc.read_page = nand_read_page_swecc;
3665 chip->ecc.read_subpage = nand_read_subpage;
3666 chip->ecc.write_page = nand_write_page_swecc;
3667 chip->ecc.read_page_raw = nand_read_page_raw;
3668 chip->ecc.write_page_raw = nand_write_page_raw;
3669 chip->ecc.read_oob = nand_read_oob_std;
3670 chip->ecc.write_oob = nand_write_oob_std;
3672 * Board driver should supply ecc.size and ecc.bytes values to
3673 * select how many bits are correctable; see nand_bch_init()
3674 * for details. Otherwise, default to 4 bits for large page
3677 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3678 chip->ecc.size = 512;
3679 chip->ecc.bytes = 7;
3681 chip->ecc.priv = nand_bch_init(mtd,
3685 if (!chip->ecc.priv) {
3686 pr_warn("BCH ECC initialization failed!\n");
3689 chip->ecc.strength =
3690 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3694 pr_warn("NAND_ECC_NONE selected by board driver. "
3695 "This is not recommended!\n");
3696 chip->ecc.read_page = nand_read_page_raw;
3697 chip->ecc.write_page = nand_write_page_raw;
3698 chip->ecc.read_oob = nand_read_oob_std;
3699 chip->ecc.read_page_raw = nand_read_page_raw;
3700 chip->ecc.write_page_raw = nand_write_page_raw;
3701 chip->ecc.write_oob = nand_write_oob_std;
3702 chip->ecc.size = mtd->writesize;
3703 chip->ecc.bytes = 0;
3704 chip->ecc.strength = 0;
3708 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3712 /* For many systems, the standard OOB write also works for raw */
3713 if (!chip->ecc.read_oob_raw)
3714 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3715 if (!chip->ecc.write_oob_raw)
3716 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3719 * The number of bytes available for a client to place data into
3720 * the out of band area.
3722 chip->ecc.layout->oobavail = 0;
3723 for (i = 0; chip->ecc.layout->oobfree[i].length
3724 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3725 chip->ecc.layout->oobavail +=
3726 chip->ecc.layout->oobfree[i].length;
3727 mtd->oobavail = chip->ecc.layout->oobavail;
3730 * Set the number of read / write steps for one page depending on ECC
3733 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3734 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3735 pr_warn("Invalid ECC parameters\n");
3738 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3740 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3741 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3742 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3743 switch (chip->ecc.steps) {
3745 mtd->subpage_sft = 1;
3750 mtd->subpage_sft = 2;
3754 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3756 /* Initialize state */
3757 chip->state = FL_READY;
3759 /* Invalidate the pagebuffer reference */
3762 /* Large page NAND with SOFT_ECC should support subpage reads */
3763 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3764 chip->options |= NAND_SUBPAGE_READ;
3766 /* Fill in remaining MTD driver data */
3767 mtd->type = MTD_NANDFLASH;
3768 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3770 mtd->_erase = nand_erase;
3772 mtd->_unpoint = NULL;
3773 mtd->_read = nand_read;
3774 mtd->_write = nand_write;
3775 mtd->_panic_write = panic_nand_write;
3776 mtd->_read_oob = nand_read_oob;
3777 mtd->_write_oob = nand_write_oob;
3778 mtd->_sync = nand_sync;
3780 mtd->_unlock = NULL;
3781 mtd->_suspend = nand_suspend;
3782 mtd->_resume = nand_resume;
3783 mtd->_block_isbad = nand_block_isbad;
3784 mtd->_block_markbad = nand_block_markbad;
3785 mtd->writebufsize = mtd->writesize;
3787 /* propagate ecc info to mtd_info */
3788 mtd->ecclayout = chip->ecc.layout;
3789 mtd->ecc_strength = chip->ecc.strength;
3790 mtd->ecc_step_size = chip->ecc.size;
3792 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3793 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3796 if (!mtd->bitflip_threshold)
3797 mtd->bitflip_threshold = mtd->ecc_strength;
3799 /* Check, if we should skip the bad block table scan */
3800 if (chip->options & NAND_SKIP_BBTSCAN)
3803 /* Build bad block table */
3804 return chip->scan_bbt(mtd);
3806 EXPORT_SYMBOL(nand_scan_tail);
3809 * is_module_text_address() isn't exported, and it's mostly a pointless
3810 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3811 * to call us from in-kernel code if the core NAND support is modular.
3814 #define caller_is_module() (1)
3816 #define caller_is_module() \
3817 is_module_text_address((unsigned long)__builtin_return_address(0))
3821 * nand_scan - [NAND Interface] Scan for the NAND device
3822 * @mtd: MTD device structure
3823 * @maxchips: number of chips to scan for
3825 * This fills out all the uninitialized function pointers with the defaults.
3826 * The flash ID is read and the mtd/chip structures are filled with the
3827 * appropriate values. The mtd->owner field must be set to the module of the
3830 int nand_scan(struct mtd_info *mtd, int maxchips)
3834 /* Many callers got this wrong, so check for it for a while... */
3835 if (!mtd->owner && caller_is_module()) {
3836 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3840 ret = nand_scan_ident(mtd, maxchips, NULL);
3842 ret = nand_scan_tail(mtd);
3845 EXPORT_SYMBOL(nand_scan);
3848 * nand_release - [NAND Interface] Free resources held by the NAND device
3849 * @mtd: MTD device structure
3851 void nand_release(struct mtd_info *mtd)
3853 struct nand_chip *chip = mtd->priv;
3855 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3856 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3858 mtd_device_unregister(mtd);
3860 /* Free bad block table memory */
3862 if (!(chip->options & NAND_OWN_BUFFERS))
3863 kfree(chip->buffers);
3865 /* Free bad block descriptor memory */
3866 if (chip->badblock_pattern && chip->badblock_pattern->options
3867 & NAND_BBT_DYNAMICSTRUCT)
3868 kfree(chip->badblock_pattern);
3870 EXPORT_SYMBOL_GPL(nand_release);
3872 static int __init nand_base_init(void)
3874 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3878 static void __exit nand_base_exit(void)
3880 led_trigger_unregister_simple(nand_led_trigger);
3883 module_init(nand_base_init);
3884 module_exit(nand_base_exit);
3886 MODULE_LICENSE("GPL");
3887 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3888 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3889 MODULE_DESCRIPTION("Generic NAND flash driver code");