drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 /* XXX U-BOOT XXX */
  36 #if 0
  37 #include <linux/module.h>
  38 #include <linux/delay.h>
  39 #include <linux/errno.h>
  40 #include <linux/err.h>
  41 #include <linux/sched.h>
  42 #include <linux/slab.h>
  43 #include <linux/types.h>
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/compatmac.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/bitops.h>
  50 #include <linux/leds.h>
  51 #include <asm/io.h>
  52
  53 #ifdef CONFIG_MTD_PARTITIONS
  54 #include <linux/mtd/partitions.h>
  55 #endif
  56
  57 #endif
  58
  59 #include <common.h>
  60
  61 #define ENOTSUPP        524     /* Operation is not supported */
  62
  63 #include <malloc.h>
  64 #include <watchdog.h>
  65 #include <linux/err.h>
  66 #include <linux/mtd/compat.h>
  67 #include <linux/mtd/mtd.h>
  68 #include <linux/mtd/nand.h>
  69 #include <linux/mtd/nand_ecc.h>
  70
  71 #include <asm/io.h>
  72 #include <asm/errno.h>
  73
  74 #ifdef CONFIG_JFFS2_NAND
  75 #include <jffs2/jffs2.h>
  76 #endif
  77
  78 /*
  79  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  80  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  81  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  82  * which is greater than (max NAND reset time / NAND status read time).
  83  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  84  */
  85 #ifndef CONFIG_SYS_NAND_RESET_CNT
  86 #define CONFIG_SYS_NAND_RESET_CNT 200000
  87 #endif
  88
  89 /* Define default oob placement schemes for large and small page devices */
  90 static struct nand_ecclayout nand_oob_8 = {
  91         .eccbytes = 3,
  92         .eccpos = {0, 1, 2},
  93         .oobfree = {
  94                 {.offset = 3,
  95                  .length = 2},
  96                 {.offset = 6,
  97                  .length = 2}}
  98 };
  99
 100 static struct nand_ecclayout nand_oob_16 = {
 101         .eccbytes = 6,
 102         .eccpos = {0, 1, 2, 3, 6, 7},
 103         .oobfree = {
 104                 {.offset = 8,
 105                  . length = 8}}
 106 };
 107
 108 static struct nand_ecclayout nand_oob_64 = {
 109         .eccbytes = 24,
 110         .eccpos = {
 111                    40, 41, 42, 43, 44, 45, 46, 47,
 112                    48, 49, 50, 51, 52, 53, 54, 55,
 113                    56, 57, 58, 59, 60, 61, 62, 63},
 114         .oobfree = {
 115                 {.offset = 2,
 116                  .length = 38}}
 117 };
 118
 119 static struct nand_ecclayout nand_oob_128 = {
 120         .eccbytes = 48,
 121         .eccpos = {
 122                     80,  81,  82,  83,  84,  85,  86,  87,
 123                     88,  89,  90,  91,  92,  93,  94,  95,
 124                     96,  97,  98,  99, 100, 101, 102, 103,
 125                    104, 105, 106, 107, 108, 109, 110, 111,
 126                    112, 113, 114, 115, 116, 117, 118, 119,
 127                    120, 121, 122, 123, 124, 125, 126, 127},
 128         .oobfree = {
 129                 {.offset = 2,
 130                  .length = 78}}
 131 };
 132
 133
 134 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 135                            int new_state);
 136
 137 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 138                              struct mtd_oob_ops *ops);
 139
 140 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 141
 142 /*
 143  * For devices which display every fart in the system on a separate LED. Is
 144  * compiled away when LED support is disabled.
 145  */
 146 /* XXX U-BOOT XXX */
 147 #if 0
 148 DEFINE_LED_TRIGGER(nand_led_trigger);
 149 #endif
 150
 151 /**
 152  * nand_release_device - [GENERIC] release chip
 153  * @mtd:        MTD device structure
 154  *
 155  * Deselect, release chip lock and wake up anyone waiting on the device
 156  */
 157 /* XXX U-BOOT XXX */
 158 #if 0
 159 static void nand_release_device(struct mtd_info *mtd)
 160 {
 161         struct nand_chip *chip = mtd->priv;
 162
 163         /* De-select the NAND device */
 164         chip->select_chip(mtd, -1);
 165
 166         /* Release the controller and the chip */
 167         spin_lock(&chip->controller->lock);
 168         chip->controller->active = NULL;
 169         chip->state = FL_READY;
 170         wake_up(&chip->controller->wq);
 171         spin_unlock(&chip->controller->lock);
 172 }
 173 #else
 174 static void nand_release_device (struct mtd_info *mtd)
 175 {
 176         struct nand_chip *this = mtd->priv;
 177         this->select_chip(mtd, -1);     /* De-select the NAND device */
 178 }
 179 #endif
 180
 181 /**
 182  * nand_read_byte - [DEFAULT] read one byte from the chip
 183  * @mtd:        MTD device structure
 184  *
 185  * Default read function for 8bit buswith
 186  */
 187 static uint8_t nand_read_byte(struct mtd_info *mtd)
 188 {
 189         struct nand_chip *chip = mtd->priv;
 190         return readb(chip->IO_ADDR_R);
 191 }
 192
 193 /**
 194  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 195  * @mtd:        MTD device structure
 196  *
 197  * Default read function for 16bit buswith with
 198  * endianess conversion
 199  */
 200 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 201 {
 202         struct nand_chip *chip = mtd->priv;
 203         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 204 }
 205
 206 /**
 207  * nand_read_word - [DEFAULT] read one word from the chip
 208  * @mtd:        MTD device structure
 209  *
 210  * Default read function for 16bit buswith without
 211  * endianess conversion
 212  */
 213 static u16 nand_read_word(struct mtd_info *mtd)
 214 {
 215         struct nand_chip *chip = mtd->priv;
 216         return readw(chip->IO_ADDR_R);
 217 }
 218
 219 /**
 220  * nand_select_chip - [DEFAULT] control CE line
 221  * @mtd:        MTD device structure
 222  * @chipnr:     chipnumber to select, -1 for deselect
 223  *
 224  * Default select function for 1 chip devices.
 225  */
 226 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 227 {
 228         struct nand_chip *chip = mtd->priv;
 229
 230         switch (chipnr) {
 231         case -1:
 232                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 233                 break;
 234         case 0:
 235                 break;
 236
 237         default:
 238                 BUG();
 239         }
 240 }
 241
 242 /**
 243  * nand_write_buf - [DEFAULT] write buffer to chip
 244  * @mtd:        MTD device structure
 245  * @buf:        data buffer
 246  * @len:        number of bytes to write
 247  *
 248  * Default write function for 8bit buswith
 249  */
 250 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 251 {
 252         int i;
 253         struct nand_chip *chip = mtd->priv;
 254
 255         for (i = 0; i < len; i++)
 256                 writeb(buf[i], chip->IO_ADDR_W);
 257 }
 258
 259 /**
 260  * nand_read_buf - [DEFAULT] read chip data into buffer
 261  * @mtd:        MTD device structure
 262  * @buf:        buffer to store date
 263  * @len:        number of bytes to read
 264  *
 265  * Default read function for 8bit buswith
 266  */
 267 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 268 {
 269         int i;
 270         struct nand_chip *chip = mtd->priv;
 271
 272         for (i = 0; i < len; i++)
 273                 buf[i] = readb(chip->IO_ADDR_R);
 274 }
 275
 276 /**
 277  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 278  * @mtd:        MTD device structure
 279  * @buf:        buffer containing the data to compare
 280  * @len:        number of bytes to compare
 281  *
 282  * Default verify function for 8bit buswith
 283  */
 284 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 285 {
 286         int i;
 287         struct nand_chip *chip = mtd->priv;
 288
 289         for (i = 0; i < len; i++)
 290                 if (buf[i] != readb(chip->IO_ADDR_R))
 291                         return -EFAULT;
 292         return 0;
 293 }
 294
 295 /**
 296  * nand_write_buf16 - [DEFAULT] write buffer to chip
 297  * @mtd:        MTD device structure
 298  * @buf:        data buffer
 299  * @len:        number of bytes to write
 300  *
 301  * Default write function for 16bit buswith
 302  */
 303 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 304 {
 305         int i;
 306         struct nand_chip *chip = mtd->priv;
 307         u16 *p = (u16 *) buf;
 308         len >>= 1;
 309
 310         for (i = 0; i < len; i++)
 311                 writew(p[i], chip->IO_ADDR_W);
 312
 313 }
 314
 315 /**
 316  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 317  * @mtd:        MTD device structure
 318  * @buf:        buffer to store date
 319  * @len:        number of bytes to read
 320  *
 321  * Default read function for 16bit buswith
 322  */
 323 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 324 {
 325         int i;
 326         struct nand_chip *chip = mtd->priv;
 327         u16 *p = (u16 *) buf;
 328         len >>= 1;
 329
 330         for (i = 0; i < len; i++)
 331                 p[i] = readw(chip->IO_ADDR_R);
 332 }
 333
 334 /**
 335  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 336  * @mtd:        MTD device structure
 337  * @buf:        buffer containing the data to compare
 338  * @len:        number of bytes to compare
 339  *
 340  * Default verify function for 16bit buswith
 341  */
 342 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 343 {
 344         int i;
 345         struct nand_chip *chip = mtd->priv;
 346         u16 *p = (u16 *) buf;
 347         len >>= 1;
 348
 349         for (i = 0; i < len; i++)
 350                 if (p[i] != readw(chip->IO_ADDR_R))
 351                         return -EFAULT;
 352
 353         return 0;
 354 }
 355
 356 /**
 357  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 358  * @mtd:        MTD device structure
 359  * @ofs:        offset from device start
 360  * @getchip:    0, if the chip is already selected
 361  *
 362  * Check, if the block is bad.
 363  */
 364 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 365 {
 366         int page, chipnr, res = 0;
 367         struct nand_chip *chip = mtd->priv;
 368         u16 bad;
 369
 370         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 371
 372         if (getchip) {
 373                 chipnr = (int)(ofs >> chip->chip_shift);
 374
 375                 nand_get_device(chip, mtd, FL_READING);
 376
 377                 /* Select the NAND device */
 378                 chip->select_chip(mtd, chipnr);
 379         }
 380
 381         if (chip->options & NAND_BUSWIDTH_16) {
 382                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 383                               page);
 384                 bad = cpu_to_le16(chip->read_word(mtd));
 385                 if (chip->badblockpos & 0x1)
 386                         bad >>= 8;
 387                 if ((bad & 0xFF) != 0xff)
 388                         res = 1;
 389         } else {
 390                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 391                 if (chip->read_byte(mtd) != 0xff)
 392                         res = 1;
 393         }
 394
 395         if (getchip)
 396                 nand_release_device(mtd);
 397
 398         return res;
 399 }
 400
 401 /**
 402  * nand_default_block_markbad - [DEFAULT] mark a block bad
 403  * @mtd:        MTD device structure
 404  * @ofs:        offset from device start
 405  *
 406  * This is the default implementation, which can be overridden by
 407  * a hardware specific driver.
 408 */
 409 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 410 {
 411         struct nand_chip *chip = mtd->priv;
 412         uint8_t buf[2] = { 0, 0 };
 413         int block, ret;
 414
 415         /* Get block number */
 416         block = (int)(ofs >> chip->bbt_erase_shift);
 417         if (chip->bbt)
 418                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 419
 420         /* Do we have a flash based bad block table ? */
 421         if (chip->options & NAND_USE_FLASH_BBT)
 422                 ret = nand_update_bbt(mtd, ofs);
 423         else {
 424                 /* We write two bytes, so we dont have to mess with 16 bit
 425                  * access
 426                  */
 427                 nand_get_device(chip, mtd, FL_WRITING);
 428                 ofs += mtd->oobsize;
 429                 chip->ops.len = chip->ops.ooblen = 2;
 430                 chip->ops.datbuf = NULL;
 431                 chip->ops.oobbuf = buf;
 432                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 433
 434                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 435                 nand_release_device(mtd);
 436         }
 437         if (!ret)
 438                 mtd->ecc_stats.badblocks++;
 439
 440         return ret;
 441 }
 442
 443 /**
 444  * nand_check_wp - [GENERIC] check if the chip is write protected
 445  * @mtd:        MTD device structure
 446  * Check, if the device is write protected
 447  *
 448  * The function expects, that the device is already selected
 449  */
 450 static int nand_check_wp(struct mtd_info *mtd)
 451 {
 452         struct nand_chip *chip = mtd->priv;
 453         /* Check the WP bit */
 454         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 455         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 456 }
 457
 458 /**
 459  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 460  * @mtd:        MTD device structure
 461  * @ofs:        offset from device start
 462  * @getchip:    0, if the chip is already selected
 463  * @allowbbt:   1, if its allowed to access the bbt area
 464  *
 465  * Check, if the block is bad. Either by reading the bad block table or
 466  * calling of the scan function.
 467  */
 468 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 469                                int allowbbt)
 470 {
 471         struct nand_chip *chip = mtd->priv;
 472
 473         if (!(chip->options & NAND_BBT_SCANNED)) {
 474                 chip->options |= NAND_BBT_SCANNED;
 475                 chip->scan_bbt(mtd);
 476         }
 477
 478         if (!chip->bbt)
 479                 return chip->block_bad(mtd, ofs, getchip);
 480
 481         /* Return info from the table */
 482         return nand_isbad_bbt(mtd, ofs, allowbbt);
 483 }
 484
 485 /*
 486  * Wait for the ready pin, after a command
 487  * The timeout is catched later.
 488  */
 489 /* XXX U-BOOT XXX */
 490 #if 0
 491 void nand_wait_ready(struct mtd_info *mtd)
 492 {
 493         struct nand_chip *chip = mtd->priv;
 494         unsigned long timeo = jiffies + 2;
 495
 496         led_trigger_event(nand_led_trigger, LED_FULL);
 497         /* wait until command is processed or timeout occures */
 498         do {
 499                 if (chip->dev_ready(mtd))
 500                         break;
 501                 touch_softlockup_watchdog();
 502         } while (time_before(jiffies, timeo));
 503         led_trigger_event(nand_led_trigger, LED_OFF);
 504 }
 505 EXPORT_SYMBOL_GPL(nand_wait_ready);
 506 #else
 507 void nand_wait_ready(struct mtd_info *mtd)
 508 {
 509         struct nand_chip *chip = mtd->priv;
 510         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 511
 512         reset_timer();
 513
 514         /* wait until command is processed or timeout occures */
 515         while (get_timer(0) < timeo) {
 516                 if (chip->dev_ready)
 517                         if (chip->dev_ready(mtd))
 518                                 break;
 519         }
 520 }
 521 #endif
 522
 523 /**
 524  * nand_command - [DEFAULT] Send command to NAND device
 525  * @mtd:        MTD device structure
 526  * @command:    the command to be sent
 527  * @column:     the column address for this command, -1 if none
 528  * @page_addr:  the page address for this command, -1 if none
 529  *
 530  * Send command to NAND device. This function is used for small page
 531  * devices (256/512 Bytes per page)
 532  */
 533 static void nand_command(struct mtd_info *mtd, unsigned int command,
 534                          int column, int page_addr)
 535 {
 536         register struct nand_chip *chip = mtd->priv;
 537         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 538         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 539
 540         /*
 541          * Write out the command to the device.
 542          */
 543         if (command == NAND_CMD_SEQIN) {
 544                 int readcmd;
 545
 546                 if (column >= mtd->writesize) {
 547                         /* OOB area */
 548                         column -= mtd->writesize;
 549                         readcmd = NAND_CMD_READOOB;
 550                 } else if (column < 256) {
 551                         /* First 256 bytes --> READ0 */
 552                         readcmd = NAND_CMD_READ0;
 553                 } else {
 554                         column -= 256;
 555                         readcmd = NAND_CMD_READ1;
 556                 }
 557                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559         }
 560         chip->cmd_ctrl(mtd, command, ctrl);
 561
 562         /*
 563          * Address cycle, when necessary
 564          */
 565         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 566         /* Serially input address */
 567         if (column != -1) {
 568                 /* Adjust columns for 16 bit buswidth */
 569                 if (chip->options & NAND_BUSWIDTH_16)
 570                         column >>= 1;
 571                 chip->cmd_ctrl(mtd, column, ctrl);
 572                 ctrl &= ~NAND_CTRL_CHANGE;
 573         }
 574         if (page_addr != -1) {
 575                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 576                 ctrl &= ~NAND_CTRL_CHANGE;
 577                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 578                 /* One more address cycle for devices > 32MiB */
 579                 if (chip->chipsize > (32 << 20))
 580                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 581         }
 582         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 583
 584         /*
 585          * program and erase have their own busy handlers
 586          * status and sequential in needs no delay
 587          */
 588         switch (command) {
 589
 590         case NAND_CMD_PAGEPROG:
 591         case NAND_CMD_ERASE1:
 592         case NAND_CMD_ERASE2:
 593         case NAND_CMD_SEQIN:
 594         case NAND_CMD_STATUS:
 595                 return;
 596
 597         case NAND_CMD_RESET:
 598                 if (chip->dev_ready)
 599                         break;
 600                 udelay(chip->chip_delay);
 601                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 602                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 603                 chip->cmd_ctrl(mtd,
 604                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 605                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 606                         (rst_sts_cnt--));
 607                 return;
 608
 609                 /* This applies to read commands */
 610         default:
 611                 /*
 612                  * If we don't have access to the busy pin, we apply the given
 613                  * command delay
 614                  */
 615                 if (!chip->dev_ready) {
 616                         udelay(chip->chip_delay);
 617                         return;
 618                 }
 619         }
 620         /* Apply this short delay always to ensure that we do wait tWB in
 621          * any case on any machine. */
 622         ndelay(100);
 623
 624         nand_wait_ready(mtd);
 625 }
 626
 627 /**
 628  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 629  * @mtd:        MTD device structure
 630  * @command:    the command to be sent
 631  * @column:     the column address for this command, -1 if none
 632  * @page_addr:  the page address for this command, -1 if none
 633  *
 634  * Send command to NAND device. This is the version for the new large page
 635  * devices We dont have the separate regions as we have in the small page
 636  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 637  */
 638 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 639                             int column, int page_addr)
 640 {
 641         register struct nand_chip *chip = mtd->priv;
 642         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 643
 644         /* Emulate NAND_CMD_READOOB */
 645         if (command == NAND_CMD_READOOB) {
 646                 column += mtd->writesize;
 647                 command = NAND_CMD_READ0;
 648         }
 649
 650         /* Command latch cycle */
 651         chip->cmd_ctrl(mtd, command & 0xff,
 652                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 653
 654         if (column != -1 || page_addr != -1) {
 655                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 656
 657                 /* Serially input address */
 658                 if (column != -1) {
 659                         /* Adjust columns for 16 bit buswidth */
 660                         if (chip->options & NAND_BUSWIDTH_16)
 661                                 column >>= 1;
 662                         chip->cmd_ctrl(mtd, column, ctrl);
 663                         ctrl &= ~NAND_CTRL_CHANGE;
 664                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 665                 }
 666                 if (page_addr != -1) {
 667                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 668                         chip->cmd_ctrl(mtd, page_addr >> 8,
 669                                        NAND_NCE | NAND_ALE);
 670                         /* One more address cycle for devices > 128MiB */
 671                         if (chip->chipsize > (128 << 20))
 672                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 673                                                NAND_NCE | NAND_ALE);
 674                 }
 675         }
 676         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 677
 678         /*
 679          * program and erase have their own busy handlers
 680          * status, sequential in, and deplete1 need no delay
 681          */
 682         switch (command) {
 683
 684         case NAND_CMD_CACHEDPROG:
 685         case NAND_CMD_PAGEPROG:
 686         case NAND_CMD_ERASE1:
 687         case NAND_CMD_ERASE2:
 688         case NAND_CMD_SEQIN:
 689         case NAND_CMD_RNDIN:
 690         case NAND_CMD_STATUS:
 691         case NAND_CMD_DEPLETE1:
 692                 return;
 693
 694                 /*
 695                  * read error status commands require only a short delay
 696                  */
 697         case NAND_CMD_STATUS_ERROR:
 698         case NAND_CMD_STATUS_ERROR0:
 699         case NAND_CMD_STATUS_ERROR1:
 700         case NAND_CMD_STATUS_ERROR2:
 701         case NAND_CMD_STATUS_ERROR3:
 702                 udelay(chip->chip_delay);
 703                 return;
 704
 705         case NAND_CMD_RESET:
 706                 if (chip->dev_ready)
 707                         break;
 708                 udelay(chip->chip_delay);
 709                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 710                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 711                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 712                                NAND_NCE | NAND_CTRL_CHANGE);
 713                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 714                         (rst_sts_cnt--));
 715                 return;
 716
 717         case NAND_CMD_RNDOUT:
 718                 /* No ready / busy check necessary */
 719                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 720                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 721                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 722                                NAND_NCE | NAND_CTRL_CHANGE);
 723                 return;
 724
 725         case NAND_CMD_READ0:
 726                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 727                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 728                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 729                                NAND_NCE | NAND_CTRL_CHANGE);
 730
 731                 /* This applies to read commands */
 732         default:
 733                 /*
 734                  * If we don't have access to the busy pin, we apply the given
 735                  * command delay
 736                  */
 737                 if (!chip->dev_ready) {
 738                         udelay(chip->chip_delay);
 739                         return;
 740                 }
 741         }
 742
 743         /* Apply this short delay always to ensure that we do wait tWB in
 744          * any case on any machine. */
 745         ndelay(100);
 746
 747         nand_wait_ready(mtd);
 748 }
 749
 750 /**
 751  * nand_get_device - [GENERIC] Get chip for selected access
 752  * @chip:       the nand chip descriptor
 753  * @mtd:        MTD device structure
 754  * @new_state:  the state which is requested
 755  *
 756  * Get the device and lock it for exclusive access
 757  */
 758 /* XXX U-BOOT XXX */
 759 #if 0
 760 static int
 761 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 762 {
 763         spinlock_t *lock = &chip->controller->lock;
 764         wait_queue_head_t *wq = &chip->controller->wq;
 765         DECLARE_WAITQUEUE(wait, current);
 766  retry:
 767         spin_lock(lock);
 768
 769         /* Hardware controller shared among independend devices */
 770         /* Hardware controller shared among independend devices */
 771         if (!chip->controller->active)
 772                 chip->controller->active = chip;
 773
 774         if (chip->controller->active == chip && chip->state == FL_READY) {
 775                 chip->state = new_state;
 776                 spin_unlock(lock);
 777                 return 0;
 778         }
 779         if (new_state == FL_PM_SUSPENDED) {
 780                 spin_unlock(lock);
 781                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 782         }
 783         set_current_state(TASK_UNINTERRUPTIBLE);
 784         add_wait_queue(wq, &wait);
 785         spin_unlock(lock);
 786         schedule();
 787         remove_wait_queue(wq, &wait);
 788         goto retry;
 789 }
 790 #else
 791 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 792 {
 793         this->state = new_state;
 794         return 0;
 795 }
 796 #endif
 797
 798 /**
 799  * nand_wait - [DEFAULT]  wait until the command is done
 800  * @mtd:        MTD device structure
 801  * @chip:       NAND chip structure
 802  *
 803  * Wait for command done. This applies to erase and program only
 804  * Erase can take up to 400ms and program up to 20ms according to
 805  * general NAND and SmartMedia specs
 806  */
 807 /* XXX U-BOOT XXX */
 808 #if 0
 809 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 810 {
 811
 812         unsigned long timeo = jiffies;
 813         int status, state = chip->state;
 814
 815         if (state == FL_ERASING)
 816                 timeo += (HZ * 400) / 1000;
 817         else
 818                 timeo += (HZ * 20) / 1000;
 819
 820         led_trigger_event(nand_led_trigger, LED_FULL);
 821
 822         /* Apply this short delay always to ensure that we do wait tWB in
 823          * any case on any machine. */
 824         ndelay(100);
 825
 826         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 827                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 828         else
 829                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 830
 831         while (time_before(jiffies, timeo)) {
 832                 if (chip->dev_ready) {
 833                         if (chip->dev_ready(mtd))
 834                                 break;
 835                 } else {
 836                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 837                                 break;
 838                 }
 839                 cond_resched();
 840         }
 841         led_trigger_event(nand_led_trigger, LED_OFF);
 842
 843         status = (int)chip->read_byte(mtd);
 844         return status;
 845 }
 846 #else
 847 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 848 {
 849         unsigned long   timeo;
 850         int state = this->state;
 851
 852         if (state == FL_ERASING)
 853                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 854         else
 855                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 856
 857         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 858                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 859         else
 860                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 861
 862         reset_timer();
 863
 864         while (1) {
 865                 if (get_timer(0) > timeo) {
 866                         printf("Timeout!");
 867                         return 0x01;
 868                 }
 869
 870                 if (this->dev_ready) {
 871                         if (this->dev_ready(mtd))
 872                                 break;
 873                 } else {
 874                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 875                                 break;
 876                 }
 877         }
 878 #ifdef PPCHAMELON_NAND_TIMER_HACK
 879         reset_timer();
 880         while (get_timer(0) < 10);
 881 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 882
 883         return this->read_byte(mtd);
 884 }
 885 #endif
 886
 887 /**
 888  * nand_read_page_raw - [Intern] read raw page data without ecc
 889  * @mtd:        mtd info structure
 890  * @chip:       nand chip info structure
 891  * @buf:        buffer to store read data
 892  */
 893 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 894                               uint8_t *buf)
 895 {
 896         chip->read_buf(mtd, buf, mtd->writesize);
 897         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 898         return 0;
 899 }
 900
 901 /**
 902  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 903  * @mtd:        mtd info structure
 904  * @chip:       nand chip info structure
 905  * @buf:        buffer to store read data
 906  */
 907 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 908                                 uint8_t *buf)
 909 {
 910         int i, eccsize = chip->ecc.size;
 911         int eccbytes = chip->ecc.bytes;
 912         int eccsteps = chip->ecc.steps;
 913         uint8_t *p = buf;
 914         uint8_t *ecc_calc = chip->buffers->ecccalc;
 915         uint8_t *ecc_code = chip->buffers->ecccode;
 916         uint32_t *eccpos = chip->ecc.layout->eccpos;
 917
 918         chip->ecc.read_page_raw(mtd, chip, buf);
 919
 920         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 921                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 922
 923         for (i = 0; i < chip->ecc.total; i++)
 924                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 925
 926         eccsteps = chip->ecc.steps;
 927         p = buf;
 928
 929         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 930                 int stat;
 931
 932                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 933                 if (stat < 0)
 934                         mtd->ecc_stats.failed++;
 935                 else
 936                         mtd->ecc_stats.corrected += stat;
 937         }
 938         return 0;
 939 }
 940
 941 /**
 942  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 943  * @mtd:        mtd info structure
 944  * @chip:       nand chip info structure
 945  * @dataofs     offset of requested data within the page
 946  * @readlen     data length
 947  * @buf:        buffer to store read data
 948  */
 949 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 950 {
 951         int start_step, end_step, num_steps;
 952         uint32_t *eccpos = chip->ecc.layout->eccpos;
 953         uint8_t *p;
 954         int data_col_addr, i, gaps = 0;
 955         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 956         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 957
 958         /* Column address wihin the page aligned to ECC size (256bytes). */
 959         start_step = data_offs / chip->ecc.size;
 960         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 961         num_steps = end_step - start_step + 1;
 962
 963         /* Data size aligned to ECC ecc.size*/
 964         datafrag_len = num_steps * chip->ecc.size;
 965         eccfrag_len = num_steps * chip->ecc.bytes;
 966
 967         data_col_addr = start_step * chip->ecc.size;
 968         /* If we read not a page aligned data */
 969         if (data_col_addr != 0)
 970                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 971
 972         p = bufpoi + data_col_addr;
 973         chip->read_buf(mtd, p, datafrag_len);
 974
 975         /* Calculate  ECC */
 976         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 977                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 978
 979         /* The performance is faster if to position offsets
 980            according to ecc.pos. Let make sure here that
 981            there are no gaps in ecc positions */
 982         for (i = 0; i < eccfrag_len - 1; i++) {
 983                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 984                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 985                         gaps = 1;
 986                         break;
 987                 }
 988         }
 989         if (gaps) {
 990                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 991                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 992         } else {
 993                 /* send the command to read the particular ecc bytes */
 994                 /* take care about buswidth alignment in read_buf */
 995                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 996                 aligned_len = eccfrag_len;
 997                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 998                         aligned_len++;
 999                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1000                         aligned_len++;
1001
1002                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1003                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1004         }
1005
1006         for (i = 0; i < eccfrag_len; i++)
1007                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1008
1009         p = bufpoi + data_col_addr;
1010         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1011                 int stat;
1012
1013                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1014                 if (stat < 0)
1015                         mtd->ecc_stats.failed++;
1016                 else
1017                         mtd->ecc_stats.corrected += stat;
1018         }
1019         return 0;
1020 }
1021
1022 /**
1023  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1024  * @mtd:        mtd info structure
1025  * @chip:       nand chip info structure
1026  * @buf:        buffer to store read data
1027  *
1028  * Not for syndrome calculating ecc controllers which need a special oob layout
1029  */
1030 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1031                                 uint8_t *buf)
1032 {
1033         int i, eccsize = chip->ecc.size;
1034         int eccbytes = chip->ecc.bytes;
1035         int eccsteps = chip->ecc.steps;
1036         uint8_t *p = buf;
1037         uint8_t *ecc_calc = chip->buffers->ecccalc;
1038         uint8_t *ecc_code = chip->buffers->ecccode;
1039         uint32_t *eccpos = chip->ecc.layout->eccpos;
1040
1041         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1042                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1043                 chip->read_buf(mtd, p, eccsize);
1044                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1045         }
1046         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1047
1048         for (i = 0; i < chip->ecc.total; i++)
1049                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1050
1051         eccsteps = chip->ecc.steps;
1052         p = buf;
1053
1054         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1055                 int stat;
1056
1057                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1058                 if (stat == -1)
1059                         mtd->ecc_stats.failed++;
1060                 else
1061                         mtd->ecc_stats.corrected += stat;
1062         }
1063         return 0;
1064 }
1065
1066 /**
1067  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1068  * @mtd:        mtd info structure
1069  * @chip:       nand chip info structure
1070  * @buf:        buffer to store read data
1071  *
1072  * The hw generator calculates the error syndrome automatically. Therefor
1073  * we need a special oob layout and handling.
1074  */
1075 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1076                                    uint8_t *buf)
1077 {
1078         int i, eccsize = chip->ecc.size;
1079         int eccbytes = chip->ecc.bytes;
1080         int eccsteps = chip->ecc.steps;
1081         uint8_t *p = buf;
1082         uint8_t *oob = chip->oob_poi;
1083
1084         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1085                 int stat;
1086
1087                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1088                 chip->read_buf(mtd, p, eccsize);
1089
1090                 if (chip->ecc.prepad) {
1091                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1092                         oob += chip->ecc.prepad;
1093                 }
1094
1095                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1096                 chip->read_buf(mtd, oob, eccbytes);
1097                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1098
1099                 if (stat < 0)
1100                         mtd->ecc_stats.failed++;
1101                 else
1102                         mtd->ecc_stats.corrected += stat;
1103
1104                 oob += eccbytes;
1105
1106                 if (chip->ecc.postpad) {
1107                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1108                         oob += chip->ecc.postpad;
1109                 }
1110         }
1111
1112         /* Calculate remaining oob bytes */
1113         i = mtd->oobsize - (oob - chip->oob_poi);
1114         if (i)
1115                 chip->read_buf(mtd, oob, i);
1116
1117         return 0;
1118 }
1119
1120 /**
1121  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1122  * @chip:       nand chip structure
1123  * @oob:        oob destination address
1124  * @ops:        oob ops structure
1125  * @len:        size of oob to transfer
1126  */
1127 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1128                                   struct mtd_oob_ops *ops, size_t len)
1129 {
1130         switch(ops->mode) {
1131
1132         case MTD_OOB_PLACE:
1133         case MTD_OOB_RAW:
1134                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1135                 return oob + len;
1136
1137         case MTD_OOB_AUTO: {
1138                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1139                 uint32_t boffs = 0, roffs = ops->ooboffs;
1140                 size_t bytes = 0;
1141
1142                 for(; free->length && len; free++, len -= bytes) {
1143                         /* Read request not from offset 0 ? */
1144                         if (unlikely(roffs)) {
1145                                 if (roffs >= free->length) {
1146                                         roffs -= free->length;
1147                                         continue;
1148                                 }
1149                                 boffs = free->offset + roffs;
1150                                 bytes = min_t(size_t, len,
1151                                               (free->length - roffs));
1152                                 roffs = 0;
1153                         } else {
1154                                 bytes = min_t(size_t, len, free->length);
1155                                 boffs = free->offset;
1156                         }
1157                         memcpy(oob, chip->oob_poi + boffs, bytes);
1158                         oob += bytes;
1159                 }
1160                 return oob;
1161         }
1162         default:
1163                 BUG();
1164         }
1165         return NULL;
1166 }
1167
1168 /**
1169  * nand_do_read_ops - [Internal] Read data with ECC
1170  *
1171  * @mtd:        MTD device structure
1172  * @from:       offset to read from
1173  * @ops:        oob ops structure
1174  *
1175  * Internal function. Called with chip held.
1176  */
1177 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1178                             struct mtd_oob_ops *ops)
1179 {
1180         int chipnr, page, realpage, col, bytes, aligned;
1181         struct nand_chip *chip = mtd->priv;
1182         struct mtd_ecc_stats stats;
1183         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1184         int sndcmd = 1;
1185         int ret = 0;
1186         uint32_t readlen = ops->len;
1187         uint32_t oobreadlen = ops->ooblen;
1188         uint8_t *bufpoi, *oob, *buf;
1189
1190         stats = mtd->ecc_stats;
1191
1192         chipnr = (int)(from >> chip->chip_shift);
1193         chip->select_chip(mtd, chipnr);
1194
1195         realpage = (int)(from >> chip->page_shift);
1196         page = realpage & chip->pagemask;
1197
1198         col = (int)(from & (mtd->writesize - 1));
1199
1200         buf = ops->datbuf;
1201         oob = ops->oobbuf;
1202
1203         while(1) {
1204                 bytes = min(mtd->writesize - col, readlen);
1205                 aligned = (bytes == mtd->writesize);
1206
1207                 /* Is the current page in the buffer ? */
1208                 if (realpage != chip->pagebuf || oob) {
1209                         bufpoi = aligned ? buf : chip->buffers->databuf;
1210
1211                         if (likely(sndcmd)) {
1212                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1213                                 sndcmd = 0;
1214                         }
1215
1216                         /* Now read the page into the buffer */
1217                         if (unlikely(ops->mode == MTD_OOB_RAW))
1218                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1219                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1220                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1221                         else
1222                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1223                         if (ret < 0)
1224                                 break;
1225
1226                         /* Transfer not aligned data */
1227                         if (!aligned) {
1228                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1229                                         chip->pagebuf = realpage;
1230                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1231                         }
1232
1233                         buf += bytes;
1234
1235                         if (unlikely(oob)) {
1236                                 /* Raw mode does data:oob:data:oob */
1237                                 if (ops->mode != MTD_OOB_RAW) {
1238                                         int toread = min(oobreadlen,
1239                                                 chip->ecc.layout->oobavail);
1240                                         if (toread) {
1241                                                 oob = nand_transfer_oob(chip,
1242                                                         oob, ops, toread);
1243                                                 oobreadlen -= toread;
1244                                         }
1245                                 } else
1246                                         buf = nand_transfer_oob(chip,
1247                                                 buf, ops, mtd->oobsize);
1248                         }
1249
1250                         if (!(chip->options & NAND_NO_READRDY)) {
1251                                 /*
1252                                  * Apply delay or wait for ready/busy pin. Do
1253                                  * this before the AUTOINCR check, so no
1254                                  * problems arise if a chip which does auto
1255                                  * increment is marked as NOAUTOINCR by the
1256                                  * board driver.
1257                                  */
1258                                 if (!chip->dev_ready)
1259                                         udelay(chip->chip_delay);
1260                                 else
1261                                         nand_wait_ready(mtd);
1262                         }
1263                 } else {
1264                         memcpy(buf, chip->buffers->databuf + col, bytes);
1265                         buf += bytes;
1266                 }
1267
1268                 readlen -= bytes;
1269
1270                 if (!readlen)
1271                         break;
1272
1273                 /* For subsequent reads align to page boundary. */
1274                 col = 0;
1275                 /* Increment page address */
1276                 realpage++;
1277
1278                 page = realpage & chip->pagemask;
1279                 /* Check, if we cross a chip boundary */
1280                 if (!page) {
1281                         chipnr++;
1282                         chip->select_chip(mtd, -1);
1283                         chip->select_chip(mtd, chipnr);
1284                 }
1285
1286                 /* Check, if the chip supports auto page increment
1287                  * or if we have hit a block boundary.
1288                  */
1289                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1290                         sndcmd = 1;
1291         }
1292
1293         ops->retlen = ops->len - (size_t) readlen;
1294         if (oob)
1295                 ops->oobretlen = ops->ooblen - oobreadlen;
1296
1297         if (ret)
1298                 return ret;
1299
1300         if (mtd->ecc_stats.failed - stats.failed)
1301                 return -EBADMSG;
1302
1303         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1304 }
1305
1306 /**
1307  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1308  * @mtd:        MTD device structure
1309  * @from:       offset to read from
1310  * @len:        number of bytes to read
1311  * @retlen:     pointer to variable to store the number of read bytes
1312  * @buf:        the databuffer to put data
1313  *
1314  * Get hold of the chip and call nand_do_read
1315  */
1316 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1317                      size_t *retlen, uint8_t *buf)
1318 {
1319         struct nand_chip *chip = mtd->priv;
1320         int ret;
1321
1322         /* Do not allow reads past end of device */
1323         if ((from + len) > mtd->size)
1324                 return -EINVAL;
1325         if (!len)
1326                 return 0;
1327
1328         nand_get_device(chip, mtd, FL_READING);
1329
1330         chip->ops.len = len;
1331         chip->ops.datbuf = buf;
1332         chip->ops.oobbuf = NULL;
1333
1334         ret = nand_do_read_ops(mtd, from, &chip->ops);
1335
1336         *retlen = chip->ops.retlen;
1337
1338         nand_release_device(mtd);
1339
1340         return ret;
1341 }
1342
1343 /**
1344  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1345  * @mtd:        mtd info structure
1346  * @chip:       nand chip info structure
1347  * @page:       page number to read
1348  * @sndcmd:     flag whether to issue read command or not
1349  */
1350 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1351                              int page, int sndcmd)
1352 {
1353         if (sndcmd) {
1354                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1355                 sndcmd = 0;
1356         }
1357         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1358         return sndcmd;
1359 }
1360
1361 /**
1362  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1363  *                          with syndromes
1364  * @mtd:        mtd info structure
1365  * @chip:       nand chip info structure
1366  * @page:       page number to read
1367  * @sndcmd:     flag whether to issue read command or not
1368  */
1369 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1370                                   int page, int sndcmd)
1371 {
1372         uint8_t *buf = chip->oob_poi;
1373         int length = mtd->oobsize;
1374         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1375         int eccsize = chip->ecc.size;
1376         uint8_t *bufpoi = buf;
1377         int i, toread, sndrnd = 0, pos;
1378
1379         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1380         for (i = 0; i < chip->ecc.steps; i++) {
1381                 if (sndrnd) {
1382                         pos = eccsize + i * (eccsize + chunk);
1383                         if (mtd->writesize > 512)
1384                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1385                         else
1386                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1387                 } else
1388                         sndrnd = 1;
1389                 toread = min_t(int, length, chunk);
1390                 chip->read_buf(mtd, bufpoi, toread);
1391                 bufpoi += toread;
1392                 length -= toread;
1393         }
1394         if (length > 0)
1395                 chip->read_buf(mtd, bufpoi, length);
1396
1397         return 1;
1398 }
1399
1400 /**
1401  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1402  * @mtd:        mtd info structure
1403  * @chip:       nand chip info structure
1404  * @page:       page number to write
1405  */
1406 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1407                               int page)
1408 {
1409         int status = 0;
1410         const uint8_t *buf = chip->oob_poi;
1411         int length = mtd->oobsize;
1412
1413         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1414         chip->write_buf(mtd, buf, length);
1415         /* Send command to program the OOB data */
1416         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1417
1418         status = chip->waitfunc(mtd, chip);
1419
1420         return status & NAND_STATUS_FAIL ? -EIO : 0;
1421 }
1422
1423 /**
1424  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1425  *                           with syndrome - only for large page flash !
1426  * @mtd:        mtd info structure
1427  * @chip:       nand chip info structure
1428  * @page:       page number to write
1429  */
1430 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1431                                    struct nand_chip *chip, int page)
1432 {
1433         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1434         int eccsize = chip->ecc.size, length = mtd->oobsize;
1435         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1436         const uint8_t *bufpoi = chip->oob_poi;
1437
1438         /*
1439          * data-ecc-data-ecc ... ecc-oob
1440          * or
1441          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1442          */
1443         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1444                 pos = steps * (eccsize + chunk);
1445                 steps = 0;
1446         } else
1447                 pos = eccsize;
1448
1449         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1450         for (i = 0; i < steps; i++) {
1451                 if (sndcmd) {
1452                         if (mtd->writesize <= 512) {
1453                                 uint32_t fill = 0xFFFFFFFF;
1454
1455                                 len = eccsize;
1456                                 while (len > 0) {
1457                                         int num = min_t(int, len, 4);
1458                                         chip->write_buf(mtd, (uint8_t *)&fill,
1459                                                         num);
1460                                         len -= num;
1461                                 }
1462                         } else {
1463                                 pos = eccsize + i * (eccsize + chunk);
1464                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1465                         }
1466                 } else
1467                         sndcmd = 1;
1468                 len = min_t(int, length, chunk);
1469                 chip->write_buf(mtd, bufpoi, len);
1470                 bufpoi += len;
1471                 length -= len;
1472         }
1473         if (length > 0)
1474                 chip->write_buf(mtd, bufpoi, length);
1475
1476         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1477         status = chip->waitfunc(mtd, chip);
1478
1479         return status & NAND_STATUS_FAIL ? -EIO : 0;
1480 }
1481
1482 /**
1483  * nand_do_read_oob - [Intern] NAND read out-of-band
1484  * @mtd:        MTD device structure
1485  * @from:       offset to read from
1486  * @ops:        oob operations description structure
1487  *
1488  * NAND read out-of-band data from the spare area
1489  */
1490 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1491                             struct mtd_oob_ops *ops)
1492 {
1493         int page, realpage, chipnr, sndcmd = 1;
1494         struct nand_chip *chip = mtd->priv;
1495         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1496         int readlen = ops->ooblen;
1497         int len;
1498         uint8_t *buf = ops->oobbuf;
1499
1500         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1501                   (unsigned long long)from, readlen);
1502
1503         if (ops->mode == MTD_OOB_AUTO)
1504                 len = chip->ecc.layout->oobavail;
1505         else
1506                 len = mtd->oobsize;
1507
1508         if (unlikely(ops->ooboffs >= len)) {
1509                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1510                           "Attempt to start read outside oob\n");
1511                 return -EINVAL;
1512         }
1513
1514         /* Do not allow reads past end of device */
1515         if (unlikely(from >= mtd->size ||
1516                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1517                                         (from >> chip->page_shift)) * len)) {
1518                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1519                           "Attempt read beyond end of device\n");
1520                 return -EINVAL;
1521         }
1522
1523         chipnr = (int)(from >> chip->chip_shift);
1524         chip->select_chip(mtd, chipnr);
1525
1526         /* Shift to get page */
1527         realpage = (int)(from >> chip->page_shift);
1528         page = realpage & chip->pagemask;
1529
1530         while(1) {
1531                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1532
1533                 len = min(len, readlen);
1534                 buf = nand_transfer_oob(chip, buf, ops, len);
1535
1536                 if (!(chip->options & NAND_NO_READRDY)) {
1537                         /*
1538                          * Apply delay or wait for ready/busy pin. Do this
1539                          * before the AUTOINCR check, so no problems arise if a
1540                          * chip which does auto increment is marked as
1541                          * NOAUTOINCR by the board driver.
1542                          */
1543                         if (!chip->dev_ready)
1544                                 udelay(chip->chip_delay);
1545                         else
1546                                 nand_wait_ready(mtd);
1547                 }
1548
1549                 readlen -= len;
1550                 if (!readlen)
1551                         break;
1552
1553                 /* Increment page address */
1554                 realpage++;
1555
1556                 page = realpage & chip->pagemask;
1557                 /* Check, if we cross a chip boundary */
1558                 if (!page) {
1559                         chipnr++;
1560                         chip->select_chip(mtd, -1);
1561                         chip->select_chip(mtd, chipnr);
1562                 }
1563
1564                 /* Check, if the chip supports auto page increment
1565                  * or if we have hit a block boundary.
1566                  */
1567                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1568                         sndcmd = 1;
1569         }
1570
1571         ops->oobretlen = ops->ooblen;
1572         return 0;
1573 }
1574
1575 /**
1576  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1577  * @mtd:        MTD device structure
1578  * @from:       offset to read from
1579  * @ops:        oob operation description structure
1580  *
1581  * NAND read data and/or out-of-band data
1582  */
1583 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1584                          struct mtd_oob_ops *ops)
1585 {
1586         struct nand_chip *chip = mtd->priv;
1587         int ret = -ENOTSUPP;
1588
1589         ops->retlen = 0;
1590
1591         /* Do not allow reads past end of device */
1592         if (ops->datbuf && (from + ops->len) > mtd->size) {
1593                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1594                           "Attempt read beyond end of device\n");
1595                 return -EINVAL;
1596         }
1597
1598         nand_get_device(chip, mtd, FL_READING);
1599
1600         switch(ops->mode) {
1601         case MTD_OOB_PLACE:
1602         case MTD_OOB_AUTO:
1603         case MTD_OOB_RAW:
1604                 break;
1605
1606         default:
1607                 goto out;
1608         }
1609
1610         if (!ops->datbuf)
1611                 ret = nand_do_read_oob(mtd, from, ops);
1612         else
1613                 ret = nand_do_read_ops(mtd, from, ops);
1614
1615  out:
1616         nand_release_device(mtd);
1617         return ret;
1618 }
1619
1620
1621 /**
1622  * nand_write_page_raw - [Intern] raw page write function
1623  * @mtd:        mtd info structure
1624  * @chip:       nand chip info structure
1625  * @buf:        data buffer
1626  */
1627 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1628                                 const uint8_t *buf)
1629 {
1630         chip->write_buf(mtd, buf, mtd->writesize);
1631         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1632 }
1633
1634 /**
1635  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1636  * @mtd:        mtd info structure
1637  * @chip:       nand chip info structure
1638  * @buf:        data buffer
1639  */
1640 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1641                                   const uint8_t *buf)
1642 {
1643         int i, eccsize = chip->ecc.size;
1644         int eccbytes = chip->ecc.bytes;
1645         int eccsteps = chip->ecc.steps;
1646         uint8_t *ecc_calc = chip->buffers->ecccalc;
1647         const uint8_t *p = buf;
1648         uint32_t *eccpos = chip->ecc.layout->eccpos;
1649
1650         /* Software ecc calculation */
1651         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1652                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1653
1654         for (i = 0; i < chip->ecc.total; i++)
1655                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1656
1657         chip->ecc.write_page_raw(mtd, chip, buf);
1658 }
1659
1660 /**
1661  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1662  * @mtd:        mtd info structure
1663  * @chip:       nand chip info structure
1664  * @buf:        data buffer
1665  */
1666 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1667                                   const uint8_t *buf)
1668 {
1669         int i, eccsize = chip->ecc.size;
1670         int eccbytes = chip->ecc.bytes;
1671         int eccsteps = chip->ecc.steps;
1672         uint8_t *ecc_calc = chip->buffers->ecccalc;
1673         const uint8_t *p = buf;
1674         uint32_t *eccpos = chip->ecc.layout->eccpos;
1675
1676         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1677                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1678                 chip->write_buf(mtd, p, eccsize);
1679                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1680         }
1681
1682         for (i = 0; i < chip->ecc.total; i++)
1683                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1684
1685         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1686 }
1687
1688 /**
1689  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1690  * @mtd:        mtd info structure
1691  * @chip:       nand chip info structure
1692  * @buf:        data buffer
1693  *
1694  * The hw generator calculates the error syndrome automatically. Therefor
1695  * we need a special oob layout and handling.
1696  */
1697 static void nand_write_page_syndrome(struct mtd_info *mtd,
1698                                     struct nand_chip *chip, const uint8_t *buf)
1699 {
1700         int i, eccsize = chip->ecc.size;
1701         int eccbytes = chip->ecc.bytes;
1702         int eccsteps = chip->ecc.steps;
1703         const uint8_t *p = buf;
1704         uint8_t *oob = chip->oob_poi;
1705
1706         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1707
1708                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1709                 chip->write_buf(mtd, p, eccsize);
1710
1711                 if (chip->ecc.prepad) {
1712                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1713                         oob += chip->ecc.prepad;
1714                 }
1715
1716                 chip->ecc.calculate(mtd, p, oob);
1717                 chip->write_buf(mtd, oob, eccbytes);
1718                 oob += eccbytes;
1719
1720                 if (chip->ecc.postpad) {
1721                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1722                         oob += chip->ecc.postpad;
1723                 }
1724         }
1725
1726         /* Calculate remaining oob bytes */
1727         i = mtd->oobsize - (oob - chip->oob_poi);
1728         if (i)
1729                 chip->write_buf(mtd, oob, i);
1730 }
1731
1732 /**
1733  * nand_write_page - [REPLACEABLE] write one page
1734  * @mtd:        MTD device structure
1735  * @chip:       NAND chip descriptor
1736  * @buf:        the data to write
1737  * @page:       page number to write
1738  * @cached:     cached programming
1739  * @raw:        use _raw version of write_page
1740  */
1741 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1742                            const uint8_t *buf, int page, int cached, int raw)
1743 {
1744         int status;
1745
1746         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1747
1748         if (unlikely(raw))
1749                 chip->ecc.write_page_raw(mtd, chip, buf);
1750         else
1751                 chip->ecc.write_page(mtd, chip, buf);
1752
1753         /*
1754          * Cached progamming disabled for now, Not sure if its worth the
1755          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1756          */
1757         cached = 0;
1758
1759         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1760
1761                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1762                 status = chip->waitfunc(mtd, chip);
1763                 /*
1764                  * See if operation failed and additional status checks are
1765                  * available
1766                  */
1767                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1768                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1769                                                page);
1770
1771                 if (status & NAND_STATUS_FAIL)
1772                         return -EIO;
1773         } else {
1774                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1775                 status = chip->waitfunc(mtd, chip);
1776         }
1777
1778 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1779         /* Send command to read back the data */
1780         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1781
1782         if (chip->verify_buf(mtd, buf, mtd->writesize))
1783                 return -EIO;
1784 #endif
1785         return 0;
1786 }
1787
1788 /**
1789  * nand_fill_oob - [Internal] Transfer client buffer to oob
1790  * @chip:       nand chip structure
1791  * @oob:        oob data buffer
1792  * @ops:        oob ops structure
1793  */
1794 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1795                                   struct mtd_oob_ops *ops)
1796 {
1797         size_t len = ops->ooblen;
1798
1799         switch(ops->mode) {
1800
1801         case MTD_OOB_PLACE:
1802         case MTD_OOB_RAW:
1803                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1804                 return oob + len;
1805
1806         case MTD_OOB_AUTO: {
1807                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1808                 uint32_t boffs = 0, woffs = ops->ooboffs;
1809                 size_t bytes = 0;
1810
1811                 for(; free->length && len; free++, len -= bytes) {
1812                         /* Write request not from offset 0 ? */
1813                         if (unlikely(woffs)) {
1814                                 if (woffs >= free->length) {
1815                                         woffs -= free->length;
1816                                         continue;
1817                                 }
1818                                 boffs = free->offset + woffs;
1819                                 bytes = min_t(size_t, len,
1820                                               (free->length - woffs));
1821                                 woffs = 0;
1822                         } else {
1823                                 bytes = min_t(size_t, len, free->length);
1824                                 boffs = free->offset;
1825                         }
1826                         memcpy(chip->oob_poi + boffs, oob, bytes);
1827                         oob += bytes;
1828                 }
1829                 return oob;
1830         }
1831         default:
1832                 BUG();
1833         }
1834         return NULL;
1835 }
1836
1837 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1838
1839 /**
1840  * nand_do_write_ops - [Internal] NAND write with ECC
1841  * @mtd:        MTD device structure
1842  * @to:         offset to write to
1843  * @ops:        oob operations description structure
1844  *
1845  * NAND write with ECC
1846  */
1847 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1848                              struct mtd_oob_ops *ops)
1849 {
1850         int chipnr, realpage, page, blockmask, column;
1851         struct nand_chip *chip = mtd->priv;
1852         uint32_t writelen = ops->len;
1853         uint8_t *oob = ops->oobbuf;
1854         uint8_t *buf = ops->datbuf;
1855         int ret, subpage;
1856
1857         ops->retlen = 0;
1858         if (!writelen)
1859                 return 0;
1860
1861         /* reject writes, which are not page aligned */
1862         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1863                 printk(KERN_NOTICE "nand_write: "
1864                        "Attempt to write not page aligned data\n");
1865                 return -EINVAL;
1866         }
1867
1868         column = to & (mtd->writesize - 1);
1869         subpage = column || (writelen & (mtd->writesize - 1));
1870
1871         if (subpage && oob)
1872                 return -EINVAL;
1873
1874         chipnr = (int)(to >> chip->chip_shift);
1875         chip->select_chip(mtd, chipnr);
1876
1877         /* Check, if it is write protected */
1878         if (nand_check_wp(mtd)) {
1879                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1880                 return -EIO;
1881         }
1882
1883         realpage = (int)(to >> chip->page_shift);
1884         page = realpage & chip->pagemask;
1885         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1886
1887         /* Invalidate the page cache, when we write to the cached page */
1888         if (to <= (chip->pagebuf << chip->page_shift) &&
1889             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1890                 chip->pagebuf = -1;
1891
1892         /* If we're not given explicit OOB data, let it be 0xFF */
1893         if (likely(!oob))
1894                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1895
1896         while(1) {
1897                 int bytes = mtd->writesize;
1898                 int cached = writelen > bytes && page != blockmask;
1899                 uint8_t *wbuf = buf;
1900
1901                 /* Partial page write ? */
1902                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1903                         cached = 0;
1904                         bytes = min_t(int, bytes - column, (int) writelen);
1905                         chip->pagebuf = -1;
1906                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1907                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1908                         wbuf = chip->buffers->databuf;
1909                 }
1910
1911                 if (unlikely(oob))
1912                         oob = nand_fill_oob(chip, oob, ops);
1913
1914                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1915                                        (ops->mode == MTD_OOB_RAW));
1916                 if (ret)
1917                         break;
1918
1919                 writelen -= bytes;
1920                 if (!writelen)
1921                         break;
1922
1923                 column = 0;
1924                 buf += bytes;
1925                 realpage++;
1926
1927                 page = realpage & chip->pagemask;
1928                 /* Check, if we cross a chip boundary */
1929                 if (!page) {
1930                         chipnr++;
1931                         chip->select_chip(mtd, -1);
1932                         chip->select_chip(mtd, chipnr);
1933                 }
1934         }
1935
1936         ops->retlen = ops->len - writelen;
1937         if (unlikely(oob))
1938                 ops->oobretlen = ops->ooblen;
1939         return ret;
1940 }
1941
1942 /**
1943  * nand_write - [MTD Interface] NAND write with ECC
1944  * @mtd:        MTD device structure
1945  * @to:         offset to write to
1946  * @len:        number of bytes to write
1947  * @retlen:     pointer to variable to store the number of written bytes
1948  * @buf:        the data to write
1949  *
1950  * NAND write with ECC
1951  */
1952 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1953                           size_t *retlen, const uint8_t *buf)
1954 {
1955         struct nand_chip *chip = mtd->priv;
1956         int ret;
1957
1958         /* Do not allow reads past end of device */
1959         if ((to + len) > mtd->size)
1960                 return -EINVAL;
1961         if (!len)
1962                 return 0;
1963
1964         nand_get_device(chip, mtd, FL_WRITING);
1965
1966         chip->ops.len = len;
1967         chip->ops.datbuf = (uint8_t *)buf;
1968         chip->ops.oobbuf = NULL;
1969
1970         ret = nand_do_write_ops(mtd, to, &chip->ops);
1971
1972         *retlen = chip->ops.retlen;
1973
1974         nand_release_device(mtd);
1975
1976         return ret;
1977 }
1978
1979 /**
1980  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1981  * @mtd:        MTD device structure
1982  * @to:         offset to write to
1983  * @ops:        oob operation description structure
1984  *
1985  * NAND write out-of-band
1986  */
1987 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1988                              struct mtd_oob_ops *ops)
1989 {
1990         int chipnr, page, status, len;
1991         struct nand_chip *chip = mtd->priv;
1992
1993         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1994                   (unsigned int)to, (int)ops->ooblen);
1995
1996         if (ops->mode == MTD_OOB_AUTO)
1997                 len = chip->ecc.layout->oobavail;
1998         else
1999                 len = mtd->oobsize;
2000
2001         /* Do not allow write past end of page */
2002         if ((ops->ooboffs + ops->ooblen) > len) {
2003                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2004                           "Attempt to write past end of page\n");
2005                 return -EINVAL;
2006         }
2007
2008         if (unlikely(ops->ooboffs >= len)) {
2009                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2010                           "Attempt to start write outside oob\n");
2011                 return -EINVAL;
2012         }
2013
2014         /* Do not allow reads past end of device */
2015         if (unlikely(to >= mtd->size ||
2016                      ops->ooboffs + ops->ooblen >
2017                         ((mtd->size >> chip->page_shift) -
2018                          (to >> chip->page_shift)) * len)) {
2019                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2020                           "Attempt write beyond end of device\n");
2021                 return -EINVAL;
2022         }
2023
2024         chipnr = (int)(to >> chip->chip_shift);
2025         chip->select_chip(mtd, chipnr);
2026
2027         /* Shift to get page */
2028         page = (int)(to >> chip->page_shift);
2029
2030         /*
2031          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2032          * of my DiskOnChip 2000 test units) will clear the whole data page too
2033          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2034          * it in the doc2000 driver in August 1999.  dwmw2.
2035          */
2036         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2037
2038         /* Check, if it is write protected */
2039         if (nand_check_wp(mtd))
2040                 return -EROFS;
2041
2042         /* Invalidate the page cache, if we write to the cached page */
2043         if (page == chip->pagebuf)
2044                 chip->pagebuf = -1;
2045
2046         memset(chip->oob_poi, 0xff, mtd->oobsize);
2047         nand_fill_oob(chip, ops->oobbuf, ops);
2048         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2049         memset(chip->oob_poi, 0xff, mtd->oobsize);
2050
2051         if (status)
2052                 return status;
2053
2054         ops->oobretlen = ops->ooblen;
2055
2056         return 0;
2057 }
2058
2059 /**
2060  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2061  * @mtd:        MTD device structure
2062  * @to:         offset to write to
2063  * @ops:        oob operation description structure
2064  */
2065 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2066                           struct mtd_oob_ops *ops)
2067 {
2068         struct nand_chip *chip = mtd->priv;
2069         int ret = -ENOTSUPP;
2070
2071         ops->retlen = 0;
2072
2073         /* Do not allow writes past end of device */
2074         if (ops->datbuf && (to + ops->len) > mtd->size) {
2075                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2076                           "Attempt read beyond end of device\n");
2077                 return -EINVAL;
2078         }
2079
2080         nand_get_device(chip, mtd, FL_WRITING);
2081
2082         switch(ops->mode) {
2083         case MTD_OOB_PLACE:
2084         case MTD_OOB_AUTO:
2085         case MTD_OOB_RAW:
2086                 break;
2087
2088         default:
2089                 goto out;
2090         }
2091
2092         if (!ops->datbuf)
2093                 ret = nand_do_write_oob(mtd, to, ops);
2094         else
2095                 ret = nand_do_write_ops(mtd, to, ops);
2096
2097  out:
2098         nand_release_device(mtd);
2099         return ret;
2100 }
2101
2102 /**
2103  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2104  * @mtd:        MTD device structure
2105  * @page:       the page address of the block which will be erased
2106  *
2107  * Standard erase command for NAND chips
2108  */
2109 static void single_erase_cmd(struct mtd_info *mtd, int page)
2110 {
2111         struct nand_chip *chip = mtd->priv;
2112         /* Send commands to erase a block */
2113         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2114         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2115 }
2116
2117 /**
2118  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2119  * @mtd:        MTD device structure
2120  * @page:       the page address of the block which will be erased
2121  *
2122  * AND multi block erase command function
2123  * Erase 4 consecutive blocks
2124  */
2125 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2126 {
2127         struct nand_chip *chip = mtd->priv;
2128         /* Send commands to erase a block */
2129         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2130         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2131         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2132         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2133         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2134 }
2135
2136 /**
2137  * nand_erase - [MTD Interface] erase block(s)
2138  * @mtd:        MTD device structure
2139  * @instr:      erase instruction
2140  *
2141  * Erase one ore more blocks
2142  */
2143 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2144 {
2145         return nand_erase_nand(mtd, instr, 0);
2146 }
2147
2148 #define BBT_PAGE_MASK   0xffffff3f
2149 /**
2150  * nand_erase_nand - [Internal] erase block(s)
2151  * @mtd:        MTD device structure
2152  * @instr:      erase instruction
2153  * @allowbbt:   allow erasing the bbt area
2154  *
2155  * Erase one ore more blocks
2156  */
2157 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2158                     int allowbbt)
2159 {
2160         int page, len, status, pages_per_block, ret, chipnr;
2161         struct nand_chip *chip = mtd->priv;
2162         int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
2163         unsigned int bbt_masked_page = 0xffffffff;
2164
2165         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2166                   (unsigned int) instr->addr, (unsigned int) instr->len);
2167
2168         /* Start address must align on block boundary */
2169         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2170                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2171                 return -EINVAL;
2172         }
2173
2174         /* Length must align on block boundary */
2175         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2176                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2177                           "nand_erase: Length not block aligned\n");
2178                 return -EINVAL;
2179         }
2180
2181         /* Do not allow erase past end of device */
2182         if ((instr->len + instr->addr) > mtd->size) {
2183                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2184                           "nand_erase: Erase past end of device\n");
2185                 return -EINVAL;
2186         }
2187
2188         instr->fail_addr = 0xffffffff;
2189
2190         /* Grab the lock and see if the device is available */
2191         nand_get_device(chip, mtd, FL_ERASING);
2192
2193         /* Shift to get first page */
2194         page = (int)(instr->addr >> chip->page_shift);
2195         chipnr = (int)(instr->addr >> chip->chip_shift);
2196
2197         /* Calculate pages in each block */
2198         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2199
2200         /* Select the NAND device */
2201         chip->select_chip(mtd, chipnr);
2202
2203         /* Check, if it is write protected */
2204         if (nand_check_wp(mtd)) {
2205                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2206                           "nand_erase: Device is write protected!!!\n");
2207                 instr->state = MTD_ERASE_FAILED;
2208                 goto erase_exit;
2209         }
2210
2211         /*
2212          * If BBT requires refresh, set the BBT page mask to see if the BBT
2213          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2214          * can not be matched. This is also done when the bbt is actually
2215          * erased to avoid recusrsive updates
2216          */
2217         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2218                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2219
2220         /* Loop through the pages */
2221         len = instr->len;
2222
2223         instr->state = MTD_ERASING;
2224
2225         while (len) {
2226                 /*
2227                  * heck if we have a bad block, we do not erase bad blocks !
2228                  */
2229                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2230                                         chip->page_shift, 0, allowbbt)) {
2231                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2232                                "bad block at page 0x%08x\n", page);
2233                         instr->state = MTD_ERASE_FAILED;
2234                         goto erase_exit;
2235                 }
2236
2237                 /*
2238                  * Invalidate the page cache, if we erase the block which
2239                  * contains the current cached page
2240                  */
2241                 if (page <= chip->pagebuf && chip->pagebuf <
2242                     (page + pages_per_block))
2243                         chip->pagebuf = -1;
2244
2245                 chip->erase_cmd(mtd, page & chip->pagemask);
2246
2247                 status = chip->waitfunc(mtd, chip);
2248
2249                 /*
2250                  * See if operation failed and additional status checks are
2251                  * available
2252                  */
2253                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2254                         status = chip->errstat(mtd, chip, FL_ERASING,
2255                                                status, page);
2256
2257                 /* See if block erase succeeded */
2258                 if (status & NAND_STATUS_FAIL) {
2259                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2260                                   "Failed erase, page 0x%08x\n", page);
2261                         instr->state = MTD_ERASE_FAILED;
2262                         instr->fail_addr = (page << chip->page_shift);
2263                         goto erase_exit;
2264                 }
2265
2266                 /*
2267                  * If BBT requires refresh, set the BBT rewrite flag to the
2268                  * page being erased
2269                  */
2270                 if (bbt_masked_page != 0xffffffff &&
2271                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2272                             rewrite_bbt[chipnr] = (page << chip->page_shift);
2273
2274                 /* Increment page address and decrement length */
2275                 len -= (1 << chip->phys_erase_shift);
2276                 page += pages_per_block;
2277
2278                 /* Check, if we cross a chip boundary */
2279                 if (len && !(page & chip->pagemask)) {
2280                         chipnr++;
2281                         chip->select_chip(mtd, -1);
2282                         chip->select_chip(mtd, chipnr);
2283
2284                         /*
2285                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2286                          * page mask to see if this BBT should be rewritten
2287                          */
2288                         if (bbt_masked_page != 0xffffffff &&
2289                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2290                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2291                                         BBT_PAGE_MASK;
2292                 }
2293         }
2294         instr->state = MTD_ERASE_DONE;
2295
2296  erase_exit:
2297
2298         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2299
2300         /* Deselect and wake up anyone waiting on the device */
2301         nand_release_device(mtd);
2302
2303         /* Do call back function */
2304         if (!ret)
2305                 mtd_erase_callback(instr);
2306
2307         /*
2308          * If BBT requires refresh and erase was successful, rewrite any
2309          * selected bad block tables
2310          */
2311         if (bbt_masked_page == 0xffffffff || ret)
2312                 return ret;
2313
2314         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2315                 if (!rewrite_bbt[chipnr])
2316                         continue;
2317                 /* update the BBT for chip */
2318                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2319                           "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2320                           chip->bbt_td->pages[chipnr]);
2321                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2322         }
2323
2324         /* Return more or less happy */
2325         return ret;
2326 }
2327
2328 /**
2329  * nand_sync - [MTD Interface] sync
2330  * @mtd:        MTD device structure
2331  *
2332  * Sync is actually a wait for chip ready function
2333  */
2334 static void nand_sync(struct mtd_info *mtd)
2335 {
2336         struct nand_chip *chip = mtd->priv;
2337
2338         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2339
2340         /* Grab the lock and see if the device is available */
2341         nand_get_device(chip, mtd, FL_SYNCING);
2342         /* Release it and go back */
2343         nand_release_device(mtd);
2344 }
2345
2346 /**
2347  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2348  * @mtd:        MTD device structure
2349  * @offs:       offset relative to mtd start
2350  */
2351 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2352 {
2353         /* Check for invalid offset */
2354         if (offs > mtd->size)
2355                 return -EINVAL;
2356
2357         return nand_block_checkbad(mtd, offs, 1, 0);
2358 }
2359
2360 /**
2361  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2362  * @mtd:        MTD device structure
2363  * @ofs:        offset relative to mtd start
2364  */
2365 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2366 {
2367         struct nand_chip *chip = mtd->priv;
2368         int ret;
2369
2370         if ((ret = nand_block_isbad(mtd, ofs))) {
2371                 /* If it was bad already, return success and do nothing. */
2372                 if (ret > 0)
2373                         return 0;
2374                 return ret;
2375         }
2376
2377         return chip->block_markbad(mtd, ofs);
2378 }
2379
2380 /**
2381  * nand_suspend - [MTD Interface] Suspend the NAND flash
2382  * @mtd:        MTD device structure
2383  */
2384 static int nand_suspend(struct mtd_info *mtd)
2385 {
2386         struct nand_chip *chip = mtd->priv;
2387
2388         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2389 }
2390
2391 /**
2392  * nand_resume - [MTD Interface] Resume the NAND flash
2393  * @mtd:        MTD device structure
2394  */
2395 static void nand_resume(struct mtd_info *mtd)
2396 {
2397         struct nand_chip *chip = mtd->priv;
2398
2399         if (chip->state == FL_PM_SUSPENDED)
2400                 nand_release_device(mtd);
2401         else
2402                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2403                        "in suspended state\n");
2404 }
2405
2406 /*
2407  * Set default functions
2408  */
2409 static void nand_set_defaults(struct nand_chip *chip, int busw)
2410 {
2411         /* check for proper chip_delay setup, set 20us if not */
2412         if (!chip->chip_delay)
2413                 chip->chip_delay = 20;
2414
2415         /* check, if a user supplied command function given */
2416         if (chip->cmdfunc == NULL)
2417                 chip->cmdfunc = nand_command;
2418
2419         /* check, if a user supplied wait function given */
2420         if (chip->waitfunc == NULL)
2421                 chip->waitfunc = nand_wait;
2422
2423         if (!chip->select_chip)
2424                 chip->select_chip = nand_select_chip;
2425         if (!chip->read_byte)
2426                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2427         if (!chip->read_word)
2428                 chip->read_word = nand_read_word;
2429         if (!chip->block_bad)
2430                 chip->block_bad = nand_block_bad;
2431         if (!chip->block_markbad)
2432                 chip->block_markbad = nand_default_block_markbad;
2433         if (!chip->write_buf)
2434                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2435         if (!chip->read_buf)
2436                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2437         if (!chip->verify_buf)
2438                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2439         if (!chip->scan_bbt)
2440                 chip->scan_bbt = nand_default_bbt;
2441
2442         if (!chip->controller) {
2443                 chip->controller = &chip->hwcontrol;
2444
2445                 /* XXX U-BOOT XXX */
2446 #if 0
2447                 spin_lock_init(&chip->controller->lock);
2448                 init_waitqueue_head(&chip->controller->wq);
2449 #endif
2450         }
2451
2452 }
2453
2454 /*
2455  * Get the flash and manufacturer id and lookup if the type is supported
2456  */
2457 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2458                                                   struct nand_chip *chip,
2459                                                   int busw, int *maf_id)
2460 {
2461         struct nand_flash_dev *type = NULL;
2462         int i, dev_id, maf_idx;
2463         int tmp_id, tmp_manf;
2464
2465         /* Select the device */
2466         chip->select_chip(mtd, 0);
2467
2468         /*
2469          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2470          * after power-up
2471          */
2472         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2473
2474         /* Send the command for reading device ID */
2475         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2476
2477         /* Read manufacturer and device IDs */
2478         *maf_id = chip->read_byte(mtd);
2479         dev_id = chip->read_byte(mtd);
2480
2481         /* Try again to make sure, as some systems the bus-hold or other
2482          * interface concerns can cause random data which looks like a
2483          * possibly credible NAND flash to appear. If the two results do
2484          * not match, ignore the device completely.
2485          */
2486
2487         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2488
2489         /* Read manufacturer and device IDs */
2490
2491         tmp_manf = chip->read_byte(mtd);
2492         tmp_id = chip->read_byte(mtd);
2493
2494         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2495                 printk(KERN_INFO "%s: second ID read did not match "
2496                        "%02x,%02x against %02x,%02x\n", __func__,
2497                        *maf_id, dev_id, tmp_manf, tmp_id);
2498                 return ERR_PTR(-ENODEV);
2499         }
2500
2501         /* Lookup the flash id */
2502         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2503                 if (dev_id == nand_flash_ids[i].id) {
2504                         type =  &nand_flash_ids[i];
2505                         break;
2506                 }
2507         }
2508
2509         if (!type)
2510                 return ERR_PTR(-ENODEV);
2511
2512         if (!mtd->name)
2513                 mtd->name = type->name;
2514
2515         chip->chipsize = type->chipsize << 20;
2516
2517         /* Newer devices have all the information in additional id bytes */
2518         if (!type->pagesize) {
2519                 int extid;
2520                 /* The 3rd id byte holds MLC / multichip data */
2521                 chip->cellinfo = chip->read_byte(mtd);
2522                 /* The 4th id byte is the important one */
2523                 extid = chip->read_byte(mtd);
2524                 /* Calc pagesize */
2525                 mtd->writesize = 1024 << (extid & 0x3);
2526                 extid >>= 2;
2527                 /* Calc oobsize */
2528                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2529                 extid >>= 2;
2530                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2531                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2532                 extid >>= 2;
2533                 /* Get buswidth information */
2534                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2535
2536         } else {
2537                 /*
2538                  * Old devices have chip data hardcoded in the device id table
2539                  */
2540                 mtd->erasesize = type->erasesize;
2541                 mtd->writesize = type->pagesize;
2542                 mtd->oobsize = mtd->writesize / 32;
2543                 busw = type->options & NAND_BUSWIDTH_16;
2544         }
2545
2546         /* Try to identify manufacturer */
2547         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2548                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2549                         break;
2550         }
2551
2552         /*
2553          * Check, if buswidth is correct. Hardware drivers should set
2554          * chip correct !
2555          */
2556         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2557                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2558                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2559                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2560                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2561                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2562                        busw ? 16 : 8);
2563                 return ERR_PTR(-EINVAL);
2564         }
2565
2566         /* Calculate the address shift from the page size */
2567         chip->page_shift = ffs(mtd->writesize) - 1;
2568         /* Convert chipsize to number of pages per chip -1. */
2569         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2570
2571         chip->bbt_erase_shift = chip->phys_erase_shift =
2572                 ffs(mtd->erasesize) - 1;
2573         chip->chip_shift = ffs(chip->chipsize) - 1;
2574
2575         /* Set the bad block position */
2576         chip->badblockpos = mtd->writesize > 512 ?
2577                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2578
2579         /* Get chip options, preserve non chip based options */
2580         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2581         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2582
2583         /*
2584          * Set chip as a default. Board drivers can override it, if necessary
2585          */
2586         chip->options |= NAND_NO_AUTOINCR;
2587
2588         /* Check if chip is a not a samsung device. Do not clear the
2589          * options for chips which are not having an extended id.
2590          */
2591         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2592                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2593
2594         /* Check for AND chips with 4 page planes */
2595         if (chip->options & NAND_4PAGE_ARRAY)
2596                 chip->erase_cmd = multi_erase_cmd;
2597         else
2598                 chip->erase_cmd = single_erase_cmd;
2599
2600         /* Do not replace user supplied command function ! */
2601         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2602                 chip->cmdfunc = nand_command_lp;
2603
2604         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2605                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2606                   nand_manuf_ids[maf_idx].name, type->name);
2607
2608         return type;
2609 }
2610
2611 /**
2612  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2613  * @mtd:             MTD device structure
2614  * @maxchips:        Number of chips to scan for
2615  *
2616  * This is the first phase of the normal nand_scan() function. It
2617  * reads the flash ID and sets up MTD fields accordingly.
2618  *
2619  * The mtd->owner field must be set to the module of the caller.
2620  */
2621 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2622 {
2623         int i, busw, nand_maf_id;
2624         struct nand_chip *chip = mtd->priv;
2625         struct nand_flash_dev *type;
2626
2627         /* Get buswidth to select the correct functions */
2628         busw = chip->options & NAND_BUSWIDTH_16;
2629         /* Set the default functions */
2630         nand_set_defaults(chip, busw);
2631
2632         /* Read the flash type */
2633         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2634
2635         if (IS_ERR(type)) {
2636 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2637                 printk(KERN_WARNING "No NAND device found!!!\n");
2638 #endif
2639                 chip->select_chip(mtd, -1);
2640                 return PTR_ERR(type);
2641         }
2642
2643         /* Check for a chip array */
2644         for (i = 1; i < maxchips; i++) {
2645                 chip->select_chip(mtd, i);
2646                 /* See comment in nand_get_flash_type for reset */
2647                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2648                 /* Send the command for reading device ID */
2649                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2650                 /* Read manufacturer and device IDs */
2651                 if (nand_maf_id != chip->read_byte(mtd) ||
2652                     type->id != chip->read_byte(mtd))
2653                         break;
2654         }
2655 #ifdef DEBUG
2656         if (i > 1)
2657                 printk(KERN_INFO "%d NAND chips detected\n", i);
2658 #endif
2659
2660         /* Store the number of chips and calc total size for mtd */
2661         chip->numchips = i;
2662         mtd->size = i * chip->chipsize;
2663
2664         return 0;
2665 }
2666
2667
2668 /**
2669  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2670  * @mtd:            MTD device structure
2671  * @maxchips:       Number of chips to scan for
2672  *
2673  * This is the second phase of the normal nand_scan() function. It
2674  * fills out all the uninitialized function pointers with the defaults
2675  * and scans for a bad block table if appropriate.
2676  */
2677 int nand_scan_tail(struct mtd_info *mtd)
2678 {
2679         int i;
2680         struct nand_chip *chip = mtd->priv;
2681
2682         if (!(chip->options & NAND_OWN_BUFFERS))
2683                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2684         if (!chip->buffers)
2685                 return -ENOMEM;
2686
2687         /* Set the internal oob buffer location, just after the page data */
2688         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2689
2690         /*
2691          * If no default placement scheme is given, select an appropriate one
2692          */
2693         if (!chip->ecc.layout) {
2694                 switch (mtd->oobsize) {
2695                 case 8:
2696                         chip->ecc.layout = &nand_oob_8;
2697                         break;
2698                 case 16:
2699                         chip->ecc.layout = &nand_oob_16;
2700                         break;
2701                 case 64:
2702                         chip->ecc.layout = &nand_oob_64;
2703                         break;
2704                 case 128:
2705                         chip->ecc.layout = &nand_oob_128;
2706                         break;
2707                 default:
2708                         printk(KERN_WARNING "No oob scheme defined for "
2709                                "oobsize %d\n", mtd->oobsize);
2710 /*                      BUG(); */
2711                 }
2712         }
2713
2714         if (!chip->write_page)
2715                 chip->write_page = nand_write_page;
2716
2717         /*
2718          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2719          * selected and we have 256 byte pagesize fallback to software ECC
2720          */
2721         if (!chip->ecc.read_page_raw)
2722                 chip->ecc.read_page_raw = nand_read_page_raw;
2723         if (!chip->ecc.write_page_raw)
2724                 chip->ecc.write_page_raw = nand_write_page_raw;
2725
2726         switch (chip->ecc.mode) {
2727         case NAND_ECC_HW:
2728                 /* Use standard hwecc read page function ? */
2729                 if (!chip->ecc.read_page)
2730                         chip->ecc.read_page = nand_read_page_hwecc;
2731                 if (!chip->ecc.write_page)
2732                         chip->ecc.write_page = nand_write_page_hwecc;
2733                 if (!chip->ecc.read_oob)
2734                         chip->ecc.read_oob = nand_read_oob_std;
2735                 if (!chip->ecc.write_oob)
2736                         chip->ecc.write_oob = nand_write_oob_std;
2737
2738         case NAND_ECC_HW_SYNDROME:
2739                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2740                      !chip->ecc.hwctl) &&
2741                     (!chip->ecc.read_page ||
2742                      chip->ecc.read_page == nand_read_page_hwecc ||
2743                      !chip->ecc.write_page ||
2744                      chip->ecc.write_page == nand_write_page_hwecc)) {
2745                         printk(KERN_WARNING "No ECC functions supplied, "
2746                                "Hardware ECC not possible\n");
2747                         BUG();
2748                 }
2749                 /* Use standard syndrome read/write page function ? */
2750                 if (!chip->ecc.read_page)
2751                         chip->ecc.read_page = nand_read_page_syndrome;
2752                 if (!chip->ecc.write_page)
2753                         chip->ecc.write_page = nand_write_page_syndrome;
2754                 if (!chip->ecc.read_oob)
2755                         chip->ecc.read_oob = nand_read_oob_syndrome;
2756                 if (!chip->ecc.write_oob)
2757                         chip->ecc.write_oob = nand_write_oob_syndrome;
2758
2759                 if (mtd->writesize >= chip->ecc.size)
2760                         break;
2761                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2762                        "%d byte page size, fallback to SW ECC\n",
2763                        chip->ecc.size, mtd->writesize);
2764                 chip->ecc.mode = NAND_ECC_SOFT;
2765
2766         case NAND_ECC_SOFT:
2767                 chip->ecc.calculate = nand_calculate_ecc;
2768                 chip->ecc.correct = nand_correct_data;
2769                 chip->ecc.read_page = nand_read_page_swecc;
2770                 chip->ecc.read_subpage = nand_read_subpage;
2771                 chip->ecc.write_page = nand_write_page_swecc;
2772                 chip->ecc.read_oob = nand_read_oob_std;
2773                 chip->ecc.write_oob = nand_write_oob_std;
2774                 chip->ecc.size = 256;
2775                 chip->ecc.bytes = 3;
2776                 break;
2777
2778         case NAND_ECC_NONE:
2779                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2780                        "This is not recommended !!\n");
2781                 chip->ecc.read_page = nand_read_page_raw;
2782                 chip->ecc.write_page = nand_write_page_raw;
2783                 chip->ecc.read_oob = nand_read_oob_std;
2784                 chip->ecc.write_oob = nand_write_oob_std;
2785                 chip->ecc.size = mtd->writesize;
2786                 chip->ecc.bytes = 0;
2787                 break;
2788
2789         default:
2790                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2791                        chip->ecc.mode);
2792                 BUG();
2793         }
2794
2795         /*
2796          * The number of bytes available for a client to place data into
2797          * the out of band area
2798          */
2799         chip->ecc.layout->oobavail = 0;
2800         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2801                 chip->ecc.layout->oobavail +=
2802                         chip->ecc.layout->oobfree[i].length;
2803         mtd->oobavail = chip->ecc.layout->oobavail;
2804
2805         /*
2806          * Set the number of read / write steps for one page depending on ECC
2807          * mode
2808          */
2809         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2810         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2811                 printk(KERN_WARNING "Invalid ecc parameters\n");
2812                 BUG();
2813         }
2814         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2815
2816         /*
2817          * Allow subpage writes up to ecc.steps. Not possible for MLC
2818          * FLASH.
2819          */
2820         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2821             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2822                 switch(chip->ecc.steps) {
2823                 case 2:
2824                         mtd->subpage_sft = 1;
2825                         break;
2826                 case 4:
2827                 case 8:
2828                         mtd->subpage_sft = 2;
2829                         break;
2830                 }
2831         }
2832         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2833
2834         /* Initialize state */
2835         chip->state = FL_READY;
2836
2837         /* De-select the device */
2838         chip->select_chip(mtd, -1);
2839
2840         /* Invalidate the pagebuffer reference */
2841         chip->pagebuf = -1;
2842
2843         /* Fill in remaining MTD driver data */
2844         mtd->type = MTD_NANDFLASH;
2845         mtd->flags = MTD_CAP_NANDFLASH;
2846         mtd->erase = nand_erase;
2847         mtd->point = NULL;
2848         mtd->unpoint = NULL;
2849         mtd->read = nand_read;
2850         mtd->write = nand_write;
2851         mtd->read_oob = nand_read_oob;
2852         mtd->write_oob = nand_write_oob;
2853         mtd->sync = nand_sync;
2854         mtd->lock = NULL;
2855         mtd->unlock = NULL;
2856         mtd->suspend = nand_suspend;
2857         mtd->resume = nand_resume;
2858         mtd->block_isbad = nand_block_isbad;
2859         mtd->block_markbad = nand_block_markbad;
2860
2861         /* propagate ecc.layout to mtd_info */
2862         mtd->ecclayout = chip->ecc.layout;
2863
2864         /* Check, if we should skip the bad block table scan */
2865         if (chip->options & NAND_SKIP_BBTSCAN)
2866                 chip->options |= NAND_BBT_SCANNED;
2867
2868         return 0;
2869 }
2870
2871 /* module_text_address() isn't exported, and it's mostly a pointless
2872    test if this is a module _anyway_ -- they'd have to try _really_ hard
2873    to call us from in-kernel code if the core NAND support is modular. */
2874 #ifdef MODULE
2875 #define caller_is_module() (1)
2876 #else
2877 #define caller_is_module() \
2878         module_text_address((unsigned long)__builtin_return_address(0))
2879 #endif
2880
2881 /**
2882  * nand_scan - [NAND Interface] Scan for the NAND device
2883  * @mtd:        MTD device structure
2884  * @maxchips:   Number of chips to scan for
2885  *
2886  * This fills out all the uninitialized function pointers
2887  * with the defaults.
2888  * The flash ID is read and the mtd/chip structures are
2889  * filled with the appropriate values.
2890  * The mtd->owner field must be set to the module of the caller
2891  *
2892  */
2893 int nand_scan(struct mtd_info *mtd, int maxchips)
2894 {
2895         int ret;
2896
2897         /* Many callers got this wrong, so check for it for a while... */
2898         /* XXX U-BOOT XXX */
2899 #if 0
2900         if (!mtd->owner && caller_is_module()) {
2901                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2902                 BUG();
2903         }
2904 #endif
2905
2906         ret = nand_scan_ident(mtd, maxchips);
2907         if (!ret)
2908                 ret = nand_scan_tail(mtd);
2909         return ret;
2910 }
2911
2912 /**
2913  * nand_release - [NAND Interface] Free resources held by the NAND device
2914  * @mtd:        MTD device structure
2915 */
2916 void nand_release(struct mtd_info *mtd)
2917 {
2918         struct nand_chip *chip = mtd->priv;
2919
2920 #ifdef CONFIG_MTD_PARTITIONS
2921         /* Deregister partitions */
2922         del_mtd_partitions(mtd);
2923 #endif
2924         /* Deregister the device */
2925         /* XXX U-BOOT XXX */
2926 #if 0
2927         del_mtd_device(mtd);
2928 #endif
2929
2930         /* Free bad block table memory */
2931         kfree(chip->bbt);
2932         if (!(chip->options & NAND_OWN_BUFFERS))
2933                 kfree(chip->buffers);
2934 }
2935
2936 /* XXX U-BOOT XXX */
2937 #if 0
2938 EXPORT_SYMBOL_GPL(nand_scan);
2939 EXPORT_SYMBOL_GPL(nand_scan_ident);
2940 EXPORT_SYMBOL_GPL(nand_scan_tail);
2941 EXPORT_SYMBOL_GPL(nand_release);
2942
2943 static int __init nand_base_init(void)
2944 {
2945         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2946         return 0;
2947 }
2948
2949 static void __exit nand_base_exit(void)
2950 {
2951         led_trigger_unregister_simple(nand_led_trigger);
2952 }
2953
2954 module_init(nand_base_init);
2955 module_exit(nand_base_exit);
2956
2957 MODULE_LICENSE("GPL");
2958 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2959 MODULE_DESCRIPTION("Generic NAND flash driver code");
2960 #endif