drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/tech/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *
  28  * This program is free software; you can redistribute it and/or modify
  29  * it under the terms of the GNU General Public License version 2 as
  30  * published by the Free Software Foundation.
  31  *
  32  */
  33
  34 /* XXX U-BOOT XXX */
  35 #if 0
  36 #include <linux/module.h>
  37 #include <linux/delay.h>
  38 #include <linux/errno.h>
  39 #include <linux/err.h>
  40 #include <linux/sched.h>
  41 #include <linux/slab.h>
  42 #include <linux/types.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/compatmac.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/bitops.h>
  49 #include <linux/leds.h>
  50 #include <asm/io.h>
  51
  52 #ifdef CONFIG_MTD_PARTITIONS
  53 #include <linux/mtd/partitions.h>
  54 #endif
  55
  56 #endif
  57
  58 #include <common.h>
  59
  60 #define ENOTSUPP        524     /* Operation is not supported */
  61
  62 #include <malloc.h>
  63 #include <watchdog.h>
  64 #include <linux/err.h>
  65 #include <linux/mtd/compat.h>
  66 #include <linux/mtd/mtd.h>
  67 #include <linux/mtd/nand.h>
  68 #include <linux/mtd/nand_ecc.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/errno.h>
  72
  73 #ifdef CONFIG_JFFS2_NAND
  74 #include <jffs2/jffs2.h>
  75 #endif
  76
  77 /* Define default oob placement schemes for large and small page devices */
  78 static struct nand_ecclayout nand_oob_8 = {
  79         .eccbytes = 3,
  80         .eccpos = {0, 1, 2},
  81         .oobfree = {
  82                 {.offset = 3,
  83                  .length = 2},
  84                 {.offset = 6,
  85                  .length = 2}}
  86 };
  87
  88 static struct nand_ecclayout nand_oob_16 = {
  89         .eccbytes = 6,
  90         .eccpos = {0, 1, 2, 3, 6, 7},
  91         .oobfree = {
  92                 {.offset = 8,
  93                  . length = 8}}
  94 };
  95
  96 static struct nand_ecclayout nand_oob_64 = {
  97         .eccbytes = 24,
  98         .eccpos = {
  99                    40, 41, 42, 43, 44, 45, 46, 47,
 100                    48, 49, 50, 51, 52, 53, 54, 55,
 101                    56, 57, 58, 59, 60, 61, 62, 63},
 102         .oobfree = {
 103                 {.offset = 2,
 104                  .length = 38}}
 105 };
 106
 107 static struct nand_ecclayout nand_oob_128 = {
 108         .eccbytes = 48,
 109         .eccpos = {
 110                     80,  81,  82,  83,  84,  85,  86,  87,
 111                     88,  89,  90,  91,  92,  93,  94,  95,
 112                     96,  97,  98,  99, 100, 101, 102, 103,
 113                    104, 105, 106, 107, 108, 109, 110, 111,
 114                    112, 113, 114, 115, 116, 117, 118, 119,
 115                    120, 121, 122, 123, 124, 125, 126, 127},
 116         .oobfree = {
 117                 {.offset = 2,
 118                  .length = 78}}
 119 };
 120
 121
 122 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 123                            int new_state);
 124
 125 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 126                              struct mtd_oob_ops *ops);
 127
 128 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 129
 130 /*
 131  * For devices which display every fart in the system on a seperate LED. Is
 132  * compiled away when LED support is disabled.
 133  */
 134 /* XXX U-BOOT XXX */
 135 #if 0
 136 DEFINE_LED_TRIGGER(nand_led_trigger);
 137 #endif
 138
 139 /**
 140  * nand_release_device - [GENERIC] release chip
 141  * @mtd:        MTD device structure
 142  *
 143  * Deselect, release chip lock and wake up anyone waiting on the device
 144  */
 145 /* XXX U-BOOT XXX */
 146 #if 0
 147 static void nand_release_device(struct mtd_info *mtd)
 148 {
 149         struct nand_chip *chip = mtd->priv;
 150
 151         /* De-select the NAND device */
 152         chip->select_chip(mtd, -1);
 153
 154         /* Release the controller and the chip */
 155         spin_lock(&chip->controller->lock);
 156         chip->controller->active = NULL;
 157         chip->state = FL_READY;
 158         wake_up(&chip->controller->wq);
 159         spin_unlock(&chip->controller->lock);
 160 }
 161 #else
 162 static void nand_release_device (struct mtd_info *mtd)
 163 {
 164         struct nand_chip *this = mtd->priv;
 165         this->select_chip(mtd, -1);     /* De-select the NAND device */
 166 }
 167 #endif
 168
 169 /**
 170  * nand_read_byte - [DEFAULT] read one byte from the chip
 171  * @mtd:        MTD device structure
 172  *
 173  * Default read function for 8bit buswith
 174  */
 175 static uint8_t nand_read_byte(struct mtd_info *mtd)
 176 {
 177         struct nand_chip *chip = mtd->priv;
 178         return readb(chip->IO_ADDR_R);
 179 }
 180
 181 /**
 182  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 183  * @mtd:        MTD device structure
 184  *
 185  * Default read function for 16bit buswith with
 186  * endianess conversion
 187  */
 188 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 189 {
 190         struct nand_chip *chip = mtd->priv;
 191         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 192 }
 193
 194 /**
 195  * nand_read_word - [DEFAULT] read one word from the chip
 196  * @mtd:        MTD device structure
 197  *
 198  * Default read function for 16bit buswith without
 199  * endianess conversion
 200  */
 201 static u16 nand_read_word(struct mtd_info *mtd)
 202 {
 203         struct nand_chip *chip = mtd->priv;
 204         return readw(chip->IO_ADDR_R);
 205 }
 206
 207 /**
 208  * nand_select_chip - [DEFAULT] control CE line
 209  * @mtd:        MTD device structure
 210  * @chipnr:     chipnumber to select, -1 for deselect
 211  *
 212  * Default select function for 1 chip devices.
 213  */
 214 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 215 {
 216         struct nand_chip *chip = mtd->priv;
 217
 218         switch (chipnr) {
 219         case -1:
 220                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 221                 break;
 222         case 0:
 223                 break;
 224
 225         default:
 226                 BUG();
 227         }
 228 }
 229
 230 /**
 231  * nand_write_buf - [DEFAULT] write buffer to chip
 232  * @mtd:        MTD device structure
 233  * @buf:        data buffer
 234  * @len:        number of bytes to write
 235  *
 236  * Default write function for 8bit buswith
 237  */
 238 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 239 {
 240         int i;
 241         struct nand_chip *chip = mtd->priv;
 242
 243         for (i = 0; i < len; i++)
 244                 writeb(buf[i], chip->IO_ADDR_W);
 245 }
 246
 247 /**
 248  * nand_read_buf - [DEFAULT] read chip data into buffer
 249  * @mtd:        MTD device structure
 250  * @buf:        buffer to store date
 251  * @len:        number of bytes to read
 252  *
 253  * Default read function for 8bit buswith
 254  */
 255 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 256 {
 257         int i;
 258         struct nand_chip *chip = mtd->priv;
 259
 260         for (i = 0; i < len; i++)
 261                 buf[i] = readb(chip->IO_ADDR_R);
 262 }
 263
 264 /**
 265  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 266  * @mtd:        MTD device structure
 267  * @buf:        buffer containing the data to compare
 268  * @len:        number of bytes to compare
 269  *
 270  * Default verify function for 8bit buswith
 271  */
 272 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 273 {
 274         int i;
 275         struct nand_chip *chip = mtd->priv;
 276
 277         for (i = 0; i < len; i++)
 278                 if (buf[i] != readb(chip->IO_ADDR_R))
 279                         return -EFAULT;
 280         return 0;
 281 }
 282
 283 /**
 284  * nand_write_buf16 - [DEFAULT] write buffer to chip
 285  * @mtd:        MTD device structure
 286  * @buf:        data buffer
 287  * @len:        number of bytes to write
 288  *
 289  * Default write function for 16bit buswith
 290  */
 291 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 292 {
 293         int i;
 294         struct nand_chip *chip = mtd->priv;
 295         u16 *p = (u16 *) buf;
 296         len >>= 1;
 297
 298         for (i = 0; i < len; i++)
 299                 writew(p[i], chip->IO_ADDR_W);
 300
 301 }
 302
 303 /**
 304  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 305  * @mtd:        MTD device structure
 306  * @buf:        buffer to store date
 307  * @len:        number of bytes to read
 308  *
 309  * Default read function for 16bit buswith
 310  */
 311 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 312 {
 313         int i;
 314         struct nand_chip *chip = mtd->priv;
 315         u16 *p = (u16 *) buf;
 316         len >>= 1;
 317
 318         for (i = 0; i < len; i++)
 319                 p[i] = readw(chip->IO_ADDR_R);
 320 }
 321
 322 /**
 323  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 324  * @mtd:        MTD device structure
 325  * @buf:        buffer containing the data to compare
 326  * @len:        number of bytes to compare
 327  *
 328  * Default verify function for 16bit buswith
 329  */
 330 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 331 {
 332         int i;
 333         struct nand_chip *chip = mtd->priv;
 334         u16 *p = (u16 *) buf;
 335         len >>= 1;
 336
 337         for (i = 0; i < len; i++)
 338                 if (p[i] != readw(chip->IO_ADDR_R))
 339                         return -EFAULT;
 340
 341         return 0;
 342 }
 343
 344 /**
 345  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 346  * @mtd:        MTD device structure
 347  * @ofs:        offset from device start
 348  * @getchip:    0, if the chip is already selected
 349  *
 350  * Check, if the block is bad.
 351  */
 352 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 353 {
 354         int page, chipnr, res = 0;
 355         struct nand_chip *chip = mtd->priv;
 356         u16 bad;
 357
 358         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 359
 360         if (getchip) {
 361                 chipnr = (int)(ofs >> chip->chip_shift);
 362
 363                 nand_get_device(chip, mtd, FL_READING);
 364
 365                 /* Select the NAND device */
 366                 chip->select_chip(mtd, chipnr);
 367         }
 368
 369         if (chip->options & NAND_BUSWIDTH_16) {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 371                               page);
 372                 bad = cpu_to_le16(chip->read_word(mtd));
 373                 if (chip->badblockpos & 0x1)
 374                         bad >>= 8;
 375                 if ((bad & 0xFF) != 0xff)
 376                         res = 1;
 377         } else {
 378                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 379                 if (chip->read_byte(mtd) != 0xff)
 380                         res = 1;
 381         }
 382
 383         if (getchip)
 384                 nand_release_device(mtd);
 385
 386         return res;
 387 }
 388
 389 /**
 390  * nand_default_block_markbad - [DEFAULT] mark a block bad
 391  * @mtd:        MTD device structure
 392  * @ofs:        offset from device start
 393  *
 394  * This is the default implementation, which can be overridden by
 395  * a hardware specific driver.
 396 */
 397 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 398 {
 399         struct nand_chip *chip = mtd->priv;
 400         uint8_t buf[2] = { 0, 0 };
 401         int block, ret;
 402
 403         /* Get block number */
 404         block = (int)(ofs >> chip->bbt_erase_shift);
 405         if (chip->bbt)
 406                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 407
 408         /* Do we have a flash based bad block table ? */
 409         if (chip->options & NAND_USE_FLASH_BBT)
 410                 ret = nand_update_bbt(mtd, ofs);
 411         else {
 412                 /* We write two bytes, so we dont have to mess with 16 bit
 413                  * access
 414                  */
 415                 ofs += mtd->oobsize;
 416                 chip->ops.len = chip->ops.ooblen = 2;
 417                 chip->ops.datbuf = NULL;
 418                 chip->ops.oobbuf = buf;
 419                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 420
 421                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 422         }
 423         if (!ret)
 424                 mtd->ecc_stats.badblocks++;
 425         return ret;
 426 }
 427
 428 /**
 429  * nand_check_wp - [GENERIC] check if the chip is write protected
 430  * @mtd:        MTD device structure
 431  * Check, if the device is write protected
 432  *
 433  * The function expects, that the device is already selected
 434  */
 435 static int nand_check_wp(struct mtd_info *mtd)
 436 {
 437         struct nand_chip *chip = mtd->priv;
 438         /* Check the WP bit */
 439         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 440         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 441 }
 442
 443 /**
 444  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 445  * @mtd:        MTD device structure
 446  * @ofs:        offset from device start
 447  * @getchip:    0, if the chip is already selected
 448  * @allowbbt:   1, if its allowed to access the bbt area
 449  *
 450  * Check, if the block is bad. Either by reading the bad block table or
 451  * calling of the scan function.
 452  */
 453 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 454                                int allowbbt)
 455 {
 456         struct nand_chip *chip = mtd->priv;
 457
 458         if (!(chip->options & NAND_BBT_SCANNED)) {
 459                 chip->scan_bbt(mtd);
 460                 chip->options |= NAND_BBT_SCANNED;
 461         }
 462
 463         if (!chip->bbt)
 464                 return chip->block_bad(mtd, ofs, getchip);
 465
 466         /* Return info from the table */
 467         return nand_isbad_bbt(mtd, ofs, allowbbt);
 468 }
 469
 470 /*
 471  * Wait for the ready pin, after a command
 472  * The timeout is catched later.
 473  */
 474 /* XXX U-BOOT XXX */
 475 #if 0
 476 void nand_wait_ready(struct mtd_info *mtd)
 477 {
 478         struct nand_chip *chip = mtd->priv;
 479         unsigned long timeo = jiffies + 2;
 480
 481         led_trigger_event(nand_led_trigger, LED_FULL);
 482         /* wait until command is processed or timeout occures */
 483         do {
 484                 if (chip->dev_ready(mtd))
 485                         break;
 486                 touch_softlockup_watchdog();
 487         } while (time_before(jiffies, timeo));
 488         led_trigger_event(nand_led_trigger, LED_OFF);
 489 }
 490 EXPORT_SYMBOL_GPL(nand_wait_ready);
 491 #else
 492 void nand_wait_ready(struct mtd_info *mtd)
 493 {
 494         struct nand_chip *chip = mtd->priv;
 495         u32 timeo = (CFG_HZ * 20) / 1000;
 496
 497         reset_timer();
 498
 499         /* wait until command is processed or timeout occures */
 500         while (get_timer(0) < timeo) {
 501                 if (chip->dev_ready)
 502                         if (chip->dev_ready(mtd))
 503                                 break;
 504         }
 505 }
 506 #endif
 507
 508 /**
 509  * nand_command - [DEFAULT] Send command to NAND device
 510  * @mtd:        MTD device structure
 511  * @command:    the command to be sent
 512  * @column:     the column address for this command, -1 if none
 513  * @page_addr:  the page address for this command, -1 if none
 514  *
 515  * Send command to NAND device. This function is used for small page
 516  * devices (256/512 Bytes per page)
 517  */
 518 static void nand_command(struct mtd_info *mtd, unsigned int command,
 519                          int column, int page_addr)
 520 {
 521         register struct nand_chip *chip = mtd->priv;
 522         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 523
 524         /*
 525          * Write out the command to the device.
 526          */
 527         if (command == NAND_CMD_SEQIN) {
 528                 int readcmd;
 529
 530                 if (column >= mtd->writesize) {
 531                         /* OOB area */
 532                         column -= mtd->writesize;
 533                         readcmd = NAND_CMD_READOOB;
 534                 } else if (column < 256) {
 535                         /* First 256 bytes --> READ0 */
 536                         readcmd = NAND_CMD_READ0;
 537                 } else {
 538                         column -= 256;
 539                         readcmd = NAND_CMD_READ1;
 540                 }
 541                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 542                 ctrl &= ~NAND_CTRL_CHANGE;
 543         }
 544         chip->cmd_ctrl(mtd, command, ctrl);
 545
 546         /*
 547          * Address cycle, when necessary
 548          */
 549         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 550         /* Serially input address */
 551         if (column != -1) {
 552                 /* Adjust columns for 16 bit buswidth */
 553                 if (chip->options & NAND_BUSWIDTH_16)
 554                         column >>= 1;
 555                 chip->cmd_ctrl(mtd, column, ctrl);
 556                 ctrl &= ~NAND_CTRL_CHANGE;
 557         }
 558         if (page_addr != -1) {
 559                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 560                 ctrl &= ~NAND_CTRL_CHANGE;
 561                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 562                 /* One more address cycle for devices > 32MiB */
 563                 if (chip->chipsize > (32 << 20))
 564                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 565         }
 566         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 567
 568         /*
 569          * program and erase have their own busy handlers
 570          * status and sequential in needs no delay
 571          */
 572         switch (command) {
 573
 574         case NAND_CMD_PAGEPROG:
 575         case NAND_CMD_ERASE1:
 576         case NAND_CMD_ERASE2:
 577         case NAND_CMD_SEQIN:
 578         case NAND_CMD_STATUS:
 579                 return;
 580
 581         case NAND_CMD_RESET:
 582                 if (chip->dev_ready)
 583                         break;
 584                 udelay(chip->chip_delay);
 585                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 586                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 587                 chip->cmd_ctrl(mtd,
 588                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 589                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 590                 return;
 591
 592                 /* This applies to read commands */
 593         default:
 594                 /*
 595                  * If we don't have access to the busy pin, we apply the given
 596                  * command delay
 597                  */
 598                 if (!chip->dev_ready) {
 599                         udelay(chip->chip_delay);
 600                         return;
 601                 }
 602         }
 603         /* Apply this short delay always to ensure that we do wait tWB in
 604          * any case on any machine. */
 605         ndelay(100);
 606
 607         nand_wait_ready(mtd);
 608 }
 609
 610 /**
 611  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 612  * @mtd:        MTD device structure
 613  * @command:    the command to be sent
 614  * @column:     the column address for this command, -1 if none
 615  * @page_addr:  the page address for this command, -1 if none
 616  *
 617  * Send command to NAND device. This is the version for the new large page
 618  * devices We dont have the separate regions as we have in the small page
 619  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 620  */
 621 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 622                             int column, int page_addr)
 623 {
 624         register struct nand_chip *chip = mtd->priv;
 625
 626         /* Emulate NAND_CMD_READOOB */
 627         if (command == NAND_CMD_READOOB) {
 628                 column += mtd->writesize;
 629                 command = NAND_CMD_READ0;
 630         }
 631
 632         /* Command latch cycle */
 633         chip->cmd_ctrl(mtd, command & 0xff,
 634                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 635
 636         if (column != -1 || page_addr != -1) {
 637                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 638
 639                 /* Serially input address */
 640                 if (column != -1) {
 641                         /* Adjust columns for 16 bit buswidth */
 642                         if (chip->options & NAND_BUSWIDTH_16)
 643                                 column >>= 1;
 644                         chip->cmd_ctrl(mtd, column, ctrl);
 645                         ctrl &= ~NAND_CTRL_CHANGE;
 646                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 647                 }
 648                 if (page_addr != -1) {
 649                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 650                         chip->cmd_ctrl(mtd, page_addr >> 8,
 651                                        NAND_NCE | NAND_ALE);
 652                         /* One more address cycle for devices > 128MiB */
 653                         if (chip->chipsize > (128 << 20))
 654                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 655                                                NAND_NCE | NAND_ALE);
 656                 }
 657         }
 658         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 659
 660         /*
 661          * program and erase have their own busy handlers
 662          * status, sequential in, and deplete1 need no delay
 663          */
 664         switch (command) {
 665
 666         case NAND_CMD_CACHEDPROG:
 667         case NAND_CMD_PAGEPROG:
 668         case NAND_CMD_ERASE1:
 669         case NAND_CMD_ERASE2:
 670         case NAND_CMD_SEQIN:
 671         case NAND_CMD_RNDIN:
 672         case NAND_CMD_STATUS:
 673         case NAND_CMD_DEPLETE1:
 674                 return;
 675
 676                 /*
 677                  * read error status commands require only a short delay
 678                  */
 679         case NAND_CMD_STATUS_ERROR:
 680         case NAND_CMD_STATUS_ERROR0:
 681         case NAND_CMD_STATUS_ERROR1:
 682         case NAND_CMD_STATUS_ERROR2:
 683         case NAND_CMD_STATUS_ERROR3:
 684                 udelay(chip->chip_delay);
 685                 return;
 686
 687         case NAND_CMD_RESET:
 688                 if (chip->dev_ready)
 689                         break;
 690                 udelay(chip->chip_delay);
 691                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 692                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 693                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 694                                NAND_NCE | NAND_CTRL_CHANGE);
 695                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 696                 return;
 697
 698         case NAND_CMD_RNDOUT:
 699                 /* No ready / busy check necessary */
 700                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 701                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 702                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 703                                NAND_NCE | NAND_CTRL_CHANGE);
 704                 return;
 705
 706         case NAND_CMD_READ0:
 707                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 708                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 709                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 710                                NAND_NCE | NAND_CTRL_CHANGE);
 711
 712                 /* This applies to read commands */
 713         default:
 714                 /*
 715                  * If we don't have access to the busy pin, we apply the given
 716                  * command delay
 717                  */
 718                 if (!chip->dev_ready) {
 719                         udelay(chip->chip_delay);
 720                         return;
 721                 }
 722         }
 723
 724         /* Apply this short delay always to ensure that we do wait tWB in
 725          * any case on any machine. */
 726         ndelay(100);
 727
 728         nand_wait_ready(mtd);
 729 }
 730
 731 /**
 732  * nand_get_device - [GENERIC] Get chip for selected access
 733  * @chip:       the nand chip descriptor
 734  * @mtd:        MTD device structure
 735  * @new_state:  the state which is requested
 736  *
 737  * Get the device and lock it for exclusive access
 738  */
 739 /* XXX U-BOOT XXX */
 740 #if 0
 741 static int
 742 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 743 {
 744         spinlock_t *lock = &chip->controller->lock;
 745         wait_queue_head_t *wq = &chip->controller->wq;
 746         DECLARE_WAITQUEUE(wait, current);
 747  retry:
 748         spin_lock(lock);
 749
 750         /* Hardware controller shared among independend devices */
 751         /* Hardware controller shared among independend devices */
 752         if (!chip->controller->active)
 753                 chip->controller->active = chip;
 754
 755         if (chip->controller->active == chip && chip->state == FL_READY) {
 756                 chip->state = new_state;
 757                 spin_unlock(lock);
 758                 return 0;
 759         }
 760         if (new_state == FL_PM_SUSPENDED) {
 761                 spin_unlock(lock);
 762                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 763         }
 764         set_current_state(TASK_UNINTERRUPTIBLE);
 765         add_wait_queue(wq, &wait);
 766         spin_unlock(lock);
 767         schedule();
 768         remove_wait_queue(wq, &wait);
 769         goto retry;
 770 }
 771 #else
 772 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 773 {
 774         this->state = new_state;
 775         return 0;
 776 }
 777 #endif
 778
 779 /**
 780  * nand_wait - [DEFAULT]  wait until the command is done
 781  * @mtd:        MTD device structure
 782  * @chip:       NAND chip structure
 783  *
 784  * Wait for command done. This applies to erase and program only
 785  * Erase can take up to 400ms and program up to 20ms according to
 786  * general NAND and SmartMedia specs
 787  */
 788 /* XXX U-BOOT XXX */
 789 #if 0
 790 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 791 {
 792
 793         unsigned long timeo = jiffies;
 794         int status, state = chip->state;
 795
 796         if (state == FL_ERASING)
 797                 timeo += (HZ * 400) / 1000;
 798         else
 799                 timeo += (HZ * 20) / 1000;
 800
 801         led_trigger_event(nand_led_trigger, LED_FULL);
 802
 803         /* Apply this short delay always to ensure that we do wait tWB in
 804          * any case on any machine. */
 805         ndelay(100);
 806
 807         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 808                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 809         else
 810                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 811
 812         while (time_before(jiffies, timeo)) {
 813                 if (chip->dev_ready) {
 814                         if (chip->dev_ready(mtd))
 815                                 break;
 816                 } else {
 817                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 818                                 break;
 819                 }
 820                 cond_resched();
 821         }
 822         led_trigger_event(nand_led_trigger, LED_OFF);
 823
 824         status = (int)chip->read_byte(mtd);
 825         return status;
 826 }
 827 #else
 828 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 829 {
 830         unsigned long   timeo;
 831         int state = this->state;
 832
 833         if (state == FL_ERASING)
 834                 timeo = (CFG_HZ * 400) / 1000;
 835         else
 836                 timeo = (CFG_HZ * 20) / 1000;
 837
 838         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 839                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 840         else
 841                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 842
 843         reset_timer();
 844
 845         while (1) {
 846                 if (get_timer(0) > timeo) {
 847                         printf("Timeout!");
 848                         return 0x01;
 849                 }
 850
 851                 if (this->dev_ready) {
 852                         if (this->dev_ready(mtd))
 853                                 break;
 854                 } else {
 855                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 856                                 break;
 857                 }
 858         }
 859 #ifdef PPCHAMELON_NAND_TIMER_HACK
 860         reset_timer();
 861         while (get_timer(0) < 10);
 862 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 863
 864         return this->read_byte(mtd);
 865 }
 866 #endif
 867
 868 /**
 869  * nand_read_page_raw - [Intern] read raw page data without ecc
 870  * @mtd:        mtd info structure
 871  * @chip:       nand chip info structure
 872  * @buf:        buffer to store read data
 873  */
 874 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 875                               uint8_t *buf)
 876 {
 877         chip->read_buf(mtd, buf, mtd->writesize);
 878         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 879         return 0;
 880 }
 881
 882 /**
 883  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 884  * @mtd:        mtd info structure
 885  * @chip:       nand chip info structure
 886  * @buf:        buffer to store read data
 887  */
 888 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 889                                 uint8_t *buf)
 890 {
 891         int i, eccsize = chip->ecc.size;
 892         int eccbytes = chip->ecc.bytes;
 893         int eccsteps = chip->ecc.steps;
 894         uint8_t *p = buf;
 895         uint8_t *ecc_calc = chip->buffers->ecccalc;
 896         uint8_t *ecc_code = chip->buffers->ecccode;
 897         uint32_t *eccpos = chip->ecc.layout->eccpos;
 898
 899         chip->ecc.read_page_raw(mtd, chip, buf);
 900
 901         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 902                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 903
 904         for (i = 0; i < chip->ecc.total; i++)
 905                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 906
 907         eccsteps = chip->ecc.steps;
 908         p = buf;
 909
 910         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 911                 int stat;
 912
 913                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 914                 if (stat == -1)
 915                         mtd->ecc_stats.failed++;
 916                 else
 917                         mtd->ecc_stats.corrected += stat;
 918         }
 919         return 0;
 920 }
 921
 922 /**
 923  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 924  * @mtd:        mtd info structure
 925  * @chip:       nand chip info structure
 926  * @buf:        buffer to store read data
 927  *
 928  * Not for syndrome calculating ecc controllers which need a special oob layout
 929  */
 930 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 931                                 uint8_t *buf)
 932 {
 933         int i, eccsize = chip->ecc.size;
 934         int eccbytes = chip->ecc.bytes;
 935         int eccsteps = chip->ecc.steps;
 936         uint8_t *p = buf;
 937         uint8_t *ecc_calc = chip->buffers->ecccalc;
 938         uint8_t *ecc_code = chip->buffers->ecccode;
 939         uint32_t *eccpos = chip->ecc.layout->eccpos;
 940
 941         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 942                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 943                 chip->read_buf(mtd, p, eccsize);
 944                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 945         }
 946         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 947
 948         for (i = 0; i < chip->ecc.total; i++)
 949                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 950
 951         eccsteps = chip->ecc.steps;
 952         p = buf;
 953
 954         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 955                 int stat;
 956
 957                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 958                 if (stat == -1)
 959                         mtd->ecc_stats.failed++;
 960                 else
 961                         mtd->ecc_stats.corrected += stat;
 962         }
 963         return 0;
 964 }
 965
 966 /**
 967  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
 968  * @mtd:        mtd info structure
 969  * @chip:       nand chip info structure
 970  * @buf:        buffer to store read data
 971  *
 972  * The hw generator calculates the error syndrome automatically. Therefor
 973  * we need a special oob layout and handling.
 974  */
 975 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 976                                    uint8_t *buf)
 977 {
 978         int i, eccsize = chip->ecc.size;
 979         int eccbytes = chip->ecc.bytes;
 980         int eccsteps = chip->ecc.steps;
 981         uint8_t *p = buf;
 982         uint8_t *oob = chip->oob_poi;
 983
 984         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 985                 int stat;
 986
 987                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 988                 chip->read_buf(mtd, p, eccsize);
 989
 990                 if (chip->ecc.prepad) {
 991                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 992                         oob += chip->ecc.prepad;
 993                 }
 994
 995                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
 996                 chip->read_buf(mtd, oob, eccbytes);
 997                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 998
 999                 if (stat == -1)
1000                         mtd->ecc_stats.failed++;
1001                 else
1002                         mtd->ecc_stats.corrected += stat;
1003
1004                 oob += eccbytes;
1005
1006                 if (chip->ecc.postpad) {
1007                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1008                         oob += chip->ecc.postpad;
1009                 }
1010         }
1011
1012         /* Calculate remaining oob bytes */
1013         i = mtd->oobsize - (oob - chip->oob_poi);
1014         if (i)
1015                 chip->read_buf(mtd, oob, i);
1016
1017         return 0;
1018 }
1019
1020 /**
1021  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1022  * @chip:       nand chip structure
1023  * @oob:        oob destination address
1024  * @ops:        oob ops structure
1025  * @len:        size of oob to transfer
1026  */
1027 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1028                                   struct mtd_oob_ops *ops, size_t len)
1029 {
1030         switch(ops->mode) {
1031
1032         case MTD_OOB_PLACE:
1033         case MTD_OOB_RAW:
1034                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1035                 return oob + len;
1036
1037         case MTD_OOB_AUTO: {
1038                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1039                 uint32_t boffs = 0, roffs = ops->ooboffs;
1040                 size_t bytes = 0;
1041
1042                 for(; free->length && len; free++, len -= bytes) {
1043                         /* Read request not from offset 0 ? */
1044                         if (unlikely(roffs)) {
1045                                 if (roffs >= free->length) {
1046                                         roffs -= free->length;
1047                                         continue;
1048                                 }
1049                                 boffs = free->offset + roffs;
1050                                 bytes = min_t(size_t, len,
1051                                               (free->length - roffs));
1052                                 roffs = 0;
1053                         } else {
1054                                 bytes = min_t(size_t, len, free->length);
1055                                 boffs = free->offset;
1056                         }
1057                         memcpy(oob, chip->oob_poi + boffs, bytes);
1058                         oob += bytes;
1059                 }
1060                 return oob;
1061         }
1062         default:
1063                 BUG();
1064         }
1065         return NULL;
1066 }
1067
1068 /**
1069  * nand_do_read_ops - [Internal] Read data with ECC
1070  *
1071  * @mtd:        MTD device structure
1072  * @from:       offset to read from
1073  * @ops:        oob ops structure
1074  *
1075  * Internal function. Called with chip held.
1076  */
1077 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1078                             struct mtd_oob_ops *ops)
1079 {
1080         int chipnr, page, realpage, col, bytes, aligned;
1081         struct nand_chip *chip = mtd->priv;
1082         struct mtd_ecc_stats stats;
1083         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1084         int sndcmd = 1;
1085         int ret = 0;
1086         uint32_t readlen = ops->len;
1087         uint32_t oobreadlen = ops->ooblen;
1088         uint8_t *bufpoi, *oob, *buf;
1089
1090         stats = mtd->ecc_stats;
1091
1092         chipnr = (int)(from >> chip->chip_shift);
1093         chip->select_chip(mtd, chipnr);
1094
1095         realpage = (int)(from >> chip->page_shift);
1096         page = realpage & chip->pagemask;
1097
1098         col = (int)(from & (mtd->writesize - 1));
1099
1100         buf = ops->datbuf;
1101         oob = ops->oobbuf;
1102
1103         while(1) {
1104                 bytes = min(mtd->writesize - col, readlen);
1105                 aligned = (bytes == mtd->writesize);
1106
1107                 /* Is the current page in the buffer ? */
1108                 if (realpage != chip->pagebuf || oob) {
1109                         bufpoi = aligned ? buf : chip->buffers->databuf;
1110
1111                         if (likely(sndcmd)) {
1112                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1113                                 sndcmd = 0;
1114                         }
1115
1116                         /* Now read the page into the buffer */
1117                         if (unlikely(ops->mode == MTD_OOB_RAW))
1118                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1119                         else
1120                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1121                         if (ret < 0)
1122                                 break;
1123
1124                         /* Transfer not aligned data */
1125                         if (!aligned) {
1126                                 chip->pagebuf = realpage;
1127                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1128                         }
1129
1130                         buf += bytes;
1131
1132                         if (unlikely(oob)) {
1133                                 /* Raw mode does data:oob:data:oob */
1134                                 if (ops->mode != MTD_OOB_RAW) {
1135                                         int toread = min(oobreadlen,
1136                                                 chip->ecc.layout->oobavail);
1137                                         if (toread) {
1138                                                 oob = nand_transfer_oob(chip,
1139                                                         oob, ops, toread);
1140                                                 oobreadlen -= toread;
1141                                         }
1142                                 } else
1143                                         buf = nand_transfer_oob(chip,
1144                                                 buf, ops, mtd->oobsize);
1145                         }
1146
1147                         if (!(chip->options & NAND_NO_READRDY)) {
1148                                 /*
1149                                  * Apply delay or wait for ready/busy pin. Do
1150                                  * this before the AUTOINCR check, so no
1151                                  * problems arise if a chip which does auto
1152                                  * increment is marked as NOAUTOINCR by the
1153                                  * board driver.
1154                                  */
1155                                 if (!chip->dev_ready)
1156                                         udelay(chip->chip_delay);
1157                                 else
1158                                         nand_wait_ready(mtd);
1159                         }
1160                 } else {
1161                         memcpy(buf, chip->buffers->databuf + col, bytes);
1162                         buf += bytes;
1163                 }
1164
1165                 readlen -= bytes;
1166
1167                 if (!readlen)
1168                         break;
1169
1170                 /* For subsequent reads align to page boundary. */
1171                 col = 0;
1172                 /* Increment page address */
1173                 realpage++;
1174
1175                 page = realpage & chip->pagemask;
1176                 /* Check, if we cross a chip boundary */
1177                 if (!page) {
1178                         chipnr++;
1179                         chip->select_chip(mtd, -1);
1180                         chip->select_chip(mtd, chipnr);
1181                 }
1182
1183                 /* Check, if the chip supports auto page increment
1184                  * or if we have hit a block boundary.
1185                  */
1186                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1187                         sndcmd = 1;
1188         }
1189
1190         ops->retlen = ops->len - (size_t) readlen;
1191         if (oob)
1192                 ops->oobretlen = ops->ooblen - oobreadlen;
1193
1194         if (ret)
1195                 return ret;
1196
1197         if (mtd->ecc_stats.failed - stats.failed)
1198                 return -EBADMSG;
1199
1200         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1201 }
1202
1203 /**
1204  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1205  * @mtd:        MTD device structure
1206  * @from:       offset to read from
1207  * @len:        number of bytes to read
1208  * @retlen:     pointer to variable to store the number of read bytes
1209  * @buf:        the databuffer to put data
1210  *
1211  * Get hold of the chip and call nand_do_read
1212  */
1213 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1214                      size_t *retlen, uint8_t *buf)
1215 {
1216         struct nand_chip *chip = mtd->priv;
1217         int ret;
1218
1219         /* Do not allow reads past end of device */
1220         if ((from + len) > mtd->size)
1221                 return -EINVAL;
1222         if (!len)
1223                 return 0;
1224
1225         nand_get_device(chip, mtd, FL_READING);
1226
1227         chip->ops.len = len;
1228         chip->ops.datbuf = buf;
1229         chip->ops.oobbuf = NULL;
1230
1231         ret = nand_do_read_ops(mtd, from, &chip->ops);
1232
1233         *retlen = chip->ops.retlen;
1234
1235         nand_release_device(mtd);
1236
1237         return ret;
1238 }
1239
1240 /**
1241  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1242  * @mtd:        mtd info structure
1243  * @chip:       nand chip info structure
1244  * @page:       page number to read
1245  * @sndcmd:     flag whether to issue read command or not
1246  */
1247 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1248                              int page, int sndcmd)
1249 {
1250         if (sndcmd) {
1251                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1252                 sndcmd = 0;
1253         }
1254         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1255         return sndcmd;
1256 }
1257
1258 /**
1259  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1260  *                          with syndromes
1261  * @mtd:        mtd info structure
1262  * @chip:       nand chip info structure
1263  * @page:       page number to read
1264  * @sndcmd:     flag whether to issue read command or not
1265  */
1266 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1267                                   int page, int sndcmd)
1268 {
1269         uint8_t *buf = chip->oob_poi;
1270         int length = mtd->oobsize;
1271         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1272         int eccsize = chip->ecc.size;
1273         uint8_t *bufpoi = buf;
1274         int i, toread, sndrnd = 0, pos;
1275
1276         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1277         for (i = 0; i < chip->ecc.steps; i++) {
1278                 if (sndrnd) {
1279                         pos = eccsize + i * (eccsize + chunk);
1280                         if (mtd->writesize > 512)
1281                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1282                         else
1283                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1284                 } else
1285                         sndrnd = 1;
1286                 toread = min_t(int, length, chunk);
1287                 chip->read_buf(mtd, bufpoi, toread);
1288                 bufpoi += toread;
1289                 length -= toread;
1290         }
1291         if (length > 0)
1292                 chip->read_buf(mtd, bufpoi, length);
1293
1294         return 1;
1295 }
1296
1297 /**
1298  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1299  * @mtd:        mtd info structure
1300  * @chip:       nand chip info structure
1301  * @page:       page number to write
1302  */
1303 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1304                               int page)
1305 {
1306         int status = 0;
1307         const uint8_t *buf = chip->oob_poi;
1308         int length = mtd->oobsize;
1309
1310         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1311         chip->write_buf(mtd, buf, length);
1312         /* Send command to program the OOB data */
1313         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1314
1315         status = chip->waitfunc(mtd, chip);
1316
1317         return status & NAND_STATUS_FAIL ? -EIO : 0;
1318 }
1319
1320 /**
1321  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1322  *                           with syndrome - only for large page flash !
1323  * @mtd:        mtd info structure
1324  * @chip:       nand chip info structure
1325  * @page:       page number to write
1326  */
1327 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1328                                    struct nand_chip *chip, int page)
1329 {
1330         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1331         int eccsize = chip->ecc.size, length = mtd->oobsize;
1332         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1333         const uint8_t *bufpoi = chip->oob_poi;
1334
1335         /*
1336          * data-ecc-data-ecc ... ecc-oob
1337          * or
1338          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1339          */
1340         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1341                 pos = steps * (eccsize + chunk);
1342                 steps = 0;
1343         } else
1344                 pos = eccsize;
1345
1346         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1347         for (i = 0; i < steps; i++) {
1348                 if (sndcmd) {
1349                         if (mtd->writesize <= 512) {
1350                                 uint32_t fill = 0xFFFFFFFF;
1351
1352                                 len = eccsize;
1353                                 while (len > 0) {
1354                                         int num = min_t(int, len, 4);
1355                                         chip->write_buf(mtd, (uint8_t *)&fill,
1356                                                         num);
1357                                         len -= num;
1358                                 }
1359                         } else {
1360                                 pos = eccsize + i * (eccsize + chunk);
1361                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1362                         }
1363                 } else
1364                         sndcmd = 1;
1365                 len = min_t(int, length, chunk);
1366                 chip->write_buf(mtd, bufpoi, len);
1367                 bufpoi += len;
1368                 length -= len;
1369         }
1370         if (length > 0)
1371                 chip->write_buf(mtd, bufpoi, length);
1372
1373         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1374         status = chip->waitfunc(mtd, chip);
1375
1376         return status & NAND_STATUS_FAIL ? -EIO : 0;
1377 }
1378
1379 /**
1380  * nand_do_read_oob - [Intern] NAND read out-of-band
1381  * @mtd:        MTD device structure
1382  * @from:       offset to read from
1383  * @ops:        oob operations description structure
1384  *
1385  * NAND read out-of-band data from the spare area
1386  */
1387 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1388                             struct mtd_oob_ops *ops)
1389 {
1390         int page, realpage, chipnr, sndcmd = 1;
1391         struct nand_chip *chip = mtd->priv;
1392         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1393         int readlen = ops->ooblen;
1394         int len;
1395         uint8_t *buf = ops->oobbuf;
1396
1397         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1398                   (unsigned long long)from, readlen);
1399
1400         if (ops->mode == MTD_OOB_AUTO)
1401                 len = chip->ecc.layout->oobavail;
1402         else
1403                 len = mtd->oobsize;
1404
1405         if (unlikely(ops->ooboffs >= len)) {
1406                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1407                           "Attempt to start read outside oob\n");
1408                 return -EINVAL;
1409         }
1410
1411         /* Do not allow reads past end of device */
1412         if (unlikely(from >= mtd->size ||
1413                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1414                                         (from >> chip->page_shift)) * len)) {
1415                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1416                           "Attempt read beyond end of device\n");
1417                 return -EINVAL;
1418         }
1419
1420         chipnr = (int)(from >> chip->chip_shift);
1421         chip->select_chip(mtd, chipnr);
1422
1423         /* Shift to get page */
1424         realpage = (int)(from >> chip->page_shift);
1425         page = realpage & chip->pagemask;
1426
1427         while(1) {
1428                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1429
1430                 len = min(len, readlen);
1431                 buf = nand_transfer_oob(chip, buf, ops, len);
1432
1433                 if (!(chip->options & NAND_NO_READRDY)) {
1434                         /*
1435                          * Apply delay or wait for ready/busy pin. Do this
1436                          * before the AUTOINCR check, so no problems arise if a
1437                          * chip which does auto increment is marked as
1438                          * NOAUTOINCR by the board driver.
1439                          */
1440                         if (!chip->dev_ready)
1441                                 udelay(chip->chip_delay);
1442                         else
1443                                 nand_wait_ready(mtd);
1444                 }
1445
1446                 readlen -= len;
1447                 if (!readlen)
1448                         break;
1449
1450                 /* Increment page address */
1451                 realpage++;
1452
1453                 page = realpage & chip->pagemask;
1454                 /* Check, if we cross a chip boundary */
1455                 if (!page) {
1456                         chipnr++;
1457                         chip->select_chip(mtd, -1);
1458                         chip->select_chip(mtd, chipnr);
1459                 }
1460
1461                 /* Check, if the chip supports auto page increment
1462                  * or if we have hit a block boundary.
1463                  */
1464                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1465                         sndcmd = 1;
1466         }
1467
1468         ops->oobretlen = ops->ooblen;
1469         return 0;
1470 }
1471
1472 /**
1473  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1474  * @mtd:        MTD device structure
1475  * @from:       offset to read from
1476  * @ops:        oob operation description structure
1477  *
1478  * NAND read data and/or out-of-band data
1479  */
1480 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1481                          struct mtd_oob_ops *ops)
1482 {
1483         struct nand_chip *chip = mtd->priv;
1484         int ret = -ENOTSUPP;
1485
1486         ops->retlen = 0;
1487
1488         /* Do not allow reads past end of device */
1489         if (ops->datbuf && (from + ops->len) > mtd->size) {
1490                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1491                           "Attempt read beyond end of device\n");
1492                 return -EINVAL;
1493         }
1494
1495         nand_get_device(chip, mtd, FL_READING);
1496
1497         switch(ops->mode) {
1498         case MTD_OOB_PLACE:
1499         case MTD_OOB_AUTO:
1500         case MTD_OOB_RAW:
1501                 break;
1502
1503         default:
1504                 goto out;
1505         }
1506
1507         if (!ops->datbuf)
1508                 ret = nand_do_read_oob(mtd, from, ops);
1509         else
1510                 ret = nand_do_read_ops(mtd, from, ops);
1511
1512  out:
1513         nand_release_device(mtd);
1514         return ret;
1515 }
1516
1517
1518 /**
1519  * nand_write_page_raw - [Intern] raw page write function
1520  * @mtd:        mtd info structure
1521  * @chip:       nand chip info structure
1522  * @buf:        data buffer
1523  */
1524 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1525                                 const uint8_t *buf)
1526 {
1527         chip->write_buf(mtd, buf, mtd->writesize);
1528         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1529 }
1530
1531 /**
1532  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1533  * @mtd:        mtd info structure
1534  * @chip:       nand chip info structure
1535  * @buf:        data buffer
1536  */
1537 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1538                                   const uint8_t *buf)
1539 {
1540         int i, eccsize = chip->ecc.size;
1541         int eccbytes = chip->ecc.bytes;
1542         int eccsteps = chip->ecc.steps;
1543         uint8_t *ecc_calc = chip->buffers->ecccalc;
1544         const uint8_t *p = buf;
1545         uint32_t *eccpos = chip->ecc.layout->eccpos;
1546
1547         /* Software ecc calculation */
1548         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1549                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1550
1551         for (i = 0; i < chip->ecc.total; i++)
1552                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1553
1554         chip->ecc.write_page_raw(mtd, chip, buf);
1555 }
1556
1557 /**
1558  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1559  * @mtd:        mtd info structure
1560  * @chip:       nand chip info structure
1561  * @buf:        data buffer
1562  */
1563 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1564                                   const uint8_t *buf)
1565 {
1566         int i, eccsize = chip->ecc.size;
1567         int eccbytes = chip->ecc.bytes;
1568         int eccsteps = chip->ecc.steps;
1569         uint8_t *ecc_calc = chip->buffers->ecccalc;
1570         const uint8_t *p = buf;
1571         uint32_t *eccpos = chip->ecc.layout->eccpos;
1572
1573         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1574                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1575                 chip->write_buf(mtd, p, eccsize);
1576                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1577         }
1578
1579         for (i = 0; i < chip->ecc.total; i++)
1580                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1581
1582         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1583 }
1584
1585 /**
1586  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1587  * @mtd:        mtd info structure
1588  * @chip:       nand chip info structure
1589  * @buf:        data buffer
1590  *
1591  * The hw generator calculates the error syndrome automatically. Therefor
1592  * we need a special oob layout and handling.
1593  */
1594 static void nand_write_page_syndrome(struct mtd_info *mtd,
1595                                     struct nand_chip *chip, const uint8_t *buf)
1596 {
1597         int i, eccsize = chip->ecc.size;
1598         int eccbytes = chip->ecc.bytes;
1599         int eccsteps = chip->ecc.steps;
1600         const uint8_t *p = buf;
1601         uint8_t *oob = chip->oob_poi;
1602
1603         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1604
1605                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1606                 chip->write_buf(mtd, p, eccsize);
1607
1608                 if (chip->ecc.prepad) {
1609                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1610                         oob += chip->ecc.prepad;
1611                 }
1612
1613                 chip->ecc.calculate(mtd, p, oob);
1614                 chip->write_buf(mtd, oob, eccbytes);
1615                 oob += eccbytes;
1616
1617                 if (chip->ecc.postpad) {
1618                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1619                         oob += chip->ecc.postpad;
1620                 }
1621         }
1622
1623         /* Calculate remaining oob bytes */
1624         i = mtd->oobsize - (oob - chip->oob_poi);
1625         if (i)
1626                 chip->write_buf(mtd, oob, i);
1627 }
1628
1629 /**
1630  * nand_write_page - [REPLACEABLE] write one page
1631  * @mtd:        MTD device structure
1632  * @chip:       NAND chip descriptor
1633  * @buf:        the data to write
1634  * @page:       page number to write
1635  * @cached:     cached programming
1636  * @raw:        use _raw version of write_page
1637  */
1638 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1639                            const uint8_t *buf, int page, int cached, int raw)
1640 {
1641         int status;
1642
1643         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1644
1645         if (unlikely(raw))
1646                 chip->ecc.write_page_raw(mtd, chip, buf);
1647         else
1648                 chip->ecc.write_page(mtd, chip, buf);
1649
1650         /*
1651          * Cached progamming disabled for now, Not sure if its worth the
1652          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1653          */
1654         cached = 0;
1655
1656         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1657
1658                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1659                 status = chip->waitfunc(mtd, chip);
1660                 /*
1661                  * See if operation failed and additional status checks are
1662                  * available
1663                  */
1664                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1665                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1666                                                page);
1667
1668                 if (status & NAND_STATUS_FAIL)
1669                         return -EIO;
1670         } else {
1671                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1672                 status = chip->waitfunc(mtd, chip);
1673         }
1674
1675 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1676         /* Send command to read back the data */
1677         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1678
1679         if (chip->verify_buf(mtd, buf, mtd->writesize))
1680                 return -EIO;
1681 #endif
1682         return 0;
1683 }
1684
1685 /**
1686  * nand_fill_oob - [Internal] Transfer client buffer to oob
1687  * @chip:       nand chip structure
1688  * @oob:        oob data buffer
1689  * @ops:        oob ops structure
1690  */
1691 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1692                                   struct mtd_oob_ops *ops)
1693 {
1694         size_t len = ops->ooblen;
1695
1696         switch(ops->mode) {
1697
1698         case MTD_OOB_PLACE:
1699         case MTD_OOB_RAW:
1700                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1701                 return oob + len;
1702
1703         case MTD_OOB_AUTO: {
1704                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1705                 uint32_t boffs = 0, woffs = ops->ooboffs;
1706                 size_t bytes = 0;
1707
1708                 for(; free->length && len; free++, len -= bytes) {
1709                         /* Write request not from offset 0 ? */
1710                         if (unlikely(woffs)) {
1711                                 if (woffs >= free->length) {
1712                                         woffs -= free->length;
1713                                         continue;
1714                                 }
1715                                 boffs = free->offset + woffs;
1716                                 bytes = min_t(size_t, len,
1717                                               (free->length - woffs));
1718                                 woffs = 0;
1719                         } else {
1720                                 bytes = min_t(size_t, len, free->length);
1721                                 boffs = free->offset;
1722                         }
1723                         memcpy(chip->oob_poi + boffs, oob, bytes);
1724                         oob += bytes;
1725                 }
1726                 return oob;
1727         }
1728         default:
1729                 BUG();
1730         }
1731         return NULL;
1732 }
1733
1734 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1735
1736 /**
1737  * nand_do_write_ops - [Internal] NAND write with ECC
1738  * @mtd:        MTD device structure
1739  * @to:         offset to write to
1740  * @ops:        oob operations description structure
1741  *
1742  * NAND write with ECC
1743  */
1744 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1745                              struct mtd_oob_ops *ops)
1746 {
1747         int chipnr, realpage, page, blockmask, column;
1748         struct nand_chip *chip = mtd->priv;
1749         uint32_t writelen = ops->len;
1750         uint8_t *oob = ops->oobbuf;
1751         uint8_t *buf = ops->datbuf;
1752         int ret, subpage;
1753
1754         ops->retlen = 0;
1755         if (!writelen)
1756                 return 0;
1757
1758         /* reject writes, which are not page aligned */
1759         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1760                 printk(KERN_NOTICE "nand_write: "
1761                        "Attempt to write not page aligned data\n");
1762                 return -EINVAL;
1763         }
1764
1765         column = to & (mtd->writesize - 1);
1766         subpage = column || (writelen & (mtd->writesize - 1));
1767
1768         if (subpage && oob)
1769                 return -EINVAL;
1770
1771         chipnr = (int)(to >> chip->chip_shift);
1772         chip->select_chip(mtd, chipnr);
1773
1774         /* Check, if it is write protected */
1775         if (nand_check_wp(mtd)) {
1776                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1777                 return -EIO;
1778         }
1779
1780         realpage = (int)(to >> chip->page_shift);
1781         page = realpage & chip->pagemask;
1782         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1783
1784         /* Invalidate the page cache, when we write to the cached page */
1785         if (to <= (chip->pagebuf << chip->page_shift) &&
1786             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1787                 chip->pagebuf = -1;
1788
1789         /* If we're not given explicit OOB data, let it be 0xFF */
1790         if (likely(!oob))
1791                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1792
1793         while(1) {
1794                 int bytes = mtd->writesize;
1795                 int cached = writelen > bytes && page != blockmask;
1796                 uint8_t *wbuf = buf;
1797
1798                 /* Partial page write ? */
1799                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1800                         cached = 0;
1801                         bytes = min_t(int, bytes - column, (int) writelen);
1802                         chip->pagebuf = -1;
1803                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1804                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1805                         wbuf = chip->buffers->databuf;
1806                 }
1807
1808                 if (unlikely(oob))
1809                         oob = nand_fill_oob(chip, oob, ops);
1810
1811                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1812                                        (ops->mode == MTD_OOB_RAW));
1813                 if (ret)
1814                         break;
1815
1816                 writelen -= bytes;
1817                 if (!writelen)
1818                         break;
1819
1820                 column = 0;
1821                 buf += bytes;
1822                 realpage++;
1823
1824                 page = realpage & chip->pagemask;
1825                 /* Check, if we cross a chip boundary */
1826                 if (!page) {
1827                         chipnr++;
1828                         chip->select_chip(mtd, -1);
1829                         chip->select_chip(mtd, chipnr);
1830                 }
1831         }
1832
1833         ops->retlen = ops->len - writelen;
1834         if (unlikely(oob))
1835                 ops->oobretlen = ops->ooblen;
1836         return ret;
1837 }
1838
1839 /**
1840  * nand_write - [MTD Interface] NAND write with ECC
1841  * @mtd:        MTD device structure
1842  * @to:         offset to write to
1843  * @len:        number of bytes to write
1844  * @retlen:     pointer to variable to store the number of written bytes
1845  * @buf:        the data to write
1846  *
1847  * NAND write with ECC
1848  */
1849 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1850                           size_t *retlen, const uint8_t *buf)
1851 {
1852         struct nand_chip *chip = mtd->priv;
1853         int ret;
1854
1855         /* Do not allow reads past end of device */
1856         if ((to + len) > mtd->size)
1857                 return -EINVAL;
1858         if (!len)
1859                 return 0;
1860
1861         nand_get_device(chip, mtd, FL_WRITING);
1862
1863         chip->ops.len = len;
1864         chip->ops.datbuf = (uint8_t *)buf;
1865         chip->ops.oobbuf = NULL;
1866
1867         ret = nand_do_write_ops(mtd, to, &chip->ops);
1868
1869         *retlen = chip->ops.retlen;
1870
1871         nand_release_device(mtd);
1872
1873         return ret;
1874 }
1875
1876 /**
1877  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1878  * @mtd:        MTD device structure
1879  * @to:         offset to write to
1880  * @ops:        oob operation description structure
1881  *
1882  * NAND write out-of-band
1883  */
1884 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1885                              struct mtd_oob_ops *ops)
1886 {
1887         int chipnr, page, status, len;
1888         struct nand_chip *chip = mtd->priv;
1889
1890         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1891                   (unsigned int)to, (int)ops->ooblen);
1892
1893         if (ops->mode == MTD_OOB_AUTO)
1894                 len = chip->ecc.layout->oobavail;
1895         else
1896                 len = mtd->oobsize;
1897
1898         /* Do not allow write past end of page */
1899         if ((ops->ooboffs + ops->ooblen) > len) {
1900                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1901                           "Attempt to write past end of page\n");
1902                 return -EINVAL;
1903         }
1904
1905         if (unlikely(ops->ooboffs >= len)) {
1906                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1907                           "Attempt to start write outside oob\n");
1908                 return -EINVAL;
1909         }
1910
1911         /* Do not allow reads past end of device */
1912         if (unlikely(to >= mtd->size ||
1913                      ops->ooboffs + ops->ooblen >
1914                         ((mtd->size >> chip->page_shift) -
1915                          (to >> chip->page_shift)) * len)) {
1916                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1917                           "Attempt write beyond end of device\n");
1918                 return -EINVAL;
1919         }
1920
1921         chipnr = (int)(to >> chip->chip_shift);
1922         chip->select_chip(mtd, chipnr);
1923
1924         /* Shift to get page */
1925         page = (int)(to >> chip->page_shift);
1926
1927         /*
1928          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1929          * of my DiskOnChip 2000 test units) will clear the whole data page too
1930          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1931          * it in the doc2000 driver in August 1999.  dwmw2.
1932          */
1933         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1934
1935         /* Check, if it is write protected */
1936         if (nand_check_wp(mtd))
1937                 return -EROFS;
1938
1939         /* Invalidate the page cache, if we write to the cached page */
1940         if (page == chip->pagebuf)
1941                 chip->pagebuf = -1;
1942
1943         memset(chip->oob_poi, 0xff, mtd->oobsize);
1944         nand_fill_oob(chip, ops->oobbuf, ops);
1945         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1946         memset(chip->oob_poi, 0xff, mtd->oobsize);
1947
1948         if (status)
1949                 return status;
1950
1951         ops->oobretlen = ops->ooblen;
1952
1953         return 0;
1954 }
1955
1956 /**
1957  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1958  * @mtd:        MTD device structure
1959  * @to:         offset to write to
1960  * @ops:        oob operation description structure
1961  */
1962 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1963                           struct mtd_oob_ops *ops)
1964 {
1965         struct nand_chip *chip = mtd->priv;
1966         int ret = -ENOTSUPP;
1967
1968         ops->retlen = 0;
1969
1970         /* Do not allow writes past end of device */
1971         if (ops->datbuf && (to + ops->len) > mtd->size) {
1972                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1973                           "Attempt read beyond end of device\n");
1974                 return -EINVAL;
1975         }
1976
1977         nand_get_device(chip, mtd, FL_WRITING);
1978
1979         switch(ops->mode) {
1980         case MTD_OOB_PLACE:
1981         case MTD_OOB_AUTO:
1982         case MTD_OOB_RAW:
1983                 break;
1984
1985         default:
1986                 goto out;
1987         }
1988
1989         if (!ops->datbuf)
1990                 ret = nand_do_write_oob(mtd, to, ops);
1991         else
1992                 ret = nand_do_write_ops(mtd, to, ops);
1993
1994  out:
1995         nand_release_device(mtd);
1996         return ret;
1997 }
1998
1999 /**
2000  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2001  * @mtd:        MTD device structure
2002  * @page:       the page address of the block which will be erased
2003  *
2004  * Standard erase command for NAND chips
2005  */
2006 static void single_erase_cmd(struct mtd_info *mtd, int page)
2007 {
2008         struct nand_chip *chip = mtd->priv;
2009         /* Send commands to erase a block */
2010         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2011         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2012 }
2013
2014 /**
2015  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2016  * @mtd:        MTD device structure
2017  * @page:       the page address of the block which will be erased
2018  *
2019  * AND multi block erase command function
2020  * Erase 4 consecutive blocks
2021  */
2022 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2023 {
2024         struct nand_chip *chip = mtd->priv;
2025         /* Send commands to erase a block */
2026         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2027         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2028         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2029         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2030         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2031 }
2032
2033 /**
2034  * nand_erase - [MTD Interface] erase block(s)
2035  * @mtd:        MTD device structure
2036  * @instr:      erase instruction
2037  *
2038  * Erase one ore more blocks
2039  */
2040 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2041 {
2042         return nand_erase_nand(mtd, instr, 0);
2043 }
2044
2045 #define BBT_PAGE_MASK   0xffffff3f
2046 /**
2047  * nand_erase_nand - [Internal] erase block(s)
2048  * @mtd:        MTD device structure
2049  * @instr:      erase instruction
2050  * @allowbbt:   allow erasing the bbt area
2051  *
2052  * Erase one ore more blocks
2053  */
2054 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2055                     int allowbbt)
2056 {
2057         int page, len, status, pages_per_block, ret, chipnr;
2058         struct nand_chip *chip = mtd->priv;
2059         int rewrite_bbt[NAND_MAX_CHIPS]={0};
2060         unsigned int bbt_masked_page = 0xffffffff;
2061
2062         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2063                   (unsigned int) instr->addr, (unsigned int) instr->len);
2064
2065         /* Start address must align on block boundary */
2066         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2067                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2068                 return -EINVAL;
2069         }
2070
2071         /* Length must align on block boundary */
2072         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2073                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2074                           "nand_erase: Length not block aligned\n");
2075                 return -EINVAL;
2076         }
2077
2078         /* Do not allow erase past end of device */
2079         if ((instr->len + instr->addr) > mtd->size) {
2080                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2081                           "nand_erase: Erase past end of device\n");
2082                 return -EINVAL;
2083         }
2084
2085         instr->fail_addr = 0xffffffff;
2086
2087         /* Grab the lock and see if the device is available */
2088         nand_get_device(chip, mtd, FL_ERASING);
2089
2090         /* Shift to get first page */
2091         page = (int)(instr->addr >> chip->page_shift);
2092         chipnr = (int)(instr->addr >> chip->chip_shift);
2093
2094         /* Calculate pages in each block */
2095         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2096
2097         /* Select the NAND device */
2098         chip->select_chip(mtd, chipnr);
2099
2100         /* Check, if it is write protected */
2101         if (nand_check_wp(mtd)) {
2102                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2103                           "nand_erase: Device is write protected!!!\n");
2104                 instr->state = MTD_ERASE_FAILED;
2105                 goto erase_exit;
2106         }
2107
2108         /*
2109          * If BBT requires refresh, set the BBT page mask to see if the BBT
2110          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2111          * can not be matched. This is also done when the bbt is actually
2112          * erased to avoid recusrsive updates
2113          */
2114         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2115                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2116
2117         /* Loop through the pages */
2118         len = instr->len;
2119
2120         instr->state = MTD_ERASING;
2121
2122         while (len) {
2123                 /*
2124                  * heck if we have a bad block, we do not erase bad blocks !
2125                  */
2126                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2127                                         chip->page_shift, 0, allowbbt)) {
2128                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2129                                "bad block at page 0x%08x\n", page);
2130                         instr->state = MTD_ERASE_FAILED;
2131                         goto erase_exit;
2132                 }
2133
2134                 /*
2135                  * Invalidate the page cache, if we erase the block which
2136                  * contains the current cached page
2137                  */
2138                 if (page <= chip->pagebuf && chip->pagebuf <
2139                     (page + pages_per_block))
2140                         chip->pagebuf = -1;
2141
2142                 chip->erase_cmd(mtd, page & chip->pagemask);
2143
2144                 status = chip->waitfunc(mtd, chip);
2145
2146                 /*
2147                  * See if operation failed and additional status checks are
2148                  * available
2149                  */
2150                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2151                         status = chip->errstat(mtd, chip, FL_ERASING,
2152                                                status, page);
2153
2154                 /* See if block erase succeeded */
2155                 if (status & NAND_STATUS_FAIL) {
2156                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2157                                   "Failed erase, page 0x%08x\n", page);
2158                         instr->state = MTD_ERASE_FAILED;
2159                         instr->fail_addr = (page << chip->page_shift);
2160                         goto erase_exit;
2161                 }
2162
2163                 /*
2164                  * If BBT requires refresh, set the BBT rewrite flag to the
2165                  * page being erased
2166                  */
2167                 if (bbt_masked_page != 0xffffffff &&
2168                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2169                             rewrite_bbt[chipnr] = (page << chip->page_shift);
2170
2171                 /* Increment page address and decrement length */
2172                 len -= (1 << chip->phys_erase_shift);
2173                 page += pages_per_block;
2174
2175                 /* Check, if we cross a chip boundary */
2176                 if (len && !(page & chip->pagemask)) {
2177                         chipnr++;
2178                         chip->select_chip(mtd, -1);
2179                         chip->select_chip(mtd, chipnr);
2180
2181                         /*
2182                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2183                          * page mask to see if this BBT should be rewritten
2184                          */
2185                         if (bbt_masked_page != 0xffffffff &&
2186                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2187                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2188                                         BBT_PAGE_MASK;
2189                 }
2190         }
2191         instr->state = MTD_ERASE_DONE;
2192
2193  erase_exit:
2194
2195         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2196         /* Do call back function */
2197         if (!ret)
2198                 mtd_erase_callback(instr);
2199
2200         /* Deselect and wake up anyone waiting on the device */
2201         nand_release_device(mtd);
2202
2203         /*
2204          * If BBT requires refresh and erase was successful, rewrite any
2205          * selected bad block tables
2206          */
2207         if (bbt_masked_page == 0xffffffff || ret)
2208                 return ret;
2209
2210         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2211                 if (!rewrite_bbt[chipnr])
2212                         continue;
2213                 /* update the BBT for chip */
2214                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2215                           "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2216                           chip->bbt_td->pages[chipnr]);
2217                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2218         }
2219
2220         /* Return more or less happy */
2221         return ret;
2222 }
2223
2224 /**
2225  * nand_sync - [MTD Interface] sync
2226  * @mtd:        MTD device structure
2227  *
2228  * Sync is actually a wait for chip ready function
2229  */
2230 static void nand_sync(struct mtd_info *mtd)
2231 {
2232         struct nand_chip *chip = mtd->priv;
2233
2234         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2235
2236         /* Grab the lock and see if the device is available */
2237         nand_get_device(chip, mtd, FL_SYNCING);
2238         /* Release it and go back */
2239         nand_release_device(mtd);
2240 }
2241
2242 /**
2243  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2244  * @mtd:        MTD device structure
2245  * @offs:       offset relative to mtd start
2246  */
2247 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2248 {
2249         /* Check for invalid offset */
2250         if (offs > mtd->size)
2251                 return -EINVAL;
2252
2253         return nand_block_checkbad(mtd, offs, 1, 0);
2254 }
2255
2256 /**
2257  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2258  * @mtd:        MTD device structure
2259  * @ofs:        offset relative to mtd start
2260  */
2261 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2262 {
2263         struct nand_chip *chip = mtd->priv;
2264         int ret;
2265
2266         if ((ret = nand_block_isbad(mtd, ofs))) {
2267                 /* If it was bad already, return success and do nothing. */
2268                 if (ret > 0)
2269                         return 0;
2270                 return ret;
2271         }
2272
2273         return chip->block_markbad(mtd, ofs);
2274 }
2275
2276 /**
2277  * nand_suspend - [MTD Interface] Suspend the NAND flash
2278  * @mtd:        MTD device structure
2279  */
2280 static int nand_suspend(struct mtd_info *mtd)
2281 {
2282         struct nand_chip *chip = mtd->priv;
2283
2284         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2285 }
2286
2287 /**
2288  * nand_resume - [MTD Interface] Resume the NAND flash
2289  * @mtd:        MTD device structure
2290  */
2291 static void nand_resume(struct mtd_info *mtd)
2292 {
2293         struct nand_chip *chip = mtd->priv;
2294
2295         if (chip->state == FL_PM_SUSPENDED)
2296                 nand_release_device(mtd);
2297         else
2298                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2299                        "in suspended state\n");
2300 }
2301
2302 /*
2303  * Set default functions
2304  */
2305 static void nand_set_defaults(struct nand_chip *chip, int busw)
2306 {
2307         /* check for proper chip_delay setup, set 20us if not */
2308         if (!chip->chip_delay)
2309                 chip->chip_delay = 20;
2310
2311         /* check, if a user supplied command function given */
2312         if (chip->cmdfunc == NULL)
2313                 chip->cmdfunc = nand_command;
2314
2315         /* check, if a user supplied wait function given */
2316         if (chip->waitfunc == NULL)
2317                 chip->waitfunc = nand_wait;
2318
2319         if (!chip->select_chip)
2320                 chip->select_chip = nand_select_chip;
2321         if (!chip->read_byte)
2322                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2323         if (!chip->read_word)
2324                 chip->read_word = nand_read_word;
2325         if (!chip->block_bad)
2326                 chip->block_bad = nand_block_bad;
2327         if (!chip->block_markbad)
2328                 chip->block_markbad = nand_default_block_markbad;
2329         if (!chip->write_buf)
2330                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2331         if (!chip->read_buf)
2332                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2333         if (!chip->verify_buf)
2334                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2335         if (!chip->scan_bbt)
2336                 chip->scan_bbt = nand_default_bbt;
2337
2338         if (!chip->controller) {
2339                 chip->controller = &chip->hwcontrol;
2340
2341                 /* XXX U-BOOT XXX */
2342 #if 0
2343                 spin_lock_init(&chip->controller->lock);
2344                 init_waitqueue_head(&chip->controller->wq);
2345 #endif
2346         }
2347
2348 }
2349
2350 /*
2351  * Get the flash and manufacturer id and lookup if the type is supported
2352  */
2353 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2354                                                   struct nand_chip *chip,
2355                                                   int busw, int *maf_id)
2356 {
2357         struct nand_flash_dev *type = NULL;
2358         int i, dev_id, maf_idx;
2359
2360         /* Select the device */
2361         chip->select_chip(mtd, 0);
2362
2363         /* Send the command for reading device ID */
2364         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2365
2366         /* Read manufacturer and device IDs */
2367         *maf_id = chip->read_byte(mtd);
2368         dev_id = chip->read_byte(mtd);
2369
2370         /* Lookup the flash id */
2371         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2372                 if (dev_id == nand_flash_ids[i].id) {
2373                         type =  &nand_flash_ids[i];
2374                         break;
2375                 }
2376         }
2377
2378         if (!type)
2379                 return ERR_PTR(-ENODEV);
2380
2381         if (!mtd->name)
2382                 mtd->name = type->name;
2383
2384         chip->chipsize = type->chipsize << 20;
2385
2386         /* Newer devices have all the information in additional id bytes */
2387         if (!type->pagesize) {
2388                 int extid;
2389                 /* The 3rd id byte holds MLC / multichip data */
2390                 chip->cellinfo = chip->read_byte(mtd);
2391                 /* The 4th id byte is the important one */
2392                 extid = chip->read_byte(mtd);
2393                 /* Calc pagesize */
2394                 mtd->writesize = 1024 << (extid & 0x3);
2395                 extid >>= 2;
2396                 /* Calc oobsize */
2397                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2398                 extid >>= 2;
2399                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2400                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2401                 extid >>= 2;
2402                 /* Get buswidth information */
2403                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2404
2405         } else {
2406                 /*
2407                  * Old devices have chip data hardcoded in the device id table
2408                  */
2409                 mtd->erasesize = type->erasesize;
2410                 mtd->writesize = type->pagesize;
2411                 mtd->oobsize = mtd->writesize / 32;
2412                 busw = type->options & NAND_BUSWIDTH_16;
2413         }
2414
2415         /* Try to identify manufacturer */
2416         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2417                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2418                         break;
2419         }
2420
2421         /*
2422          * Check, if buswidth is correct. Hardware drivers should set
2423          * chip correct !
2424          */
2425         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2426                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2427                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2428                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2429                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2430                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2431                        busw ? 16 : 8);
2432                 return ERR_PTR(-EINVAL);
2433         }
2434
2435         /* Calculate the address shift from the page size */
2436         chip->page_shift = ffs(mtd->writesize) - 1;
2437         /* Convert chipsize to number of pages per chip -1. */
2438         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2439
2440         chip->bbt_erase_shift = chip->phys_erase_shift =
2441                 ffs(mtd->erasesize) - 1;
2442         chip->chip_shift = ffs(chip->chipsize) - 1;
2443
2444         /* Set the bad block position */
2445         chip->badblockpos = mtd->writesize > 512 ?
2446                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2447
2448         /* Get chip options, preserve non chip based options */
2449         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2450         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2451
2452         /*
2453          * Set chip as a default. Board drivers can override it, if necessary
2454          */
2455         chip->options |= NAND_NO_AUTOINCR;
2456
2457         /* Check if chip is a not a samsung device. Do not clear the
2458          * options for chips which are not having an extended id.
2459          */
2460         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2461                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2462
2463         /* Check for AND chips with 4 page planes */
2464         if (chip->options & NAND_4PAGE_ARRAY)
2465                 chip->erase_cmd = multi_erase_cmd;
2466         else
2467                 chip->erase_cmd = single_erase_cmd;
2468
2469         /* Do not replace user supplied command function ! */
2470         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2471                 chip->cmdfunc = nand_command_lp;
2472
2473         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2474                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2475                   nand_manuf_ids[maf_idx].name, type->name);
2476
2477         return type;
2478 }
2479
2480 /**
2481  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2482  * @mtd:             MTD device structure
2483  * @maxchips:        Number of chips to scan for
2484  *
2485  * This is the first phase of the normal nand_scan() function. It
2486  * reads the flash ID and sets up MTD fields accordingly.
2487  *
2488  * The mtd->owner field must be set to the module of the caller.
2489  */
2490 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2491 {
2492         int i, busw, nand_maf_id;
2493         struct nand_chip *chip = mtd->priv;
2494         struct nand_flash_dev *type;
2495
2496         /* Get buswidth to select the correct functions */
2497         busw = chip->options & NAND_BUSWIDTH_16;
2498         /* Set the default functions */
2499         nand_set_defaults(chip, busw);
2500
2501         /* Read the flash type */
2502         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2503
2504         if (IS_ERR(type)) {
2505                 printk(KERN_WARNING "No NAND device found!!!\n");
2506                 chip->select_chip(mtd, -1);
2507                 return PTR_ERR(type);
2508         }
2509
2510         /* Check for a chip array */
2511         for (i = 1; i < maxchips; i++) {
2512                 chip->select_chip(mtd, i);
2513                 /* Send the command for reading device ID */
2514                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2515                 /* Read manufacturer and device IDs */
2516                 if (nand_maf_id != chip->read_byte(mtd) ||
2517                     type->id != chip->read_byte(mtd))
2518                         break;
2519         }
2520         if (i > 1)
2521                 printk(KERN_INFO "%d NAND chips detected\n", i);
2522
2523         /* Store the number of chips and calc total size for mtd */
2524         chip->numchips = i;
2525         mtd->size = i * chip->chipsize;
2526
2527         return 0;
2528 }
2529
2530
2531 /**
2532  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2533  * @mtd:            MTD device structure
2534  * @maxchips:       Number of chips to scan for
2535  *
2536  * This is the second phase of the normal nand_scan() function. It
2537  * fills out all the uninitialized function pointers with the defaults
2538  * and scans for a bad block table if appropriate.
2539  */
2540 int nand_scan_tail(struct mtd_info *mtd)
2541 {
2542         int i;
2543         struct nand_chip *chip = mtd->priv;
2544
2545         if (!(chip->options & NAND_OWN_BUFFERS))
2546                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2547         if (!chip->buffers)
2548                 return -ENOMEM;
2549
2550         /* Set the internal oob buffer location, just after the page data */
2551         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2552
2553         /*
2554          * If no default placement scheme is given, select an appropriate one
2555          */
2556         if (!chip->ecc.layout) {
2557                 switch (mtd->oobsize) {
2558                 case 8:
2559                         chip->ecc.layout = &nand_oob_8;
2560                         break;
2561                 case 16:
2562                         chip->ecc.layout = &nand_oob_16;
2563                         break;
2564                 case 64:
2565                         chip->ecc.layout = &nand_oob_64;
2566                         break;
2567                 case 128:
2568                         chip->ecc.layout = &nand_oob_128;
2569                         break;
2570                 default:
2571                         printk(KERN_WARNING "No oob scheme defined for "
2572                                "oobsize %d\n", mtd->oobsize);
2573 /*                      BUG(); */
2574                 }
2575         }
2576
2577         if (!chip->write_page)
2578                 chip->write_page = nand_write_page;
2579
2580         /*
2581          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2582          * selected and we have 256 byte pagesize fallback to software ECC
2583          */
2584         if (!chip->ecc.read_page_raw)
2585                 chip->ecc.read_page_raw = nand_read_page_raw;
2586         if (!chip->ecc.write_page_raw)
2587                 chip->ecc.write_page_raw = nand_write_page_raw;
2588
2589         switch (chip->ecc.mode) {
2590         case NAND_ECC_HW:
2591                 /* Use standard hwecc read page function ? */
2592                 if (!chip->ecc.read_page)
2593                         chip->ecc.read_page = nand_read_page_hwecc;
2594                 if (!chip->ecc.write_page)
2595                         chip->ecc.write_page = nand_write_page_hwecc;
2596                 if (!chip->ecc.read_oob)
2597                         chip->ecc.read_oob = nand_read_oob_std;
2598                 if (!chip->ecc.write_oob)
2599                         chip->ecc.write_oob = nand_write_oob_std;
2600
2601         case NAND_ECC_HW_SYNDROME:
2602                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2603                      !chip->ecc.hwctl) &&
2604                     (!chip->ecc.read_page ||
2605                      chip->ecc.read_page == nand_read_page_hwecc ||
2606                      !chip->ecc.write_page ||
2607                      chip->ecc.write_page == nand_write_page_hwecc)) {
2608                         printk(KERN_WARNING "No ECC functions supplied, "
2609                                "Hardware ECC not possible\n");
2610                         BUG();
2611                 }
2612                 /* Use standard syndrome read/write page function ? */
2613                 if (!chip->ecc.read_page)
2614                         chip->ecc.read_page = nand_read_page_syndrome;
2615                 if (!chip->ecc.write_page)
2616                         chip->ecc.write_page = nand_write_page_syndrome;
2617                 if (!chip->ecc.read_oob)
2618                         chip->ecc.read_oob = nand_read_oob_syndrome;
2619                 if (!chip->ecc.write_oob)
2620                         chip->ecc.write_oob = nand_write_oob_syndrome;
2621
2622                 if (mtd->writesize >= chip->ecc.size)
2623                         break;
2624                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2625                        "%d byte page size, fallback to SW ECC\n",
2626                        chip->ecc.size, mtd->writesize);
2627                 chip->ecc.mode = NAND_ECC_SOFT;
2628
2629         case NAND_ECC_SOFT:
2630                 chip->ecc.calculate = nand_calculate_ecc;
2631                 chip->ecc.correct = nand_correct_data;
2632                 chip->ecc.read_page = nand_read_page_swecc;
2633                 chip->ecc.write_page = nand_write_page_swecc;
2634                 chip->ecc.read_oob = nand_read_oob_std;
2635                 chip->ecc.write_oob = nand_write_oob_std;
2636                 chip->ecc.size = 256;
2637                 chip->ecc.bytes = 3;
2638                 break;
2639
2640         case NAND_ECC_NONE:
2641                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2642                        "This is not recommended !!\n");
2643                 chip->ecc.read_page = nand_read_page_raw;
2644                 chip->ecc.write_page = nand_write_page_raw;
2645                 chip->ecc.read_oob = nand_read_oob_std;
2646                 chip->ecc.write_oob = nand_write_oob_std;
2647                 chip->ecc.size = mtd->writesize;
2648                 chip->ecc.bytes = 0;
2649                 break;
2650
2651         default:
2652                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2653                        chip->ecc.mode);
2654                 BUG();
2655         }
2656
2657         /*
2658          * The number of bytes available for a client to place data into
2659          * the out of band area
2660          */
2661         chip->ecc.layout->oobavail = 0;
2662         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2663                 chip->ecc.layout->oobavail +=
2664                         chip->ecc.layout->oobfree[i].length;
2665         mtd->oobavail = chip->ecc.layout->oobavail;
2666
2667         /*
2668          * Set the number of read / write steps for one page depending on ECC
2669          * mode
2670          */
2671         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2672         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2673                 printk(KERN_WARNING "Invalid ecc parameters\n");
2674                 BUG();
2675         }
2676         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2677
2678         /*
2679          * Allow subpage writes up to ecc.steps. Not possible for MLC
2680          * FLASH.
2681          */
2682         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2683             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2684                 switch(chip->ecc.steps) {
2685                 case 2:
2686                         mtd->subpage_sft = 1;
2687                         break;
2688                 case 4:
2689                 case 8:
2690                         mtd->subpage_sft = 2;
2691                         break;
2692                 }
2693         }
2694         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2695
2696         /* Initialize state */
2697         chip->state = FL_READY;
2698
2699         /* De-select the device */
2700         chip->select_chip(mtd, -1);
2701
2702         /* Invalidate the pagebuffer reference */
2703         chip->pagebuf = -1;
2704
2705         /* Fill in remaining MTD driver data */
2706         mtd->type = MTD_NANDFLASH;
2707         mtd->flags = MTD_CAP_NANDFLASH;
2708         mtd->erase = nand_erase;
2709         mtd->point = NULL;
2710         mtd->unpoint = NULL;
2711         mtd->read = nand_read;
2712         mtd->write = nand_write;
2713         mtd->read_oob = nand_read_oob;
2714         mtd->write_oob = nand_write_oob;
2715         mtd->sync = nand_sync;
2716         mtd->lock = NULL;
2717         mtd->unlock = NULL;
2718         mtd->suspend = nand_suspend;
2719         mtd->resume = nand_resume;
2720         mtd->block_isbad = nand_block_isbad;
2721         mtd->block_markbad = nand_block_markbad;
2722
2723         /* propagate ecc.layout to mtd_info */
2724         mtd->ecclayout = chip->ecc.layout;
2725
2726         /* Check, if we should skip the bad block table scan */
2727         if (chip->options & NAND_SKIP_BBTSCAN)
2728                 chip->options |= NAND_BBT_SCANNED;
2729
2730         return 0;
2731 }
2732
2733 /* module_text_address() isn't exported, and it's mostly a pointless
2734    test if this is a module _anyway_ -- they'd have to try _really_ hard
2735    to call us from in-kernel code if the core NAND support is modular. */
2736 #ifdef MODULE
2737 #define caller_is_module() (1)
2738 #else
2739 #define caller_is_module() \
2740         module_text_address((unsigned long)__builtin_return_address(0))
2741 #endif
2742
2743 /**
2744  * nand_scan - [NAND Interface] Scan for the NAND device
2745  * @mtd:        MTD device structure
2746  * @maxchips:   Number of chips to scan for
2747  *
2748  * This fills out all the uninitialized function pointers
2749  * with the defaults.
2750  * The flash ID is read and the mtd/chip structures are
2751  * filled with the appropriate values.
2752  * The mtd->owner field must be set to the module of the caller
2753  *
2754  */
2755 int nand_scan(struct mtd_info *mtd, int maxchips)
2756 {
2757         int ret;
2758
2759         /* Many callers got this wrong, so check for it for a while... */
2760         /* XXX U-BOOT XXX */
2761 #if 0
2762         if (!mtd->owner && caller_is_module()) {
2763                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2764                 BUG();
2765         }
2766 #endif
2767
2768         ret = nand_scan_ident(mtd, maxchips);
2769         if (!ret)
2770                 ret = nand_scan_tail(mtd);
2771         return ret;
2772 }
2773
2774 /**
2775  * nand_release - [NAND Interface] Free resources held by the NAND device
2776  * @mtd:        MTD device structure
2777 */
2778 void nand_release(struct mtd_info *mtd)
2779 {
2780         struct nand_chip *chip = mtd->priv;
2781
2782 #ifdef CONFIG_MTD_PARTITIONS
2783         /* Deregister partitions */
2784         del_mtd_partitions(mtd);
2785 #endif
2786         /* Deregister the device */
2787         /* XXX U-BOOT XXX */
2788 #if 0
2789         del_mtd_device(mtd);
2790 #endif
2791
2792         /* Free bad block table memory */
2793         kfree(chip->bbt);
2794         if (!(chip->options & NAND_OWN_BUFFERS))
2795                 kfree(chip->buffers);
2796 }
2797
2798 /* XXX U-BOOT XXX */
2799 #if 0
2800 EXPORT_SYMBOL_GPL(nand_scan);
2801 EXPORT_SYMBOL_GPL(nand_scan_ident);
2802 EXPORT_SYMBOL_GPL(nand_scan_tail);
2803 EXPORT_SYMBOL_GPL(nand_release);
2804
2805 static int __init nand_base_init(void)
2806 {
2807         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2808         return 0;
2809 }
2810
2811 static void __exit nand_base_exit(void)
2812 {
2813         led_trigger_unregister_simple(nand_led_trigger);
2814 }
2815
2816 module_init(nand_base_init);
2817 module_exit(nand_base_exit);
2818
2819 MODULE_LICENSE("GPL");
2820 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2821 MODULE_DESCRIPTION("Generic NAND flash driver code");
2822 #endif